| T809 |
/workspace/coverage/default/14.spi_device_ram_cfg.500500353 |
|
|
Mar 21 02:18:46 PM PDT 24 |
Mar 21 02:18:47 PM PDT 24 |
31259280 ps |
| T810 |
/workspace/coverage/default/0.spi_device_tpm_all.2397606676 |
|
|
Mar 21 02:15:53 PM PDT 24 |
Mar 21 02:16:07 PM PDT 24 |
23633207504 ps |
| T811 |
/workspace/coverage/default/49.spi_device_mailbox.3538434455 |
|
|
Mar 21 02:23:00 PM PDT 24 |
Mar 21 02:23:14 PM PDT 24 |
11030614165 ps |
| T812 |
/workspace/coverage/default/2.spi_device_pass_cmd_filtering.1702341336 |
|
|
Mar 21 02:16:26 PM PDT 24 |
Mar 21 02:16:36 PM PDT 24 |
7381048607 ps |
| T813 |
/workspace/coverage/default/2.spi_device_stress_all.1261710194 |
|
|
Mar 21 02:16:25 PM PDT 24 |
Mar 21 02:18:28 PM PDT 24 |
58414638934 ps |
| T814 |
/workspace/coverage/default/16.spi_device_mailbox.291729429 |
|
|
Mar 21 02:19:07 PM PDT 24 |
Mar 21 02:19:27 PM PDT 24 |
5867600925 ps |
| T815 |
/workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2415474246 |
|
|
Mar 21 02:22:39 PM PDT 24 |
Mar 21 02:23:03 PM PDT 24 |
14935637644 ps |
| T816 |
/workspace/coverage/default/1.spi_device_flash_all.936957455 |
|
|
Mar 21 02:16:17 PM PDT 24 |
Mar 21 02:16:41 PM PDT 24 |
6891636603 ps |
| T817 |
/workspace/coverage/default/16.spi_device_pass_addr_payload_swap.2358235920 |
|
|
Mar 21 02:19:08 PM PDT 24 |
Mar 21 02:19:12 PM PDT 24 |
443906668 ps |
| T818 |
/workspace/coverage/default/24.spi_device_tpm_sts_read.2269223267 |
|
|
Mar 21 02:20:13 PM PDT 24 |
Mar 21 02:20:14 PM PDT 24 |
82390161 ps |
| T819 |
/workspace/coverage/default/40.spi_device_pass_cmd_filtering.2763035501 |
|
|
Mar 21 02:21:57 PM PDT 24 |
Mar 21 02:22:19 PM PDT 24 |
38211276402 ps |
| T253 |
/workspace/coverage/default/6.spi_device_flash_all.2146196903 |
|
|
Mar 21 02:17:26 PM PDT 24 |
Mar 21 02:23:54 PM PDT 24 |
250440148038 ps |
| T820 |
/workspace/coverage/default/45.spi_device_tpm_sts_read.3717857125 |
|
|
Mar 21 02:22:31 PM PDT 24 |
Mar 21 02:22:32 PM PDT 24 |
66174236 ps |
| T821 |
/workspace/coverage/default/31.spi_device_pass_addr_payload_swap.151803599 |
|
|
Mar 21 02:21:00 PM PDT 24 |
Mar 21 02:21:06 PM PDT 24 |
669002909 ps |
| T822 |
/workspace/coverage/default/45.spi_device_cfg_cmd.3427079671 |
|
|
Mar 21 02:22:30 PM PDT 24 |
Mar 21 02:22:33 PM PDT 24 |
64209630 ps |
| T823 |
/workspace/coverage/default/27.spi_device_flash_all.1978589095 |
|
|
Mar 21 02:20:42 PM PDT 24 |
Mar 21 02:23:02 PM PDT 24 |
21829925105 ps |
| T824 |
/workspace/coverage/default/38.spi_device_intercept.3771634705 |
|
|
Mar 21 02:21:57 PM PDT 24 |
Mar 21 02:22:06 PM PDT 24 |
3488641061 ps |
| T825 |
/workspace/coverage/default/3.spi_device_pass_cmd_filtering.784597164 |
|
|
Mar 21 02:16:39 PM PDT 24 |
Mar 21 02:16:46 PM PDT 24 |
590762786 ps |
| T826 |
/workspace/coverage/default/26.spi_device_alert_test.3506610802 |
|
|
Mar 21 02:20:42 PM PDT 24 |
Mar 21 02:20:43 PM PDT 24 |
156367498 ps |
| T827 |
/workspace/coverage/default/28.spi_device_read_buffer_direct.3650998190 |
|
|
Mar 21 02:20:50 PM PDT 24 |
Mar 21 02:20:54 PM PDT 24 |
217943909 ps |
| T828 |
/workspace/coverage/default/43.spi_device_csb_read.1058627444 |
|
|
Mar 21 02:22:22 PM PDT 24 |
Mar 21 02:22:23 PM PDT 24 |
59959851 ps |
| T829 |
/workspace/coverage/default/3.spi_device_tpm_read_hw_reg.3876184057 |
|
|
Mar 21 02:16:28 PM PDT 24 |
Mar 21 02:16:34 PM PDT 24 |
2148652962 ps |
| T830 |
/workspace/coverage/default/5.spi_device_flash_and_tpm.352620483 |
|
|
Mar 21 02:17:08 PM PDT 24 |
Mar 21 02:17:51 PM PDT 24 |
6890078196 ps |
| T831 |
/workspace/coverage/default/18.spi_device_tpm_read_hw_reg.2618611507 |
|
|
Mar 21 02:19:28 PM PDT 24 |
Mar 21 02:19:31 PM PDT 24 |
1233856898 ps |
| T832 |
/workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.585402703 |
|
|
Mar 21 02:20:51 PM PDT 24 |
Mar 21 02:22:25 PM PDT 24 |
95646826765 ps |
| T833 |
/workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.3705379555 |
|
|
Mar 21 02:19:45 PM PDT 24 |
Mar 21 02:21:44 PM PDT 24 |
15509876941 ps |
| T834 |
/workspace/coverage/default/6.spi_device_upload.3764855408 |
|
|
Mar 21 02:17:25 PM PDT 24 |
Mar 21 02:17:31 PM PDT 24 |
1462581008 ps |
| T835 |
/workspace/coverage/default/20.spi_device_mailbox.3596978334 |
|
|
Mar 21 02:19:56 PM PDT 24 |
Mar 21 02:20:06 PM PDT 24 |
1216815834 ps |
| T836 |
/workspace/coverage/default/12.spi_device_pass_addr_payload_swap.2517664545 |
|
|
Mar 21 02:18:38 PM PDT 24 |
Mar 21 02:18:42 PM PDT 24 |
3295117414 ps |
| T837 |
/workspace/coverage/default/37.spi_device_upload.3715407900 |
|
|
Mar 21 02:21:43 PM PDT 24 |
Mar 21 02:21:54 PM PDT 24 |
2871207170 ps |
| T245 |
/workspace/coverage/default/12.spi_device_flash_and_tpm.1321185048 |
|
|
Mar 21 02:18:30 PM PDT 24 |
Mar 21 02:24:12 PM PDT 24 |
196619179802 ps |
| T838 |
/workspace/coverage/default/9.spi_device_tpm_all.3310301387 |
|
|
Mar 21 02:17:56 PM PDT 24 |
Mar 21 02:18:44 PM PDT 24 |
13103130951 ps |
| T839 |
/workspace/coverage/default/3.spi_device_flash_and_tpm.924405025 |
|
|
Mar 21 02:16:39 PM PDT 24 |
Mar 21 02:18:47 PM PDT 24 |
21479359517 ps |
| T840 |
/workspace/coverage/default/41.spi_device_flash_mode.2870175541 |
|
|
Mar 21 02:22:08 PM PDT 24 |
Mar 21 02:22:34 PM PDT 24 |
4059833059 ps |
| T841 |
/workspace/coverage/default/21.spi_device_read_buffer_direct.2761101599 |
|
|
Mar 21 02:19:59 PM PDT 24 |
Mar 21 02:20:03 PM PDT 24 |
148084855 ps |
| T842 |
/workspace/coverage/default/22.spi_device_upload.2982060335 |
|
|
Mar 21 02:20:06 PM PDT 24 |
Mar 21 02:20:13 PM PDT 24 |
2132828059 ps |
| T66 |
/workspace/coverage/default/0.spi_device_sec_cm.767291524 |
|
|
Mar 21 02:16:17 PM PDT 24 |
Mar 21 02:16:18 PM PDT 24 |
236256518 ps |
| T843 |
/workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.3238094526 |
|
|
Mar 21 02:18:53 PM PDT 24 |
Mar 21 02:20:00 PM PDT 24 |
54991720488 ps |
| T237 |
/workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.3017368587 |
|
|
Mar 21 02:21:43 PM PDT 24 |
Mar 21 02:25:17 PM PDT 24 |
19793852806 ps |
| T844 |
/workspace/coverage/default/3.spi_device_csb_read.520887594 |
|
|
Mar 21 02:16:27 PM PDT 24 |
Mar 21 02:16:28 PM PDT 24 |
113599609 ps |
| T845 |
/workspace/coverage/default/37.spi_device_mailbox.1710342834 |
|
|
Mar 21 02:21:43 PM PDT 24 |
Mar 21 02:21:51 PM PDT 24 |
606366728 ps |
| T846 |
/workspace/coverage/default/0.spi_device_pass_addr_payload_swap.832220456 |
|
|
Mar 21 02:15:55 PM PDT 24 |
Mar 21 02:16:11 PM PDT 24 |
9378759912 ps |
| T847 |
/workspace/coverage/default/4.spi_device_upload.3874452432 |
|
|
Mar 21 02:16:58 PM PDT 24 |
Mar 21 02:17:04 PM PDT 24 |
949952095 ps |
| T848 |
/workspace/coverage/default/19.spi_device_ram_cfg.1185064941 |
|
|
Mar 21 02:19:44 PM PDT 24 |
Mar 21 02:19:45 PM PDT 24 |
35302709 ps |
| T849 |
/workspace/coverage/default/34.spi_device_mailbox.1794547804 |
|
|
Mar 21 02:21:22 PM PDT 24 |
Mar 21 02:21:48 PM PDT 24 |
38067903953 ps |
| T850 |
/workspace/coverage/default/10.spi_device_alert_test.1433507437 |
|
|
Mar 21 02:18:09 PM PDT 24 |
Mar 21 02:18:10 PM PDT 24 |
13693841 ps |
| T851 |
/workspace/coverage/default/12.spi_device_ram_cfg.3656430533 |
|
|
Mar 21 02:18:17 PM PDT 24 |
Mar 21 02:18:18 PM PDT 24 |
23174907 ps |
| T852 |
/workspace/coverage/default/16.spi_device_flash_mode.293906428 |
|
|
Mar 21 02:19:29 PM PDT 24 |
Mar 21 02:19:46 PM PDT 24 |
3547519868 ps |
| T853 |
/workspace/coverage/default/48.spi_device_pass_addr_payload_swap.1770749358 |
|
|
Mar 21 02:22:47 PM PDT 24 |
Mar 21 02:23:04 PM PDT 24 |
10022417003 ps |
| T854 |
/workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.94941521 |
|
|
Mar 21 02:22:07 PM PDT 24 |
Mar 21 02:23:23 PM PDT 24 |
49652886703 ps |
| T855 |
/workspace/coverage/default/10.spi_device_tpm_rw.3718649856 |
|
|
Mar 21 02:17:59 PM PDT 24 |
Mar 21 02:18:00 PM PDT 24 |
69862475 ps |
| T856 |
/workspace/coverage/default/26.spi_device_flash_and_tpm.1889176363 |
|
|
Mar 21 02:20:29 PM PDT 24 |
Mar 21 02:21:52 PM PDT 24 |
6937981101 ps |
| T857 |
/workspace/coverage/default/26.spi_device_cfg_cmd.2296771528 |
|
|
Mar 21 02:20:30 PM PDT 24 |
Mar 21 02:20:34 PM PDT 24 |
527922877 ps |
| T858 |
/workspace/coverage/default/7.spi_device_read_buffer_direct.4181821699 |
|
|
Mar 21 02:17:38 PM PDT 24 |
Mar 21 02:17:44 PM PDT 24 |
594230555 ps |
| T859 |
/workspace/coverage/default/47.spi_device_stress_all.154700752 |
|
|
Mar 21 02:22:48 PM PDT 24 |
Mar 21 02:29:46 PM PDT 24 |
40242439483 ps |
| T860 |
/workspace/coverage/default/49.spi_device_tpm_all.3013460732 |
|
|
Mar 21 02:22:59 PM PDT 24 |
Mar 21 02:23:10 PM PDT 24 |
1649046032 ps |
| T861 |
/workspace/coverage/default/19.spi_device_cfg_cmd.3958053595 |
|
|
Mar 21 02:19:45 PM PDT 24 |
Mar 21 02:19:50 PM PDT 24 |
1492372451 ps |
| T862 |
/workspace/coverage/default/27.spi_device_mailbox.911976801 |
|
|
Mar 21 02:20:41 PM PDT 24 |
Mar 21 02:21:06 PM PDT 24 |
16001744029 ps |
| T863 |
/workspace/coverage/default/10.spi_device_tpm_read_hw_reg.2139710336 |
|
|
Mar 21 02:17:56 PM PDT 24 |
Mar 21 02:18:31 PM PDT 24 |
13202030177 ps |
| T864 |
/workspace/coverage/default/23.spi_device_intercept.2850866307 |
|
|
Mar 21 02:20:00 PM PDT 24 |
Mar 21 02:20:04 PM PDT 24 |
175184388 ps |
| T865 |
/workspace/coverage/default/2.spi_device_tpm_all.2013757794 |
|
|
Mar 21 02:16:26 PM PDT 24 |
Mar 21 02:16:44 PM PDT 24 |
7697170613 ps |
| T866 |
/workspace/coverage/default/36.spi_device_tpm_rw.2508818076 |
|
|
Mar 21 02:21:44 PM PDT 24 |
Mar 21 02:21:45 PM PDT 24 |
13178239 ps |
| T867 |
/workspace/coverage/default/19.spi_device_flash_all.534066655 |
|
|
Mar 21 02:19:45 PM PDT 24 |
Mar 21 02:20:15 PM PDT 24 |
19504411272 ps |
| T868 |
/workspace/coverage/default/11.spi_device_csb_read.925131441 |
|
|
Mar 21 02:18:09 PM PDT 24 |
Mar 21 02:18:10 PM PDT 24 |
52526335 ps |
| T869 |
/workspace/coverage/default/1.spi_device_intercept.253047311 |
|
|
Mar 21 02:16:15 PM PDT 24 |
Mar 21 02:16:25 PM PDT 24 |
3720486689 ps |
| T870 |
/workspace/coverage/default/38.spi_device_flash_mode.857998040 |
|
|
Mar 21 02:21:56 PM PDT 24 |
Mar 21 02:22:51 PM PDT 24 |
45250420582 ps |
| T871 |
/workspace/coverage/default/42.spi_device_intercept.4143432876 |
|
|
Mar 21 02:22:19 PM PDT 24 |
Mar 21 02:22:21 PM PDT 24 |
74949245 ps |
| T872 |
/workspace/coverage/default/30.spi_device_intercept.1014615417 |
|
|
Mar 21 02:20:53 PM PDT 24 |
Mar 21 02:20:56 PM PDT 24 |
345567256 ps |
| T873 |
/workspace/coverage/default/44.spi_device_tpm_all.3801244525 |
|
|
Mar 21 02:22:31 PM PDT 24 |
Mar 21 02:22:48 PM PDT 24 |
17528501008 ps |
| T874 |
/workspace/coverage/default/12.spi_device_alert_test.254170880 |
|
|
Mar 21 02:18:31 PM PDT 24 |
Mar 21 02:18:33 PM PDT 24 |
180440823 ps |
| T875 |
/workspace/coverage/default/19.spi_device_tpm_sts_read.3230638767 |
|
|
Mar 21 02:19:45 PM PDT 24 |
Mar 21 02:19:46 PM PDT 24 |
96884319 ps |
| T876 |
/workspace/coverage/default/48.spi_device_upload.2206890338 |
|
|
Mar 21 02:22:50 PM PDT 24 |
Mar 21 02:23:01 PM PDT 24 |
2926832635 ps |
| T239 |
/workspace/coverage/default/20.spi_device_pass_addr_payload_swap.3395069543 |
|
|
Mar 21 02:19:54 PM PDT 24 |
Mar 21 02:20:00 PM PDT 24 |
630950816 ps |
| T877 |
/workspace/coverage/default/31.spi_device_mailbox.1809684921 |
|
|
Mar 21 02:21:05 PM PDT 24 |
Mar 21 02:22:06 PM PDT 24 |
97258120519 ps |
| T878 |
/workspace/coverage/default/2.spi_device_flash_mode.3290114482 |
|
|
Mar 21 02:16:27 PM PDT 24 |
Mar 21 02:16:56 PM PDT 24 |
3123310446 ps |
| T879 |
/workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.346837836 |
|
|
Mar 21 02:22:37 PM PDT 24 |
Mar 21 02:27:01 PM PDT 24 |
34608644495 ps |
| T880 |
/workspace/coverage/default/19.spi_device_mailbox.3637955160 |
|
|
Mar 21 02:19:44 PM PDT 24 |
Mar 21 02:19:56 PM PDT 24 |
1910409413 ps |
| T881 |
/workspace/coverage/default/33.spi_device_flash_all.2309854052 |
|
|
Mar 21 02:21:17 PM PDT 24 |
Mar 21 02:24:48 PM PDT 24 |
44410523635 ps |
| T882 |
/workspace/coverage/default/13.spi_device_intercept.4122924570 |
|
|
Mar 21 02:18:45 PM PDT 24 |
Mar 21 02:18:55 PM PDT 24 |
11216615166 ps |
| T883 |
/workspace/coverage/default/26.spi_device_pass_cmd_filtering.4114236009 |
|
|
Mar 21 02:20:28 PM PDT 24 |
Mar 21 02:20:40 PM PDT 24 |
1699392868 ps |
| T884 |
/workspace/coverage/default/10.spi_device_upload.773514420 |
|
|
Mar 21 02:18:07 PM PDT 24 |
Mar 21 02:18:16 PM PDT 24 |
1876743355 ps |
| T885 |
/workspace/coverage/default/12.spi_device_tpm_sts_read.3694428099 |
|
|
Mar 21 02:18:29 PM PDT 24 |
Mar 21 02:18:31 PM PDT 24 |
247596359 ps |
| T886 |
/workspace/coverage/default/0.spi_device_flash_and_tpm.2506007651 |
|
|
Mar 21 02:16:11 PM PDT 24 |
Mar 21 02:23:42 PM PDT 24 |
341797339438 ps |
| T887 |
/workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.2671467585 |
|
|
Mar 21 02:16:30 PM PDT 24 |
Mar 21 02:25:03 PM PDT 24 |
143685184548 ps |
| T254 |
/workspace/coverage/default/3.spi_device_flash_all.2009065405 |
|
|
Mar 21 02:16:37 PM PDT 24 |
Mar 21 02:24:17 PM PDT 24 |
204686701842 ps |
| T888 |
/workspace/coverage/default/32.spi_device_tpm_rw.672908801 |
|
|
Mar 21 02:20:59 PM PDT 24 |
Mar 21 02:21:03 PM PDT 24 |
223567956 ps |
| T889 |
/workspace/coverage/default/48.spi_device_flash_all.3846673512 |
|
|
Mar 21 02:22:50 PM PDT 24 |
Mar 21 02:23:56 PM PDT 24 |
36892474223 ps |
| T890 |
/workspace/coverage/default/29.spi_device_upload.1446820069 |
|
|
Mar 21 02:20:51 PM PDT 24 |
Mar 21 02:20:58 PM PDT 24 |
953916278 ps |
| T891 |
/workspace/coverage/default/26.spi_device_upload.411936241 |
|
|
Mar 21 02:20:30 PM PDT 24 |
Mar 21 02:20:41 PM PDT 24 |
1035020916 ps |
| T67 |
/workspace/coverage/default/2.spi_device_sec_cm.4210342279 |
|
|
Mar 21 02:16:26 PM PDT 24 |
Mar 21 02:16:27 PM PDT 24 |
50967243 ps |
| T892 |
/workspace/coverage/default/3.spi_device_tpm_rw.4064140581 |
|
|
Mar 21 02:16:26 PM PDT 24 |
Mar 21 02:16:27 PM PDT 24 |
15082099 ps |
| T893 |
/workspace/coverage/default/4.spi_device_csb_read.2511584917 |
|
|
Mar 21 02:16:48 PM PDT 24 |
Mar 21 02:16:49 PM PDT 24 |
13001550 ps |
| T894 |
/workspace/coverage/default/32.spi_device_stress_all.259609467 |
|
|
Mar 21 02:21:10 PM PDT 24 |
Mar 21 02:24:00 PM PDT 24 |
61295270846 ps |
| T895 |
/workspace/coverage/default/24.spi_device_stress_all.2530023221 |
|
|
Mar 21 02:20:22 PM PDT 24 |
Mar 21 02:20:24 PM PDT 24 |
138136797 ps |
| T896 |
/workspace/coverage/default/17.spi_device_pass_cmd_filtering.2523593302 |
|
|
Mar 21 02:19:28 PM PDT 24 |
Mar 21 02:19:33 PM PDT 24 |
958311214 ps |
| T897 |
/workspace/coverage/default/40.spi_device_alert_test.1596970606 |
|
|
Mar 21 02:22:07 PM PDT 24 |
Mar 21 02:22:08 PM PDT 24 |
14937656 ps |
| T898 |
/workspace/coverage/default/18.spi_device_flash_and_tpm.3869772891 |
|
|
Mar 21 02:19:44 PM PDT 24 |
Mar 21 02:21:53 PM PDT 24 |
9387235615 ps |
| T899 |
/workspace/coverage/default/22.spi_device_pass_cmd_filtering.54348527 |
|
|
Mar 21 02:19:54 PM PDT 24 |
Mar 21 02:20:14 PM PDT 24 |
7732235074 ps |
| T900 |
/workspace/coverage/default/31.spi_device_tpm_rw.1334928147 |
|
|
Mar 21 02:20:58 PM PDT 24 |
Mar 21 02:21:08 PM PDT 24 |
268257294 ps |
| T901 |
/workspace/coverage/default/0.spi_device_cfg_cmd.713216453 |
|
|
Mar 21 02:16:05 PM PDT 24 |
Mar 21 02:16:07 PM PDT 24 |
64659472 ps |
| T902 |
/workspace/coverage/default/9.spi_device_upload.4150324185 |
|
|
Mar 21 02:17:59 PM PDT 24 |
Mar 21 02:18:10 PM PDT 24 |
1550803179 ps |
| T903 |
/workspace/coverage/default/6.spi_device_read_buffer_direct.3264953932 |
|
|
Mar 21 02:17:24 PM PDT 24 |
Mar 21 02:17:30 PM PDT 24 |
1402877472 ps |
| T904 |
/workspace/coverage/default/35.spi_device_pass_cmd_filtering.811931358 |
|
|
Mar 21 02:21:29 PM PDT 24 |
Mar 21 02:21:33 PM PDT 24 |
369876666 ps |
| T905 |
/workspace/coverage/default/8.spi_device_tpm_all.193244486 |
|
|
Mar 21 02:17:36 PM PDT 24 |
Mar 21 02:18:01 PM PDT 24 |
4246702772 ps |
| T906 |
/workspace/coverage/default/15.spi_device_mailbox.3091061999 |
|
|
Mar 21 02:18:57 PM PDT 24 |
Mar 21 02:19:05 PM PDT 24 |
696622643 ps |
| T243 |
/workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.2836878672 |
|
|
Mar 21 02:18:53 PM PDT 24 |
Mar 21 02:21:13 PM PDT 24 |
37619454394 ps |
| T907 |
/workspace/coverage/default/1.spi_device_tpm_sts_read.1333263342 |
|
|
Mar 21 02:16:20 PM PDT 24 |
Mar 21 02:16:21 PM PDT 24 |
26509466 ps |
| T908 |
/workspace/coverage/default/2.spi_device_tpm_read_hw_reg.1342524994 |
|
|
Mar 21 02:16:25 PM PDT 24 |
Mar 21 02:16:33 PM PDT 24 |
1189267797 ps |
| T68 |
/workspace/coverage/default/1.spi_device_sec_cm.4134427790 |
|
|
Mar 21 02:16:16 PM PDT 24 |
Mar 21 02:16:18 PM PDT 24 |
1121826359 ps |
| T909 |
/workspace/coverage/default/29.spi_device_flash_all.3303800656 |
|
|
Mar 21 02:20:53 PM PDT 24 |
Mar 21 02:21:37 PM PDT 24 |
8884203486 ps |
| T910 |
/workspace/coverage/default/15.spi_device_flash_mode.965379687 |
|
|
Mar 21 02:18:55 PM PDT 24 |
Mar 21 02:19:28 PM PDT 24 |
4718575528 ps |
| T911 |
/workspace/coverage/default/29.spi_device_mailbox.4077562168 |
|
|
Mar 21 02:20:53 PM PDT 24 |
Mar 21 02:21:27 PM PDT 24 |
28051111345 ps |
| T912 |
/workspace/coverage/default/36.spi_device_flash_and_tpm.804170718 |
|
|
Mar 21 02:21:43 PM PDT 24 |
Mar 21 02:23:45 PM PDT 24 |
9653121318 ps |
| T913 |
/workspace/coverage/default/4.spi_device_pass_addr_payload_swap.1279016101 |
|
|
Mar 21 02:16:49 PM PDT 24 |
Mar 21 02:17:08 PM PDT 24 |
44514235912 ps |
| T914 |
/workspace/coverage/default/49.spi_device_pass_addr_payload_swap.3103138232 |
|
|
Mar 21 02:23:01 PM PDT 24 |
Mar 21 02:23:07 PM PDT 24 |
2735801522 ps |
| T915 |
/workspace/coverage/default/32.spi_device_intercept.2494748502 |
|
|
Mar 21 02:21:07 PM PDT 24 |
Mar 21 02:21:18 PM PDT 24 |
3226015248 ps |
| T916 |
/workspace/coverage/default/44.spi_device_upload.2821889881 |
|
|
Mar 21 02:22:30 PM PDT 24 |
Mar 21 02:22:37 PM PDT 24 |
861282876 ps |
| T917 |
/workspace/coverage/default/9.spi_device_flash_and_tpm.398933400 |
|
|
Mar 21 02:17:58 PM PDT 24 |
Mar 21 02:22:45 PM PDT 24 |
218595331851 ps |
| T918 |
/workspace/coverage/default/32.spi_device_flash_and_tpm.2827291860 |
|
|
Mar 21 02:21:13 PM PDT 24 |
Mar 21 02:25:58 PM PDT 24 |
158404201268 ps |
| T919 |
/workspace/coverage/default/28.spi_device_mailbox.718242186 |
|
|
Mar 21 02:20:44 PM PDT 24 |
Mar 21 02:21:14 PM PDT 24 |
10037814809 ps |
| T920 |
/workspace/coverage/default/9.spi_device_alert_test.1749949757 |
|
|
Mar 21 02:17:56 PM PDT 24 |
Mar 21 02:17:57 PM PDT 24 |
46955723 ps |
| T921 |
/workspace/coverage/default/48.spi_device_csb_read.3903049830 |
|
|
Mar 21 02:22:54 PM PDT 24 |
Mar 21 02:22:55 PM PDT 24 |
200768973 ps |
| T922 |
/workspace/coverage/default/22.spi_device_tpm_rw.726049362 |
|
|
Mar 21 02:19:54 PM PDT 24 |
Mar 21 02:19:56 PM PDT 24 |
172568645 ps |
| T238 |
/workspace/coverage/default/20.spi_device_stress_all.3637665620 |
|
|
Mar 21 02:19:57 PM PDT 24 |
Mar 21 02:24:39 PM PDT 24 |
18626782334 ps |
| T923 |
/workspace/coverage/default/21.spi_device_tpm_all.4190877590 |
|
|
Mar 21 02:20:00 PM PDT 24 |
Mar 21 02:20:32 PM PDT 24 |
11248744379 ps |
| T137 |
/workspace/coverage/default/40.spi_device_stress_all.2678726437 |
|
|
Mar 21 02:22:06 PM PDT 24 |
Mar 21 02:34:59 PM PDT 24 |
110958128260 ps |
| T924 |
/workspace/coverage/default/16.spi_device_cfg_cmd.4216597205 |
|
|
Mar 21 02:19:28 PM PDT 24 |
Mar 21 02:19:33 PM PDT 24 |
1098737425 ps |
| T925 |
/workspace/coverage/default/3.spi_device_read_buffer_direct.3013284238 |
|
|
Mar 21 02:16:37 PM PDT 24 |
Mar 21 02:16:45 PM PDT 24 |
2864730510 ps |
| T926 |
/workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.692910861 |
|
|
Mar 21 02:20:40 PM PDT 24 |
Mar 21 02:21:42 PM PDT 24 |
28951862912 ps |
| T927 |
/workspace/coverage/default/18.spi_device_tpm_all.2090799685 |
|
|
Mar 21 02:19:45 PM PDT 24 |
Mar 21 02:20:13 PM PDT 24 |
26062200317 ps |
| T928 |
/workspace/coverage/default/9.spi_device_stress_all.2259291345 |
|
|
Mar 21 02:17:56 PM PDT 24 |
Mar 21 02:17:58 PM PDT 24 |
97965928 ps |
| T929 |
/workspace/coverage/default/27.spi_device_csb_read.3089608340 |
|
|
Mar 21 02:20:42 PM PDT 24 |
Mar 21 02:20:43 PM PDT 24 |
15705240 ps |
| T930 |
/workspace/coverage/default/37.spi_device_intercept.40128572 |
|
|
Mar 21 02:21:43 PM PDT 24 |
Mar 21 02:21:55 PM PDT 24 |
16544582458 ps |
| T931 |
/workspace/coverage/default/29.spi_device_pass_addr_payload_swap.1129926090 |
|
|
Mar 21 02:20:51 PM PDT 24 |
Mar 21 02:20:58 PM PDT 24 |
787553090 ps |
| T932 |
/workspace/coverage/default/19.spi_device_stress_all.922575282 |
|
|
Mar 21 02:19:45 PM PDT 24 |
Mar 21 02:19:46 PM PDT 24 |
160724627 ps |
| T933 |
/workspace/coverage/default/20.spi_device_flash_and_tpm.4230765625 |
|
|
Mar 21 02:19:57 PM PDT 24 |
Mar 21 02:25:04 PM PDT 24 |
308976179865 ps |
| T934 |
/workspace/coverage/default/37.spi_device_alert_test.3284633308 |
|
|
Mar 21 02:21:58 PM PDT 24 |
Mar 21 02:21:58 PM PDT 24 |
15806979 ps |
| T935 |
/workspace/coverage/default/9.spi_device_intercept.295153206 |
|
|
Mar 21 02:17:55 PM PDT 24 |
Mar 21 02:18:03 PM PDT 24 |
1937407505 ps |
| T936 |
/workspace/coverage/default/47.spi_device_tpm_sts_read.1780166546 |
|
|
Mar 21 02:22:48 PM PDT 24 |
Mar 21 02:22:50 PM PDT 24 |
66923201 ps |
| T937 |
/workspace/coverage/default/43.spi_device_intercept.799790108 |
|
|
Mar 21 02:22:23 PM PDT 24 |
Mar 21 02:22:38 PM PDT 24 |
3915450431 ps |
| T938 |
/workspace/coverage/default/43.spi_device_tpm_read_hw_reg.305776613 |
|
|
Mar 21 02:22:22 PM PDT 24 |
Mar 21 02:22:24 PM PDT 24 |
199432937 ps |
| T939 |
/workspace/coverage/default/41.spi_device_cfg_cmd.2886706106 |
|
|
Mar 21 02:22:06 PM PDT 24 |
Mar 21 02:22:10 PM PDT 24 |
930109692 ps |
| T940 |
/workspace/coverage/default/46.spi_device_alert_test.472784234 |
|
|
Mar 21 02:22:39 PM PDT 24 |
Mar 21 02:22:40 PM PDT 24 |
14573681 ps |
| T941 |
/workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.1257781800 |
|
|
Mar 21 02:21:56 PM PDT 24 |
Mar 21 02:24:35 PM PDT 24 |
86492196796 ps |
| T942 |
/workspace/coverage/default/38.spi_device_tpm_read_hw_reg.1323310618 |
|
|
Mar 21 02:22:00 PM PDT 24 |
Mar 21 02:22:02 PM PDT 24 |
240568358 ps |
| T943 |
/workspace/coverage/default/7.spi_device_flash_all.2475203896 |
|
|
Mar 21 02:17:38 PM PDT 24 |
Mar 21 02:23:48 PM PDT 24 |
150405617951 ps |
| T944 |
/workspace/coverage/default/18.spi_device_pass_addr_payload_swap.1435944808 |
|
|
Mar 21 02:19:44 PM PDT 24 |
Mar 21 02:20:06 PM PDT 24 |
17880017989 ps |
| T945 |
/workspace/coverage/default/26.spi_device_read_buffer_direct.3833950480 |
|
|
Mar 21 02:20:28 PM PDT 24 |
Mar 21 02:20:32 PM PDT 24 |
185254924 ps |
| T249 |
/workspace/coverage/default/36.spi_device_flash_all.3818860485 |
|
|
Mar 21 02:21:43 PM PDT 24 |
Mar 21 02:25:19 PM PDT 24 |
101422465510 ps |
| T946 |
/workspace/coverage/default/5.spi_device_stress_all.1546740327 |
|
|
Mar 21 02:17:10 PM PDT 24 |
Mar 21 02:26:30 PM PDT 24 |
1496312912838 ps |
| T947 |
/workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.4213263542 |
|
|
Mar 21 02:22:23 PM PDT 24 |
Mar 21 02:25:24 PM PDT 24 |
100211273543 ps |
| T948 |
/workspace/coverage/default/44.spi_device_intercept.2446366801 |
|
|
Mar 21 02:22:28 PM PDT 24 |
Mar 21 02:22:33 PM PDT 24 |
2504060954 ps |
| T949 |
/workspace/coverage/default/31.spi_device_flash_all.2160660005 |
|
|
Mar 21 02:20:59 PM PDT 24 |
Mar 21 02:22:15 PM PDT 24 |
7432866228 ps |
| T950 |
/workspace/coverage/default/26.spi_device_flash_mode.1939624504 |
|
|
Mar 21 02:20:30 PM PDT 24 |
Mar 21 02:20:44 PM PDT 24 |
4469539821 ps |
| T951 |
/workspace/coverage/default/2.spi_device_ram_cfg.732826599 |
|
|
Mar 21 02:16:24 PM PDT 24 |
Mar 21 02:16:25 PM PDT 24 |
16464168 ps |
| T952 |
/workspace/coverage/default/12.spi_device_tpm_read_hw_reg.716980978 |
|
|
Mar 21 02:18:19 PM PDT 24 |
Mar 21 02:18:36 PM PDT 24 |
6835088680 ps |
| T953 |
/workspace/coverage/default/32.spi_device_pass_cmd_filtering.2978680290 |
|
|
Mar 21 02:21:07 PM PDT 24 |
Mar 21 02:21:11 PM PDT 24 |
1070075315 ps |
| T954 |
/workspace/coverage/default/22.spi_device_alert_test.968705609 |
|
|
Mar 21 02:20:08 PM PDT 24 |
Mar 21 02:20:09 PM PDT 24 |
54500015 ps |
| T955 |
/workspace/coverage/default/19.spi_device_tpm_read_hw_reg.3097437866 |
|
|
Mar 21 02:19:42 PM PDT 24 |
Mar 21 02:20:23 PM PDT 24 |
14263435723 ps |
| T956 |
/workspace/coverage/default/42.spi_device_cfg_cmd.42503193 |
|
|
Mar 21 02:22:19 PM PDT 24 |
Mar 21 02:22:22 PM PDT 24 |
224221724 ps |
| T957 |
/workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.4010043645 |
|
|
Mar 21 02:18:37 PM PDT 24 |
Mar 21 02:20:14 PM PDT 24 |
13564026438 ps |
| T138 |
/workspace/coverage/default/6.spi_device_stress_all.2775216809 |
|
|
Mar 21 02:17:27 PM PDT 24 |
Mar 21 02:17:28 PM PDT 24 |
168849656 ps |
| T958 |
/workspace/coverage/default/19.spi_device_pass_cmd_filtering.3515455842 |
|
|
Mar 21 02:19:45 PM PDT 24 |
Mar 21 02:19:52 PM PDT 24 |
7027457511 ps |
| T959 |
/workspace/coverage/default/14.spi_device_tpm_sts_read.3192748976 |
|
|
Mar 21 02:18:43 PM PDT 24 |
Mar 21 02:18:45 PM PDT 24 |
63686768 ps |
| T960 |
/workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.897976481 |
|
|
Mar 21 02:16:08 PM PDT 24 |
Mar 21 02:22:04 PM PDT 24 |
172417791094 ps |
| T961 |
/workspace/coverage/default/2.spi_device_flash_all.1591457886 |
|
|
Mar 21 02:16:24 PM PDT 24 |
Mar 21 02:24:33 PM PDT 24 |
97513164716 ps |
| T962 |
/workspace/coverage/default/38.spi_device_csb_read.1024499309 |
|
|
Mar 21 02:21:57 PM PDT 24 |
Mar 21 02:21:58 PM PDT 24 |
24610990 ps |
| T963 |
/workspace/coverage/default/11.spi_device_intercept.458954040 |
|
|
Mar 21 02:18:21 PM PDT 24 |
Mar 21 02:18:24 PM PDT 24 |
428358099 ps |
| T964 |
/workspace/coverage/default/15.spi_device_flash_and_tpm.500077884 |
|
|
Mar 21 02:18:51 PM PDT 24 |
Mar 21 02:19:34 PM PDT 24 |
10621365917 ps |
| T965 |
/workspace/coverage/default/32.spi_device_read_buffer_direct.3689695756 |
|
|
Mar 21 02:21:10 PM PDT 24 |
Mar 21 02:21:15 PM PDT 24 |
4982494575 ps |
| T107 |
/workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3363945546 |
|
|
Mar 21 01:53:11 PM PDT 24 |
Mar 21 01:53:12 PM PDT 24 |
62888696 ps |
| T966 |
/workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.946819479 |
|
|
Mar 21 01:53:47 PM PDT 24 |
Mar 21 01:53:49 PM PDT 24 |
132249956 ps |
| T967 |
/workspace/coverage/cover_reg_top/5.spi_device_intr_test.3076609351 |
|
|
Mar 21 01:53:14 PM PDT 24 |
Mar 21 01:53:15 PM PDT 24 |
12578407 ps |
| T968 |
/workspace/coverage/cover_reg_top/8.spi_device_intr_test.1384449471 |
|
|
Mar 21 01:53:13 PM PDT 24 |
Mar 21 01:53:14 PM PDT 24 |
32382416 ps |
| T56 |
/workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1251887817 |
|
|
Mar 21 01:53:14 PM PDT 24 |
Mar 21 01:53:26 PM PDT 24 |
192580736 ps |
| T969 |
/workspace/coverage/cover_reg_top/11.spi_device_intr_test.211111321 |
|
|
Mar 21 01:53:20 PM PDT 24 |
Mar 21 01:53:21 PM PDT 24 |
14800246 ps |
| T57 |
/workspace/coverage/cover_reg_top/0.spi_device_tl_errors.281167133 |
|
|
Mar 21 01:52:52 PM PDT 24 |
Mar 21 01:52:55 PM PDT 24 |
573853819 ps |
| T58 |
/workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1629247610 |
|
|
Mar 21 01:52:58 PM PDT 24 |
Mar 21 01:53:10 PM PDT 24 |
436767833 ps |
| T87 |
/workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1438202257 |
|
|
Mar 21 01:52:59 PM PDT 24 |
Mar 21 01:53:02 PM PDT 24 |
306518900 ps |
| T89 |
/workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.196200044 |
|
|
Mar 21 01:53:02 PM PDT 24 |
Mar 21 01:53:23 PM PDT 24 |
3106331923 ps |
| T970 |
/workspace/coverage/cover_reg_top/14.spi_device_intr_test.159748872 |
|
|
Mar 21 01:53:44 PM PDT 24 |
Mar 21 01:53:44 PM PDT 24 |
14007864 ps |
| T108 |
/workspace/coverage/cover_reg_top/12.spi_device_csr_rw.402198056 |
|
|
Mar 21 01:53:46 PM PDT 24 |
Mar 21 01:53:47 PM PDT 24 |
17771936 ps |
| T971 |
/workspace/coverage/cover_reg_top/47.spi_device_intr_test.1894700323 |
|
|
Mar 21 01:54:23 PM PDT 24 |
Mar 21 01:54:24 PM PDT 24 |
44192560 ps |
| T972 |
/workspace/coverage/cover_reg_top/33.spi_device_intr_test.1164869672 |
|
|
Mar 21 01:54:03 PM PDT 24 |
Mar 21 01:54:04 PM PDT 24 |
132130458 ps |
| T88 |
/workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.4019305270 |
|
|
Mar 21 01:53:11 PM PDT 24 |
Mar 21 01:53:15 PM PDT 24 |
150992570 ps |
| T973 |
/workspace/coverage/cover_reg_top/9.spi_device_intr_test.883325628 |
|
|
Mar 21 01:53:24 PM PDT 24 |
Mar 21 01:53:25 PM PDT 24 |
41218213 ps |
| T90 |
/workspace/coverage/cover_reg_top/3.spi_device_tl_errors.983391837 |
|
|
Mar 21 01:53:01 PM PDT 24 |
Mar 21 01:53:04 PM PDT 24 |
207084730 ps |
| T974 |
/workspace/coverage/cover_reg_top/15.spi_device_intr_test.235144879 |
|
|
Mar 21 01:53:45 PM PDT 24 |
Mar 21 01:53:46 PM PDT 24 |
18256437 ps |
| T109 |
/workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.978986670 |
|
|
Mar 21 01:52:59 PM PDT 24 |
Mar 21 01:53:01 PM PDT 24 |
193689416 ps |
| T110 |
/workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.4041945579 |
|
|
Mar 21 01:53:02 PM PDT 24 |
Mar 21 01:53:04 PM PDT 24 |
28859149 ps |
| T102 |
/workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1478188101 |
|
|
Mar 21 01:53:13 PM PDT 24 |
Mar 21 01:53:35 PM PDT 24 |
3175526446 ps |
| T111 |
/workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2143457566 |
|
|
Mar 21 01:54:03 PM PDT 24 |
Mar 21 01:54:05 PM PDT 24 |
209233513 ps |
| T101 |
/workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3582571544 |
|
|
Mar 21 01:53:45 PM PDT 24 |
Mar 21 01:54:08 PM PDT 24 |
2064044620 ps |
| T975 |
/workspace/coverage/cover_reg_top/21.spi_device_intr_test.484429186 |
|
|
Mar 21 01:54:04 PM PDT 24 |
Mar 21 01:54:04 PM PDT 24 |
24607210 ps |
| T112 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3712794312 |
|
|
Mar 21 01:52:57 PM PDT 24 |
Mar 21 01:53:09 PM PDT 24 |
750683773 ps |
| T976 |
/workspace/coverage/cover_reg_top/37.spi_device_intr_test.1239082188 |
|
|
Mar 21 01:54:02 PM PDT 24 |
Mar 21 01:54:03 PM PDT 24 |
37634913 ps |
| T977 |
/workspace/coverage/cover_reg_top/42.spi_device_intr_test.694274953 |
|
|
Mar 21 01:54:03 PM PDT 24 |
Mar 21 01:54:04 PM PDT 24 |
14599294 ps |
| T113 |
/workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.4138027692 |
|
|
Mar 21 01:52:57 PM PDT 24 |
Mar 21 01:53:13 PM PDT 24 |
1464274596 ps |
| T978 |
/workspace/coverage/cover_reg_top/31.spi_device_intr_test.1479518222 |
|
|
Mar 21 01:54:01 PM PDT 24 |
Mar 21 01:54:01 PM PDT 24 |
13767784 ps |
| T92 |
/workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1405596603 |
|
|
Mar 21 01:52:49 PM PDT 24 |
Mar 21 01:53:11 PM PDT 24 |
3276103671 ps |
| T103 |
/workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3470681984 |
|
|
Mar 21 01:52:51 PM PDT 24 |
Mar 21 01:53:00 PM PDT 24 |
304051826 ps |
| T91 |
/workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3120753418 |
|
|
Mar 21 01:54:01 PM PDT 24 |
Mar 21 01:54:04 PM PDT 24 |
230256671 ps |
| T979 |
/workspace/coverage/cover_reg_top/2.spi_device_mem_walk.4119206266 |
|
|
Mar 21 01:52:49 PM PDT 24 |
Mar 21 01:52:49 PM PDT 24 |
13599528 ps |
| T980 |
/workspace/coverage/cover_reg_top/41.spi_device_intr_test.1984465020 |
|
|
Mar 21 01:54:03 PM PDT 24 |
Mar 21 01:54:03 PM PDT 24 |
19860446 ps |
| T981 |
/workspace/coverage/cover_reg_top/48.spi_device_intr_test.868388465 |
|
|
Mar 21 01:54:20 PM PDT 24 |
Mar 21 01:54:21 PM PDT 24 |
83420363 ps |
| T78 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2752218530 |
|
|
Mar 21 01:52:54 PM PDT 24 |
Mar 21 01:52:55 PM PDT 24 |
322829155 ps |
| T127 |
/workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.78981180 |
|
|
Mar 21 01:54:03 PM PDT 24 |
Mar 21 01:54:06 PM PDT 24 |
450588671 ps |
| T93 |
/workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2876443432 |
|
|
Mar 21 01:53:48 PM PDT 24 |
Mar 21 01:53:52 PM PDT 24 |
171355219 ps |
| T982 |
/workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3388977929 |
|
|
Mar 21 01:52:56 PM PDT 24 |
Mar 21 01:53:22 PM PDT 24 |
6008154417 ps |
| T983 |
/workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.623355332 |
|
|
Mar 21 01:53:02 PM PDT 24 |
Mar 21 01:53:05 PM PDT 24 |
68626410 ps |
| T94 |
/workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3603803133 |
|
|
Mar 21 01:53:20 PM PDT 24 |
Mar 21 01:53:24 PM PDT 24 |
699404428 ps |
| T98 |
/workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.709244743 |
|
|
Mar 21 01:54:03 PM PDT 24 |
Mar 21 01:54:06 PM PDT 24 |
151614339 ps |
| T984 |
/workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1577247214 |
|
|
Mar 21 01:53:25 PM PDT 24 |
Mar 21 01:53:28 PM PDT 24 |
34130974 ps |
| T128 |
/workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1393988895 |
|
|
Mar 21 01:54:04 PM PDT 24 |
Mar 21 01:54:12 PM PDT 24 |
346189158 ps |
| T129 |
/workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2709249654 |
|
|
Mar 21 01:54:04 PM PDT 24 |
Mar 21 01:54:13 PM PDT 24 |
1432376950 ps |
| T985 |
/workspace/coverage/cover_reg_top/32.spi_device_intr_test.708591475 |
|
|
Mar 21 01:54:01 PM PDT 24 |
Mar 21 01:54:02 PM PDT 24 |
19804312 ps |
| T986 |
/workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.4164596896 |
|
|
Mar 21 01:53:48 PM PDT 24 |
Mar 21 01:53:51 PM PDT 24 |
41657873 ps |
| T987 |
/workspace/coverage/cover_reg_top/10.spi_device_intr_test.2420352778 |
|
|
Mar 21 01:53:30 PM PDT 24 |
Mar 21 01:53:31 PM PDT 24 |
13655016 ps |
| T95 |
/workspace/coverage/cover_reg_top/17.spi_device_tl_errors.199679620 |
|
|
Mar 21 01:53:59 PM PDT 24 |
Mar 21 01:54:02 PM PDT 24 |
555751086 ps |
| T97 |
/workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1582354076 |
|
|
Mar 21 01:53:46 PM PDT 24 |
Mar 21 01:53:49 PM PDT 24 |
42401706 ps |
| T988 |
/workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1919354446 |
|
|
Mar 21 01:53:44 PM PDT 24 |
Mar 21 01:53:46 PM PDT 24 |
56728621 ps |
| T989 |
/workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3614765354 |
|
|
Mar 21 01:53:03 PM PDT 24 |
Mar 21 01:53:12 PM PDT 24 |
1027245302 ps |
| T990 |
/workspace/coverage/cover_reg_top/36.spi_device_intr_test.2400607529 |
|
|
Mar 21 01:54:01 PM PDT 24 |
Mar 21 01:54:02 PM PDT 24 |
54850357 ps |
| T991 |
/workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1631611186 |
|
|
Mar 21 01:53:23 PM PDT 24 |
Mar 21 01:53:28 PM PDT 24 |
58869804 ps |
| T992 |
/workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1138823079 |
|
|
Mar 21 01:52:52 PM PDT 24 |
Mar 21 01:52:55 PM PDT 24 |
48298616 ps |
| T79 |
/workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1268136499 |
|
|
Mar 21 01:53:00 PM PDT 24 |
Mar 21 01:53:02 PM PDT 24 |
101837269 ps |
| T993 |
/workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1167295756 |
|
|
Mar 21 01:53:04 PM PDT 24 |
Mar 21 01:53:08 PM PDT 24 |
597762155 ps |
| T114 |
/workspace/coverage/cover_reg_top/15.spi_device_csr_rw.526309133 |
|
|
Mar 21 01:53:44 PM PDT 24 |
Mar 21 01:53:47 PM PDT 24 |
390709126 ps |
| T994 |
/workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1371763215 |
|
|
Mar 21 01:53:24 PM PDT 24 |
Mar 21 01:53:26 PM PDT 24 |
37833629 ps |
| T130 |
/workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3069320519 |
|
|
Mar 21 01:53:21 PM PDT 24 |
Mar 21 01:53:37 PM PDT 24 |
1423048914 ps |
| T995 |
/workspace/coverage/cover_reg_top/23.spi_device_intr_test.2308133038 |
|
|
Mar 21 01:54:07 PM PDT 24 |
Mar 21 01:54:08 PM PDT 24 |
32233649 ps |
| T996 |
/workspace/coverage/cover_reg_top/26.spi_device_intr_test.278552529 |
|
|
Mar 21 01:54:02 PM PDT 24 |
Mar 21 01:54:03 PM PDT 24 |
28413712 ps |
| T100 |
/workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2707617400 |
|
|
Mar 21 01:53:13 PM PDT 24 |
Mar 21 01:53:19 PM PDT 24 |
204448728 ps |
| T997 |
/workspace/coverage/cover_reg_top/3.spi_device_intr_test.1859035590 |
|
|
Mar 21 01:53:02 PM PDT 24 |
Mar 21 01:53:03 PM PDT 24 |
38407883 ps |
| T998 |
/workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3413397746 |
|
|
Mar 21 01:53:45 PM PDT 24 |
Mar 21 01:53:49 PM PDT 24 |
281465814 ps |
| T999 |
/workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3872936722 |
|
|
Mar 21 01:53:45 PM PDT 24 |
Mar 21 01:53:49 PM PDT 24 |
221910348 ps |
| T1000 |
/workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2224261558 |
|
|
Mar 21 01:53:05 PM PDT 24 |
Mar 21 01:53:06 PM PDT 24 |
160790219 ps |
| T131 |
/workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.248342263 |
|
|
Mar 21 01:52:50 PM PDT 24 |
Mar 21 01:52:54 PM PDT 24 |
334271036 ps |
| T148 |
/workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1552008081 |
|
|
Mar 21 01:53:27 PM PDT 24 |
Mar 21 01:53:45 PM PDT 24 |
313854831 ps |
| T1001 |
/workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1849579461 |
|
|
Mar 21 01:53:42 PM PDT 24 |
Mar 21 01:53:46 PM PDT 24 |
160351688 ps |
| T115 |
/workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3530032279 |
|
|
Mar 21 01:53:09 PM PDT 24 |
Mar 21 01:53:11 PM PDT 24 |
521895758 ps |
| T1002 |
/workspace/coverage/cover_reg_top/24.spi_device_intr_test.1800233270 |
|
|
Mar 21 01:54:01 PM PDT 24 |
Mar 21 01:54:02 PM PDT 24 |
48674362 ps |
| T146 |
/workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3527662241 |
|
|
Mar 21 01:53:23 PM PDT 24 |
Mar 21 01:53:39 PM PDT 24 |
630707851 ps |
| T1003 |
/workspace/coverage/cover_reg_top/6.spi_device_intr_test.45172314 |
|
|
Mar 21 01:53:13 PM PDT 24 |
Mar 21 01:53:14 PM PDT 24 |
44711566 ps |
| T1004 |
/workspace/coverage/cover_reg_top/49.spi_device_intr_test.3359235867 |
|
|
Mar 21 01:54:14 PM PDT 24 |
Mar 21 01:54:15 PM PDT 24 |
20024862 ps |
| T1005 |
/workspace/coverage/cover_reg_top/16.spi_device_intr_test.1586564719 |
|
|
Mar 21 01:53:42 PM PDT 24 |
Mar 21 01:53:43 PM PDT 24 |
13718941 ps |
| T1006 |
/workspace/coverage/cover_reg_top/11.spi_device_csr_rw.862195543 |
|
|
Mar 21 01:53:23 PM PDT 24 |
Mar 21 01:53:26 PM PDT 24 |
113611441 ps |
| T116 |
/workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2423749205 |
|
|
Mar 21 01:53:44 PM PDT 24 |
Mar 21 01:53:46 PM PDT 24 |
47201929 ps |
| T1007 |
/workspace/coverage/cover_reg_top/7.spi_device_intr_test.2436111387 |
|
|
Mar 21 01:53:13 PM PDT 24 |
Mar 21 01:53:15 PM PDT 24 |
14414451 ps |
| T1008 |
/workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1094693153 |
|
|
Mar 21 01:53:54 PM PDT 24 |
Mar 21 01:54:14 PM PDT 24 |
311664405 ps |