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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.95 98.31 94.34 98.61 89.36 97.00 95.84 98.22


Total test records in report: 1095
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T1009 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1285767926 Mar 21 01:54:03 PM PDT 24 Mar 21 01:54:04 PM PDT 24 19121469 ps
T1010 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1967450732 Mar 21 01:53:15 PM PDT 24 Mar 21 01:53:18 PM PDT 24 87041650 ps
T99 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2969121434 Mar 21 01:53:10 PM PDT 24 Mar 21 01:53:14 PM PDT 24 154493658 ps
T1011 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3591726836 Mar 21 01:53:03 PM PDT 24 Mar 21 01:53:19 PM PDT 24 1358068678 ps
T1012 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2942634693 Mar 21 01:54:05 PM PDT 24 Mar 21 01:54:05 PM PDT 24 12316116 ps
T117 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1493511600 Mar 21 01:54:01 PM PDT 24 Mar 21 01:54:04 PM PDT 24 34683469 ps
T1013 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3894961919 Mar 21 01:54:01 PM PDT 24 Mar 21 01:54:02 PM PDT 24 43007037 ps
T118 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3749457275 Mar 21 01:53:00 PM PDT 24 Mar 21 01:53:02 PM PDT 24 70165900 ps
T1014 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2893047904 Mar 21 01:54:18 PM PDT 24 Mar 21 01:54:19 PM PDT 24 13840301 ps
T1015 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.895132661 Mar 21 01:53:02 PM PDT 24 Mar 21 01:53:31 PM PDT 24 1216738459 ps
T96 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1744443975 Mar 21 01:53:47 PM PDT 24 Mar 21 01:53:50 PM PDT 24 256861125 ps
T1016 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3376909510 Mar 21 01:52:59 PM PDT 24 Mar 21 01:53:00 PM PDT 24 59002605 ps
T1017 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3773443013 Mar 21 01:52:53 PM PDT 24 Mar 21 01:52:58 PM PDT 24 1033804991 ps
T1018 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3818743968 Mar 21 01:53:12 PM PDT 24 Mar 21 01:53:14 PM PDT 24 219991748 ps
T80 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2320925912 Mar 21 01:53:01 PM PDT 24 Mar 21 01:53:02 PM PDT 24 94427730 ps
T1019 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.774626885 Mar 21 01:52:50 PM PDT 24 Mar 21 01:52:51 PM PDT 24 14179226 ps
T1020 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3419237762 Mar 21 01:53:00 PM PDT 24 Mar 21 01:53:09 PM PDT 24 425313855 ps
T119 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3486926377 Mar 21 01:53:48 PM PDT 24 Mar 21 01:53:50 PM PDT 24 131432547 ps
T1021 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3045767403 Mar 21 01:53:43 PM PDT 24 Mar 21 01:53:52 PM PDT 24 1860326546 ps
T81 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3464461628 Mar 21 01:52:54 PM PDT 24 Mar 21 01:52:55 PM PDT 24 87378048 ps
T1022 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.476657412 Mar 21 01:53:02 PM PDT 24 Mar 21 01:53:05 PM PDT 24 241804679 ps
T147 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3675371056 Mar 21 01:53:11 PM PDT 24 Mar 21 01:53:34 PM PDT 24 1036073914 ps
T1023 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2701161063 Mar 21 01:53:43 PM PDT 24 Mar 21 01:53:56 PM PDT 24 213044734 ps
T1024 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.732780748 Mar 21 01:54:05 PM PDT 24 Mar 21 01:54:09 PM PDT 24 139820010 ps
T1025 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2667349114 Mar 21 01:54:03 PM PDT 24 Mar 21 01:54:04 PM PDT 24 15058390 ps
T1026 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2145416351 Mar 21 01:54:05 PM PDT 24 Mar 21 01:54:06 PM PDT 24 23675502 ps
T1027 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.573199379 Mar 21 01:54:00 PM PDT 24 Mar 21 01:54:01 PM PDT 24 17144706 ps
T1028 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2753954662 Mar 21 01:54:02 PM PDT 24 Mar 21 01:54:03 PM PDT 24 137719558 ps
T1029 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2020283827 Mar 21 01:53:22 PM PDT 24 Mar 21 01:53:24 PM PDT 24 136047912 ps
T1030 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2594493972 Mar 21 01:53:00 PM PDT 24 Mar 21 01:53:16 PM PDT 24 14385747993 ps
T1031 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.392367531 Mar 21 01:54:17 PM PDT 24 Mar 21 01:54:18 PM PDT 24 25533421 ps
T1032 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3759235429 Mar 21 01:53:30 PM PDT 24 Mar 21 01:53:32 PM PDT 24 122249995 ps
T1033 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.825740180 Mar 21 01:54:02 PM PDT 24 Mar 21 01:54:03 PM PDT 24 22657144 ps
T1034 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1731081849 Mar 21 01:52:49 PM PDT 24 Mar 21 01:52:50 PM PDT 24 34327264 ps
T1035 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2475001465 Mar 21 01:52:55 PM PDT 24 Mar 21 01:52:59 PM PDT 24 707534850 ps
T1036 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2623089963 Mar 21 01:54:02 PM PDT 24 Mar 21 01:54:03 PM PDT 24 44736751 ps
T1037 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2334124714 Mar 21 01:53:03 PM PDT 24 Mar 21 01:53:07 PM PDT 24 407469271 ps
T1038 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2768444731 Mar 21 01:54:01 PM PDT 24 Mar 21 01:54:02 PM PDT 24 57617193 ps
T1039 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2484419343 Mar 21 01:52:59 PM PDT 24 Mar 21 01:53:20 PM PDT 24 354081927 ps
T1040 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3477470513 Mar 21 01:53:46 PM PDT 24 Mar 21 01:53:51 PM PDT 24 60683829 ps
T1041 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.1350713601 Mar 21 01:54:01 PM PDT 24 Mar 21 01:54:02 PM PDT 24 15479114 ps
T1042 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.29537903 Mar 21 01:53:02 PM PDT 24 Mar 21 01:53:04 PM PDT 24 204288450 ps
T1043 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2124101292 Mar 21 01:53:48 PM PDT 24 Mar 21 01:53:53 PM PDT 24 200959268 ps
T1044 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3364629314 Mar 21 01:54:04 PM PDT 24 Mar 21 01:54:04 PM PDT 24 123463493 ps
T1045 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.856998577 Mar 21 01:53:23 PM PDT 24 Mar 21 01:53:25 PM PDT 24 85554343 ps
T1046 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.542167759 Mar 21 01:53:21 PM PDT 24 Mar 21 01:53:24 PM PDT 24 76677589 ps
T1047 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1335362431 Mar 21 01:53:05 PM PDT 24 Mar 21 01:53:06 PM PDT 24 41316184 ps
T1048 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.407872804 Mar 21 01:52:50 PM PDT 24 Mar 21 01:52:59 PM PDT 24 321429816 ps
T1049 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.306852813 Mar 21 01:53:12 PM PDT 24 Mar 21 01:53:16 PM PDT 24 200011999 ps
T1050 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.539253866 Mar 21 01:53:10 PM PDT 24 Mar 21 01:53:15 PM PDT 24 323445068 ps
T1051 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3901624853 Mar 21 01:54:20 PM PDT 24 Mar 21 01:54:21 PM PDT 24 14274261 ps
T1052 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1288384384 Mar 21 01:53:47 PM PDT 24 Mar 21 01:53:49 PM PDT 24 160721781 ps
T1053 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2887597607 Mar 21 01:53:25 PM PDT 24 Mar 21 01:53:27 PM PDT 24 892652408 ps
T1054 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2170460768 Mar 21 01:53:11 PM PDT 24 Mar 21 01:53:13 PM PDT 24 128799483 ps
T1055 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3780181364 Mar 21 01:52:57 PM PDT 24 Mar 21 01:52:59 PM PDT 24 137323393 ps
T1056 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1860459018 Mar 21 01:53:12 PM PDT 24 Mar 21 01:53:16 PM PDT 24 43230613 ps
T1057 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3387489210 Mar 21 01:52:51 PM PDT 24 Mar 21 01:52:52 PM PDT 24 44609162 ps
T1058 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1499309160 Mar 21 01:53:25 PM PDT 24 Mar 21 01:53:29 PM PDT 24 69001731 ps
T1059 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.242088360 Mar 21 01:53:19 PM PDT 24 Mar 21 01:53:21 PM PDT 24 62319335 ps
T1060 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3242176805 Mar 21 01:54:00 PM PDT 24 Mar 21 01:54:01 PM PDT 24 31166573 ps
T1061 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3138949596 Mar 21 01:53:14 PM PDT 24 Mar 21 01:53:22 PM PDT 24 551308617 ps
T1062 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1487972499 Mar 21 01:53:29 PM PDT 24 Mar 21 01:53:31 PM PDT 24 47067490 ps
T1063 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.636087611 Mar 21 01:53:22 PM PDT 24 Mar 21 01:53:26 PM PDT 24 43008678 ps
T1064 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2174930175 Mar 21 01:54:04 PM PDT 24 Mar 21 01:54:05 PM PDT 24 53698106 ps
T1065 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3479958275 Mar 21 01:52:57 PM PDT 24 Mar 21 01:52:59 PM PDT 24 25578394 ps
T1066 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1330270726 Mar 21 01:53:43 PM PDT 24 Mar 21 01:53:44 PM PDT 24 16924991 ps
T1067 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1744560466 Mar 21 01:54:02 PM PDT 24 Mar 21 01:54:06 PM PDT 24 382471698 ps
T1068 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2588109616 Mar 21 01:53:48 PM PDT 24 Mar 21 01:54:04 PM PDT 24 1073930577 ps
T1069 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.715897539 Mar 21 01:53:12 PM PDT 24 Mar 21 01:53:14 PM PDT 24 140714681 ps
T1070 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3482136082 Mar 21 01:53:30 PM PDT 24 Mar 21 01:53:32 PM PDT 24 39828594 ps
T1071 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1490186554 Mar 21 01:53:19 PM PDT 24 Mar 21 01:53:23 PM PDT 24 99358096 ps
T1072 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2251032799 Mar 21 01:53:22 PM PDT 24 Mar 21 01:53:24 PM PDT 24 114536644 ps
T1073 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2873402841 Mar 21 01:52:56 PM PDT 24 Mar 21 01:52:58 PM PDT 24 255145854 ps
T1074 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3366901455 Mar 21 01:53:13 PM PDT 24 Mar 21 01:53:28 PM PDT 24 2111748029 ps
T1075 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2775621055 Mar 21 01:52:49 PM PDT 24 Mar 21 01:52:51 PM PDT 24 77067678 ps
T1076 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2948548503 Mar 21 01:54:18 PM PDT 24 Mar 21 01:54:19 PM PDT 24 15918439 ps
T1077 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.101809761 Mar 21 01:52:52 PM PDT 24 Mar 21 01:52:53 PM PDT 24 27239670 ps
T1078 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2945781684 Mar 21 01:54:02 PM PDT 24 Mar 21 01:54:03 PM PDT 24 15208010 ps
T1079 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1252240894 Mar 21 01:52:50 PM PDT 24 Mar 21 01:52:53 PM PDT 24 74754287 ps
T1080 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1607190045 Mar 21 01:52:52 PM PDT 24 Mar 21 01:52:53 PM PDT 24 19332347 ps
T1081 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2839758141 Mar 21 01:54:02 PM PDT 24 Mar 21 01:54:04 PM PDT 24 51949367 ps
T1082 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.945933662 Mar 21 01:53:00 PM PDT 24 Mar 21 01:53:02 PM PDT 24 61819729 ps
T1083 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3152321027 Mar 21 01:52:54 PM PDT 24 Mar 21 01:52:54 PM PDT 24 20477531 ps
T1084 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1618356206 Mar 21 01:53:03 PM PDT 24 Mar 21 01:53:05 PM PDT 24 20717067 ps
T1085 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.4055448048 Mar 21 01:53:03 PM PDT 24 Mar 21 01:53:06 PM PDT 24 38732413 ps
T1086 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1190882491 Mar 21 01:53:44 PM PDT 24 Mar 21 01:53:47 PM PDT 24 405135049 ps
T1087 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2522799997 Mar 21 01:54:02 PM PDT 24 Mar 21 01:54:04 PM PDT 24 151492678 ps
T1088 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.462240459 Mar 21 01:54:03 PM PDT 24 Mar 21 01:54:06 PM PDT 24 148297795 ps
T1089 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3831278294 Mar 21 01:52:59 PM PDT 24 Mar 21 01:53:41 PM PDT 24 26950689018 ps
T1090 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3793036901 Mar 21 01:54:02 PM PDT 24 Mar 21 01:54:06 PM PDT 24 42622822 ps
T1091 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3215519921 Mar 21 01:53:01 PM PDT 24 Mar 21 01:53:05 PM PDT 24 480964842 ps
T1092 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1785792135 Mar 21 01:53:13 PM PDT 24 Mar 21 01:53:15 PM PDT 24 105680092 ps
T1093 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2471994685 Mar 21 01:53:21 PM PDT 24 Mar 21 01:53:23 PM PDT 24 152445174 ps
T1094 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1816104310 Mar 21 01:53:49 PM PDT 24 Mar 21 01:53:51 PM PDT 24 282021142 ps
T1095 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2384384299 Mar 21 01:54:00 PM PDT 24 Mar 21 01:54:01 PM PDT 24 19472946 ps

Test location /workspace/coverage/default/39.spi_device_stress_all.1002203066
Short name T1
Test name
Test status
Simulation time 10723570466 ps
CPU time 78.78 seconds
Started Mar 21 02:21:55 PM PDT 24
Finished Mar 21 02:23:14 PM PDT 24
Peak memory 254216 kb
Host smart-5288649e-d017-4671-9fc9-bbee78b00a3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002203066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.1002203066
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.1258951017
Short name T26
Test name
Test status
Simulation time 234794053167 ps
CPU time 659.02 seconds
Started Mar 21 02:22:26 PM PDT 24
Finished Mar 21 02:33:25 PM PDT 24
Peak memory 263924 kb
Host smart-1a156ec5-2db4-4e29-9609-0dc472677212
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258951017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.1258951017
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3582571544
Short name T101
Test name
Test status
Simulation time 2064044620 ps
CPU time 23.31 seconds
Started Mar 21 01:53:45 PM PDT 24
Finished Mar 21 01:54:08 PM PDT 24
Peak memory 215412 kb
Host smart-bce6c6f2-7ba1-4ac4-9c5e-172903a3936a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582571544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.3582571544
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.2118408268
Short name T20
Test name
Test status
Simulation time 117851902902 ps
CPU time 265.41 seconds
Started Mar 21 02:21:19 PM PDT 24
Finished Mar 21 02:25:45 PM PDT 24
Peak memory 265444 kb
Host smart-8fd4cb39-7d4b-44ea-a118-9c35d608f4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118408268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.2118408268
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.1491973275
Short name T120
Test name
Test status
Simulation time 141353480620 ps
CPU time 257.12 seconds
Started Mar 21 02:20:24 PM PDT 24
Finished Mar 21 02:24:41 PM PDT 24
Peak memory 252904 kb
Host smart-0d2ab569-47da-45f5-bdc3-5016b3f357de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491973275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.1491973275
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.4052143192
Short name T446
Test name
Test status
Simulation time 17768526 ps
CPU time 0.74 seconds
Started Mar 21 02:15:53 PM PDT 24
Finished Mar 21 02:15:54 PM PDT 24
Peak memory 216080 kb
Host smart-f4e86e25-8c7a-4a18-8756-743496d9d4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052143192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.4052143192
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.1459476724
Short name T121
Test name
Test status
Simulation time 322059541117 ps
CPU time 571.5 seconds
Started Mar 21 02:21:54 PM PDT 24
Finished Mar 21 02:31:26 PM PDT 24
Peak memory 266608 kb
Host smart-14f70e60-3c65-4f83-8267-202f4ac8446d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459476724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.1459476724
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.156974384
Short name T17
Test name
Test status
Simulation time 53796976791 ps
CPU time 193.54 seconds
Started Mar 21 02:21:28 PM PDT 24
Finished Mar 21 02:24:42 PM PDT 24
Peak memory 265464 kb
Host smart-cbaf2e38-d1f3-4f18-8354-ee9da6a4af5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156974384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.156974384
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.3683829046
Short name T47
Test name
Test status
Simulation time 1038102534854 ps
CPU time 1908.9 seconds
Started Mar 21 02:21:16 PM PDT 24
Finished Mar 21 02:53:05 PM PDT 24
Peak memory 287012 kb
Host smart-6c98a98b-a9f4-4e80-abb6-9adc4651f6bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683829046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.3683829046
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.1084486450
Short name T3
Test name
Test status
Simulation time 25590029088 ps
CPU time 30.24 seconds
Started Mar 21 02:22:49 PM PDT 24
Finished Mar 21 02:23:20 PM PDT 24
Peak memory 240328 kb
Host smart-fa28df58-66e2-4eb3-b253-9669b84f22cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084486450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.1084486450
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.4102444336
Short name T181
Test name
Test status
Simulation time 684143272009 ps
CPU time 637.19 seconds
Started Mar 21 02:21:45 PM PDT 24
Finished Mar 21 02:32:22 PM PDT 24
Peak memory 267740 kb
Host smart-2e3cb3b7-1e30-40e2-9f59-4acfc1e0446d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102444336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.4102444336
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.3882852324
Short name T54
Test name
Test status
Simulation time 14326048 ps
CPU time 0.73 seconds
Started Mar 21 02:18:43 PM PDT 24
Finished Mar 21 02:18:45 PM PDT 24
Peak memory 204624 kb
Host smart-50588cc8-49e0-4f0c-9bb5-6084a8db227e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882852324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
3882852324
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2876443432
Short name T93
Test name
Test status
Simulation time 171355219 ps
CPU time 4.07 seconds
Started Mar 21 01:53:48 PM PDT 24
Finished Mar 21 01:53:52 PM PDT 24
Peak memory 215348 kb
Host smart-b1162a20-31da-4dfd-bdd0-8302b0a9d27b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876443432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
2876443432
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.3168733722
Short name T180
Test name
Test status
Simulation time 79253457199 ps
CPU time 490.22 seconds
Started Mar 21 02:22:07 PM PDT 24
Finished Mar 21 02:30:18 PM PDT 24
Peak memory 288508 kb
Host smart-a99f00d8-6291-4623-b8ec-08497e6ae0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168733722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.3168733722
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.608758159
Short name T11
Test name
Test status
Simulation time 33464345369 ps
CPU time 141.27 seconds
Started Mar 21 02:20:00 PM PDT 24
Finished Mar 21 02:22:22 PM PDT 24
Peak memory 256252 kb
Host smart-39ab57b4-d818-478f-8282-859a9a2a20f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608758159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle
.608758159
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.4138027692
Short name T113
Test name
Test status
Simulation time 1464274596 ps
CPU time 16.02 seconds
Started Mar 21 01:52:57 PM PDT 24
Finished Mar 21 01:53:13 PM PDT 24
Peak memory 206928 kb
Host smart-fe82c7e9-c2b1-4a45-a36d-7c45515cd2ae
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138027692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.4138027692
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.314335792
Short name T187
Test name
Test status
Simulation time 89986979276 ps
CPU time 668.08 seconds
Started Mar 21 02:20:52 PM PDT 24
Finished Mar 21 02:32:01 PM PDT 24
Peak memory 273172 kb
Host smart-ab44d917-58d3-40e3-b86e-c9864890e082
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314335792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stres
s_all.314335792
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.2630862963
Short name T164
Test name
Test status
Simulation time 51197264135 ps
CPU time 347.91 seconds
Started Mar 21 02:22:37 PM PDT 24
Finished Mar 21 02:28:25 PM PDT 24
Peak memory 257252 kb
Host smart-b4e883be-5524-4678-babf-266f49fbfa3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630862963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.2630862963
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.767291524
Short name T66
Test name
Test status
Simulation time 236256518 ps
CPU time 1.07 seconds
Started Mar 21 02:16:17 PM PDT 24
Finished Mar 21 02:16:18 PM PDT 24
Peak memory 234736 kb
Host smart-93f0e7f4-e637-42ff-aa38-9aa315f05735
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767291524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.767291524
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.947382777
Short name T244
Test name
Test status
Simulation time 77747662810 ps
CPU time 423.02 seconds
Started Mar 21 02:21:26 PM PDT 24
Finished Mar 21 02:28:30 PM PDT 24
Peak memory 268492 kb
Host smart-a3ed81ce-202d-4784-8daa-3d5295fcdfdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947382777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.947382777
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.1556939022
Short name T193
Test name
Test status
Simulation time 36385571218 ps
CPU time 175.19 seconds
Started Mar 21 02:18:52 PM PDT 24
Finished Mar 21 02:21:48 PM PDT 24
Peak memory 266276 kb
Host smart-bba150c9-f59c-4335-a2e4-ee4fea956618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556939022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.1556939022
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.3017368587
Short name T237
Test name
Test status
Simulation time 19793852806 ps
CPU time 213.75 seconds
Started Mar 21 02:21:43 PM PDT 24
Finished Mar 21 02:25:17 PM PDT 24
Peak memory 284804 kb
Host smart-5a55aa99-ba91-45a6-8402-cb3bb09fb9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017368587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.3017368587
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.3016685017
Short name T28
Test name
Test status
Simulation time 5639974012 ps
CPU time 52.04 seconds
Started Mar 21 02:22:23 PM PDT 24
Finished Mar 21 02:23:15 PM PDT 24
Peak memory 265192 kb
Host smart-1aacb111-a50c-4200-8dd9-b3c0e192c8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016685017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.3016685017
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.670349020
Short name T190
Test name
Test status
Simulation time 7286266724 ps
CPU time 34.96 seconds
Started Mar 21 02:19:44 PM PDT 24
Finished Mar 21 02:20:19 PM PDT 24
Peak memory 240816 kb
Host smart-00cfeb90-4223-4824-a0d7-c0a3bd97fe7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670349020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.670349020
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1405596603
Short name T92
Test name
Test status
Simulation time 3276103671 ps
CPU time 21.72 seconds
Started Mar 21 01:52:49 PM PDT 24
Finished Mar 21 01:53:11 PM PDT 24
Peak memory 215288 kb
Host smart-f1db388e-c144-49b9-b3ed-b58cd0e474fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405596603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.1405596603
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.315998558
Short name T10
Test name
Test status
Simulation time 8255224632 ps
CPU time 57.21 seconds
Started Mar 21 02:18:41 PM PDT 24
Finished Mar 21 02:19:39 PM PDT 24
Peak memory 267044 kb
Host smart-c7774054-8549-4e9a-bb1d-7b0a1871e1c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315998558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.315998558
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.1535351530
Short name T150
Test name
Test status
Simulation time 96926574413 ps
CPU time 599.21 seconds
Started Mar 21 02:19:54 PM PDT 24
Finished Mar 21 02:29:54 PM PDT 24
Peak memory 273564 kb
Host smart-7d381b79-3426-41f9-9de8-d56381e1341b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535351530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.1535351530
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.3332153926
Short name T479
Test name
Test status
Simulation time 5884809105 ps
CPU time 28.51 seconds
Started Mar 21 02:21:30 PM PDT 24
Finished Mar 21 02:21:59 PM PDT 24
Peak memory 231584 kb
Host smart-8e929816-e29e-46cb-88a0-679258d32b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332153926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.3332153926
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2707617400
Short name T100
Test name
Test status
Simulation time 204448728 ps
CPU time 4.9 seconds
Started Mar 21 01:53:13 PM PDT 24
Finished Mar 21 01:53:19 PM PDT 24
Peak memory 215404 kb
Host smart-5a245abf-ea86-4ce8-a4e9-0b8f318265a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707617400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.2
707617400
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1393988895
Short name T128
Test name
Test status
Simulation time 346189158 ps
CPU time 7.97 seconds
Started Mar 21 01:54:04 PM PDT 24
Finished Mar 21 01:54:12 PM PDT 24
Peak memory 215184 kb
Host smart-0f6bb3a3-6a93-43fa-ab4b-e3c6d9e279fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393988895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.1393988895
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.2058171646
Short name T145
Test name
Test status
Simulation time 2323951735 ps
CPU time 34.09 seconds
Started Mar 21 02:18:07 PM PDT 24
Finished Mar 21 02:18:41 PM PDT 24
Peak memory 249112 kb
Host smart-c6a976ff-48b4-4635-bf06-7f3cfe656882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058171646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.2058171646
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.2836878672
Short name T243
Test name
Test status
Simulation time 37619454394 ps
CPU time 139.91 seconds
Started Mar 21 02:18:53 PM PDT 24
Finished Mar 21 02:21:13 PM PDT 24
Peak memory 249092 kb
Host smart-425417cc-4ce9-48e0-98d5-6d78b92cd138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836878672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.2836878672
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.3721901524
Short name T260
Test name
Test status
Simulation time 18972891947 ps
CPU time 128.36 seconds
Started Mar 21 02:19:29 PM PDT 24
Finished Mar 21 02:21:38 PM PDT 24
Peak memory 265512 kb
Host smart-53968f57-f2b5-4565-8a5b-9c5a84a1f876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721901524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.3721901524
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.2685261982
Short name T70
Test name
Test status
Simulation time 227836087 ps
CPU time 9.93 seconds
Started Mar 21 02:22:38 PM PDT 24
Finished Mar 21 02:22:48 PM PDT 24
Peak memory 234360 kb
Host smart-fbeb3e20-7b18-45b0-b983-33315405d201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685261982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.2685261982
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.2071289213
Short name T25
Test name
Test status
Simulation time 5806207143 ps
CPU time 17.96 seconds
Started Mar 21 02:20:51 PM PDT 24
Finished Mar 21 02:21:09 PM PDT 24
Peak memory 240556 kb
Host smart-8157343d-6a7b-4f51-afb5-367ebc7ba5ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071289213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.2071289213
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.2784583345
Short name T233
Test name
Test status
Simulation time 43761742 ps
CPU time 2.83 seconds
Started Mar 21 02:16:14 PM PDT 24
Finished Mar 21 02:16:17 PM PDT 24
Peak memory 233324 kb
Host smart-750f6309-47f1-4e45-a9af-ec82ce1026b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784583345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.2784583345
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.778529567
Short name T222
Test name
Test status
Simulation time 113994988118 ps
CPU time 749.43 seconds
Started Mar 21 02:18:08 PM PDT 24
Finished Mar 21 02:30:37 PM PDT 24
Peak memory 267476 kb
Host smart-e80f8426-ea3c-44c3-a861-f13f0150b17e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778529567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.778529567
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.975937950
Short name T287
Test name
Test status
Simulation time 3647114342 ps
CPU time 4.78 seconds
Started Mar 21 02:18:09 PM PDT 24
Finished Mar 21 02:18:14 PM PDT 24
Peak memory 216144 kb
Host smart-4941eb1d-6f3e-41d7-b126-6a34e0bfac8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975937950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.975937950
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2969121434
Short name T99
Test name
Test status
Simulation time 154493658 ps
CPU time 3.69 seconds
Started Mar 21 01:53:10 PM PDT 24
Finished Mar 21 01:53:14 PM PDT 24
Peak memory 215288 kb
Host smart-954632e8-aff2-4109-abcd-9e308881a1d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969121434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.2
969121434
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2752218530
Short name T78
Test name
Test status
Simulation time 322829155 ps
CPU time 1.25 seconds
Started Mar 21 01:52:54 PM PDT 24
Finished Mar 21 01:52:55 PM PDT 24
Peak memory 206824 kb
Host smart-3f3da2f3-9493-4392-82cb-226855e69dfb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752218530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.2752218530
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.407872804
Short name T1048
Test name
Test status
Simulation time 321429816 ps
CPU time 8.95 seconds
Started Mar 21 01:52:50 PM PDT 24
Finished Mar 21 01:52:59 PM PDT 24
Peak memory 206936 kb
Host smart-6f5ff93c-7639-4a45-97a0-fac1845fc404
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407872804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_aliasing.407872804
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3712794312
Short name T112
Test name
Test status
Simulation time 750683773 ps
CPU time 12.02 seconds
Started Mar 21 01:52:57 PM PDT 24
Finished Mar 21 01:53:09 PM PDT 24
Peak memory 206844 kb
Host smart-6295587d-32e7-465b-9c42-277447e318cc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712794312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.3712794312
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2475001465
Short name T1035
Test name
Test status
Simulation time 707534850 ps
CPU time 3.89 seconds
Started Mar 21 01:52:55 PM PDT 24
Finished Mar 21 01:52:59 PM PDT 24
Peak memory 217632 kb
Host smart-d678653b-e109-40d5-afc2-6d989680c9b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475001465 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.2475001465
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1731081849
Short name T1034
Test name
Test status
Simulation time 34327264 ps
CPU time 1.25 seconds
Started Mar 21 01:52:49 PM PDT 24
Finished Mar 21 01:52:50 PM PDT 24
Peak memory 215020 kb
Host smart-004994d9-bdaf-4b21-be75-39b90b6b8c1f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731081849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.1
731081849
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1607190045
Short name T1080
Test name
Test status
Simulation time 19332347 ps
CPU time 0.74 seconds
Started Mar 21 01:52:52 PM PDT 24
Finished Mar 21 01:52:53 PM PDT 24
Peak memory 203504 kb
Host smart-99e19982-54f5-4b5c-a250-e52419eba8ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607190045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.1
607190045
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2775621055
Short name T1075
Test name
Test status
Simulation time 77067678 ps
CPU time 1.3 seconds
Started Mar 21 01:52:49 PM PDT 24
Finished Mar 21 01:52:51 PM PDT 24
Peak memory 215268 kb
Host smart-b576fc19-7ff8-461c-b52b-aee37280a7e3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775621055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.2775621055
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.101809761
Short name T1077
Test name
Test status
Simulation time 27239670 ps
CPU time 0.66 seconds
Started Mar 21 01:52:52 PM PDT 24
Finished Mar 21 01:52:53 PM PDT 24
Peak memory 203388 kb
Host smart-6908894e-8b63-4d67-bc44-94a253ab5b0e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101809761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem
_walk.101809761
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3479958275
Short name T1065
Test name
Test status
Simulation time 25578394 ps
CPU time 1.7 seconds
Started Mar 21 01:52:57 PM PDT 24
Finished Mar 21 01:52:59 PM PDT 24
Peak memory 215200 kb
Host smart-6374ca93-cd6a-41fb-b581-801c46052150
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479958275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.3479958275
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.281167133
Short name T57
Test name
Test status
Simulation time 573853819 ps
CPU time 2.38 seconds
Started Mar 21 01:52:52 PM PDT 24
Finished Mar 21 01:52:55 PM PDT 24
Peak memory 216280 kb
Host smart-111616a8-b58f-416d-9974-9943653299d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281167133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.281167133
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3388977929
Short name T982
Test name
Test status
Simulation time 6008154417 ps
CPU time 26.02 seconds
Started Mar 21 01:52:56 PM PDT 24
Finished Mar 21 01:53:22 PM PDT 24
Peak memory 206944 kb
Host smart-dab86e28-3e21-488a-b446-b7cac2374345
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388977929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.3388977929
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3464461628
Short name T81
Test name
Test status
Simulation time 87378048 ps
CPU time 1.35 seconds
Started Mar 21 01:52:54 PM PDT 24
Finished Mar 21 01:52:55 PM PDT 24
Peak memory 206892 kb
Host smart-909c0fc5-ab04-4199-8a07-cd70a9d00177
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464461628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.3464461628
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.248342263
Short name T131
Test name
Test status
Simulation time 334271036 ps
CPU time 4.01 seconds
Started Mar 21 01:52:50 PM PDT 24
Finished Mar 21 01:52:54 PM PDT 24
Peak memory 217064 kb
Host smart-e6f21c60-a8a3-4311-af74-321bb455a0b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248342263 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.248342263
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3780181364
Short name T1055
Test name
Test status
Simulation time 137323393 ps
CPU time 2.07 seconds
Started Mar 21 01:52:57 PM PDT 24
Finished Mar 21 01:52:59 PM PDT 24
Peak memory 215144 kb
Host smart-b34a1033-7026-4279-b59c-f9f3c097c1b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780181364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
780181364
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3387489210
Short name T1057
Test name
Test status
Simulation time 44609162 ps
CPU time 0.76 seconds
Started Mar 21 01:52:51 PM PDT 24
Finished Mar 21 01:52:52 PM PDT 24
Peak memory 203544 kb
Host smart-3bb6f520-38c0-42b2-977b-5593509d2c91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387489210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.3
387489210
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1138823079
Short name T992
Test name
Test status
Simulation time 48298616 ps
CPU time 1.91 seconds
Started Mar 21 01:52:52 PM PDT 24
Finished Mar 21 01:52:55 PM PDT 24
Peak memory 215200 kb
Host smart-7f331018-9be4-4940-8817-d0e82f394f71
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138823079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.1138823079
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3152321027
Short name T1083
Test name
Test status
Simulation time 20477531 ps
CPU time 0.66 seconds
Started Mar 21 01:52:54 PM PDT 24
Finished Mar 21 01:52:54 PM PDT 24
Peak memory 203396 kb
Host smart-5140ae4e-2a0d-4680-afac-4bf65dd8b458
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152321027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.3152321027
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2873402841
Short name T1073
Test name
Test status
Simulation time 255145854 ps
CPU time 1.8 seconds
Started Mar 21 01:52:56 PM PDT 24
Finished Mar 21 01:52:58 PM PDT 24
Peak memory 215120 kb
Host smart-d421acde-5d1d-40f0-a857-8331f9b117c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873402841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.2873402841
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3773443013
Short name T1017
Test name
Test status
Simulation time 1033804991 ps
CPU time 4.6 seconds
Started Mar 21 01:52:53 PM PDT 24
Finished Mar 21 01:52:58 PM PDT 24
Peak memory 215380 kb
Host smart-333df9da-b599-421e-b27d-dca8a654e243
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773443013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.3
773443013
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1629247610
Short name T58
Test name
Test status
Simulation time 436767833 ps
CPU time 11.97 seconds
Started Mar 21 01:52:58 PM PDT 24
Finished Mar 21 01:53:10 PM PDT 24
Peak memory 215140 kb
Host smart-525151de-ab2c-4af7-852e-a275e3f07179
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629247610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.1629247610
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1631611186
Short name T991
Test name
Test status
Simulation time 58869804 ps
CPU time 4.09 seconds
Started Mar 21 01:53:23 PM PDT 24
Finished Mar 21 01:53:28 PM PDT 24
Peak memory 217720 kb
Host smart-c22b4880-8910-4e40-b10e-e124eb033989
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631611186 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.1631611186
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3482136082
Short name T1070
Test name
Test status
Simulation time 39828594 ps
CPU time 2.44 seconds
Started Mar 21 01:53:30 PM PDT 24
Finished Mar 21 01:53:32 PM PDT 24
Peak memory 215152 kb
Host smart-6417b1df-d62f-4ead-bd5c-a7a05c64b070
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482136082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
3482136082
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2420352778
Short name T987
Test name
Test status
Simulation time 13655016 ps
CPU time 0.74 seconds
Started Mar 21 01:53:30 PM PDT 24
Finished Mar 21 01:53:31 PM PDT 24
Peak memory 203556 kb
Host smart-c829ed25-cb31-433e-be91-7761e1c88a23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420352778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
2420352778
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.636087611
Short name T1063
Test name
Test status
Simulation time 43008678 ps
CPU time 2.62 seconds
Started Mar 21 01:53:22 PM PDT 24
Finished Mar 21 01:53:26 PM PDT 24
Peak memory 215180 kb
Host smart-bdee6469-37fd-4652-80ac-405da3aefe3b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636087611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.s
pi_device_same_csr_outstanding.636087611
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3603803133
Short name T94
Test name
Test status
Simulation time 699404428 ps
CPU time 4.29 seconds
Started Mar 21 01:53:20 PM PDT 24
Finished Mar 21 01:53:24 PM PDT 24
Peak memory 215284 kb
Host smart-7899c1fd-bb33-4271-9ef6-d8b57153251f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603803133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
3603803133
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1552008081
Short name T148
Test name
Test status
Simulation time 313854831 ps
CPU time 18.44 seconds
Started Mar 21 01:53:27 PM PDT 24
Finished Mar 21 01:53:45 PM PDT 24
Peak memory 215196 kb
Host smart-195c7a23-4be2-4452-be07-75414adb46d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552008081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.1552008081
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.856998577
Short name T1045
Test name
Test status
Simulation time 85554343 ps
CPU time 1.72 seconds
Started Mar 21 01:53:23 PM PDT 24
Finished Mar 21 01:53:25 PM PDT 24
Peak memory 215152 kb
Host smart-0770e2fb-c800-416a-85bc-583ef9f5eb00
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856998577 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.856998577
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.862195543
Short name T1006
Test name
Test status
Simulation time 113611441 ps
CPU time 2 seconds
Started Mar 21 01:53:23 PM PDT 24
Finished Mar 21 01:53:26 PM PDT 24
Peak memory 215120 kb
Host smart-b70f3b16-a661-48b8-8660-e7e323bda7ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862195543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.862195543
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.211111321
Short name T969
Test name
Test status
Simulation time 14800246 ps
CPU time 0.73 seconds
Started Mar 21 01:53:20 PM PDT 24
Finished Mar 21 01:53:21 PM PDT 24
Peak memory 203592 kb
Host smart-2f7f56a6-d96f-4a3f-ace1-6787bb817a37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211111321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.211111321
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2471994685
Short name T1093
Test name
Test status
Simulation time 152445174 ps
CPU time 1.91 seconds
Started Mar 21 01:53:21 PM PDT 24
Finished Mar 21 01:53:23 PM PDT 24
Peak memory 215108 kb
Host smart-460d6671-294b-40e7-9a64-1eff25bffcdf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471994685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.2471994685
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2251032799
Short name T1072
Test name
Test status
Simulation time 114536644 ps
CPU time 2.06 seconds
Started Mar 21 01:53:22 PM PDT 24
Finished Mar 21 01:53:24 PM PDT 24
Peak memory 215288 kb
Host smart-f4ee0c65-7e82-4a96-a3cd-2fc7571fcf31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251032799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
2251032799
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3069320519
Short name T130
Test name
Test status
Simulation time 1423048914 ps
CPU time 16.42 seconds
Started Mar 21 01:53:21 PM PDT 24
Finished Mar 21 01:53:37 PM PDT 24
Peak memory 215220 kb
Host smart-a179663d-a24a-4b3d-80d4-b8e98a94b202
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069320519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.3069320519
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1919354446
Short name T988
Test name
Test status
Simulation time 56728621 ps
CPU time 1.76 seconds
Started Mar 21 01:53:44 PM PDT 24
Finished Mar 21 01:53:46 PM PDT 24
Peak memory 215208 kb
Host smart-0bf15688-88ed-410d-87ad-ebe619eef154
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919354446 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.1919354446
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.402198056
Short name T108
Test name
Test status
Simulation time 17771936 ps
CPU time 1.18 seconds
Started Mar 21 01:53:46 PM PDT 24
Finished Mar 21 01:53:47 PM PDT 24
Peak memory 215176 kb
Host smart-43acd300-9855-4b6d-a933-faf2ac3fc02f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402198056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.402198056
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1487972499
Short name T1062
Test name
Test status
Simulation time 47067490 ps
CPU time 0.74 seconds
Started Mar 21 01:53:29 PM PDT 24
Finished Mar 21 01:53:31 PM PDT 24
Peak memory 203616 kb
Host smart-355a82c6-4092-4e0e-9e47-e0ff1b4f06d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487972499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
1487972499
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3477470513
Short name T1040
Test name
Test status
Simulation time 60683829 ps
CPU time 3.69 seconds
Started Mar 21 01:53:46 PM PDT 24
Finished Mar 21 01:53:51 PM PDT 24
Peak memory 215116 kb
Host smart-36567c3e-e2ea-4095-a470-2fe29cd7f5ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477470513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.3477470513
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.542167759
Short name T1046
Test name
Test status
Simulation time 76677589 ps
CPU time 2.39 seconds
Started Mar 21 01:53:21 PM PDT 24
Finished Mar 21 01:53:24 PM PDT 24
Peak memory 215420 kb
Host smart-54a16fa9-0c7a-4f85-b46b-413a1318d38b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542167759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.542167759
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3527662241
Short name T146
Test name
Test status
Simulation time 630707851 ps
CPU time 15.24 seconds
Started Mar 21 01:53:23 PM PDT 24
Finished Mar 21 01:53:39 PM PDT 24
Peak memory 216772 kb
Host smart-18ad7f93-bc29-44dd-8c58-08b542d3f317
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527662241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.3527662241
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1816104310
Short name T1094
Test name
Test status
Simulation time 282021142 ps
CPU time 1.72 seconds
Started Mar 21 01:53:49 PM PDT 24
Finished Mar 21 01:53:51 PM PDT 24
Peak memory 215260 kb
Host smart-e3491d33-3d59-4cb4-981d-1d825b1d0a7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816104310 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.1816104310
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1288384384
Short name T1052
Test name
Test status
Simulation time 160721781 ps
CPU time 2.11 seconds
Started Mar 21 01:53:47 PM PDT 24
Finished Mar 21 01:53:49 PM PDT 24
Peak memory 215092 kb
Host smart-30edf601-25c5-415f-b96c-be7f9090ea41
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288384384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
1288384384
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1330270726
Short name T1066
Test name
Test status
Simulation time 16924991 ps
CPU time 0.72 seconds
Started Mar 21 01:53:43 PM PDT 24
Finished Mar 21 01:53:44 PM PDT 24
Peak memory 203624 kb
Host smart-4b797c44-4636-4637-8cb8-246f95de2cb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330270726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
1330270726
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.946819479
Short name T966
Test name
Test status
Simulation time 132249956 ps
CPU time 1.99 seconds
Started Mar 21 01:53:47 PM PDT 24
Finished Mar 21 01:53:49 PM PDT 24
Peak memory 215124 kb
Host smart-a3657723-ea6d-4bd2-8aee-1e9a953fc2d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946819479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.s
pi_device_same_csr_outstanding.946819479
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1849579461
Short name T1001
Test name
Test status
Simulation time 160351688 ps
CPU time 2.87 seconds
Started Mar 21 01:53:42 PM PDT 24
Finished Mar 21 01:53:46 PM PDT 24
Peak memory 216228 kb
Host smart-d4487dba-bebc-4cae-bd81-042736eef23e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849579461 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.1849579461
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3486926377
Short name T119
Test name
Test status
Simulation time 131432547 ps
CPU time 1.26 seconds
Started Mar 21 01:53:48 PM PDT 24
Finished Mar 21 01:53:50 PM PDT 24
Peak memory 206952 kb
Host smart-47487d98-c6a9-48fb-b492-761e4f7477c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486926377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
3486926377
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.159748872
Short name T970
Test name
Test status
Simulation time 14007864 ps
CPU time 0.7 seconds
Started Mar 21 01:53:44 PM PDT 24
Finished Mar 21 01:53:44 PM PDT 24
Peak memory 203568 kb
Host smart-7cd384f7-7efd-4fb7-8fde-8db8977abb33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159748872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.159748872
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.4164596896
Short name T986
Test name
Test status
Simulation time 41657873 ps
CPU time 2.79 seconds
Started Mar 21 01:53:48 PM PDT 24
Finished Mar 21 01:53:51 PM PDT 24
Peak memory 215232 kb
Host smart-d3f99d32-5c98-4e0e-a7b1-003a29653d3c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164596896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.4164596896
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2124101292
Short name T1043
Test name
Test status
Simulation time 200959268 ps
CPU time 4.27 seconds
Started Mar 21 01:53:48 PM PDT 24
Finished Mar 21 01:53:53 PM PDT 24
Peak memory 215380 kb
Host smart-1f222b6e-84b5-4e10-ae90-687a3618419c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124101292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
2124101292
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3045767403
Short name T1021
Test name
Test status
Simulation time 1860326546 ps
CPU time 8.72 seconds
Started Mar 21 01:53:43 PM PDT 24
Finished Mar 21 01:53:52 PM PDT 24
Peak memory 215196 kb
Host smart-26a560ef-d598-457e-addc-ab1fa749408d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045767403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.3045767403
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3413397746
Short name T998
Test name
Test status
Simulation time 281465814 ps
CPU time 3.85 seconds
Started Mar 21 01:53:45 PM PDT 24
Finished Mar 21 01:53:49 PM PDT 24
Peak memory 216744 kb
Host smart-a94095ed-6cb7-4044-81f8-555272ab56f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413397746 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.3413397746
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.526309133
Short name T114
Test name
Test status
Simulation time 390709126 ps
CPU time 2.39 seconds
Started Mar 21 01:53:44 PM PDT 24
Finished Mar 21 01:53:47 PM PDT 24
Peak memory 215148 kb
Host smart-47b72d0a-7a8c-4f23-85c5-1ff39989f000
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526309133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.526309133
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.235144879
Short name T974
Test name
Test status
Simulation time 18256437 ps
CPU time 0.69 seconds
Started Mar 21 01:53:45 PM PDT 24
Finished Mar 21 01:53:46 PM PDT 24
Peak memory 203548 kb
Host smart-f0017d86-9222-43fa-81f4-02b9e38034e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235144879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.235144879
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1190882491
Short name T1086
Test name
Test status
Simulation time 405135049 ps
CPU time 3.06 seconds
Started Mar 21 01:53:44 PM PDT 24
Finished Mar 21 01:53:47 PM PDT 24
Peak memory 215224 kb
Host smart-74223c46-c8da-43d2-9264-cfb616650ccd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190882491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.1190882491
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1582354076
Short name T97
Test name
Test status
Simulation time 42401706 ps
CPU time 3.19 seconds
Started Mar 21 01:53:46 PM PDT 24
Finished Mar 21 01:53:49 PM PDT 24
Peak memory 215384 kb
Host smart-1257fd9b-0731-4576-b084-23e90a152b23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582354076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
1582354076
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2701161063
Short name T1023
Test name
Test status
Simulation time 213044734 ps
CPU time 13.04 seconds
Started Mar 21 01:53:43 PM PDT 24
Finished Mar 21 01:53:56 PM PDT 24
Peak memory 215236 kb
Host smart-bfb2e740-c3aa-4487-942a-8ecd37204dc5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701161063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.2701161063
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.709244743
Short name T98
Test name
Test status
Simulation time 151614339 ps
CPU time 2.94 seconds
Started Mar 21 01:54:03 PM PDT 24
Finished Mar 21 01:54:06 PM PDT 24
Peak memory 216532 kb
Host smart-e1db10c1-bd57-4cc9-8f97-23d443652f3a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709244743 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.709244743
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2423749205
Short name T116
Test name
Test status
Simulation time 47201929 ps
CPU time 1.93 seconds
Started Mar 21 01:53:44 PM PDT 24
Finished Mar 21 01:53:46 PM PDT 24
Peak memory 215168 kb
Host smart-fdbb053b-aeaa-481c-b3a4-b46ce7a11c00
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423749205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
2423749205
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1586564719
Short name T1005
Test name
Test status
Simulation time 13718941 ps
CPU time 0.69 seconds
Started Mar 21 01:53:42 PM PDT 24
Finished Mar 21 01:53:43 PM PDT 24
Peak memory 203496 kb
Host smart-63d3f8eb-4939-4705-842b-98add4ea28b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586564719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
1586564719
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3872936722
Short name T999
Test name
Test status
Simulation time 221910348 ps
CPU time 3.86 seconds
Started Mar 21 01:53:45 PM PDT 24
Finished Mar 21 01:53:49 PM PDT 24
Peak memory 215220 kb
Host smart-9f7131af-0c1a-45d7-b639-3820be8d400b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872936722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.3872936722
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1744443975
Short name T96
Test name
Test status
Simulation time 256861125 ps
CPU time 2.15 seconds
Started Mar 21 01:53:47 PM PDT 24
Finished Mar 21 01:53:50 PM PDT 24
Peak memory 215260 kb
Host smart-6779ff68-f6af-410d-8a79-4a9910486539
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744443975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
1744443975
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2588109616
Short name T1068
Test name
Test status
Simulation time 1073930577 ps
CPU time 15.74 seconds
Started Mar 21 01:53:48 PM PDT 24
Finished Mar 21 01:54:04 PM PDT 24
Peak memory 215372 kb
Host smart-497b3255-b7f5-43b6-b00b-d851bad5ef81
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588109616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.2588109616
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.825740180
Short name T1033
Test name
Test status
Simulation time 22657144 ps
CPU time 1.54 seconds
Started Mar 21 01:54:02 PM PDT 24
Finished Mar 21 01:54:03 PM PDT 24
Peak memory 215264 kb
Host smart-15cc954f-747f-4df9-a54a-624394664515
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825740180 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.825740180
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2522799997
Short name T1087
Test name
Test status
Simulation time 151492678 ps
CPU time 2.1 seconds
Started Mar 21 01:54:02 PM PDT 24
Finished Mar 21 01:54:04 PM PDT 24
Peak memory 215152 kb
Host smart-d77ad335-97b7-4985-8baf-cf2413ada036
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522799997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
2522799997
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1285767926
Short name T1009
Test name
Test status
Simulation time 19121469 ps
CPU time 0.74 seconds
Started Mar 21 01:54:03 PM PDT 24
Finished Mar 21 01:54:04 PM PDT 24
Peak memory 203564 kb
Host smart-5fc15a42-c4fb-4173-ab52-d11a8a071439
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285767926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
1285767926
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1744560466
Short name T1067
Test name
Test status
Simulation time 382471698 ps
CPU time 3.91 seconds
Started Mar 21 01:54:02 PM PDT 24
Finished Mar 21 01:54:06 PM PDT 24
Peak memory 215240 kb
Host smart-9b7bd68e-0816-454f-b202-ed876b914fb1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744560466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.1744560466
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.199679620
Short name T95
Test name
Test status
Simulation time 555751086 ps
CPU time 3.07 seconds
Started Mar 21 01:53:59 PM PDT 24
Finished Mar 21 01:54:02 PM PDT 24
Peak memory 215376 kb
Host smart-97a79fbb-c571-495a-9476-6491ca51a1af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199679620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.199679620
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1094693153
Short name T1008
Test name
Test status
Simulation time 311664405 ps
CPU time 19.37 seconds
Started Mar 21 01:53:54 PM PDT 24
Finished Mar 21 01:54:14 PM PDT 24
Peak memory 215644 kb
Host smart-56556e86-a34b-4202-b057-136dfaea5d2c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094693153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.1094693153
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2839758141
Short name T1081
Test name
Test status
Simulation time 51949367 ps
CPU time 1.74 seconds
Started Mar 21 01:54:02 PM PDT 24
Finished Mar 21 01:54:04 PM PDT 24
Peak memory 215204 kb
Host smart-12f60045-040e-45f3-bce2-416f2ecae343
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839758141 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.2839758141
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1493511600
Short name T117
Test name
Test status
Simulation time 34683469 ps
CPU time 2.39 seconds
Started Mar 21 01:54:01 PM PDT 24
Finished Mar 21 01:54:04 PM PDT 24
Peak memory 215068 kb
Host smart-c1483af1-81e1-4728-b30c-5755344a6837
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493511600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
1493511600
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.573199379
Short name T1027
Test name
Test status
Simulation time 17144706 ps
CPU time 0.74 seconds
Started Mar 21 01:54:00 PM PDT 24
Finished Mar 21 01:54:01 PM PDT 24
Peak memory 203584 kb
Host smart-e89e5578-7880-4205-9aa4-f73b842ac5e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573199379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.573199379
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.78981180
Short name T127
Test name
Test status
Simulation time 450588671 ps
CPU time 2.97 seconds
Started Mar 21 01:54:03 PM PDT 24
Finished Mar 21 01:54:06 PM PDT 24
Peak memory 215180 kb
Host smart-f954abb9-bf14-4ebc-883b-6dffc3fa515e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78981180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sp
i_device_same_csr_outstanding.78981180
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3120753418
Short name T91
Test name
Test status
Simulation time 230256671 ps
CPU time 3.09 seconds
Started Mar 21 01:54:01 PM PDT 24
Finished Mar 21 01:54:04 PM PDT 24
Peak memory 215340 kb
Host smart-8546f970-d6ef-467f-b655-2d24e86826de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120753418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
3120753418
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2709249654
Short name T129
Test name
Test status
Simulation time 1432376950 ps
CPU time 8.89 seconds
Started Mar 21 01:54:04 PM PDT 24
Finished Mar 21 01:54:13 PM PDT 24
Peak memory 215176 kb
Host smart-7fcaa471-cc47-4208-98e9-21536f700ba9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709249654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.2709249654
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3793036901
Short name T1090
Test name
Test status
Simulation time 42622822 ps
CPU time 3.24 seconds
Started Mar 21 01:54:02 PM PDT 24
Finished Mar 21 01:54:06 PM PDT 24
Peak memory 217536 kb
Host smart-6ae65bc4-cc70-4dd8-9629-d5a8471ee14c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793036901 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.3793036901
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2143457566
Short name T111
Test name
Test status
Simulation time 209233513 ps
CPU time 1.39 seconds
Started Mar 21 01:54:03 PM PDT 24
Finished Mar 21 01:54:05 PM PDT 24
Peak memory 207132 kb
Host smart-010c8714-7a12-4bb0-a73c-979d9bb5843c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143457566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
2143457566
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2768444731
Short name T1038
Test name
Test status
Simulation time 57617193 ps
CPU time 0.82 seconds
Started Mar 21 01:54:01 PM PDT 24
Finished Mar 21 01:54:02 PM PDT 24
Peak memory 203536 kb
Host smart-77147254-753b-4d4a-af35-1cb2900e7274
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768444731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
2768444731
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.462240459
Short name T1088
Test name
Test status
Simulation time 148297795 ps
CPU time 2.97 seconds
Started Mar 21 01:54:03 PM PDT 24
Finished Mar 21 01:54:06 PM PDT 24
Peak memory 215244 kb
Host smart-0fe6c6ef-083c-43e1-9079-6e207d7f9569
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462240459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.s
pi_device_same_csr_outstanding.462240459
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.732780748
Short name T1024
Test name
Test status
Simulation time 139820010 ps
CPU time 3.8 seconds
Started Mar 21 01:54:05 PM PDT 24
Finished Mar 21 01:54:09 PM PDT 24
Peak memory 215284 kb
Host smart-98e96ab2-bc69-415d-8194-74c15aef0a75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732780748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.732780748
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3419237762
Short name T1020
Test name
Test status
Simulation time 425313855 ps
CPU time 9.28 seconds
Started Mar 21 01:53:00 PM PDT 24
Finished Mar 21 01:53:09 PM PDT 24
Peak memory 215128 kb
Host smart-30325df6-0712-4ddd-bfbf-f45515898ae4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419237762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.3419237762
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3831278294
Short name T1089
Test name
Test status
Simulation time 26950689018 ps
CPU time 41.19 seconds
Started Mar 21 01:52:59 PM PDT 24
Finished Mar 21 01:53:41 PM PDT 24
Peak memory 215216 kb
Host smart-595920db-28bc-4439-a57b-d3c7919399e2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831278294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.3831278294
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1268136499
Short name T79
Test name
Test status
Simulation time 101837269 ps
CPU time 1.41 seconds
Started Mar 21 01:53:00 PM PDT 24
Finished Mar 21 01:53:02 PM PDT 24
Peak memory 206960 kb
Host smart-fca67c95-2bbb-4066-b0ec-bccad1892a67
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268136499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.1268136499
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1438202257
Short name T87
Test name
Test status
Simulation time 306518900 ps
CPU time 2.68 seconds
Started Mar 21 01:52:59 PM PDT 24
Finished Mar 21 01:53:02 PM PDT 24
Peak memory 216604 kb
Host smart-c9f92fb5-8e25-4397-aba9-f240bfd5663f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438202257 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.1438202257
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.4055448048
Short name T1085
Test name
Test status
Simulation time 38732413 ps
CPU time 2.39 seconds
Started Mar 21 01:53:03 PM PDT 24
Finished Mar 21 01:53:06 PM PDT 24
Peak memory 215180 kb
Host smart-0ece9677-ff94-41f9-beb9-f8fcb9c24eb9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055448048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.4
055448048
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.774626885
Short name T1019
Test name
Test status
Simulation time 14179226 ps
CPU time 0.72 seconds
Started Mar 21 01:52:50 PM PDT 24
Finished Mar 21 01:52:51 PM PDT 24
Peak memory 203668 kb
Host smart-24b616d1-7b82-4a2b-9d00-8f6356f653fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774626885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.774626885
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.29537903
Short name T1042
Test name
Test status
Simulation time 204288450 ps
CPU time 1.74 seconds
Started Mar 21 01:53:02 PM PDT 24
Finished Mar 21 01:53:04 PM PDT 24
Peak memory 215280 kb
Host smart-898f52ad-20d4-4596-be6d-6fd5e78c807d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29537903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi
_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_d
evice_mem_partial_access.29537903
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.4119206266
Short name T979
Test name
Test status
Simulation time 13599528 ps
CPU time 0.67 seconds
Started Mar 21 01:52:49 PM PDT 24
Finished Mar 21 01:52:49 PM PDT 24
Peak memory 203424 kb
Host smart-d9029940-e6d0-462c-bb19-abeca8b83352
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119206266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.4119206266
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.623355332
Short name T983
Test name
Test status
Simulation time 68626410 ps
CPU time 2.62 seconds
Started Mar 21 01:53:02 PM PDT 24
Finished Mar 21 01:53:05 PM PDT 24
Peak memory 215116 kb
Host smart-bc60e0b5-47be-47f7-b7db-4c3c94f9cb0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623355332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sp
i_device_same_csr_outstanding.623355332
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1252240894
Short name T1079
Test name
Test status
Simulation time 74754287 ps
CPU time 2.4 seconds
Started Mar 21 01:52:50 PM PDT 24
Finished Mar 21 01:52:53 PM PDT 24
Peak memory 207120 kb
Host smart-546495b9-b8da-4da4-92ff-643ea0be89ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252240894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.1
252240894
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3470681984
Short name T103
Test name
Test status
Simulation time 304051826 ps
CPU time 8.29 seconds
Started Mar 21 01:52:51 PM PDT 24
Finished Mar 21 01:53:00 PM PDT 24
Peak memory 215216 kb
Host smart-f5b8c186-a73c-4749-b2f3-011d229fa89b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470681984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.3470681984
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2753954662
Short name T1028
Test name
Test status
Simulation time 137719558 ps
CPU time 0.79 seconds
Started Mar 21 01:54:02 PM PDT 24
Finished Mar 21 01:54:03 PM PDT 24
Peak memory 203604 kb
Host smart-9b471dbf-a800-40cc-a026-e588b215dda9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753954662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
2753954662
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.484429186
Short name T975
Test name
Test status
Simulation time 24607210 ps
CPU time 0.72 seconds
Started Mar 21 01:54:04 PM PDT 24
Finished Mar 21 01:54:04 PM PDT 24
Peak memory 203580 kb
Host smart-3727f422-13de-4cca-94b0-12421f465806
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484429186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.484429186
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2174930175
Short name T1064
Test name
Test status
Simulation time 53698106 ps
CPU time 0.75 seconds
Started Mar 21 01:54:04 PM PDT 24
Finished Mar 21 01:54:05 PM PDT 24
Peak memory 203588 kb
Host smart-d9e8636d-2e69-4d2d-8acb-e743771a1cfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174930175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
2174930175
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2308133038
Short name T995
Test name
Test status
Simulation time 32233649 ps
CPU time 0.76 seconds
Started Mar 21 01:54:07 PM PDT 24
Finished Mar 21 01:54:08 PM PDT 24
Peak memory 203604 kb
Host smart-16127aa1-8739-4c16-bdbe-739c9729ef80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308133038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
2308133038
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1800233270
Short name T1002
Test name
Test status
Simulation time 48674362 ps
CPU time 0.76 seconds
Started Mar 21 01:54:01 PM PDT 24
Finished Mar 21 01:54:02 PM PDT 24
Peak memory 203632 kb
Host smart-e7ad739e-8cc1-45a5-95a9-cf2d662f1896
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800233270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
1800233270
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2667349114
Short name T1025
Test name
Test status
Simulation time 15058390 ps
CPU time 0.78 seconds
Started Mar 21 01:54:03 PM PDT 24
Finished Mar 21 01:54:04 PM PDT 24
Peak memory 203556 kb
Host smart-97073b19-dc30-464c-a59b-438e0279d1ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667349114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
2667349114
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.278552529
Short name T996
Test name
Test status
Simulation time 28413712 ps
CPU time 0.81 seconds
Started Mar 21 01:54:02 PM PDT 24
Finished Mar 21 01:54:03 PM PDT 24
Peak memory 203548 kb
Host smart-a63dcef3-afcd-471b-99d7-3ba2fefcd9f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278552529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.278552529
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3364629314
Short name T1044
Test name
Test status
Simulation time 123463493 ps
CPU time 0.72 seconds
Started Mar 21 01:54:04 PM PDT 24
Finished Mar 21 01:54:04 PM PDT 24
Peak memory 203584 kb
Host smart-4ab32e2a-bb50-495b-b350-8fdab8396132
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364629314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
3364629314
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2945781684
Short name T1078
Test name
Test status
Simulation time 15208010 ps
CPU time 0.77 seconds
Started Mar 21 01:54:02 PM PDT 24
Finished Mar 21 01:54:03 PM PDT 24
Peak memory 203592 kb
Host smart-3291be94-d047-4d2e-94af-f53e7f6c2e8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945781684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
2945781684
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2384384299
Short name T1095
Test name
Test status
Simulation time 19472946 ps
CPU time 0.69 seconds
Started Mar 21 01:54:00 PM PDT 24
Finished Mar 21 01:54:01 PM PDT 24
Peak memory 203636 kb
Host smart-5d6cbb7f-2b3c-4c7a-b208-4a612daef382
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384384299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
2384384299
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2594493972
Short name T1030
Test name
Test status
Simulation time 14385747993 ps
CPU time 16.19 seconds
Started Mar 21 01:53:00 PM PDT 24
Finished Mar 21 01:53:16 PM PDT 24
Peak memory 215116 kb
Host smart-e576516d-1ca9-4ffa-aff7-23791b5ff152
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594493972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.2594493972
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.895132661
Short name T1015
Test name
Test status
Simulation time 1216738459 ps
CPU time 27.71 seconds
Started Mar 21 01:53:02 PM PDT 24
Finished Mar 21 01:53:31 PM PDT 24
Peak memory 206932 kb
Host smart-4b8430f1-c219-45a5-9b4c-ca9418643165
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895132661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_bit_bash.895132661
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2320925912
Short name T80
Test name
Test status
Simulation time 94427730 ps
CPU time 1.4 seconds
Started Mar 21 01:53:01 PM PDT 24
Finished Mar 21 01:53:02 PM PDT 24
Peak memory 216104 kb
Host smart-e53a6dda-d8ee-4e16-83b5-7dd87d5bf08e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320925912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.2320925912
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.945933662
Short name T1082
Test name
Test status
Simulation time 61819729 ps
CPU time 1.75 seconds
Started Mar 21 01:53:00 PM PDT 24
Finished Mar 21 01:53:02 PM PDT 24
Peak memory 216296 kb
Host smart-be6a0d13-374c-4290-8865-f40def536a80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945933662 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.945933662
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3749457275
Short name T118
Test name
Test status
Simulation time 70165900 ps
CPU time 1.35 seconds
Started Mar 21 01:53:00 PM PDT 24
Finished Mar 21 01:53:02 PM PDT 24
Peak memory 206904 kb
Host smart-757dee83-9c3d-4793-aebb-fb0097cb1b0d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749457275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.3
749457275
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1859035590
Short name T997
Test name
Test status
Simulation time 38407883 ps
CPU time 0.72 seconds
Started Mar 21 01:53:02 PM PDT 24
Finished Mar 21 01:53:03 PM PDT 24
Peak memory 203584 kb
Host smart-d96d269b-7c7b-4a66-8a84-734ec830b54d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859035590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.1
859035590
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1618356206
Short name T1084
Test name
Test status
Simulation time 20717067 ps
CPU time 1.25 seconds
Started Mar 21 01:53:03 PM PDT 24
Finished Mar 21 01:53:05 PM PDT 24
Peak memory 215188 kb
Host smart-efc208bf-c090-4d9e-bdee-581708fe8796
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618356206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.1618356206
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2224261558
Short name T1000
Test name
Test status
Simulation time 160790219 ps
CPU time 0.67 seconds
Started Mar 21 01:53:05 PM PDT 24
Finished Mar 21 01:53:06 PM PDT 24
Peak memory 203384 kb
Host smart-34cd58f9-89b4-40d9-a082-c4e7fd00b37a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224261558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.2224261558
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1167295756
Short name T993
Test name
Test status
Simulation time 597762155 ps
CPU time 3.83 seconds
Started Mar 21 01:53:04 PM PDT 24
Finished Mar 21 01:53:08 PM PDT 24
Peak memory 215184 kb
Host smart-13b16500-1066-45a2-a908-35a1469d7fac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167295756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.1167295756
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.983391837
Short name T90
Test name
Test status
Simulation time 207084730 ps
CPU time 3.66 seconds
Started Mar 21 01:53:01 PM PDT 24
Finished Mar 21 01:53:04 PM PDT 24
Peak memory 215460 kb
Host smart-365f7655-ec3c-46de-b020-c59ff27fba2f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983391837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.983391837
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.196200044
Short name T89
Test name
Test status
Simulation time 3106331923 ps
CPU time 20.58 seconds
Started Mar 21 01:53:02 PM PDT 24
Finished Mar 21 01:53:23 PM PDT 24
Peak memory 215828 kb
Host smart-1e0ac84a-7d87-4992-af6d-69f810e7293d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196200044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_
tl_intg_err.196200044
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3894961919
Short name T1013
Test name
Test status
Simulation time 43007037 ps
CPU time 0.72 seconds
Started Mar 21 01:54:01 PM PDT 24
Finished Mar 21 01:54:02 PM PDT 24
Peak memory 203492 kb
Host smart-a2abbf8a-90fe-4cb9-a9b6-d553e9458c84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894961919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
3894961919
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1479518222
Short name T978
Test name
Test status
Simulation time 13767784 ps
CPU time 0.68 seconds
Started Mar 21 01:54:01 PM PDT 24
Finished Mar 21 01:54:01 PM PDT 24
Peak memory 203528 kb
Host smart-3af7e6d7-8922-48f0-9a92-f2b718dd5fc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479518222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
1479518222
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.708591475
Short name T985
Test name
Test status
Simulation time 19804312 ps
CPU time 0.81 seconds
Started Mar 21 01:54:01 PM PDT 24
Finished Mar 21 01:54:02 PM PDT 24
Peak memory 203580 kb
Host smart-3ed1819b-5523-47e7-bd56-c72b7c0846a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708591475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.708591475
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1164869672
Short name T972
Test name
Test status
Simulation time 132130458 ps
CPU time 0.74 seconds
Started Mar 21 01:54:03 PM PDT 24
Finished Mar 21 01:54:04 PM PDT 24
Peak memory 203576 kb
Host smart-402f9075-0dbd-4b33-b559-fcf701e752c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164869672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
1164869672
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2623089963
Short name T1036
Test name
Test status
Simulation time 44736751 ps
CPU time 0.78 seconds
Started Mar 21 01:54:02 PM PDT 24
Finished Mar 21 01:54:03 PM PDT 24
Peak memory 203524 kb
Host smart-e10d87da-1e35-4678-8ad6-aee61998cb33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623089963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
2623089963
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2145416351
Short name T1026
Test name
Test status
Simulation time 23675502 ps
CPU time 0.72 seconds
Started Mar 21 01:54:05 PM PDT 24
Finished Mar 21 01:54:06 PM PDT 24
Peak memory 203588 kb
Host smart-199eccb7-30a9-48b6-b205-14a5ac609480
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145416351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
2145416351
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2400607529
Short name T990
Test name
Test status
Simulation time 54850357 ps
CPU time 0.74 seconds
Started Mar 21 01:54:01 PM PDT 24
Finished Mar 21 01:54:02 PM PDT 24
Peak memory 203536 kb
Host smart-3118124c-8826-44d0-8834-c85f83a1cb11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400607529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
2400607529
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1239082188
Short name T976
Test name
Test status
Simulation time 37634913 ps
CPU time 0.7 seconds
Started Mar 21 01:54:02 PM PDT 24
Finished Mar 21 01:54:03 PM PDT 24
Peak memory 203500 kb
Host smart-193efd5e-a0ff-4d55-86c3-6ba2a2a62d88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239082188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
1239082188
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.1350713601
Short name T1041
Test name
Test status
Simulation time 15479114 ps
CPU time 0.76 seconds
Started Mar 21 01:54:01 PM PDT 24
Finished Mar 21 01:54:02 PM PDT 24
Peak memory 203564 kb
Host smart-cf7313ac-2386-49dc-8c9b-038883a407b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350713601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
1350713601
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3242176805
Short name T1060
Test name
Test status
Simulation time 31166573 ps
CPU time 0.76 seconds
Started Mar 21 01:54:00 PM PDT 24
Finished Mar 21 01:54:01 PM PDT 24
Peak memory 203668 kb
Host smart-84b7fb0a-4b4c-4825-a70b-6e813bf620cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242176805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
3242176805
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3614765354
Short name T989
Test name
Test status
Simulation time 1027245302 ps
CPU time 8.67 seconds
Started Mar 21 01:53:03 PM PDT 24
Finished Mar 21 01:53:12 PM PDT 24
Peak memory 206948 kb
Host smart-ff01203d-bcb6-4b21-98e6-8f1e80f74fd7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614765354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.3614765354
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2484419343
Short name T1039
Test name
Test status
Simulation time 354081927 ps
CPU time 20.96 seconds
Started Mar 21 01:52:59 PM PDT 24
Finished Mar 21 01:53:20 PM PDT 24
Peak memory 206908 kb
Host smart-df72067c-929a-4e1d-b579-ac1c1dbc50ad
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484419343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.2484419343
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.4041945579
Short name T110
Test name
Test status
Simulation time 28859149 ps
CPU time 1 seconds
Started Mar 21 01:53:02 PM PDT 24
Finished Mar 21 01:53:04 PM PDT 24
Peak memory 206620 kb
Host smart-37f98a6c-289d-4df0-b58a-c1762324696d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041945579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.4041945579
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.715897539
Short name T1069
Test name
Test status
Simulation time 140714681 ps
CPU time 1.66 seconds
Started Mar 21 01:53:12 PM PDT 24
Finished Mar 21 01:53:14 PM PDT 24
Peak memory 215184 kb
Host smart-edae6fc9-9e56-46e7-b677-28865b799466
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715897539 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.715897539
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2334124714
Short name T1037
Test name
Test status
Simulation time 407469271 ps
CPU time 2.82 seconds
Started Mar 21 01:53:03 PM PDT 24
Finished Mar 21 01:53:07 PM PDT 24
Peak memory 215088 kb
Host smart-28d4b808-a4e0-49d8-8c3c-cd80342d39d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334124714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.2
334124714
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3376909510
Short name T1016
Test name
Test status
Simulation time 59002605 ps
CPU time 0.77 seconds
Started Mar 21 01:52:59 PM PDT 24
Finished Mar 21 01:53:00 PM PDT 24
Peak memory 203592 kb
Host smart-cf052f79-4787-4f9d-871e-94c2df65bddf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376909510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.3
376909510
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.978986670
Short name T109
Test name
Test status
Simulation time 193689416 ps
CPU time 1.78 seconds
Started Mar 21 01:52:59 PM PDT 24
Finished Mar 21 01:53:01 PM PDT 24
Peak memory 215260 kb
Host smart-6ca6c9e5-4212-4301-8d16-28bb9fb092b3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978986670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_
device_mem_partial_access.978986670
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1335362431
Short name T1047
Test name
Test status
Simulation time 41316184 ps
CPU time 0.64 seconds
Started Mar 21 01:53:05 PM PDT 24
Finished Mar 21 01:53:06 PM PDT 24
Peak memory 203392 kb
Host smart-d1e0cc9e-03d7-4bba-a6cf-a58ab72cf781
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335362431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.1335362431
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.476657412
Short name T1022
Test name
Test status
Simulation time 241804679 ps
CPU time 1.8 seconds
Started Mar 21 01:53:02 PM PDT 24
Finished Mar 21 01:53:05 PM PDT 24
Peak memory 215120 kb
Host smart-bf1ff26e-3ead-43cf-8cde-f787762ff942
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476657412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sp
i_device_same_csr_outstanding.476657412
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3215519921
Short name T1091
Test name
Test status
Simulation time 480964842 ps
CPU time 3.52 seconds
Started Mar 21 01:53:01 PM PDT 24
Finished Mar 21 01:53:05 PM PDT 24
Peak memory 216372 kb
Host smart-614c1877-14c3-4767-94c2-bf67c67ac9f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215519921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.3
215519921
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3591726836
Short name T1011
Test name
Test status
Simulation time 1358068678 ps
CPU time 15.15 seconds
Started Mar 21 01:53:03 PM PDT 24
Finished Mar 21 01:53:19 PM PDT 24
Peak memory 215108 kb
Host smart-00697f5d-cc98-4697-a371-822fdfc68628
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591726836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.3591726836
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2942634693
Short name T1012
Test name
Test status
Simulation time 12316116 ps
CPU time 0.72 seconds
Started Mar 21 01:54:05 PM PDT 24
Finished Mar 21 01:54:05 PM PDT 24
Peak memory 203524 kb
Host smart-9cae05d0-8a32-4819-aae3-dbd358acc9ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942634693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
2942634693
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1984465020
Short name T980
Test name
Test status
Simulation time 19860446 ps
CPU time 0.76 seconds
Started Mar 21 01:54:03 PM PDT 24
Finished Mar 21 01:54:03 PM PDT 24
Peak memory 203564 kb
Host smart-7c913106-e517-4c06-8dfe-6f096dd755d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984465020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
1984465020
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.694274953
Short name T977
Test name
Test status
Simulation time 14599294 ps
CPU time 0.78 seconds
Started Mar 21 01:54:03 PM PDT 24
Finished Mar 21 01:54:04 PM PDT 24
Peak memory 203552 kb
Host smart-343fd4a3-84a7-48ec-af0a-a8a4f974b63c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694274953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.694274953
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3901624853
Short name T1051
Test name
Test status
Simulation time 14274261 ps
CPU time 0.71 seconds
Started Mar 21 01:54:20 PM PDT 24
Finished Mar 21 01:54:21 PM PDT 24
Peak memory 203176 kb
Host smart-7c3a7173-5f80-49f8-a409-0d56768692bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901624853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
3901624853
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.392367531
Short name T1031
Test name
Test status
Simulation time 25533421 ps
CPU time 0.78 seconds
Started Mar 21 01:54:17 PM PDT 24
Finished Mar 21 01:54:18 PM PDT 24
Peak memory 203588 kb
Host smart-53cbbba9-b0fe-42aa-9d17-40a9323a9c27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392367531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.392367531
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2893047904
Short name T1014
Test name
Test status
Simulation time 13840301 ps
CPU time 0.77 seconds
Started Mar 21 01:54:18 PM PDT 24
Finished Mar 21 01:54:19 PM PDT 24
Peak memory 203600 kb
Host smart-a19a4055-33c0-4d66-9a47-a1479cd56dba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893047904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
2893047904
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2948548503
Short name T1076
Test name
Test status
Simulation time 15918439 ps
CPU time 0.73 seconds
Started Mar 21 01:54:18 PM PDT 24
Finished Mar 21 01:54:19 PM PDT 24
Peak memory 203592 kb
Host smart-38d46e52-684c-49aa-a890-f0b5a30e7ed7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948548503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
2948548503
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1894700323
Short name T971
Test name
Test status
Simulation time 44192560 ps
CPU time 0.73 seconds
Started Mar 21 01:54:23 PM PDT 24
Finished Mar 21 01:54:24 PM PDT 24
Peak memory 203572 kb
Host smart-6abb0af5-371b-4eab-bbe4-1648b13d479f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894700323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
1894700323
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.868388465
Short name T981
Test name
Test status
Simulation time 83420363 ps
CPU time 0.7 seconds
Started Mar 21 01:54:20 PM PDT 24
Finished Mar 21 01:54:21 PM PDT 24
Peak memory 203552 kb
Host smart-8dd721a7-1483-482e-a187-c8598cff36f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868388465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.868388465
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3359235867
Short name T1004
Test name
Test status
Simulation time 20024862 ps
CPU time 0.7 seconds
Started Mar 21 01:54:14 PM PDT 24
Finished Mar 21 01:54:15 PM PDT 24
Peak memory 203540 kb
Host smart-9df1a3d2-e01e-4000-bfde-6296c728cca6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359235867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
3359235867
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.306852813
Short name T1049
Test name
Test status
Simulation time 200011999 ps
CPU time 3.44 seconds
Started Mar 21 01:53:12 PM PDT 24
Finished Mar 21 01:53:16 PM PDT 24
Peak memory 217496 kb
Host smart-a0adca01-3957-4932-b94c-c20ca80a6de8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306852813 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.306852813
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.242088360
Short name T1059
Test name
Test status
Simulation time 62319335 ps
CPU time 2.04 seconds
Started Mar 21 01:53:19 PM PDT 24
Finished Mar 21 01:53:21 PM PDT 24
Peak memory 215088 kb
Host smart-c0127bcc-f583-45d6-a09a-607d63fc920b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242088360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.242088360
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3076609351
Short name T967
Test name
Test status
Simulation time 12578407 ps
CPU time 0.75 seconds
Started Mar 21 01:53:14 PM PDT 24
Finished Mar 21 01:53:15 PM PDT 24
Peak memory 203564 kb
Host smart-501a9b10-58f2-4ff4-8e91-ac90c4d8550f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076609351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.3
076609351
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1499309160
Short name T1058
Test name
Test status
Simulation time 69001731 ps
CPU time 3.73 seconds
Started Mar 21 01:53:25 PM PDT 24
Finished Mar 21 01:53:29 PM PDT 24
Peak memory 215196 kb
Host smart-c8bbe0f5-f3b7-4abb-8557-b576ce3e602c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499309160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.1499309160
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.539253866
Short name T1050
Test name
Test status
Simulation time 323445068 ps
CPU time 4.72 seconds
Started Mar 21 01:53:10 PM PDT 24
Finished Mar 21 01:53:15 PM PDT 24
Peak memory 215416 kb
Host smart-5dbb698b-eb1a-4378-a7e2-532404b3f440
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539253866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.539253866
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3366901455
Short name T1074
Test name
Test status
Simulation time 2111748029 ps
CPU time 14.71 seconds
Started Mar 21 01:53:13 PM PDT 24
Finished Mar 21 01:53:28 PM PDT 24
Peak memory 215224 kb
Host smart-86a3e081-594c-4d03-a1d1-7b572458f7e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366901455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.3366901455
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1785792135
Short name T1092
Test name
Test status
Simulation time 105680092 ps
CPU time 1.97 seconds
Started Mar 21 01:53:13 PM PDT 24
Finished Mar 21 01:53:15 PM PDT 24
Peak memory 216312 kb
Host smart-b0a42dee-b838-442c-b4b5-5e95dd234c60
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785792135 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.1785792135
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1967450732
Short name T1010
Test name
Test status
Simulation time 87041650 ps
CPU time 2.78 seconds
Started Mar 21 01:53:15 PM PDT 24
Finished Mar 21 01:53:18 PM PDT 24
Peak memory 215180 kb
Host smart-e6abc4ad-1131-4763-b590-be986c78695a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967450732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.1
967450732
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.45172314
Short name T1003
Test name
Test status
Simulation time 44711566 ps
CPU time 0.7 seconds
Started Mar 21 01:53:13 PM PDT 24
Finished Mar 21 01:53:14 PM PDT 24
Peak memory 203540 kb
Host smart-a410e612-e16c-4b79-8c1e-ba77e392106e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45172314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.45172314
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3818743968
Short name T1018
Test name
Test status
Simulation time 219991748 ps
CPU time 1.67 seconds
Started Mar 21 01:53:12 PM PDT 24
Finished Mar 21 01:53:14 PM PDT 24
Peak memory 207000 kb
Host smart-5b2a4436-0e5c-479d-b524-b7282d15e3f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818743968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.3818743968
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1490186554
Short name T1071
Test name
Test status
Simulation time 99358096 ps
CPU time 3.22 seconds
Started Mar 21 01:53:19 PM PDT 24
Finished Mar 21 01:53:23 PM PDT 24
Peak memory 215520 kb
Host smart-eb2260b3-e23c-407a-b7e3-fc60e6b2aeff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490186554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.1
490186554
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1251887817
Short name T56
Test name
Test status
Simulation time 192580736 ps
CPU time 12.37 seconds
Started Mar 21 01:53:14 PM PDT 24
Finished Mar 21 01:53:26 PM PDT 24
Peak memory 215204 kb
Host smart-2cab0621-fa23-4f61-b4a7-cd96ae652334
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251887817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.1251887817
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1577247214
Short name T984
Test name
Test status
Simulation time 34130974 ps
CPU time 2.45 seconds
Started Mar 21 01:53:25 PM PDT 24
Finished Mar 21 01:53:28 PM PDT 24
Peak memory 216248 kb
Host smart-1a3869cf-6dd4-4b9d-865b-a4b35a07b674
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577247214 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.1577247214
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3530032279
Short name T115
Test name
Test status
Simulation time 521895758 ps
CPU time 1.98 seconds
Started Mar 21 01:53:09 PM PDT 24
Finished Mar 21 01:53:11 PM PDT 24
Peak memory 215068 kb
Host smart-35109a54-5cb0-4e40-abc8-dc982a288dd8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530032279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.3
530032279
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2436111387
Short name T1007
Test name
Test status
Simulation time 14414451 ps
CPU time 0.74 seconds
Started Mar 21 01:53:13 PM PDT 24
Finished Mar 21 01:53:15 PM PDT 24
Peak memory 203604 kb
Host smart-ab4cdf9c-ac36-4930-b3f5-72b426a89764
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436111387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.2
436111387
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2170460768
Short name T1054
Test name
Test status
Simulation time 128799483 ps
CPU time 1.74 seconds
Started Mar 21 01:53:11 PM PDT 24
Finished Mar 21 01:53:13 PM PDT 24
Peak memory 215272 kb
Host smart-bf946081-67e2-419f-98b7-400c26c96be6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170460768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.2170460768
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3675371056
Short name T147
Test name
Test status
Simulation time 1036073914 ps
CPU time 23 seconds
Started Mar 21 01:53:11 PM PDT 24
Finished Mar 21 01:53:34 PM PDT 24
Peak memory 215196 kb
Host smart-cb578f07-20ef-4d4e-a7dd-408618a248c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675371056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.3675371056
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.4019305270
Short name T88
Test name
Test status
Simulation time 150992570 ps
CPU time 3.66 seconds
Started Mar 21 01:53:11 PM PDT 24
Finished Mar 21 01:53:15 PM PDT 24
Peak memory 217852 kb
Host smart-ca3d93ce-01ed-4e32-8358-64cdc2131b47
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019305270 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.4019305270
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3363945546
Short name T107
Test name
Test status
Simulation time 62888696 ps
CPU time 1.77 seconds
Started Mar 21 01:53:11 PM PDT 24
Finished Mar 21 01:53:12 PM PDT 24
Peak memory 215196 kb
Host smart-447aaac4-b302-405b-99f4-248a15158b9b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363945546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.3
363945546
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1384449471
Short name T968
Test name
Test status
Simulation time 32382416 ps
CPU time 0.7 seconds
Started Mar 21 01:53:13 PM PDT 24
Finished Mar 21 01:53:14 PM PDT 24
Peak memory 203616 kb
Host smart-515660e1-ffa0-4b36-b623-237f42bc846c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384449471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.1
384449471
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1860459018
Short name T1056
Test name
Test status
Simulation time 43230613 ps
CPU time 2.66 seconds
Started Mar 21 01:53:12 PM PDT 24
Finished Mar 21 01:53:16 PM PDT 24
Peak memory 215132 kb
Host smart-62672c41-14c1-44ad-8b2b-391693d6994a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860459018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.1860459018
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2887597607
Short name T1053
Test name
Test status
Simulation time 892652408 ps
CPU time 1.85 seconds
Started Mar 21 01:53:25 PM PDT 24
Finished Mar 21 01:53:27 PM PDT 24
Peak memory 215320 kb
Host smart-c388ba52-00e0-49d8-8bd2-b792dfea1960
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887597607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.2
887597607
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3138949596
Short name T1061
Test name
Test status
Simulation time 551308617 ps
CPU time 7.58 seconds
Started Mar 21 01:53:14 PM PDT 24
Finished Mar 21 01:53:22 PM PDT 24
Peak memory 215224 kb
Host smart-7b6ecd4f-b44d-4956-a31e-4470db557393
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138949596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.3138949596
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3759235429
Short name T1032
Test name
Test status
Simulation time 122249995 ps
CPU time 1.68 seconds
Started Mar 21 01:53:30 PM PDT 24
Finished Mar 21 01:53:32 PM PDT 24
Peak memory 215260 kb
Host smart-aad303ae-7271-4434-b307-f0a6c4096030
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759235429 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.3759235429
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1371763215
Short name T994
Test name
Test status
Simulation time 37833629 ps
CPU time 1.36 seconds
Started Mar 21 01:53:24 PM PDT 24
Finished Mar 21 01:53:26 PM PDT 24
Peak memory 206908 kb
Host smart-57739cf4-8317-424d-8dc7-5ba9e5c36b71
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371763215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.1
371763215
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.883325628
Short name T973
Test name
Test status
Simulation time 41218213 ps
CPU time 0.74 seconds
Started Mar 21 01:53:24 PM PDT 24
Finished Mar 21 01:53:25 PM PDT 24
Peak memory 203652 kb
Host smart-5b713938-3f5f-4998-b27b-5d81a51481b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883325628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.883325628
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2020283827
Short name T1029
Test name
Test status
Simulation time 136047912 ps
CPU time 1.74 seconds
Started Mar 21 01:53:22 PM PDT 24
Finished Mar 21 01:53:24 PM PDT 24
Peak memory 215212 kb
Host smart-7e5c5287-65f5-4236-9100-576a80be9f7f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020283827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.2020283827
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1478188101
Short name T102
Test name
Test status
Simulation time 3175526446 ps
CPU time 21.82 seconds
Started Mar 21 01:53:13 PM PDT 24
Finished Mar 21 01:53:35 PM PDT 24
Peak memory 215240 kb
Host smart-9e287175-0f96-44ee-aebe-808e003c04af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478188101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.1478188101
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.577854397
Short name T547
Test name
Test status
Simulation time 94386560 ps
CPU time 0.73 seconds
Started Mar 21 02:16:16 PM PDT 24
Finished Mar 21 02:16:17 PM PDT 24
Peak memory 205340 kb
Host smart-28550a91-556c-4c1b-885b-e56ac6e1ca16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577854397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.577854397
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.713216453
Short name T901
Test name
Test status
Simulation time 64659472 ps
CPU time 2.34 seconds
Started Mar 21 02:16:05 PM PDT 24
Finished Mar 21 02:16:07 PM PDT 24
Peak memory 218772 kb
Host smart-2a8ceac6-a1e9-4a5e-9d54-fabd5a57ce61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713216453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.713216453
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.666738168
Short name T687
Test name
Test status
Simulation time 37364136 ps
CPU time 0.76 seconds
Started Mar 21 02:15:55 PM PDT 24
Finished Mar 21 02:15:56 PM PDT 24
Peak memory 206352 kb
Host smart-bbd61b2f-f673-4577-b9e7-aee709ebd897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666738168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.666738168
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.3154612749
Short name T23
Test name
Test status
Simulation time 14082725654 ps
CPU time 68.24 seconds
Started Mar 21 02:16:06 PM PDT 24
Finished Mar 21 02:17:15 PM PDT 24
Peak memory 249016 kb
Host smart-4b100f05-784b-4022-bbcc-162b2d2a667a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154612749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.3154612749
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.2506007651
Short name T886
Test name
Test status
Simulation time 341797339438 ps
CPU time 450.26 seconds
Started Mar 21 02:16:11 PM PDT 24
Finished Mar 21 02:23:42 PM PDT 24
Peak memory 254228 kb
Host smart-a5e7f7c6-d49d-414c-9534-f6d1ccbcdbb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506007651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.2506007651
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.897976481
Short name T960
Test name
Test status
Simulation time 172417791094 ps
CPU time 356.12 seconds
Started Mar 21 02:16:08 PM PDT 24
Finished Mar 21 02:22:04 PM PDT 24
Peak memory 264544 kb
Host smart-4525457d-952e-43d9-bd79-7894dc9c8de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897976481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle.
897976481
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.3803791998
Short name T692
Test name
Test status
Simulation time 1627047089 ps
CPU time 18.01 seconds
Started Mar 21 02:16:07 PM PDT 24
Finished Mar 21 02:16:25 PM PDT 24
Peak memory 234044 kb
Host smart-89222574-530a-4d32-81a0-3f3bdb22859a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803791998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.3803791998
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.1996664990
Short name T519
Test name
Test status
Simulation time 1677822813 ps
CPU time 3.22 seconds
Started Mar 21 02:15:57 PM PDT 24
Finished Mar 21 02:16:00 PM PDT 24
Peak memory 218316 kb
Host smart-30d367df-be1e-4c35-ac1f-19b1ec6c515a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996664990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.1996664990
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.3657764706
Short name T367
Test name
Test status
Simulation time 58388132946 ps
CPU time 31.91 seconds
Started Mar 21 02:16:09 PM PDT 24
Finished Mar 21 02:16:41 PM PDT 24
Peak memory 232608 kb
Host smart-e3f416c2-6eaf-457e-a911-692228d2b3fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657764706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.3657764706
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.832220456
Short name T846
Test name
Test status
Simulation time 9378759912 ps
CPU time 15.67 seconds
Started Mar 21 02:15:55 PM PDT 24
Finished Mar 21 02:16:11 PM PDT 24
Peak memory 237472 kb
Host smart-4b7b9004-9191-4156-9940-b711ab0c159b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832220456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.
832220456
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.3920769940
Short name T586
Test name
Test status
Simulation time 1087048566 ps
CPU time 3.95 seconds
Started Mar 21 02:15:58 PM PDT 24
Finished Mar 21 02:16:02 PM PDT 24
Peak memory 224628 kb
Host smart-e3fdfa6d-1558-41e6-9b9d-9211663f7cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920769940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.3920769940
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.2587338601
Short name T383
Test name
Test status
Simulation time 1120228544 ps
CPU time 4.77 seconds
Started Mar 21 02:16:11 PM PDT 24
Finished Mar 21 02:16:16 PM PDT 24
Peak memory 223200 kb
Host smart-db5c949c-6a2b-4358-8c75-4ab802afd496
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2587338601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.2587338601
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.633790956
Short name T59
Test name
Test status
Simulation time 58907064604 ps
CPU time 56.46 seconds
Started Mar 21 02:16:05 PM PDT 24
Finished Mar 21 02:17:02 PM PDT 24
Peak memory 240828 kb
Host smart-c42da95e-659b-4f23-8c6b-dbe3b21e4b70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633790956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress
_all.633790956
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.2397606676
Short name T810
Test name
Test status
Simulation time 23633207504 ps
CPU time 13.8 seconds
Started Mar 21 02:15:53 PM PDT 24
Finished Mar 21 02:16:07 PM PDT 24
Peak memory 216240 kb
Host smart-3d4a21cc-3747-49ce-9815-c1a69f755c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397606676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.2397606676
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.3438703057
Short name T548
Test name
Test status
Simulation time 4190902018 ps
CPU time 3.64 seconds
Started Mar 21 02:15:52 PM PDT 24
Finished Mar 21 02:15:56 PM PDT 24
Peak memory 216172 kb
Host smart-704116c0-c61d-4506-9da4-f946c8154763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438703057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.3438703057
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.1893770019
Short name T410
Test name
Test status
Simulation time 21165386 ps
CPU time 0.97 seconds
Started Mar 21 02:15:56 PM PDT 24
Finished Mar 21 02:15:57 PM PDT 24
Peak memory 206624 kb
Host smart-72d1e403-5ad1-44b5-a15c-9b52e1396f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893770019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.1893770019
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.3634540693
Short name T729
Test name
Test status
Simulation time 26788828 ps
CPU time 0.81 seconds
Started Mar 21 02:15:58 PM PDT 24
Finished Mar 21 02:15:59 PM PDT 24
Peak memory 205884 kb
Host smart-205e435a-a72a-450e-a838-6da2f962af30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634540693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.3634540693
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.225376212
Short name T412
Test name
Test status
Simulation time 648440084 ps
CPU time 5.34 seconds
Started Mar 21 02:16:06 PM PDT 24
Finished Mar 21 02:16:11 PM PDT 24
Peak memory 234128 kb
Host smart-6f872640-04f2-4212-b0bd-010c70449f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225376212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.225376212
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.132354396
Short name T583
Test name
Test status
Simulation time 27711589 ps
CPU time 0.74 seconds
Started Mar 21 02:16:30 PM PDT 24
Finished Mar 21 02:16:30 PM PDT 24
Peak memory 205252 kb
Host smart-3a4be25a-0a68-4c0c-aac9-145c3f8dd8d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132354396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.132354396
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.2397534297
Short name T365
Test name
Test status
Simulation time 47354454 ps
CPU time 0.75 seconds
Started Mar 21 02:16:15 PM PDT 24
Finished Mar 21 02:16:15 PM PDT 24
Peak memory 205304 kb
Host smart-1a701849-fa39-419b-9f7c-8fd72c71d6f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397534297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.2397534297
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.936957455
Short name T816
Test name
Test status
Simulation time 6891636603 ps
CPU time 23.72 seconds
Started Mar 21 02:16:17 PM PDT 24
Finished Mar 21 02:16:41 PM PDT 24
Peak memory 238600 kb
Host smart-0d8e8078-6682-4e4c-9841-266ab3d2c00b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936957455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.936957455
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.2895768971
Short name T46
Test name
Test status
Simulation time 68315382212 ps
CPU time 261.95 seconds
Started Mar 21 02:16:17 PM PDT 24
Finished Mar 21 02:20:39 PM PDT 24
Peak memory 252688 kb
Host smart-14916b6f-4c54-4f99-be9a-4b47786518ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895768971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.2895768971
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.2844934577
Short name T736
Test name
Test status
Simulation time 37600655408 ps
CPU time 17.72 seconds
Started Mar 21 02:16:20 PM PDT 24
Finished Mar 21 02:16:37 PM PDT 24
Peak memory 240832 kb
Host smart-546cbfe7-c291-428a-a7af-7edd7c3efb25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844934577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.2844934577
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.253047311
Short name T869
Test name
Test status
Simulation time 3720486689 ps
CPU time 10.25 seconds
Started Mar 21 02:16:15 PM PDT 24
Finished Mar 21 02:16:25 PM PDT 24
Peak memory 219516 kb
Host smart-d9e8e45b-5fa1-4c7e-842f-59c0c15ef94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253047311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.253047311
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.2540476340
Short name T605
Test name
Test status
Simulation time 697438576 ps
CPU time 5.18 seconds
Started Mar 21 02:16:13 PM PDT 24
Finished Mar 21 02:16:18 PM PDT 24
Peak memory 217188 kb
Host smart-b8b2a696-a08a-4f7b-9329-59c926670c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540476340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.2540476340
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.3121360626
Short name T684
Test name
Test status
Simulation time 2647971737 ps
CPU time 6.96 seconds
Started Mar 21 02:16:17 PM PDT 24
Finished Mar 21 02:16:24 PM PDT 24
Peak memory 218628 kb
Host smart-6cda5a5d-8c82-4956-8d50-e3ccd538fc32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121360626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.3121360626
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.4219563619
Short name T156
Test name
Test status
Simulation time 628284581 ps
CPU time 7.29 seconds
Started Mar 21 02:16:15 PM PDT 24
Finished Mar 21 02:16:23 PM PDT 24
Peak memory 235624 kb
Host smart-10273df1-ce6a-430a-a97c-cc78887395ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219563619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.4219563619
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_ram_cfg.60582093
Short name T797
Test name
Test status
Simulation time 16942184 ps
CPU time 0.76 seconds
Started Mar 21 02:16:20 PM PDT 24
Finished Mar 21 02:16:21 PM PDT 24
Peak memory 216144 kb
Host smart-08351d35-3a21-4efc-a706-c5ed94ac2a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60582093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_ram_cfg.60582093
Directory /workspace/1.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.4090404060
Short name T296
Test name
Test status
Simulation time 1104154239 ps
CPU time 5.99 seconds
Started Mar 21 02:16:13 PM PDT 24
Finished Mar 21 02:16:20 PM PDT 24
Peak memory 222352 kb
Host smart-03cd4af8-481a-4876-91e9-65846c26beb8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4090404060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.4090404060
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.4134427790
Short name T68
Test name
Test status
Simulation time 1121826359 ps
CPU time 1.17 seconds
Started Mar 21 02:16:16 PM PDT 24
Finished Mar 21 02:16:18 PM PDT 24
Peak memory 234768 kb
Host smart-ce581098-4d0b-45bb-9e3c-ecb7eb7b7fd1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134427790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.4134427790
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.2161199450
Short name T662
Test name
Test status
Simulation time 261022464 ps
CPU time 1.16 seconds
Started Mar 21 02:16:13 PM PDT 24
Finished Mar 21 02:16:14 PM PDT 24
Peak memory 206580 kb
Host smart-a05cf186-2e06-4320-a03f-c3f079e4a89a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161199450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.2161199450
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.2679883689
Short name T750
Test name
Test status
Simulation time 32297610658 ps
CPU time 30.01 seconds
Started Mar 21 02:16:20 PM PDT 24
Finished Mar 21 02:16:50 PM PDT 24
Peak memory 216264 kb
Host smart-d3cba6f9-049f-48d8-bebd-72d376b11991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679883689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.2679883689
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.2262313926
Short name T738
Test name
Test status
Simulation time 8474044909 ps
CPU time 12.53 seconds
Started Mar 21 02:16:13 PM PDT 24
Finished Mar 21 02:16:26 PM PDT 24
Peak memory 216180 kb
Host smart-b8c89b6a-a6c5-4445-833a-8b5e8e41d9a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262313926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.2262313926
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.1608227076
Short name T635
Test name
Test status
Simulation time 269143260 ps
CPU time 5.41 seconds
Started Mar 21 02:16:19 PM PDT 24
Finished Mar 21 02:16:25 PM PDT 24
Peak memory 216300 kb
Host smart-ca3c47f3-1ee7-46e5-8eae-526df05435db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608227076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.1608227076
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.1333263342
Short name T907
Test name
Test status
Simulation time 26509466 ps
CPU time 0.73 seconds
Started Mar 21 02:16:20 PM PDT 24
Finished Mar 21 02:16:21 PM PDT 24
Peak memory 205612 kb
Host smart-13f958ee-7730-4ef8-8abe-71561f7a6ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333263342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.1333263342
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.1156904724
Short name T232
Test name
Test status
Simulation time 8801548771 ps
CPU time 15.86 seconds
Started Mar 21 02:16:17 PM PDT 24
Finished Mar 21 02:16:33 PM PDT 24
Peak memory 249004 kb
Host smart-2a2c56f5-e120-4a4f-aac8-2759dc7609c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156904724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.1156904724
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.1433507437
Short name T850
Test name
Test status
Simulation time 13693841 ps
CPU time 0.72 seconds
Started Mar 21 02:18:09 PM PDT 24
Finished Mar 21 02:18:10 PM PDT 24
Peak memory 204604 kb
Host smart-e950f449-3ca4-4284-8655-eaf72964f3e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433507437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
1433507437
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.3964540543
Short name T228
Test name
Test status
Simulation time 101390501 ps
CPU time 3.63 seconds
Started Mar 21 02:18:07 PM PDT 24
Finished Mar 21 02:18:10 PM PDT 24
Peak memory 234560 kb
Host smart-07aa4b99-3c8e-4ab0-a8f5-63c1c364c995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964540543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.3964540543
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.698689081
Short name T280
Test name
Test status
Simulation time 37074535 ps
CPU time 0.78 seconds
Started Mar 21 02:17:56 PM PDT 24
Finished Mar 21 02:17:57 PM PDT 24
Peak memory 206288 kb
Host smart-668d2cbd-7326-4650-a4f7-921d52586e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698689081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.698689081
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.2270245213
Short name T30
Test name
Test status
Simulation time 126994414890 ps
CPU time 234.19 seconds
Started Mar 21 02:18:06 PM PDT 24
Finished Mar 21 02:22:01 PM PDT 24
Peak memory 265408 kb
Host smart-2785b16a-02b7-45ac-b8be-b035441e829e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270245213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.2270245213
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.3322934398
Short name T636
Test name
Test status
Simulation time 75304075353 ps
CPU time 76.03 seconds
Started Mar 21 02:18:07 PM PDT 24
Finished Mar 21 02:19:23 PM PDT 24
Peak memory 257240 kb
Host smart-74ee3770-9912-4584-a053-32906bdecf33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322934398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.3322934398
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.291098107
Short name T427
Test name
Test status
Simulation time 3739533356 ps
CPU time 4.68 seconds
Started Mar 21 02:17:57 PM PDT 24
Finished Mar 21 02:18:02 PM PDT 24
Peak memory 224392 kb
Host smart-f5523009-723b-4ba8-951f-ceae82624044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291098107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.291098107
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.3798045199
Short name T656
Test name
Test status
Simulation time 806275150 ps
CPU time 6.6 seconds
Started Mar 21 02:18:10 PM PDT 24
Finished Mar 21 02:18:17 PM PDT 24
Peak memory 228804 kb
Host smart-16f6514f-1323-4367-8d34-beb27976b466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798045199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.3798045199
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.3920860654
Short name T226
Test name
Test status
Simulation time 1212283670 ps
CPU time 6.18 seconds
Started Mar 21 02:17:56 PM PDT 24
Finished Mar 21 02:18:03 PM PDT 24
Peak memory 233444 kb
Host smart-2ac3ac5f-caea-4cfd-b5c6-61b9c0e99134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920860654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.3920860654
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.4244609104
Short name T472
Test name
Test status
Simulation time 16895728787 ps
CPU time 15.97 seconds
Started Mar 21 02:17:56 PM PDT 24
Finished Mar 21 02:18:12 PM PDT 24
Peak memory 255456 kb
Host smart-dacfc90e-8080-49f9-b008-ad81475a469d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244609104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.4244609104
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_ram_cfg.2428479883
Short name T800
Test name
Test status
Simulation time 20319971 ps
CPU time 0.72 seconds
Started Mar 21 02:17:57 PM PDT 24
Finished Mar 21 02:17:58 PM PDT 24
Peak memory 216100 kb
Host smart-b788dfad-d7db-448f-b945-c9babe3df4ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428479883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_ram_cfg.2428479883
Directory /workspace/10.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.1470364040
Short name T104
Test name
Test status
Simulation time 4337923111 ps
CPU time 7.26 seconds
Started Mar 21 02:18:08 PM PDT 24
Finished Mar 21 02:18:15 PM PDT 24
Peak memory 222736 kb
Host smart-b2795deb-57dd-4dd9-8da9-ec775221583a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1470364040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.1470364040
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.2058249776
Short name T301
Test name
Test status
Simulation time 43215922 ps
CPU time 0.92 seconds
Started Mar 21 02:18:06 PM PDT 24
Finished Mar 21 02:18:07 PM PDT 24
Peak memory 206676 kb
Host smart-97aa58fd-05de-45c3-9cf7-cadcbf67dbf7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058249776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.2058249776
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.2042004647
Short name T77
Test name
Test status
Simulation time 32802120294 ps
CPU time 39.29 seconds
Started Mar 21 02:17:57 PM PDT 24
Finished Mar 21 02:18:36 PM PDT 24
Peak memory 216180 kb
Host smart-a17fc430-ef81-4384-97d3-56e8e5f71d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042004647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.2042004647
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.2139710336
Short name T863
Test name
Test status
Simulation time 13202030177 ps
CPU time 34.95 seconds
Started Mar 21 02:17:56 PM PDT 24
Finished Mar 21 02:18:31 PM PDT 24
Peak memory 216120 kb
Host smart-4845c15d-4591-4fbd-b490-b797a59505d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139710336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.2139710336
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.3718649856
Short name T855
Test name
Test status
Simulation time 69862475 ps
CPU time 1.38 seconds
Started Mar 21 02:17:59 PM PDT 24
Finished Mar 21 02:18:00 PM PDT 24
Peak memory 216168 kb
Host smart-4958e043-e50a-4f44-98c4-8244f28df65a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718649856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.3718649856
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.1539323277
Short name T489
Test name
Test status
Simulation time 80967882 ps
CPU time 0.95 seconds
Started Mar 21 02:17:57 PM PDT 24
Finished Mar 21 02:17:58 PM PDT 24
Peak memory 206628 kb
Host smart-4dd0a177-b5c1-417c-8492-336b97eef7c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539323277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.1539323277
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.773514420
Short name T884
Test name
Test status
Simulation time 1876743355 ps
CPU time 8.35 seconds
Started Mar 21 02:18:07 PM PDT 24
Finished Mar 21 02:18:16 PM PDT 24
Peak memory 233444 kb
Host smart-51b62320-54e2-4065-a994-e1f2ab6c2bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773514420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.773514420
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.1808236708
Short name T413
Test name
Test status
Simulation time 15725787 ps
CPU time 0.74 seconds
Started Mar 21 02:18:19 PM PDT 24
Finished Mar 21 02:18:20 PM PDT 24
Peak memory 205252 kb
Host smart-7ede8803-bbb1-472e-a20a-88ac1b084ec6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808236708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
1808236708
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.2634576073
Short name T614
Test name
Test status
Simulation time 1415580006 ps
CPU time 3.94 seconds
Started Mar 21 02:18:20 PM PDT 24
Finished Mar 21 02:18:24 PM PDT 24
Peak memory 233524 kb
Host smart-d9c31a55-7801-4e9c-83de-7a991d79425b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634576073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.2634576073
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.925131441
Short name T868
Test name
Test status
Simulation time 52526335 ps
CPU time 0.79 seconds
Started Mar 21 02:18:09 PM PDT 24
Finished Mar 21 02:18:10 PM PDT 24
Peak memory 206332 kb
Host smart-5e75c414-60d8-4656-9ad3-7080367a4522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925131441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.925131441
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.2239055338
Short name T235
Test name
Test status
Simulation time 15617407737 ps
CPU time 110 seconds
Started Mar 21 02:18:19 PM PDT 24
Finished Mar 21 02:20:10 PM PDT 24
Peak memory 254880 kb
Host smart-b780eb2a-1e94-493a-88a6-1d533870074e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239055338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.2239055338
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.74005599
Short name T261
Test name
Test status
Simulation time 16740471004 ps
CPU time 106.93 seconds
Started Mar 21 02:18:19 PM PDT 24
Finished Mar 21 02:20:06 PM PDT 24
Peak memory 249476 kb
Host smart-d2934555-d990-4c27-9a03-f4819259b83b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74005599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.74005599
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.239180258
Short name T159
Test name
Test status
Simulation time 111647005694 ps
CPU time 806.25 seconds
Started Mar 21 02:18:17 PM PDT 24
Finished Mar 21 02:31:44 PM PDT 24
Peak memory 254608 kb
Host smart-6864d012-b2c4-4d43-9131-5cb0d23b7d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239180258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle
.239180258
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.4092789986
Short name T516
Test name
Test status
Simulation time 506714735 ps
CPU time 12.84 seconds
Started Mar 21 02:18:18 PM PDT 24
Finished Mar 21 02:18:31 PM PDT 24
Peak memory 235812 kb
Host smart-4855c922-0c14-4922-ba56-9cde97dd040e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092789986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.4092789986
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.458954040
Short name T963
Test name
Test status
Simulation time 428358099 ps
CPU time 3.2 seconds
Started Mar 21 02:18:21 PM PDT 24
Finished Mar 21 02:18:24 PM PDT 24
Peak memory 218404 kb
Host smart-50188339-31f0-4cb6-ad46-5dfeb072d30e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458954040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.458954040
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.3749254702
Short name T199
Test name
Test status
Simulation time 26942855055 ps
CPU time 42.61 seconds
Started Mar 21 02:18:21 PM PDT 24
Finished Mar 21 02:19:04 PM PDT 24
Peak memory 237552 kb
Host smart-0a87cda5-aa21-4633-9006-2b0d053318bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749254702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.3749254702
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.2422692646
Short name T219
Test name
Test status
Simulation time 5794676807 ps
CPU time 7.65 seconds
Started Mar 21 02:18:18 PM PDT 24
Finished Mar 21 02:18:26 PM PDT 24
Peak memory 221200 kb
Host smart-7694bda3-4208-4807-ab89-7cd4a52926d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422692646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.2422692646
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.433891749
Short name T776
Test name
Test status
Simulation time 691268067 ps
CPU time 8.1 seconds
Started Mar 21 02:18:20 PM PDT 24
Finished Mar 21 02:18:28 PM PDT 24
Peak memory 232488 kb
Host smart-a4cbbd7a-9e12-4726-9761-59d22330c9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433891749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.433891749
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_ram_cfg.3509197636
Short name T63
Test name
Test status
Simulation time 15988628 ps
CPU time 0.77 seconds
Started Mar 21 02:18:09 PM PDT 24
Finished Mar 21 02:18:10 PM PDT 24
Peak memory 216116 kb
Host smart-9fb1e5c1-4404-43c2-bf75-4e4e69b23ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509197636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_ram_cfg.3509197636
Directory /workspace/11.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.636586846
Short name T381
Test name
Test status
Simulation time 1917605622 ps
CPU time 3.83 seconds
Started Mar 21 02:18:22 PM PDT 24
Finished Mar 21 02:18:27 PM PDT 24
Peak memory 221632 kb
Host smart-a2738a7e-c092-40dd-995d-165289e20029
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=636586846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dire
ct.636586846
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.327922491
Short name T268
Test name
Test status
Simulation time 2243738850 ps
CPU time 31.53 seconds
Started Mar 21 02:18:17 PM PDT 24
Finished Mar 21 02:18:49 PM PDT 24
Peak memory 216464 kb
Host smart-aafc3c1b-63cf-4185-aef3-51c3212ee2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327922491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.327922491
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.3218543618
Short name T285
Test name
Test status
Simulation time 140320606 ps
CPU time 1.18 seconds
Started Mar 21 02:18:07 PM PDT 24
Finished Mar 21 02:18:08 PM PDT 24
Peak memory 207920 kb
Host smart-bf40f782-deda-4900-9eee-8785c19a5bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218543618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.3218543618
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.3575192613
Short name T488
Test name
Test status
Simulation time 36003783 ps
CPU time 0.9 seconds
Started Mar 21 02:18:09 PM PDT 24
Finished Mar 21 02:18:10 PM PDT 24
Peak memory 205612 kb
Host smart-de23dc4c-c287-43d9-9857-64133bab563e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575192613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.3575192613
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.2990813477
Short name T549
Test name
Test status
Simulation time 6248309657 ps
CPU time 8.08 seconds
Started Mar 21 02:18:19 PM PDT 24
Finished Mar 21 02:18:27 PM PDT 24
Peak memory 233856 kb
Host smart-049ba447-3f8b-411a-a92e-64297b99dbbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990813477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.2990813477
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.254170880
Short name T874
Test name
Test status
Simulation time 180440823 ps
CPU time 0.82 seconds
Started Mar 21 02:18:31 PM PDT 24
Finished Mar 21 02:18:33 PM PDT 24
Peak memory 205292 kb
Host smart-27ddf3a7-c22c-4694-b454-3305e92eff7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254170880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.254170880
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.1428252026
Short name T201
Test name
Test status
Simulation time 146059952 ps
CPU time 2.7 seconds
Started Mar 21 02:18:30 PM PDT 24
Finished Mar 21 02:18:34 PM PDT 24
Peak memory 218840 kb
Host smart-27b42d4d-b579-46e7-855a-9a69c38c7bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428252026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.1428252026
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.3959212588
Short name T700
Test name
Test status
Simulation time 21198036 ps
CPU time 0.8 seconds
Started Mar 21 02:18:19 PM PDT 24
Finished Mar 21 02:18:20 PM PDT 24
Peak memory 206248 kb
Host smart-420f18a1-425a-421a-ac71-077f2f15b6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959212588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.3959212588
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.2773723111
Short name T561
Test name
Test status
Simulation time 2762021403 ps
CPU time 17.05 seconds
Started Mar 21 02:18:43 PM PDT 24
Finished Mar 21 02:19:01 PM PDT 24
Peak memory 240836 kb
Host smart-ed91c896-8c9a-406b-97d1-52ebfb0ee554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773723111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.2773723111
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.1321185048
Short name T245
Test name
Test status
Simulation time 196619179802 ps
CPU time 341.89 seconds
Started Mar 21 02:18:30 PM PDT 24
Finished Mar 21 02:24:12 PM PDT 24
Peak memory 256732 kb
Host smart-7117fd35-7285-4d2c-91cb-f0226ffae2df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321185048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.1321185048
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.4010043645
Short name T957
Test name
Test status
Simulation time 13564026438 ps
CPU time 96.74 seconds
Started Mar 21 02:18:37 PM PDT 24
Finished Mar 21 02:20:14 PM PDT 24
Peak memory 240916 kb
Host smart-2b4374b2-f2e5-4294-910e-32295a2ff999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010043645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.4010043645
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.2939475260
Short name T670
Test name
Test status
Simulation time 9632369985 ps
CPU time 18.08 seconds
Started Mar 21 02:18:31 PM PDT 24
Finished Mar 21 02:18:50 PM PDT 24
Peak memory 233220 kb
Host smart-9d286717-852d-4e21-88a5-95e01c692a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939475260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.2939475260
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.1718332316
Short name T356
Test name
Test status
Simulation time 266102114 ps
CPU time 3.46 seconds
Started Mar 21 02:18:30 PM PDT 24
Finished Mar 21 02:18:35 PM PDT 24
Peak memory 224308 kb
Host smart-200ce01c-f68b-4352-abdd-2db4da03b5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718332316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.1718332316
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.2390778711
Short name T526
Test name
Test status
Simulation time 30865430364 ps
CPU time 45.85 seconds
Started Mar 21 02:18:31 PM PDT 24
Finished Mar 21 02:19:18 PM PDT 24
Peak memory 249020 kb
Host smart-437effda-90c2-41df-80d4-a39cb5a682ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390778711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.2390778711
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.2517664545
Short name T836
Test name
Test status
Simulation time 3295117414 ps
CPU time 4.12 seconds
Started Mar 21 02:18:38 PM PDT 24
Finished Mar 21 02:18:42 PM PDT 24
Peak memory 216624 kb
Host smart-a2ed81b5-2b36-4da1-bcac-337a181df54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517664545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.2517664545
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.1053069265
Short name T643
Test name
Test status
Simulation time 547125775 ps
CPU time 3.71 seconds
Started Mar 21 02:18:30 PM PDT 24
Finished Mar 21 02:18:35 PM PDT 24
Peak memory 233372 kb
Host smart-cdad3378-4b21-4ac0-9a5a-3225ad95968d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053069265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.1053069265
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_ram_cfg.3656430533
Short name T851
Test name
Test status
Simulation time 23174907 ps
CPU time 0.74 seconds
Started Mar 21 02:18:17 PM PDT 24
Finished Mar 21 02:18:18 PM PDT 24
Peak memory 216096 kb
Host smart-45bf3d95-bfd9-412c-b138-372910aad3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656430533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_ram_cfg.3656430533
Directory /workspace/12.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.1070235857
Short name T704
Test name
Test status
Simulation time 991349902 ps
CPU time 4.94 seconds
Started Mar 21 02:18:30 PM PDT 24
Finished Mar 21 02:18:36 PM PDT 24
Peak memory 222132 kb
Host smart-bb7dd278-483f-466b-a8cb-cb95747e5f7c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1070235857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.1070235857
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.320095165
Short name T259
Test name
Test status
Simulation time 97148669736 ps
CPU time 405.04 seconds
Started Mar 21 02:18:30 PM PDT 24
Finished Mar 21 02:25:15 PM PDT 24
Peak memory 256980 kb
Host smart-22e92924-9222-4918-8d6e-ba84b1b85dd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320095165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stres
s_all.320095165
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.2386452870
Short name T727
Test name
Test status
Simulation time 7091929463 ps
CPU time 41.06 seconds
Started Mar 21 02:18:20 PM PDT 24
Finished Mar 21 02:19:01 PM PDT 24
Peak memory 220976 kb
Host smart-25c92a19-11fb-4bfa-adbb-3e19db085c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386452870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.2386452870
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.716980978
Short name T952
Test name
Test status
Simulation time 6835088680 ps
CPU time 16.97 seconds
Started Mar 21 02:18:19 PM PDT 24
Finished Mar 21 02:18:36 PM PDT 24
Peak memory 216228 kb
Host smart-d4c842ca-e7ce-4698-adbc-c8d0ac009059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716980978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.716980978
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.2132097953
Short name T297
Test name
Test status
Simulation time 161603926 ps
CPU time 1.31 seconds
Started Mar 21 02:18:30 PM PDT 24
Finished Mar 21 02:18:32 PM PDT 24
Peak memory 216124 kb
Host smart-b2ab351b-6858-431a-a6d1-d49b9598ca21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132097953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.2132097953
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.3694428099
Short name T885
Test name
Test status
Simulation time 247596359 ps
CPU time 0.91 seconds
Started Mar 21 02:18:29 PM PDT 24
Finished Mar 21 02:18:31 PM PDT 24
Peak memory 205588 kb
Host smart-b3c653e4-29d3-4c56-bdcb-377d3c27f0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694428099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.3694428099
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.1574374124
Short name T409
Test name
Test status
Simulation time 1926247581 ps
CPU time 3.79 seconds
Started Mar 21 02:18:31 PM PDT 24
Finished Mar 21 02:18:36 PM PDT 24
Peak memory 218568 kb
Host smart-42432185-3b44-43aa-adea-2ed947bba850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574374124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.1574374124
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.3413335188
Short name T476
Test name
Test status
Simulation time 226214946 ps
CPU time 2.53 seconds
Started Mar 21 02:18:42 PM PDT 24
Finished Mar 21 02:18:45 PM PDT 24
Peak memory 218424 kb
Host smart-457ac059-0da2-4191-af71-d26f7413d7e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413335188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.3413335188
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.1875573205
Short name T391
Test name
Test status
Simulation time 62820659 ps
CPU time 0.8 seconds
Started Mar 21 02:18:29 PM PDT 24
Finished Mar 21 02:18:30 PM PDT 24
Peak memory 206688 kb
Host smart-e6b05683-0705-4321-8ebf-36744655b385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875573205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.1875573205
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.1722476629
Short name T357
Test name
Test status
Simulation time 16894125298 ps
CPU time 28.84 seconds
Started Mar 21 02:18:44 PM PDT 24
Finished Mar 21 02:19:14 PM PDT 24
Peak memory 249124 kb
Host smart-d6013f71-0248-449d-a4e4-4caa3eb0abba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722476629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.1722476629
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.3683423401
Short name T154
Test name
Test status
Simulation time 6106275018 ps
CPU time 80.92 seconds
Started Mar 21 02:18:43 PM PDT 24
Finished Mar 21 02:20:05 PM PDT 24
Peak memory 265360 kb
Host smart-d134b097-4f9e-4b73-841e-0d61fe2d6863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683423401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.3683423401
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.3295842384
Short name T449
Test name
Test status
Simulation time 10659862716 ps
CPU time 32.64 seconds
Started Mar 21 02:18:42 PM PDT 24
Finished Mar 21 02:19:16 PM PDT 24
Peak memory 235876 kb
Host smart-bd3a0233-5358-46f4-a981-7bdca78b355b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295842384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.3295842384
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.4122924570
Short name T882
Test name
Test status
Simulation time 11216615166 ps
CPU time 8.98 seconds
Started Mar 21 02:18:45 PM PDT 24
Finished Mar 21 02:18:55 PM PDT 24
Peak memory 234804 kb
Host smart-cb68edca-0cdb-43ba-9bf9-4c18b7a60df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122924570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.4122924570
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.948461455
Short name T308
Test name
Test status
Simulation time 1327441842 ps
CPU time 10.66 seconds
Started Mar 21 02:18:43 PM PDT 24
Finished Mar 21 02:18:55 PM PDT 24
Peak memory 240316 kb
Host smart-5ec73032-d02a-473e-8d1b-bf92b449b178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948461455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.948461455
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.3665994658
Short name T749
Test name
Test status
Simulation time 718328720 ps
CPU time 4.66 seconds
Started Mar 21 02:18:41 PM PDT 24
Finished Mar 21 02:18:47 PM PDT 24
Peak memory 233548 kb
Host smart-03c31cc4-ff4f-4486-94ed-d8f018fd1bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665994658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.3665994658
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.903297283
Short name T33
Test name
Test status
Simulation time 1547810436 ps
CPU time 7.38 seconds
Started Mar 21 02:18:45 PM PDT 24
Finished Mar 21 02:18:53 PM PDT 24
Peak memory 235340 kb
Host smart-a9eb3e52-ab69-4633-8998-fccf33245cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903297283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.903297283
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_ram_cfg.3356719061
Short name T765
Test name
Test status
Simulation time 17944116 ps
CPU time 0.79 seconds
Started Mar 21 02:18:32 PM PDT 24
Finished Mar 21 02:18:33 PM PDT 24
Peak memory 216092 kb
Host smart-e31f5726-f1a6-4748-9b1b-ef666e83d215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356719061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_ram_cfg.3356719061
Directory /workspace/13.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.3776782056
Short name T371
Test name
Test status
Simulation time 334065222 ps
CPU time 3.38 seconds
Started Mar 21 02:18:42 PM PDT 24
Finished Mar 21 02:18:46 PM PDT 24
Peak memory 222216 kb
Host smart-0556fc60-39d5-4b20-997f-dc7319436b86
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3776782056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.3776782056
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.2544454534
Short name T134
Test name
Test status
Simulation time 15461597175 ps
CPU time 183.54 seconds
Started Mar 21 02:18:41 PM PDT 24
Finished Mar 21 02:21:45 PM PDT 24
Peak memory 272512 kb
Host smart-c45854cc-6421-44b8-b2b2-35835abfb7bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544454534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.2544454534
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.3437796483
Short name T724
Test name
Test status
Simulation time 713981954 ps
CPU time 7.38 seconds
Started Mar 21 02:18:30 PM PDT 24
Finished Mar 21 02:18:38 PM PDT 24
Peak memory 216064 kb
Host smart-6eb16f4d-ff49-4df3-8ecf-6d0e5b90e345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437796483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.3437796483
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.1926399290
Short name T668
Test name
Test status
Simulation time 4415008143 ps
CPU time 11.52 seconds
Started Mar 21 02:18:34 PM PDT 24
Finished Mar 21 02:18:46 PM PDT 24
Peak memory 216112 kb
Host smart-382c0a9b-adc2-44b8-b526-4828543d7cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926399290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.1926399290
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.3084760702
Short name T507
Test name
Test status
Simulation time 126697515 ps
CPU time 6.06 seconds
Started Mar 21 02:18:33 PM PDT 24
Finished Mar 21 02:18:39 PM PDT 24
Peak memory 216128 kb
Host smart-f4889eed-9f77-4d69-8b5f-09fb49d84d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084760702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.3084760702
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.1964443226
Short name T348
Test name
Test status
Simulation time 121294589 ps
CPU time 1.05 seconds
Started Mar 21 02:18:34 PM PDT 24
Finished Mar 21 02:18:35 PM PDT 24
Peak memory 205560 kb
Host smart-f9c6de26-dd79-4076-bebd-2c87da7921af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964443226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.1964443226
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.3021340
Short name T205
Test name
Test status
Simulation time 9117488615 ps
CPU time 8.72 seconds
Started Mar 21 02:18:45 PM PDT 24
Finished Mar 21 02:18:54 PM PDT 24
Peak memory 234000 kb
Host smart-1183b7b8-51b9-4e0b-8c56-a5b8f7f2b82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.3021340
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.2330787172
Short name T703
Test name
Test status
Simulation time 14587299 ps
CPU time 0.74 seconds
Started Mar 21 02:18:54 PM PDT 24
Finished Mar 21 02:18:55 PM PDT 24
Peak memory 205244 kb
Host smart-1777db90-a3a5-4af4-b414-cebcadc6a23e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330787172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
2330787172
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.3809327766
Short name T279
Test name
Test status
Simulation time 8577353585 ps
CPU time 6.37 seconds
Started Mar 21 02:18:41 PM PDT 24
Finished Mar 21 02:18:48 PM PDT 24
Peak memory 219792 kb
Host smart-bc19c7d8-3a04-4092-8b8e-2c051f9a0049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809327766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.3809327766
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.1417284670
Short name T591
Test name
Test status
Simulation time 55276237 ps
CPU time 0.82 seconds
Started Mar 21 02:18:42 PM PDT 24
Finished Mar 21 02:18:44 PM PDT 24
Peak memory 206292 kb
Host smart-6d17bd1c-c207-4f62-b8ae-ca91e102ad5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417284670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.1417284670
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.3714810301
Short name T735
Test name
Test status
Simulation time 65372641220 ps
CPU time 89.42 seconds
Started Mar 21 02:18:53 PM PDT 24
Finished Mar 21 02:20:22 PM PDT 24
Peak memory 248984 kb
Host smart-d801b337-4034-462f-93e2-0a4d68484a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714810301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.3714810301
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.1412025264
Short name T610
Test name
Test status
Simulation time 24165483722 ps
CPU time 35.62 seconds
Started Mar 21 02:18:55 PM PDT 24
Finished Mar 21 02:19:31 PM PDT 24
Peak memory 240096 kb
Host smart-0cb9811c-a4ff-4d61-a446-806a5cd5998f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412025264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.1412025264
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.159420203
Short name T751
Test name
Test status
Simulation time 368271320 ps
CPU time 3.16 seconds
Started Mar 21 02:18:41 PM PDT 24
Finished Mar 21 02:18:45 PM PDT 24
Peak memory 218428 kb
Host smart-781e8cdd-6b32-443f-ab88-6a3ac4f5b5ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159420203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.159420203
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.248370098
Short name T4
Test name
Test status
Simulation time 1680179746 ps
CPU time 9.07 seconds
Started Mar 21 02:18:43 PM PDT 24
Finished Mar 21 02:18:53 PM PDT 24
Peak memory 233920 kb
Host smart-30ccb71f-a327-46a0-99b8-590a65a5dce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248370098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.248370098
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.305516097
Short name T465
Test name
Test status
Simulation time 9327394852 ps
CPU time 24.04 seconds
Started Mar 21 02:18:42 PM PDT 24
Finished Mar 21 02:19:07 PM PDT 24
Peak memory 224304 kb
Host smart-7f56c073-686a-46e0-b0b2-028d4ed381f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305516097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap
.305516097
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.3648656255
Short name T689
Test name
Test status
Simulation time 12077470271 ps
CPU time 34.38 seconds
Started Mar 21 02:18:43 PM PDT 24
Finished Mar 21 02:19:18 PM PDT 24
Peak memory 234944 kb
Host smart-bca47259-2657-42ca-819d-efea7e93eb81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648656255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.3648656255
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_ram_cfg.500500353
Short name T809
Test name
Test status
Simulation time 31259280 ps
CPU time 0.75 seconds
Started Mar 21 02:18:46 PM PDT 24
Finished Mar 21 02:18:47 PM PDT 24
Peak memory 216020 kb
Host smart-3ae33274-af7b-48d2-8844-a27c0609c860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500500353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_ram_cfg.500500353
Directory /workspace/14.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.1753582597
Short name T715
Test name
Test status
Simulation time 405260592 ps
CPU time 3.37 seconds
Started Mar 21 02:18:56 PM PDT 24
Finished Mar 21 02:19:00 PM PDT 24
Peak memory 222256 kb
Host smart-16fdeb4e-6b40-4cec-86be-1c975d8ed2cd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1753582597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.1753582597
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.1162612877
Short name T60
Test name
Test status
Simulation time 1509961499736 ps
CPU time 662.59 seconds
Started Mar 21 02:18:55 PM PDT 24
Finished Mar 21 02:29:58 PM PDT 24
Peak memory 269628 kb
Host smart-4c6ce7a4-1318-4e8e-a5e6-76cbbdbbb58a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162612877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.1162612877
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.2350195846
Short name T475
Test name
Test status
Simulation time 1338472034 ps
CPU time 10.81 seconds
Started Mar 21 02:18:42 PM PDT 24
Finished Mar 21 02:18:54 PM PDT 24
Peak memory 216140 kb
Host smart-f151dced-35b8-49f1-b6a1-15e544d29761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350195846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.2350195846
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.2281972968
Short name T732
Test name
Test status
Simulation time 42967261146 ps
CPU time 38.65 seconds
Started Mar 21 02:18:43 PM PDT 24
Finished Mar 21 02:19:22 PM PDT 24
Peak memory 216152 kb
Host smart-f1577fdf-c47e-451d-bda1-97c475e10c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281972968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.2281972968
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.2462925083
Short name T420
Test name
Test status
Simulation time 65675287 ps
CPU time 1.8 seconds
Started Mar 21 02:18:43 PM PDT 24
Finished Mar 21 02:18:46 PM PDT 24
Peak memory 216108 kb
Host smart-3d7e3a3a-22b0-4cb1-8ad0-9944a33cb723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462925083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.2462925083
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.3192748976
Short name T959
Test name
Test status
Simulation time 63686768 ps
CPU time 0.82 seconds
Started Mar 21 02:18:43 PM PDT 24
Finished Mar 21 02:18:45 PM PDT 24
Peak memory 205624 kb
Host smart-41b1df2f-662d-4261-a53d-b78b5bda179b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192748976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.3192748976
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.1588166245
Short name T716
Test name
Test status
Simulation time 370603895 ps
CPU time 5.48 seconds
Started Mar 21 02:18:43 PM PDT 24
Finished Mar 21 02:18:49 PM PDT 24
Peak memory 234848 kb
Host smart-ab803a7e-a38a-4c3c-976a-5d836ceb478c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588166245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.1588166245
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.811478139
Short name T387
Test name
Test status
Simulation time 26909500 ps
CPU time 0.74 seconds
Started Mar 21 02:19:10 PM PDT 24
Finished Mar 21 02:19:11 PM PDT 24
Peak memory 205272 kb
Host smart-7bb7ed03-7013-41cd-beab-ebbb26490727
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811478139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.811478139
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.2779797652
Short name T444
Test name
Test status
Simulation time 39183507 ps
CPU time 2.35 seconds
Started Mar 21 02:18:54 PM PDT 24
Finished Mar 21 02:18:56 PM PDT 24
Peak memory 232572 kb
Host smart-3125ae8e-fda5-452d-a3ed-b3ec5e949758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779797652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.2779797652
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.1640992085
Short name T754
Test name
Test status
Simulation time 49929788 ps
CPU time 0.78 seconds
Started Mar 21 02:18:52 PM PDT 24
Finished Mar 21 02:18:53 PM PDT 24
Peak memory 205340 kb
Host smart-71e0b7e3-2550-49e7-8ce1-d51d78ecb7d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640992085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.1640992085
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.436327007
Short name T490
Test name
Test status
Simulation time 43339214656 ps
CPU time 101.25 seconds
Started Mar 21 02:18:53 PM PDT 24
Finished Mar 21 02:20:34 PM PDT 24
Peak memory 253040 kb
Host smart-c162e5a4-0d73-40be-a7b4-163b93846ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436327007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.436327007
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.500077884
Short name T964
Test name
Test status
Simulation time 10621365917 ps
CPU time 42.26 seconds
Started Mar 21 02:18:51 PM PDT 24
Finished Mar 21 02:19:34 PM PDT 24
Peak memory 238632 kb
Host smart-51c4a0ec-baef-4ada-bc89-15f8cc688383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500077884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.500077884
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.3238094526
Short name T843
Test name
Test status
Simulation time 54991720488 ps
CPU time 67.18 seconds
Started Mar 21 02:18:53 PM PDT 24
Finished Mar 21 02:20:00 PM PDT 24
Peak memory 254328 kb
Host smart-45a3ce43-6e3a-40d2-94e6-9106ee3c2d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238094526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.3238094526
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.965379687
Short name T910
Test name
Test status
Simulation time 4718575528 ps
CPU time 31.88 seconds
Started Mar 21 02:18:55 PM PDT 24
Finished Mar 21 02:19:28 PM PDT 24
Peak memory 243332 kb
Host smart-0dedc57e-e4ef-44a2-a0da-923af3631091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965379687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.965379687
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.2460169139
Short name T615
Test name
Test status
Simulation time 2965912839 ps
CPU time 8.43 seconds
Started Mar 21 02:18:53 PM PDT 24
Finished Mar 21 02:19:01 PM PDT 24
Peak memory 224380 kb
Host smart-99a8ae26-2d84-43ff-babd-1fc64246a395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460169139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.2460169139
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.3091061999
Short name T906
Test name
Test status
Simulation time 696622643 ps
CPU time 6.35 seconds
Started Mar 21 02:18:57 PM PDT 24
Finished Mar 21 02:19:05 PM PDT 24
Peak memory 224324 kb
Host smart-8472111c-ffe8-4d27-bd3d-730a085e4f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091061999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.3091061999
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.379423583
Short name T459
Test name
Test status
Simulation time 2360271557 ps
CPU time 3.37 seconds
Started Mar 21 02:18:54 PM PDT 24
Finished Mar 21 02:18:57 PM PDT 24
Peak memory 218356 kb
Host smart-12ad0067-ea92-44fe-a44c-43256715b4d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379423583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap
.379423583
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.2142130529
Short name T669
Test name
Test status
Simulation time 4836567903 ps
CPU time 8.13 seconds
Started Mar 21 02:18:56 PM PDT 24
Finished Mar 21 02:19:05 PM PDT 24
Peak memory 233620 kb
Host smart-f93fa915-15d6-4040-899c-74610db927c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142130529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.2142130529
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_ram_cfg.4058337208
Short name T555
Test name
Test status
Simulation time 46195320 ps
CPU time 0.72 seconds
Started Mar 21 02:18:54 PM PDT 24
Finished Mar 21 02:18:55 PM PDT 24
Peak memory 216088 kb
Host smart-1f8d980e-5a1b-4d2d-83c0-2014f7349eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058337208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_ram_cfg.4058337208
Directory /workspace/15.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.1543587606
Short name T125
Test name
Test status
Simulation time 3132584335 ps
CPU time 5.06 seconds
Started Mar 21 02:18:53 PM PDT 24
Finished Mar 21 02:18:58 PM PDT 24
Peak memory 222948 kb
Host smart-9682a6ba-024a-4e58-b4d4-4057d1f814e1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1543587606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.1543587606
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.440405374
Short name T136
Test name
Test status
Simulation time 2714098707 ps
CPU time 55.29 seconds
Started Mar 21 02:18:57 PM PDT 24
Finished Mar 21 02:19:52 PM PDT 24
Peak memory 257144 kb
Host smart-e8d91543-abe2-446c-ba48-a2f75d34e28a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440405374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stres
s_all.440405374
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.1869616659
Short name T39
Test name
Test status
Simulation time 5804651543 ps
CPU time 28.56 seconds
Started Mar 21 02:18:54 PM PDT 24
Finished Mar 21 02:19:22 PM PDT 24
Peak memory 216136 kb
Host smart-d738b55d-8eac-4171-9547-1d69cbdd57b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869616659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.1869616659
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.1391803580
Short name T14
Test name
Test status
Simulation time 6937332218 ps
CPU time 17.55 seconds
Started Mar 21 02:18:55 PM PDT 24
Finished Mar 21 02:19:13 PM PDT 24
Peak memory 216140 kb
Host smart-7acdb62c-d76f-4fd5-9a26-30c2225588de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391803580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.1391803580
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.185307235
Short name T632
Test name
Test status
Simulation time 62455773 ps
CPU time 0.93 seconds
Started Mar 21 02:18:53 PM PDT 24
Finished Mar 21 02:18:54 PM PDT 24
Peak memory 206648 kb
Host smart-234476a5-95ea-4897-acbc-988e72eb05b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185307235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.185307235
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.738725202
Short name T710
Test name
Test status
Simulation time 69011711 ps
CPU time 0.83 seconds
Started Mar 21 02:18:56 PM PDT 24
Finished Mar 21 02:18:57 PM PDT 24
Peak memory 205592 kb
Host smart-5a4a9c02-4166-4e71-af06-e7af15d778e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738725202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.738725202
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.2632489618
Short name T478
Test name
Test status
Simulation time 6684608212 ps
CPU time 8.96 seconds
Started Mar 21 02:18:52 PM PDT 24
Finished Mar 21 02:19:02 PM PDT 24
Peak memory 233892 kb
Host smart-ab47500b-b7df-45de-871a-51bda40fdda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632489618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.2632489618
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.3848099839
Short name T709
Test name
Test status
Simulation time 63088547 ps
CPU time 0.73 seconds
Started Mar 21 02:19:30 PM PDT 24
Finished Mar 21 02:19:31 PM PDT 24
Peak memory 205584 kb
Host smart-fc1e5d31-f81d-454f-8e48-8b85ba4edbda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848099839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
3848099839
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.4216597205
Short name T924
Test name
Test status
Simulation time 1098737425 ps
CPU time 5.38 seconds
Started Mar 21 02:19:28 PM PDT 24
Finished Mar 21 02:19:33 PM PDT 24
Peak memory 233692 kb
Host smart-ff85b4c9-54ab-4a09-9b62-1a1cf4ebcaca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216597205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.4216597205
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.3104912674
Short name T363
Test name
Test status
Simulation time 154266956 ps
CPU time 0.78 seconds
Started Mar 21 02:19:08 PM PDT 24
Finished Mar 21 02:19:09 PM PDT 24
Peak memory 205264 kb
Host smart-14d3ea91-c474-4392-8cbe-5855e81a6a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104912674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.3104912674
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.3203343278
Short name T469
Test name
Test status
Simulation time 8377871559 ps
CPU time 42.33 seconds
Started Mar 21 02:19:29 PM PDT 24
Finished Mar 21 02:20:12 PM PDT 24
Peak memory 234556 kb
Host smart-4aec1aa4-0087-408c-b22d-f0bb1c0343ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203343278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.3203343278
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.2085374008
Short name T21
Test name
Test status
Simulation time 2394584002 ps
CPU time 33.25 seconds
Started Mar 21 02:19:29 PM PDT 24
Finished Mar 21 02:20:02 PM PDT 24
Peak memory 233696 kb
Host smart-c1b33d82-bc43-4c09-9104-12df0fb8a813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085374008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.2085374008
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.293906428
Short name T852
Test name
Test status
Simulation time 3547519868 ps
CPU time 16.51 seconds
Started Mar 21 02:19:29 PM PDT 24
Finished Mar 21 02:19:46 PM PDT 24
Peak memory 239288 kb
Host smart-8253b4f4-6e81-4e2d-9431-03db4d04cb54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293906428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.293906428
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.1838862195
Short name T538
Test name
Test status
Simulation time 5984296909 ps
CPU time 10.38 seconds
Started Mar 21 02:19:09 PM PDT 24
Finished Mar 21 02:19:19 PM PDT 24
Peak memory 220184 kb
Host smart-8a3b1620-2c0c-43b8-97ca-d342e68e8af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838862195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.1838862195
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.291729429
Short name T814
Test name
Test status
Simulation time 5867600925 ps
CPU time 19.12 seconds
Started Mar 21 02:19:07 PM PDT 24
Finished Mar 21 02:19:27 PM PDT 24
Peak memory 231512 kb
Host smart-fd556292-037c-4b2c-8da4-e8a63d421bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291729429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.291729429
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.2358235920
Short name T817
Test name
Test status
Simulation time 443906668 ps
CPU time 3.41 seconds
Started Mar 21 02:19:08 PM PDT 24
Finished Mar 21 02:19:12 PM PDT 24
Peak memory 234408 kb
Host smart-9e5bf734-79df-45f5-b00a-b5286e3e7b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358235920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.2358235920
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.3802351849
Short name T321
Test name
Test status
Simulation time 463147791 ps
CPU time 5.83 seconds
Started Mar 21 02:19:07 PM PDT 24
Finished Mar 21 02:19:13 PM PDT 24
Peak memory 240720 kb
Host smart-735787af-a690-423f-9366-10510e4c6c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802351849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.3802351849
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_ram_cfg.2503975527
Short name T524
Test name
Test status
Simulation time 15755035 ps
CPU time 0.74 seconds
Started Mar 21 02:19:09 PM PDT 24
Finished Mar 21 02:19:10 PM PDT 24
Peak memory 216140 kb
Host smart-a6338f0e-2511-4b7e-ade9-d00850d2f5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503975527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_ram_cfg.2503975527
Directory /workspace/16.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.1225306318
Short name T307
Test name
Test status
Simulation time 10464171616 ps
CPU time 6.48 seconds
Started Mar 21 02:19:28 PM PDT 24
Finished Mar 21 02:19:34 PM PDT 24
Peak memory 220124 kb
Host smart-7b03069f-e6e7-4b0b-9f70-13460513f153
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1225306318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.1225306318
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.3841575895
Short name T142
Test name
Test status
Simulation time 69557700 ps
CPU time 1.18 seconds
Started Mar 21 02:19:29 PM PDT 24
Finished Mar 21 02:19:30 PM PDT 24
Peak memory 206856 kb
Host smart-c731ff9b-d21d-4547-9c87-34d410367abe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841575895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.3841575895
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.3145424400
Short name T273
Test name
Test status
Simulation time 96620065151 ps
CPU time 47.11 seconds
Started Mar 21 02:19:07 PM PDT 24
Finished Mar 21 02:19:54 PM PDT 24
Peak memory 216204 kb
Host smart-ee660d5b-cd01-4c59-bbf2-32b6992ffe15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145424400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.3145424400
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.2746031785
Short name T312
Test name
Test status
Simulation time 1121054883 ps
CPU time 8.13 seconds
Started Mar 21 02:19:08 PM PDT 24
Finished Mar 21 02:19:17 PM PDT 24
Peak memory 216072 kb
Host smart-1abc11ba-31cd-46bb-9943-e2201178cd27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746031785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.2746031785
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.3071161192
Short name T532
Test name
Test status
Simulation time 42578817 ps
CPU time 1.48 seconds
Started Mar 21 02:19:09 PM PDT 24
Finished Mar 21 02:19:11 PM PDT 24
Peak memory 207900 kb
Host smart-d5c471ca-dc38-4bf3-8bd0-e87326a1a115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071161192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.3071161192
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.2135077148
Short name T75
Test name
Test status
Simulation time 56918975 ps
CPU time 0.84 seconds
Started Mar 21 02:19:07 PM PDT 24
Finished Mar 21 02:19:08 PM PDT 24
Peak memory 205592 kb
Host smart-6c7c82a7-68e2-4b75-af54-fea831934cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135077148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.2135077148
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.3158966605
Short name T793
Test name
Test status
Simulation time 4814980348 ps
CPU time 7.17 seconds
Started Mar 21 02:19:30 PM PDT 24
Finished Mar 21 02:19:37 PM PDT 24
Peak memory 219996 kb
Host smart-07f97b00-4059-4cec-ae9c-f4bb0750edec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158966605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.3158966605
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.3460375002
Short name T484
Test name
Test status
Simulation time 49015790 ps
CPU time 0.79 seconds
Started Mar 21 02:19:32 PM PDT 24
Finished Mar 21 02:19:33 PM PDT 24
Peak memory 205232 kb
Host smart-95645c0c-756e-4ef8-b1c7-904e13332e82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460375002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
3460375002
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.835798285
Short name T494
Test name
Test status
Simulation time 2144334316 ps
CPU time 6.33 seconds
Started Mar 21 02:19:31 PM PDT 24
Finished Mar 21 02:19:37 PM PDT 24
Peak memory 233532 kb
Host smart-06853027-9487-47c1-b3f9-6fcca10cb7bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835798285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.835798285
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.2526579480
Short name T631
Test name
Test status
Simulation time 15719674 ps
CPU time 0.81 seconds
Started Mar 21 02:19:29 PM PDT 24
Finished Mar 21 02:19:30 PM PDT 24
Peak memory 206324 kb
Host smart-fe5f51f2-d84c-4c9c-9e19-244c33a81124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526579480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.2526579480
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.2167899540
Short name T22
Test name
Test status
Simulation time 37991693959 ps
CPU time 82.91 seconds
Started Mar 21 02:19:29 PM PDT 24
Finished Mar 21 02:20:52 PM PDT 24
Peak memory 250228 kb
Host smart-d50b0efb-5452-47c8-badc-de335eed407f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167899540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.2167899540
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.2125565539
Short name T256
Test name
Test status
Simulation time 418788018941 ps
CPU time 478.05 seconds
Started Mar 21 02:19:27 PM PDT 24
Finished Mar 21 02:27:25 PM PDT 24
Peak memory 250132 kb
Host smart-a76decdc-249f-4c95-a73e-5c9735801fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125565539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.2125565539
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.1263162431
Short name T760
Test name
Test status
Simulation time 200787017177 ps
CPU time 341.64 seconds
Started Mar 21 02:19:31 PM PDT 24
Finished Mar 21 02:25:12 PM PDT 24
Peak memory 273536 kb
Host smart-a8006ca6-46cd-4bd6-a4d3-93f25710a039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263162431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.1263162431
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.36530328
Short name T514
Test name
Test status
Simulation time 1480502268 ps
CPU time 9.5 seconds
Started Mar 21 02:19:28 PM PDT 24
Finished Mar 21 02:19:38 PM PDT 24
Peak memory 234820 kb
Host smart-c88c6ce8-a2f8-4bf9-9a44-7a36c7036ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36530328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.36530328
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.3316237865
Short name T176
Test name
Test status
Simulation time 467108654 ps
CPU time 5.89 seconds
Started Mar 21 02:19:30 PM PDT 24
Finished Mar 21 02:19:36 PM PDT 24
Peak memory 236736 kb
Host smart-90384242-791d-4a9d-8471-32e51958059b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316237865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.3316237865
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.3761689768
Short name T202
Test name
Test status
Simulation time 4685868154 ps
CPU time 14.75 seconds
Started Mar 21 02:19:29 PM PDT 24
Finished Mar 21 02:19:44 PM PDT 24
Peak memory 233416 kb
Host smart-3fb0812e-230e-47b5-b121-09223486f9c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761689768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.3761689768
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.172604596
Short name T251
Test name
Test status
Simulation time 106378535 ps
CPU time 2.35 seconds
Started Mar 21 02:19:30 PM PDT 24
Finished Mar 21 02:19:32 PM PDT 24
Peak memory 232496 kb
Host smart-89b04727-ceab-4fff-a07a-1e86b4a4a849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172604596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap
.172604596
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.2523593302
Short name T896
Test name
Test status
Simulation time 958311214 ps
CPU time 4.77 seconds
Started Mar 21 02:19:28 PM PDT 24
Finished Mar 21 02:19:33 PM PDT 24
Peak memory 232592 kb
Host smart-2b5bc122-0e20-4814-8e99-91b685bea3b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523593302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.2523593302
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_ram_cfg.3333759297
Short name T512
Test name
Test status
Simulation time 74433119 ps
CPU time 0.75 seconds
Started Mar 21 02:19:29 PM PDT 24
Finished Mar 21 02:19:29 PM PDT 24
Peak memory 216040 kb
Host smart-5c716a21-6b46-4039-9b9d-f285c06f9664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333759297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_ram_cfg.3333759297
Directory /workspace/17.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.2301605753
Short name T124
Test name
Test status
Simulation time 1971283054 ps
CPU time 7.73 seconds
Started Mar 21 02:19:30 PM PDT 24
Finished Mar 21 02:19:37 PM PDT 24
Peak memory 222796 kb
Host smart-6ebea355-c058-4dc5-a40b-0dbb6f4fe1ae
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2301605753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.2301605753
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.2548467124
Short name T189
Test name
Test status
Simulation time 273585327337 ps
CPU time 598.67 seconds
Started Mar 21 02:19:29 PM PDT 24
Finished Mar 21 02:29:28 PM PDT 24
Peak memory 282236 kb
Host smart-8469b9dc-e469-4ab3-8d65-09fc3c26975a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548467124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.2548467124
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.2255674176
Short name T782
Test name
Test status
Simulation time 2746891545 ps
CPU time 13.11 seconds
Started Mar 21 02:19:29 PM PDT 24
Finished Mar 21 02:19:42 PM PDT 24
Peak memory 219652 kb
Host smart-987d981d-4b7a-43e3-a056-ec521c41cb7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255674176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.2255674176
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.2353315848
Short name T329
Test name
Test status
Simulation time 8690554987 ps
CPU time 9.87 seconds
Started Mar 21 02:19:31 PM PDT 24
Finished Mar 21 02:19:41 PM PDT 24
Peak memory 216176 kb
Host smart-d97483c8-760e-49c0-b120-652060831991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353315848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.2353315848
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.3035257196
Short name T756
Test name
Test status
Simulation time 473126531 ps
CPU time 4.45 seconds
Started Mar 21 02:19:28 PM PDT 24
Finished Mar 21 02:19:32 PM PDT 24
Peak memory 216032 kb
Host smart-e0a21f4e-9210-4fd9-a587-b146a33583bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035257196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.3035257196
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.4293534547
Short name T511
Test name
Test status
Simulation time 112943074 ps
CPU time 1.1 seconds
Started Mar 21 02:19:27 PM PDT 24
Finished Mar 21 02:19:28 PM PDT 24
Peak memory 206580 kb
Host smart-8c1efaf2-5ce1-46c9-a52a-13f7a35bfaf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293534547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.4293534547
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.942553850
Short name T209
Test name
Test status
Simulation time 10350472406 ps
CPU time 17.35 seconds
Started Mar 21 02:19:28 PM PDT 24
Finished Mar 21 02:19:45 PM PDT 24
Peak memory 219660 kb
Host smart-d7f4c6bb-5fcb-4b9a-978d-4fcd3b23724c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942553850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.942553850
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.3949515533
Short name T745
Test name
Test status
Simulation time 51080244 ps
CPU time 0.75 seconds
Started Mar 21 02:19:46 PM PDT 24
Finished Mar 21 02:19:47 PM PDT 24
Peak memory 204664 kb
Host smart-b9ec3dba-b768-46ff-b680-00395b2ba7cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949515533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
3949515533
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.3817811339
Short name T320
Test name
Test status
Simulation time 5513180623 ps
CPU time 4.96 seconds
Started Mar 21 02:19:45 PM PDT 24
Finished Mar 21 02:19:51 PM PDT 24
Peak memory 217848 kb
Host smart-5582786c-72be-406a-9b92-489c8543981e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817811339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.3817811339
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.2346490372
Short name T399
Test name
Test status
Simulation time 17069269 ps
CPU time 0.81 seconds
Started Mar 21 02:19:31 PM PDT 24
Finished Mar 21 02:19:32 PM PDT 24
Peak memory 206340 kb
Host smart-77e94ec7-6880-4433-8754-c19adaaf14a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346490372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2346490372
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.3869772891
Short name T898
Test name
Test status
Simulation time 9387235615 ps
CPU time 129.14 seconds
Started Mar 21 02:19:44 PM PDT 24
Finished Mar 21 02:21:53 PM PDT 24
Peak memory 257204 kb
Host smart-382641f0-361e-4628-889f-dd325dde14be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869772891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.3869772891
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.3705379555
Short name T833
Test name
Test status
Simulation time 15509876941 ps
CPU time 118.62 seconds
Started Mar 21 02:19:45 PM PDT 24
Finished Mar 21 02:21:44 PM PDT 24
Peak memory 251952 kb
Host smart-c3ca6139-0539-4913-a2ef-7ab52411d28e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705379555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.3705379555
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.1359800864
Short name T345
Test name
Test status
Simulation time 18189795819 ps
CPU time 25.53 seconds
Started Mar 21 02:19:46 PM PDT 24
Finished Mar 21 02:20:12 PM PDT 24
Peak memory 240668 kb
Host smart-13c4b04a-2ba5-4b90-bff2-275d24076d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359800864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.1359800864
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.1107853853
Short name T174
Test name
Test status
Simulation time 482588127 ps
CPU time 4.78 seconds
Started Mar 21 02:19:43 PM PDT 24
Finished Mar 21 02:19:48 PM PDT 24
Peak memory 233392 kb
Host smart-2364628e-a8b9-4967-a3a3-c202adfafee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107853853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.1107853853
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.853326599
Short name T456
Test name
Test status
Simulation time 9862029701 ps
CPU time 29.93 seconds
Started Mar 21 02:19:43 PM PDT 24
Finished Mar 21 02:20:13 PM PDT 24
Peak memory 229288 kb
Host smart-c671a930-17a5-433e-82e2-e082f5aca2e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853326599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.853326599
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.1435944808
Short name T944
Test name
Test status
Simulation time 17880017989 ps
CPU time 22.04 seconds
Started Mar 21 02:19:44 PM PDT 24
Finished Mar 21 02:20:06 PM PDT 24
Peak memory 229208 kb
Host smart-6f4fb3c0-30c1-47fc-ae13-20fc4347d42d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435944808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.1435944808
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.2412085854
Short name T140
Test name
Test status
Simulation time 1108025171 ps
CPU time 4.07 seconds
Started Mar 21 02:19:46 PM PDT 24
Finished Mar 21 02:19:50 PM PDT 24
Peak memory 226368 kb
Host smart-94d04729-21d5-4cb6-8dec-d4678d49a032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412085854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.2412085854
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_ram_cfg.1297511672
Short name T803
Test name
Test status
Simulation time 19534761 ps
CPU time 0.77 seconds
Started Mar 21 02:19:27 PM PDT 24
Finished Mar 21 02:19:29 PM PDT 24
Peak memory 216072 kb
Host smart-4d3af8de-13b6-40c2-8b46-dad33e16c3ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297511672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_ram_cfg.1297511672
Directory /workspace/18.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.2060870848
Short name T544
Test name
Test status
Simulation time 3299157997 ps
CPU time 5.4 seconds
Started Mar 21 02:19:46 PM PDT 24
Finished Mar 21 02:19:52 PM PDT 24
Peak memory 222868 kb
Host smart-bee09895-5b69-43c9-bcc8-84d6e93ce2d4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2060870848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.2060870848
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.580062525
Short name T48
Test name
Test status
Simulation time 230208760384 ps
CPU time 892.79 seconds
Started Mar 21 02:19:45 PM PDT 24
Finished Mar 21 02:34:38 PM PDT 24
Peak memory 287412 kb
Host smart-2959df06-71ee-4b33-95f0-e31c852ef657
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580062525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stres
s_all.580062525
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.2090799685
Short name T927
Test name
Test status
Simulation time 26062200317 ps
CPU time 28.23 seconds
Started Mar 21 02:19:45 PM PDT 24
Finished Mar 21 02:20:13 PM PDT 24
Peak memory 216128 kb
Host smart-9dbf90d1-3607-4ff3-9899-02d0d297f6b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090799685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.2090799685
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.2618611507
Short name T831
Test name
Test status
Simulation time 1233856898 ps
CPU time 1.88 seconds
Started Mar 21 02:19:28 PM PDT 24
Finished Mar 21 02:19:31 PM PDT 24
Peak memory 207800 kb
Host smart-12fa6eb2-f173-4164-ae06-5e8fd306d164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618611507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.2618611507
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.3615585497
Short name T742
Test name
Test status
Simulation time 1363596696 ps
CPU time 1.94 seconds
Started Mar 21 02:19:43 PM PDT 24
Finished Mar 21 02:19:45 PM PDT 24
Peak memory 216036 kb
Host smart-2906c2a0-8cfd-40bb-a3ba-12491b56fd4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615585497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.3615585497
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.1345357582
Short name T380
Test name
Test status
Simulation time 238272776 ps
CPU time 0.9 seconds
Started Mar 21 02:19:45 PM PDT 24
Finished Mar 21 02:19:46 PM PDT 24
Peak memory 205604 kb
Host smart-f10e54cf-b6a3-44b5-9bc4-ebb1a8871281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345357582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.1345357582
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.1914278711
Short name T182
Test name
Test status
Simulation time 4999709397 ps
CPU time 20.58 seconds
Started Mar 21 02:19:45 PM PDT 24
Finished Mar 21 02:20:05 PM PDT 24
Peak memory 230368 kb
Host smart-ace14eed-cf3a-4b0f-b3b9-db40e31a1f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914278711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.1914278711
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.1796529644
Short name T677
Test name
Test status
Simulation time 46402363 ps
CPU time 0.68 seconds
Started Mar 21 02:19:46 PM PDT 24
Finished Mar 21 02:19:47 PM PDT 24
Peak memory 205252 kb
Host smart-b0f27ad4-dacd-4953-aeb3-92c54e17cd22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796529644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
1796529644
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.3958053595
Short name T861
Test name
Test status
Simulation time 1492372451 ps
CPU time 4.46 seconds
Started Mar 21 02:19:45 PM PDT 24
Finished Mar 21 02:19:50 PM PDT 24
Peak memory 219140 kb
Host smart-f3eb46ad-2305-4e9f-9964-f0eda07df353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958053595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.3958053595
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.3714838963
Short name T15
Test name
Test status
Simulation time 20034872 ps
CPU time 0.82 seconds
Started Mar 21 02:19:45 PM PDT 24
Finished Mar 21 02:19:46 PM PDT 24
Peak memory 206324 kb
Host smart-705cce16-6f74-4a14-a714-b64c56c121e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714838963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.3714838963
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.534066655
Short name T867
Test name
Test status
Simulation time 19504411272 ps
CPU time 29.79 seconds
Started Mar 21 02:19:45 PM PDT 24
Finished Mar 21 02:20:15 PM PDT 24
Peak memory 239284 kb
Host smart-ea9af4db-55d9-4a08-9633-e3f69ce42e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534066655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.534066655
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.1454523730
Short name T774
Test name
Test status
Simulation time 32009153597 ps
CPU time 136.19 seconds
Started Mar 21 02:19:44 PM PDT 24
Finished Mar 21 02:22:00 PM PDT 24
Peak memory 257300 kb
Host smart-adf27589-8b06-4727-b422-9abd9bdbbdd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454523730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.1454523730
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.13820589
Short name T497
Test name
Test status
Simulation time 3471070761 ps
CPU time 71.6 seconds
Started Mar 21 02:19:44 PM PDT 24
Finished Mar 21 02:20:56 PM PDT 24
Peak memory 250196 kb
Host smart-ab548d8c-be22-473a-a11b-62a338582377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13820589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle.13820589
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.2592736336
Short name T455
Test name
Test status
Simulation time 871355813 ps
CPU time 15.17 seconds
Started Mar 21 02:19:44 PM PDT 24
Finished Mar 21 02:19:59 PM PDT 24
Peak memory 240464 kb
Host smart-2df87562-bfd6-477e-89d0-7c2cabb799e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592736336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.2592736336
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.1700924418
Short name T725
Test name
Test status
Simulation time 1203756230 ps
CPU time 4.53 seconds
Started Mar 21 02:19:43 PM PDT 24
Finished Mar 21 02:19:48 PM PDT 24
Peak memory 233656 kb
Host smart-36cbbd17-0e66-480b-8e90-f4bf877d8878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700924418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.1700924418
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.3637955160
Short name T880
Test name
Test status
Simulation time 1910409413 ps
CPU time 11.52 seconds
Started Mar 21 02:19:44 PM PDT 24
Finished Mar 21 02:19:56 PM PDT 24
Peak memory 217924 kb
Host smart-c4bf777c-3834-4cd0-b95c-b5cc4b0b9d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637955160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.3637955160
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.1524929460
Short name T31
Test name
Test status
Simulation time 31288632222 ps
CPU time 37.78 seconds
Started Mar 21 02:19:46 PM PDT 24
Finished Mar 21 02:20:25 PM PDT 24
Peak memory 235144 kb
Host smart-ad8f6609-e342-455e-875d-2fba7eb19c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524929460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.1524929460
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.3515455842
Short name T958
Test name
Test status
Simulation time 7027457511 ps
CPU time 7.22 seconds
Started Mar 21 02:19:45 PM PDT 24
Finished Mar 21 02:19:52 PM PDT 24
Peak memory 220716 kb
Host smart-0884c0ae-7447-461c-972d-230929702c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515455842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.3515455842
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_ram_cfg.1185064941
Short name T848
Test name
Test status
Simulation time 35302709 ps
CPU time 0.71 seconds
Started Mar 21 02:19:44 PM PDT 24
Finished Mar 21 02:19:45 PM PDT 24
Peak memory 216096 kb
Host smart-ac9e1e61-61dd-452b-87d8-cbec313c5bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185064941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_ram_cfg.1185064941
Directory /workspace/19.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.257129126
Short name T480
Test name
Test status
Simulation time 1268975782 ps
CPU time 5.74 seconds
Started Mar 21 02:19:45 PM PDT 24
Finished Mar 21 02:19:50 PM PDT 24
Peak memory 220388 kb
Host smart-ef3cf0f2-1be9-4e70-a605-8a5bc5b7190e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=257129126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dire
ct.257129126
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.922575282
Short name T932
Test name
Test status
Simulation time 160724627 ps
CPU time 1.02 seconds
Started Mar 21 02:19:45 PM PDT 24
Finished Mar 21 02:19:46 PM PDT 24
Peak memory 206460 kb
Host smart-dc9822f5-4ca8-4b27-abae-9b2042644307
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922575282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stres
s_all.922575282
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.556946022
Short name T805
Test name
Test status
Simulation time 4198990889 ps
CPU time 7.23 seconds
Started Mar 21 02:19:45 PM PDT 24
Finished Mar 21 02:19:52 PM PDT 24
Peak memory 216204 kb
Host smart-af38f526-6273-4837-8612-78491b104a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556946022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.556946022
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.3097437866
Short name T955
Test name
Test status
Simulation time 14263435723 ps
CPU time 41.01 seconds
Started Mar 21 02:19:42 PM PDT 24
Finished Mar 21 02:20:23 PM PDT 24
Peak memory 216104 kb
Host smart-927629ce-22fb-4259-a351-66d16647503a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097437866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.3097437866
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.1229364325
Short name T708
Test name
Test status
Simulation time 428477329 ps
CPU time 2.21 seconds
Started Mar 21 02:19:44 PM PDT 24
Finished Mar 21 02:19:46 PM PDT 24
Peak memory 216228 kb
Host smart-4c1b79fe-75f8-4e25-82a1-009da120d3b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229364325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.1229364325
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.3230638767
Short name T875
Test name
Test status
Simulation time 96884319 ps
CPU time 0.97 seconds
Started Mar 21 02:19:45 PM PDT 24
Finished Mar 21 02:19:46 PM PDT 24
Peak memory 206584 kb
Host smart-af093193-f7f1-4102-8c94-065f11e66d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230638767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.3230638767
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.1583913822
Short name T616
Test name
Test status
Simulation time 983107706 ps
CPU time 9.16 seconds
Started Mar 21 02:19:45 PM PDT 24
Finished Mar 21 02:19:54 PM PDT 24
Peak memory 222580 kb
Host smart-28f10fa2-ce22-41fc-8295-a61056870ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583913822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.1583913822
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.2540256770
Short name T311
Test name
Test status
Simulation time 12069554 ps
CPU time 0.73 seconds
Started Mar 21 02:16:27 PM PDT 24
Finished Mar 21 02:16:28 PM PDT 24
Peak memory 205248 kb
Host smart-a88cdb0e-551c-4500-b4a6-865a36fe8769
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540256770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.2
540256770
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.594636340
Short name T278
Test name
Test status
Simulation time 1855634039 ps
CPU time 5.31 seconds
Started Mar 21 02:16:24 PM PDT 24
Finished Mar 21 02:16:30 PM PDT 24
Peak memory 219172 kb
Host smart-70e146c2-2d60-4ac3-95ea-a879ca300126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594636340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.594636340
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.3132852391
Short name T461
Test name
Test status
Simulation time 14152215 ps
CPU time 0.77 seconds
Started Mar 21 02:16:27 PM PDT 24
Finished Mar 21 02:16:28 PM PDT 24
Peak memory 206676 kb
Host smart-48e1b345-5061-4f3f-ae75-86b49032fe6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132852391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.3132852391
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.1591457886
Short name T961
Test name
Test status
Simulation time 97513164716 ps
CPU time 488.89 seconds
Started Mar 21 02:16:24 PM PDT 24
Finished Mar 21 02:24:33 PM PDT 24
Peak memory 260048 kb
Host smart-0ac421a1-01c2-4e09-a6a1-7566f63fa670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591457886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.1591457886
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.2746227018
Short name T537
Test name
Test status
Simulation time 3734687925 ps
CPU time 77.32 seconds
Started Mar 21 02:16:25 PM PDT 24
Finished Mar 21 02:17:42 PM PDT 24
Peak memory 255392 kb
Host smart-ec9d4cca-b38c-40f9-9ec0-c99277eee972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746227018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.2746227018
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.2671467585
Short name T887
Test name
Test status
Simulation time 143685184548 ps
CPU time 513.42 seconds
Started Mar 21 02:16:30 PM PDT 24
Finished Mar 21 02:25:03 PM PDT 24
Peak memory 267912 kb
Host smart-535ecc6d-5680-4072-bd01-a2cd714cdd4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671467585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.2671467585
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.3290114482
Short name T878
Test name
Test status
Simulation time 3123310446 ps
CPU time 28.69 seconds
Started Mar 21 02:16:27 PM PDT 24
Finished Mar 21 02:16:56 PM PDT 24
Peak memory 249056 kb
Host smart-7886de03-2aed-4d80-b8d8-841c69ed6a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290114482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.3290114482
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.2138943132
Short name T630
Test name
Test status
Simulation time 147909431 ps
CPU time 2.71 seconds
Started Mar 21 02:16:22 PM PDT 24
Finished Mar 21 02:16:25 PM PDT 24
Peak memory 217524 kb
Host smart-5fa089ba-2b9d-4837-a67e-6c8f3d1e05a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138943132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.2138943132
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.182171333
Short name T153
Test name
Test status
Simulation time 80610854569 ps
CPU time 49.51 seconds
Started Mar 21 02:16:26 PM PDT 24
Finished Mar 21 02:17:15 PM PDT 24
Peak memory 235464 kb
Host smart-64ab3a70-f25e-4d7d-a873-5640107f9b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182171333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.182171333
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.578603877
Short name T580
Test name
Test status
Simulation time 5553127053 ps
CPU time 17.72 seconds
Started Mar 21 02:16:27 PM PDT 24
Finished Mar 21 02:16:44 PM PDT 24
Peak memory 233484 kb
Host smart-3eacf8fb-f851-4a5b-9254-688739e9e3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578603877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.
578603877
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.1702341336
Short name T812
Test name
Test status
Simulation time 7381048607 ps
CPU time 10.13 seconds
Started Mar 21 02:16:26 PM PDT 24
Finished Mar 21 02:16:36 PM PDT 24
Peak memory 238368 kb
Host smart-ff1d9737-7a54-482b-b83e-88651afe4dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702341336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.1702341336
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_ram_cfg.732826599
Short name T951
Test name
Test status
Simulation time 16464168 ps
CPU time 0.75 seconds
Started Mar 21 02:16:24 PM PDT 24
Finished Mar 21 02:16:25 PM PDT 24
Peak memory 215996 kb
Host smart-10963ab3-f214-428f-bcee-eb99cfe3ae04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732826599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_ram_cfg.732826599
Directory /workspace/2.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.1078048103
Short name T562
Test name
Test status
Simulation time 2933845502 ps
CPU time 5.64 seconds
Started Mar 21 02:16:28 PM PDT 24
Finished Mar 21 02:16:33 PM PDT 24
Peak memory 222796 kb
Host smart-671d7b9e-68d4-45bd-ac75-e6afc9993ff5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1078048103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.1078048103
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.4210342279
Short name T67
Test name
Test status
Simulation time 50967243 ps
CPU time 0.96 seconds
Started Mar 21 02:16:26 PM PDT 24
Finished Mar 21 02:16:27 PM PDT 24
Peak memory 234400 kb
Host smart-53427c4f-6520-4b97-b30c-dabce2b51ee1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210342279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.4210342279
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.1261710194
Short name T813
Test name
Test status
Simulation time 58414638934 ps
CPU time 122.98 seconds
Started Mar 21 02:16:25 PM PDT 24
Finished Mar 21 02:18:28 PM PDT 24
Peak memory 249196 kb
Host smart-8970daa9-8273-46df-8b27-939e55016826
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261710194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.1261710194
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.2013757794
Short name T865
Test name
Test status
Simulation time 7697170613 ps
CPU time 17.6 seconds
Started Mar 21 02:16:26 PM PDT 24
Finished Mar 21 02:16:44 PM PDT 24
Peak memory 217616 kb
Host smart-99390a7c-1281-4ad6-802c-d83bafab0e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013757794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.2013757794
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.1342524994
Short name T908
Test name
Test status
Simulation time 1189267797 ps
CPU time 7 seconds
Started Mar 21 02:16:25 PM PDT 24
Finished Mar 21 02:16:33 PM PDT 24
Peak memory 216032 kb
Host smart-a98351b3-cdb2-4ee3-8c65-e60d4ea2b0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342524994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.1342524994
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.2876036923
Short name T536
Test name
Test status
Simulation time 75734530 ps
CPU time 4.38 seconds
Started Mar 21 02:16:28 PM PDT 24
Finished Mar 21 02:16:32 PM PDT 24
Peak memory 216192 kb
Host smart-120c7bea-4042-457a-af41-b506bc7260fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876036923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.2876036923
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.3140432350
Short name T402
Test name
Test status
Simulation time 63684072 ps
CPU time 0.91 seconds
Started Mar 21 02:16:30 PM PDT 24
Finished Mar 21 02:16:31 PM PDT 24
Peak memory 205600 kb
Host smart-1ff3701d-37b1-4613-b12e-96d2d4dde30e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140432350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.3140432350
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.3417499679
Short name T525
Test name
Test status
Simulation time 5658359840 ps
CPU time 8.21 seconds
Started Mar 21 02:16:28 PM PDT 24
Finished Mar 21 02:16:36 PM PDT 24
Peak memory 218628 kb
Host smart-d6642056-5f73-44cc-aa94-20154e7e163e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417499679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.3417499679
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.1409669756
Short name T436
Test name
Test status
Simulation time 38773125 ps
CPU time 0.74 seconds
Started Mar 21 02:19:58 PM PDT 24
Finished Mar 21 02:19:59 PM PDT 24
Peak memory 204680 kb
Host smart-8c182f0f-ab8d-41e1-a8cc-1bae4f718ed2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409669756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
1409669756
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.3441981469
Short name T450
Test name
Test status
Simulation time 42013130 ps
CPU time 2.78 seconds
Started Mar 21 02:19:57 PM PDT 24
Finished Mar 21 02:20:00 PM PDT 24
Peak memory 233528 kb
Host smart-a1962bf0-ce59-4c30-b6be-41527981b4fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441981469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.3441981469
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.2356606947
Short name T452
Test name
Test status
Simulation time 35338089 ps
CPU time 0.76 seconds
Started Mar 21 02:19:54 PM PDT 24
Finished Mar 21 02:19:55 PM PDT 24
Peak memory 206668 kb
Host smart-25a1584e-ce2f-4806-894d-e8e2f142947f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356606947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.2356606947
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.3154095725
Short name T240
Test name
Test status
Simulation time 20939915165 ps
CPU time 138.62 seconds
Started Mar 21 02:19:58 PM PDT 24
Finished Mar 21 02:22:16 PM PDT 24
Peak memory 254444 kb
Host smart-afa9c9df-7b9d-404f-bece-f1f96d981869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154095725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.3154095725
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.4230765625
Short name T933
Test name
Test status
Simulation time 308976179865 ps
CPU time 307.08 seconds
Started Mar 21 02:19:57 PM PDT 24
Finished Mar 21 02:25:04 PM PDT 24
Peak memory 262912 kb
Host smart-ed133ad7-786e-4be4-b4ca-1c1923a865c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230765625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.4230765625
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.1132599826
Short name T376
Test name
Test status
Simulation time 5029757621 ps
CPU time 11.18 seconds
Started Mar 21 02:19:57 PM PDT 24
Finished Mar 21 02:20:09 PM PDT 24
Peak memory 236312 kb
Host smart-277ef83b-9cee-4212-a9a6-289a7241ee39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132599826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.1132599826
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.277328748
Short name T570
Test name
Test status
Simulation time 5325576805 ps
CPU time 10.57 seconds
Started Mar 21 02:19:55 PM PDT 24
Finished Mar 21 02:20:06 PM PDT 24
Peak memory 234328 kb
Host smart-a21185e8-7d13-4c7c-b3aa-e24d352bfe7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277328748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.277328748
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.3596978334
Short name T835
Test name
Test status
Simulation time 1216815834 ps
CPU time 9.86 seconds
Started Mar 21 02:19:56 PM PDT 24
Finished Mar 21 02:20:06 PM PDT 24
Peak memory 226664 kb
Host smart-4a3414c6-8e73-4a5d-ab3f-cff48a5bd2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596978334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.3596978334
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.3395069543
Short name T239
Test name
Test status
Simulation time 630950816 ps
CPU time 6.24 seconds
Started Mar 21 02:19:54 PM PDT 24
Finished Mar 21 02:20:00 PM PDT 24
Peak memory 218664 kb
Host smart-db94a99f-4463-4e20-8ea3-bf44a5f61c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395069543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.3395069543
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.3540962792
Short name T9
Test name
Test status
Simulation time 6458413147 ps
CPU time 18.55 seconds
Started Mar 21 02:19:54 PM PDT 24
Finished Mar 21 02:20:13 PM PDT 24
Peak memory 233540 kb
Host smart-18a1040d-803c-4635-850b-897974a53525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540962792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.3540962792
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.3510526184
Short name T565
Test name
Test status
Simulation time 334534398 ps
CPU time 4.26 seconds
Started Mar 21 02:20:01 PM PDT 24
Finished Mar 21 02:20:05 PM PDT 24
Peak memory 219016 kb
Host smart-1b18e1e9-633c-4cd6-adf5-59a88651160f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3510526184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.3510526184
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.3637665620
Short name T238
Test name
Test status
Simulation time 18626782334 ps
CPU time 281.27 seconds
Started Mar 21 02:19:57 PM PDT 24
Finished Mar 21 02:24:39 PM PDT 24
Peak memory 298304 kb
Host smart-8b74405b-13a5-4606-8f81-4a3f7487d60a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637665620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.3637665620
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.2370284541
Short name T602
Test name
Test status
Simulation time 25150249226 ps
CPU time 61.72 seconds
Started Mar 21 02:19:59 PM PDT 24
Finished Mar 21 02:21:01 PM PDT 24
Peak memory 216220 kb
Host smart-054ba4c1-f1a4-4e96-b21c-2cd16cebf400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370284541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.2370284541
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.2315019067
Short name T808
Test name
Test status
Simulation time 3689066685 ps
CPU time 11.17 seconds
Started Mar 21 02:19:58 PM PDT 24
Finished Mar 21 02:20:09 PM PDT 24
Peak memory 216212 kb
Host smart-97f023fa-3adc-464e-b2ae-fe0d422db830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315019067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.2315019067
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.2594203949
Short name T678
Test name
Test status
Simulation time 87914127 ps
CPU time 1.85 seconds
Started Mar 21 02:19:59 PM PDT 24
Finished Mar 21 02:20:01 PM PDT 24
Peak memory 216188 kb
Host smart-efb268f4-0355-43bf-9276-88a596fadaea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594203949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.2594203949
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.1907906190
Short name T392
Test name
Test status
Simulation time 1081142037 ps
CPU time 0.96 seconds
Started Mar 21 02:19:58 PM PDT 24
Finished Mar 21 02:19:59 PM PDT 24
Peak memory 205868 kb
Host smart-d3749952-cbec-49e2-b7e6-7e9ea7adb4da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907906190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.1907906190
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.2427688199
Short name T143
Test name
Test status
Simulation time 15068091812 ps
CPU time 34.42 seconds
Started Mar 21 02:19:59 PM PDT 24
Finished Mar 21 02:20:33 PM PDT 24
Peak memory 245576 kb
Host smart-fc34594d-b467-4c5c-b61d-be6fb771c680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427688199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.2427688199
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.300260766
Short name T315
Test name
Test status
Simulation time 24193504 ps
CPU time 0.75 seconds
Started Mar 21 02:20:01 PM PDT 24
Finished Mar 21 02:20:02 PM PDT 24
Peak memory 204672 kb
Host smart-a2abb5ec-2f3c-4f0b-aafe-9639065c900b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300260766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.300260766
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.3963828654
Short name T628
Test name
Test status
Simulation time 11871929496 ps
CPU time 9.96 seconds
Started Mar 21 02:19:57 PM PDT 24
Finished Mar 21 02:20:07 PM PDT 24
Peak memory 234528 kb
Host smart-b17f8f72-f877-40a8-a748-1479dccc67cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963828654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.3963828654
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.862702224
Short name T690
Test name
Test status
Simulation time 33718928 ps
CPU time 0.75 seconds
Started Mar 21 02:20:00 PM PDT 24
Finished Mar 21 02:20:01 PM PDT 24
Peak memory 205292 kb
Host smart-e8c8e4a9-a1bc-40a2-936b-ab6968adabcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862702224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.862702224
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.3033217214
Short name T458
Test name
Test status
Simulation time 137771548065 ps
CPU time 91.73 seconds
Started Mar 21 02:19:57 PM PDT 24
Finished Mar 21 02:21:29 PM PDT 24
Peak memory 249332 kb
Host smart-1990d0de-b22b-48a0-8cfe-adb7858bd912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033217214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.3033217214
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.3554408808
Short name T246
Test name
Test status
Simulation time 74837938208 ps
CPU time 413.43 seconds
Started Mar 21 02:19:54 PM PDT 24
Finished Mar 21 02:26:48 PM PDT 24
Peak memory 256380 kb
Host smart-d428c8a5-f4d2-4321-a375-35507eed996f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554408808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.3554408808
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.841398604
Short name T766
Test name
Test status
Simulation time 730615885 ps
CPU time 13.3 seconds
Started Mar 21 02:19:53 PM PDT 24
Finished Mar 21 02:20:06 PM PDT 24
Peak memory 240724 kb
Host smart-481b8170-ac8c-488a-9aa9-ccf6190a6870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841398604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.841398604
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.2810007665
Short name T139
Test name
Test status
Simulation time 93337779 ps
CPU time 2.45 seconds
Started Mar 21 02:19:54 PM PDT 24
Finished Mar 21 02:19:57 PM PDT 24
Peak memory 216640 kb
Host smart-ba7acc85-e5e6-4161-b1c4-15970b662425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810007665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.2810007665
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.1325179731
Short name T792
Test name
Test status
Simulation time 1763552682 ps
CPU time 6.19 seconds
Started Mar 21 02:19:57 PM PDT 24
Finished Mar 21 02:20:04 PM PDT 24
Peak memory 224332 kb
Host smart-2bab7bea-2c49-4785-8462-e12ae0ea30dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325179731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.1325179731
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.1654403723
Short name T559
Test name
Test status
Simulation time 286768881 ps
CPU time 4.39 seconds
Started Mar 21 02:19:57 PM PDT 24
Finished Mar 21 02:20:02 PM PDT 24
Peak memory 218536 kb
Host smart-bfeedfab-411f-41d6-b317-7210a1e21c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654403723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.1654403723
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.4202096106
Short name T693
Test name
Test status
Simulation time 4349580330 ps
CPU time 6.4 seconds
Started Mar 21 02:20:00 PM PDT 24
Finished Mar 21 02:20:07 PM PDT 24
Peak memory 233676 kb
Host smart-5c32b25a-022e-4d25-9610-a95161f9c85f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202096106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.4202096106
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.2761101599
Short name T841
Test name
Test status
Simulation time 148084855 ps
CPU time 3.61 seconds
Started Mar 21 02:19:59 PM PDT 24
Finished Mar 21 02:20:03 PM PDT 24
Peak memory 222712 kb
Host smart-ddb18452-2a58-4c4c-9a39-7cb6b7b21845
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2761101599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.2761101599
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.2799366519
Short name T802
Test name
Test status
Simulation time 17026035065 ps
CPU time 124.24 seconds
Started Mar 21 02:19:56 PM PDT 24
Finished Mar 21 02:22:00 PM PDT 24
Peak memory 253032 kb
Host smart-1424fe39-0de7-4701-bd00-1fdb330c3a65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799366519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.2799366519
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.4190877590
Short name T923
Test name
Test status
Simulation time 11248744379 ps
CPU time 32.03 seconds
Started Mar 21 02:20:00 PM PDT 24
Finished Mar 21 02:20:32 PM PDT 24
Peak memory 216236 kb
Host smart-0b3718dd-bde1-4707-aa40-2da4519439ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190877590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.4190877590
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.1327580293
Short name T424
Test name
Test status
Simulation time 2051030066 ps
CPU time 9.57 seconds
Started Mar 21 02:20:00 PM PDT 24
Finished Mar 21 02:20:10 PM PDT 24
Peak memory 216120 kb
Host smart-63a78b03-0bd2-4ef5-b8b3-75e0d8997057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327580293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.1327580293
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.2108989307
Short name T499
Test name
Test status
Simulation time 14305182 ps
CPU time 0.81 seconds
Started Mar 21 02:19:56 PM PDT 24
Finished Mar 21 02:19:57 PM PDT 24
Peak memory 205528 kb
Host smart-c7a87fde-4567-490f-836b-cc7aec0527bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108989307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.2108989307
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.509407383
Short name T595
Test name
Test status
Simulation time 185040834 ps
CPU time 0.94 seconds
Started Mar 21 02:19:58 PM PDT 24
Finished Mar 21 02:19:59 PM PDT 24
Peak memory 206648 kb
Host smart-d71b40b3-422a-4987-b496-e8378e2f0bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509407383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.509407383
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.2188355939
Short name T197
Test name
Test status
Simulation time 6223647562 ps
CPU time 10.82 seconds
Started Mar 21 02:19:53 PM PDT 24
Finished Mar 21 02:20:04 PM PDT 24
Peak memory 229460 kb
Host smart-e682481e-2cc6-4c7b-bc7b-dec286ffc32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188355939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.2188355939
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.968705609
Short name T954
Test name
Test status
Simulation time 54500015 ps
CPU time 0.71 seconds
Started Mar 21 02:20:08 PM PDT 24
Finished Mar 21 02:20:09 PM PDT 24
Peak memory 205252 kb
Host smart-e82d8613-02ca-4a93-9642-2ff28c8dfa3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968705609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.968705609
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.3617471297
Short name T629
Test name
Test status
Simulation time 405908856 ps
CPU time 3.84 seconds
Started Mar 21 02:20:04 PM PDT 24
Finished Mar 21 02:20:09 PM PDT 24
Peak memory 234084 kb
Host smart-7b1d1977-5272-435a-af26-83ba31d5bc0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617471297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.3617471297
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.2281070767
Short name T309
Test name
Test status
Simulation time 82776499 ps
CPU time 0.78 seconds
Started Mar 21 02:19:55 PM PDT 24
Finished Mar 21 02:19:57 PM PDT 24
Peak memory 206340 kb
Host smart-a51adf97-226e-43fe-a72f-817bb7563e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281070767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.2281070767
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.3744499214
Short name T74
Test name
Test status
Simulation time 567733088446 ps
CPU time 277.45 seconds
Started Mar 21 02:20:05 PM PDT 24
Finished Mar 21 02:24:44 PM PDT 24
Peak memory 264464 kb
Host smart-3522a575-6d2b-4538-b2a8-0d18745b4566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744499214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.3744499214
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.2768665640
Short name T791
Test name
Test status
Simulation time 16445413833 ps
CPU time 113.55 seconds
Started Mar 21 02:20:06 PM PDT 24
Finished Mar 21 02:22:00 PM PDT 24
Peak memory 266312 kb
Host smart-fa3befdc-a00a-4b7e-b227-1a68f8621003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768665640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.2768665640
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.1818953676
Short name T481
Test name
Test status
Simulation time 85386932379 ps
CPU time 322.7 seconds
Started Mar 21 02:20:05 PM PDT 24
Finished Mar 21 02:25:29 PM PDT 24
Peak memory 255340 kb
Host smart-ee7fe652-d608-48b9-abc2-d19c895dcf84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818953676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.1818953676
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.202546251
Short name T752
Test name
Test status
Simulation time 8198494369 ps
CPU time 43.67 seconds
Started Mar 21 02:20:09 PM PDT 24
Finished Mar 21 02:20:53 PM PDT 24
Peak memory 252432 kb
Host smart-d15a14b8-c695-4ed6-939a-8b63ee3469a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202546251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.202546251
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.2174176710
Short name T439
Test name
Test status
Simulation time 592724280 ps
CPU time 4.11 seconds
Started Mar 21 02:20:05 PM PDT 24
Finished Mar 21 02:20:09 PM PDT 24
Peak memory 217604 kb
Host smart-09f581c2-1b84-4483-b34e-411f88f33afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174176710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.2174176710
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.2347982857
Short name T349
Test name
Test status
Simulation time 7731999307 ps
CPU time 23.32 seconds
Started Mar 21 02:20:09 PM PDT 24
Finished Mar 21 02:20:32 PM PDT 24
Peak memory 231436 kb
Host smart-954bf138-19a2-4e05-af9b-65aca23195dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347982857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.2347982857
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.1226228737
Short name T601
Test name
Test status
Simulation time 7051363055 ps
CPU time 6.2 seconds
Started Mar 21 02:20:05 PM PDT 24
Finished Mar 21 02:20:11 PM PDT 24
Peak memory 232644 kb
Host smart-336ed869-533b-4d5b-81f4-a0986cbf35e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226228737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.1226228737
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.54348527
Short name T899
Test name
Test status
Simulation time 7732235074 ps
CPU time 19.51 seconds
Started Mar 21 02:19:54 PM PDT 24
Finished Mar 21 02:20:14 PM PDT 24
Peak memory 223400 kb
Host smart-3b8c4066-5efb-494e-8759-b84624886277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54348527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.54348527
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.790385362
Short name T451
Test name
Test status
Simulation time 1165803994 ps
CPU time 6.13 seconds
Started Mar 21 02:20:03 PM PDT 24
Finished Mar 21 02:20:09 PM PDT 24
Peak memory 220420 kb
Host smart-63c8d598-207e-4c60-a596-83126d4c86f7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=790385362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dire
ct.790385362
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.1828131221
Short name T49
Test name
Test status
Simulation time 874614925776 ps
CPU time 1231.36 seconds
Started Mar 21 02:20:03 PM PDT 24
Finished Mar 21 02:40:34 PM PDT 24
Peak memory 300592 kb
Host smart-1adedcae-9823-4872-bed5-54167fe48c14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828131221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.1828131221
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.1464517111
Short name T425
Test name
Test status
Simulation time 645040682 ps
CPU time 3.17 seconds
Started Mar 21 02:19:57 PM PDT 24
Finished Mar 21 02:20:01 PM PDT 24
Peak memory 216168 kb
Host smart-702f604c-a4fe-4fbb-8f12-51857b233101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464517111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.1464517111
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.2624048017
Short name T355
Test name
Test status
Simulation time 10581053025 ps
CPU time 11.81 seconds
Started Mar 21 02:20:00 PM PDT 24
Finished Mar 21 02:20:12 PM PDT 24
Peak memory 216160 kb
Host smart-8c83376d-c080-4012-ad58-78a2883ce69e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624048017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.2624048017
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.726049362
Short name T922
Test name
Test status
Simulation time 172568645 ps
CPU time 1.44 seconds
Started Mar 21 02:19:54 PM PDT 24
Finished Mar 21 02:19:56 PM PDT 24
Peak memory 207896 kb
Host smart-9905f1d8-8ab8-4951-9a3c-59daa8036397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726049362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.726049362
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.2785128331
Short name T768
Test name
Test status
Simulation time 65447843 ps
CPU time 0.94 seconds
Started Mar 21 02:19:53 PM PDT 24
Finished Mar 21 02:19:55 PM PDT 24
Peak memory 205576 kb
Host smart-2ced7972-f251-4192-9a3d-47565b776484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785128331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.2785128331
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.2982060335
Short name T842
Test name
Test status
Simulation time 2132828059 ps
CPU time 6.48 seconds
Started Mar 21 02:20:06 PM PDT 24
Finished Mar 21 02:20:13 PM PDT 24
Peak memory 240744 kb
Host smart-8ea27575-5e2f-48dd-8caa-8235940d8897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982060335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.2982060335
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.3600639200
Short name T794
Test name
Test status
Simulation time 15798363 ps
CPU time 0.68 seconds
Started Mar 21 02:20:12 PM PDT 24
Finished Mar 21 02:20:13 PM PDT 24
Peak memory 205256 kb
Host smart-dbe936cd-e0e2-4318-8447-2ebbf8291f8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600639200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
3600639200
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.1028917926
Short name T622
Test name
Test status
Simulation time 2886791720 ps
CPU time 4.11 seconds
Started Mar 21 02:20:12 PM PDT 24
Finished Mar 21 02:20:16 PM PDT 24
Peak memory 219780 kb
Host smart-eb96afb8-0b8a-4a14-9c43-a14c28b64f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028917926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.1028917926
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.613507052
Short name T16
Test name
Test status
Simulation time 19249136 ps
CPU time 0.83 seconds
Started Mar 21 02:20:02 PM PDT 24
Finished Mar 21 02:20:03 PM PDT 24
Peak memory 205308 kb
Host smart-2632e7b1-d920-4bc5-a069-b37e0c44b5e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613507052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.613507052
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.1783741525
Short name T423
Test name
Test status
Simulation time 41137380273 ps
CPU time 213.22 seconds
Started Mar 21 02:20:13 PM PDT 24
Finished Mar 21 02:23:47 PM PDT 24
Peak memory 251096 kb
Host smart-a567e16b-ff70-4082-af48-79e672887010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783741525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.1783741525
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.4011537713
Short name T533
Test name
Test status
Simulation time 15302444552 ps
CPU time 116.67 seconds
Started Mar 21 02:20:45 PM PDT 24
Finished Mar 21 02:22:42 PM PDT 24
Peak memory 234932 kb
Host smart-7819726f-942a-4882-8375-a6b062a654b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011537713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.4011537713
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.3476972642
Short name T568
Test name
Test status
Simulation time 2365422651 ps
CPU time 43.67 seconds
Started Mar 21 02:20:14 PM PDT 24
Finished Mar 21 02:20:58 PM PDT 24
Peak memory 255276 kb
Host smart-2ec5e699-19c9-4b63-9d4a-402bc9ee3547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476972642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.3476972642
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.167366722
Short name T726
Test name
Test status
Simulation time 3995574528 ps
CPU time 16.54 seconds
Started Mar 21 02:20:11 PM PDT 24
Finished Mar 21 02:20:28 PM PDT 24
Peak memory 232544 kb
Host smart-bfeafd74-5214-4af1-bc98-c7fb4744dc35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167366722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.167366722
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.2850866307
Short name T864
Test name
Test status
Simulation time 175184388 ps
CPU time 3.07 seconds
Started Mar 21 02:20:00 PM PDT 24
Finished Mar 21 02:20:04 PM PDT 24
Peak memory 232560 kb
Host smart-74779621-f452-4b28-b276-7cfc6fcc99c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850866307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.2850866307
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.1748900043
Short name T417
Test name
Test status
Simulation time 42608723765 ps
CPU time 32.9 seconds
Started Mar 21 02:20:13 PM PDT 24
Finished Mar 21 02:20:46 PM PDT 24
Peak memory 249408 kb
Host smart-e1eb3131-993a-447d-9d46-d51106b40915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748900043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.1748900043
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.3295903018
Short name T32
Test name
Test status
Simulation time 2063614565 ps
CPU time 4.65 seconds
Started Mar 21 02:20:09 PM PDT 24
Finished Mar 21 02:20:13 PM PDT 24
Peak memory 216472 kb
Host smart-9e096eb6-ad34-49c4-8923-a621eb381ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295903018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.3295903018
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.343232619
Short name T362
Test name
Test status
Simulation time 7437275470 ps
CPU time 12.96 seconds
Started Mar 21 02:20:02 PM PDT 24
Finished Mar 21 02:20:15 PM PDT 24
Peak memory 226920 kb
Host smart-842641af-30ac-4b4c-b71f-b25cbe3ea5fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343232619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.343232619
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.1274169830
Short name T467
Test name
Test status
Simulation time 274142791 ps
CPU time 3.97 seconds
Started Mar 21 02:20:14 PM PDT 24
Finished Mar 21 02:20:18 PM PDT 24
Peak memory 218520 kb
Host smart-194539f6-2b6a-484e-9c3c-e2e2022ddb4a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1274169830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.1274169830
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.4090536855
Short name T82
Test name
Test status
Simulation time 7121402752 ps
CPU time 86.43 seconds
Started Mar 21 02:20:13 PM PDT 24
Finished Mar 21 02:21:39 PM PDT 24
Peak memory 253600 kb
Host smart-ce3aa590-e560-4144-b525-71517f4d7ba2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090536855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.4090536855
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.1543868282
Short name T395
Test name
Test status
Simulation time 962318615 ps
CPU time 3.79 seconds
Started Mar 21 02:20:01 PM PDT 24
Finished Mar 21 02:20:05 PM PDT 24
Peak memory 216124 kb
Host smart-2cb842ae-1b27-4af8-8afd-9c83ccd09c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543868282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.1543868282
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.414471581
Short name T759
Test name
Test status
Simulation time 23062687716 ps
CPU time 20.09 seconds
Started Mar 21 02:20:09 PM PDT 24
Finished Mar 21 02:20:29 PM PDT 24
Peak memory 216156 kb
Host smart-25ebbf8d-e961-489e-8d34-0630625a9100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414471581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.414471581
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.3295992126
Short name T284
Test name
Test status
Simulation time 74554376 ps
CPU time 0.71 seconds
Started Mar 21 02:20:05 PM PDT 24
Finished Mar 21 02:20:07 PM PDT 24
Peak memory 205588 kb
Host smart-8d79f811-0891-4772-a616-e26fb51cd60f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295992126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.3295992126
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.3380019446
Short name T333
Test name
Test status
Simulation time 26637903 ps
CPU time 0.83 seconds
Started Mar 21 02:20:02 PM PDT 24
Finished Mar 21 02:20:03 PM PDT 24
Peak memory 205588 kb
Host smart-0f8f614c-7474-4aa0-9747-bb14931171bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380019446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.3380019446
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.2364678264
Short name T553
Test name
Test status
Simulation time 1840476139 ps
CPU time 6.5 seconds
Started Mar 21 02:20:12 PM PDT 24
Finished Mar 21 02:20:18 PM PDT 24
Peak memory 219852 kb
Host smart-0ed444d9-83bd-43b3-aa62-a65d62729a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364678264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.2364678264
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.2221932194
Short name T606
Test name
Test status
Simulation time 42585225 ps
CPU time 0.7 seconds
Started Mar 21 02:20:18 PM PDT 24
Finished Mar 21 02:20:19 PM PDT 24
Peak memory 205204 kb
Host smart-c6e6653c-f9e6-412e-be4f-09db6e9adcb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221932194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
2221932194
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.1752341921
Short name T414
Test name
Test status
Simulation time 570050379 ps
CPU time 4.16 seconds
Started Mar 21 02:20:12 PM PDT 24
Finished Mar 21 02:20:16 PM PDT 24
Peak memory 234892 kb
Host smart-b92e82ec-9960-4dcf-a16f-02cbe0c5d524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752341921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.1752341921
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.4045747897
Short name T338
Test name
Test status
Simulation time 26265938 ps
CPU time 0.75 seconds
Started Mar 21 02:20:12 PM PDT 24
Finished Mar 21 02:20:12 PM PDT 24
Peak memory 205304 kb
Host smart-e1b59967-10c6-4b88-ba1b-ea530c370b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045747897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.4045747897
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.218015171
Short name T161
Test name
Test status
Simulation time 95474568118 ps
CPU time 219.06 seconds
Started Mar 21 02:20:19 PM PDT 24
Finished Mar 21 02:23:58 PM PDT 24
Peak memory 261284 kb
Host smart-0eebcc5a-1b18-40d0-85d1-06ad29b43cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218015171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.218015171
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.3650145572
Short name T785
Test name
Test status
Simulation time 537020910 ps
CPU time 8.55 seconds
Started Mar 21 02:20:13 PM PDT 24
Finished Mar 21 02:20:22 PM PDT 24
Peak memory 232532 kb
Host smart-49813f94-995b-42ea-bfb7-ea4d48a8bf25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650145572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.3650145572
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.3402139709
Short name T302
Test name
Test status
Simulation time 93570207 ps
CPU time 2.86 seconds
Started Mar 21 02:20:11 PM PDT 24
Finished Mar 21 02:20:14 PM PDT 24
Peak memory 233552 kb
Host smart-39cf5cb8-d9d3-4179-9cff-8b508d68cc6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402139709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3402139709
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.2480030500
Short name T426
Test name
Test status
Simulation time 20293707228 ps
CPU time 17.58 seconds
Started Mar 21 02:20:12 PM PDT 24
Finished Mar 21 02:20:30 PM PDT 24
Peak memory 237796 kb
Host smart-e8d23bc5-a1a4-4fd8-9867-d07c9959c7d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480030500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.2480030500
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.3647469331
Short name T255
Test name
Test status
Simulation time 8573355798 ps
CPU time 14.33 seconds
Started Mar 21 02:20:14 PM PDT 24
Finished Mar 21 02:20:29 PM PDT 24
Peak memory 234056 kb
Host smart-2f8edc59-df63-467a-94cc-b9e0dc6a86e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647469331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.3647469331
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.1110900790
Short name T177
Test name
Test status
Simulation time 39700556 ps
CPU time 2.56 seconds
Started Mar 21 02:20:14 PM PDT 24
Finished Mar 21 02:20:17 PM PDT 24
Peak memory 234004 kb
Host smart-ae6ed468-96a9-45e5-895e-128d42664144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110900790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.1110900790
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.2742356671
Short name T330
Test name
Test status
Simulation time 1283530838 ps
CPU time 5.99 seconds
Started Mar 21 02:20:19 PM PDT 24
Finished Mar 21 02:20:26 PM PDT 24
Peak memory 222364 kb
Host smart-15aa6a87-5b7f-4943-a0c2-0676472a41a6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2742356671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.2742356671
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.2530023221
Short name T895
Test name
Test status
Simulation time 138136797 ps
CPU time 1.18 seconds
Started Mar 21 02:20:22 PM PDT 24
Finished Mar 21 02:20:24 PM PDT 24
Peak memory 207592 kb
Host smart-c9ef5def-6385-44ff-922d-7a0a37c91626
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530023221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.2530023221
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.2389060369
Short name T271
Test name
Test status
Simulation time 15908178475 ps
CPU time 36.06 seconds
Started Mar 21 02:20:12 PM PDT 24
Finished Mar 21 02:20:48 PM PDT 24
Peak memory 216232 kb
Host smart-690b41b4-0d88-4964-a22b-c49e1380d918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389060369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.2389060369
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.3080497101
Short name T295
Test name
Test status
Simulation time 6316065717 ps
CPU time 19.2 seconds
Started Mar 21 02:20:12 PM PDT 24
Finished Mar 21 02:20:31 PM PDT 24
Peak memory 216096 kb
Host smart-e5b827f1-088d-46b4-95f6-1e58942f1afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080497101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.3080497101
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.3524658561
Short name T647
Test name
Test status
Simulation time 65928610 ps
CPU time 1.23 seconds
Started Mar 21 02:20:11 PM PDT 24
Finished Mar 21 02:20:12 PM PDT 24
Peak memory 215964 kb
Host smart-cde77ae1-e2a7-417b-937d-313d55073a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524658561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.3524658561
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.2269223267
Short name T818
Test name
Test status
Simulation time 82390161 ps
CPU time 0.72 seconds
Started Mar 21 02:20:13 PM PDT 24
Finished Mar 21 02:20:14 PM PDT 24
Peak memory 205596 kb
Host smart-07a9a9ac-d0fe-4201-93d9-38bcb2e026da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269223267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.2269223267
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.1123954319
Short name T642
Test name
Test status
Simulation time 477418235 ps
CPU time 5.18 seconds
Started Mar 21 02:20:12 PM PDT 24
Finished Mar 21 02:20:17 PM PDT 24
Peak memory 225344 kb
Host smart-86e440ad-12c8-4a86-a26c-014cdb17cdb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123954319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.1123954319
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.3714558450
Short name T552
Test name
Test status
Simulation time 14365278 ps
CPU time 0.73 seconds
Started Mar 21 02:20:29 PM PDT 24
Finished Mar 21 02:20:30 PM PDT 24
Peak memory 204700 kb
Host smart-f4da630e-6637-4d6e-aa97-6820973e9c65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714558450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
3714558450
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.875524968
Short name T229
Test name
Test status
Simulation time 466573200 ps
CPU time 2.48 seconds
Started Mar 21 02:20:29 PM PDT 24
Finished Mar 21 02:20:32 PM PDT 24
Peak memory 224336 kb
Host smart-4baf8f00-7d16-420b-a541-8556088f42a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875524968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.875524968
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.284862207
Short name T405
Test name
Test status
Simulation time 47773821 ps
CPU time 0.76 seconds
Started Mar 21 02:20:18 PM PDT 24
Finished Mar 21 02:20:20 PM PDT 24
Peak memory 205272 kb
Host smart-db10a95b-dc4c-47a5-a1d7-9f7ee4cc7bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284862207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.284862207
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.1478007810
Short name T653
Test name
Test status
Simulation time 21994160063 ps
CPU time 57.09 seconds
Started Mar 21 02:20:29 PM PDT 24
Finished Mar 21 02:21:26 PM PDT 24
Peak memory 248936 kb
Host smart-089a38db-2eeb-4678-8cc4-1dfdf50c3806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478007810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.1478007810
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.109108591
Short name T83
Test name
Test status
Simulation time 41230547572 ps
CPU time 298.54 seconds
Started Mar 21 02:20:32 PM PDT 24
Finished Mar 21 02:25:30 PM PDT 24
Peak memory 262848 kb
Host smart-a112647b-50f7-4751-a7fc-2f0a9bd27d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109108591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.109108591
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.3784266341
Short name T435
Test name
Test status
Simulation time 22763106955 ps
CPU time 44.42 seconds
Started Mar 21 02:20:30 PM PDT 24
Finished Mar 21 02:21:15 PM PDT 24
Peak memory 222376 kb
Host smart-b3affdbf-cd8b-4d76-bf02-a4a077031ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784266341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.3784266341
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.3551515749
Short name T428
Test name
Test status
Simulation time 6957339228 ps
CPU time 26.44 seconds
Started Mar 21 02:20:30 PM PDT 24
Finished Mar 21 02:20:57 PM PDT 24
Peak memory 233752 kb
Host smart-ed1e2eb9-9d2f-4c34-b984-07df2c430539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551515749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.3551515749
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.3274415587
Short name T331
Test name
Test status
Simulation time 408236885 ps
CPU time 3.2 seconds
Started Mar 21 02:20:21 PM PDT 24
Finished Mar 21 02:20:24 PM PDT 24
Peak memory 232564 kb
Host smart-efa64585-0949-41da-9d65-5f493e60d78e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274415587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.3274415587
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.1510167191
Short name T569
Test name
Test status
Simulation time 587745440 ps
CPU time 4.79 seconds
Started Mar 21 02:20:20 PM PDT 24
Finished Mar 21 02:20:26 PM PDT 24
Peak memory 224248 kb
Host smart-d6003d06-80ed-430b-bb6a-028144f7a0f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510167191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.1510167191
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.2605674617
Short name T431
Test name
Test status
Simulation time 197201378 ps
CPU time 2.27 seconds
Started Mar 21 02:20:19 PM PDT 24
Finished Mar 21 02:20:21 PM PDT 24
Peak memory 224236 kb
Host smart-a6769b7a-52d3-45c4-9be1-5aa10c71c274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605674617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.2605674617
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.2518058399
Short name T531
Test name
Test status
Simulation time 7831868898 ps
CPU time 10.88 seconds
Started Mar 21 02:20:20 PM PDT 24
Finished Mar 21 02:20:32 PM PDT 24
Peak memory 236760 kb
Host smart-01a2ccf4-0f13-4362-b839-b34e7e3562e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518058399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.2518058399
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.3327280196
Short name T780
Test name
Test status
Simulation time 1072875386 ps
CPU time 5.79 seconds
Started Mar 21 02:20:30 PM PDT 24
Finished Mar 21 02:20:36 PM PDT 24
Peak memory 222824 kb
Host smart-a6485bcc-b485-41e2-8258-9c14e893ba72
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3327280196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.3327280196
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.4033538745
Short name T195
Test name
Test status
Simulation time 19619336301 ps
CPU time 120 seconds
Started Mar 21 02:20:28 PM PDT 24
Finished Mar 21 02:22:29 PM PDT 24
Peak memory 266728 kb
Host smart-c25d3d8a-a5be-48af-b563-342fbf406465
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033538745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.4033538745
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.1146622552
Short name T364
Test name
Test status
Simulation time 42934319051 ps
CPU time 74.94 seconds
Started Mar 21 02:20:24 PM PDT 24
Finished Mar 21 02:21:39 PM PDT 24
Peak memory 216192 kb
Host smart-a536ff9f-63af-433a-b55c-2d6f7853056d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146622552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.1146622552
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.1950924722
Short name T474
Test name
Test status
Simulation time 7237003605 ps
CPU time 9.92 seconds
Started Mar 21 02:20:19 PM PDT 24
Finished Mar 21 02:20:31 PM PDT 24
Peak memory 216188 kb
Host smart-e8087932-0ff4-4976-8170-1027adfe3704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950924722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.1950924722
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.988129653
Short name T696
Test name
Test status
Simulation time 91546335 ps
CPU time 1.2 seconds
Started Mar 21 02:20:20 PM PDT 24
Finished Mar 21 02:20:22 PM PDT 24
Peak memory 216076 kb
Host smart-881330f3-8e43-4b0c-a466-1ff1d099117b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988129653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.988129653
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.994032417
Short name T589
Test name
Test status
Simulation time 34394594 ps
CPU time 0.85 seconds
Started Mar 21 02:20:21 PM PDT 24
Finished Mar 21 02:20:22 PM PDT 24
Peak memory 205604 kb
Host smart-9291318c-5c3a-486f-b5fe-bdc486f0c863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994032417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.994032417
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.521365389
Short name T623
Test name
Test status
Simulation time 222233801 ps
CPU time 3.84 seconds
Started Mar 21 02:20:30 PM PDT 24
Finished Mar 21 02:20:34 PM PDT 24
Peak memory 233504 kb
Host smart-9587ce6c-2878-46e2-9f4a-b92bcc847ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521365389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.521365389
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.3506610802
Short name T826
Test name
Test status
Simulation time 156367498 ps
CPU time 0.75 seconds
Started Mar 21 02:20:42 PM PDT 24
Finished Mar 21 02:20:43 PM PDT 24
Peak memory 205256 kb
Host smart-a6254c5f-ff23-4529-ac4c-d9dfce7d8388
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506610802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
3506610802
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.2296771528
Short name T857
Test name
Test status
Simulation time 527922877 ps
CPU time 3.82 seconds
Started Mar 21 02:20:30 PM PDT 24
Finished Mar 21 02:20:34 PM PDT 24
Peak memory 224284 kb
Host smart-d8b0e112-6b39-40de-8b89-db27cdf03cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296771528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.2296771528
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.3558768910
Short name T483
Test name
Test status
Simulation time 17234826 ps
CPU time 0.75 seconds
Started Mar 21 02:20:28 PM PDT 24
Finished Mar 21 02:20:29 PM PDT 24
Peak memory 206344 kb
Host smart-427caeba-518c-4633-93a2-9d74392598b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558768910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.3558768910
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.1373049750
Short name T178
Test name
Test status
Simulation time 22805691678 ps
CPU time 141.38 seconds
Started Mar 21 02:21:11 PM PDT 24
Finished Mar 21 02:23:33 PM PDT 24
Peak memory 248952 kb
Host smart-f424bde0-8f07-4790-bf87-67884196e254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373049750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.1373049750
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.1889176363
Short name T856
Test name
Test status
Simulation time 6937981101 ps
CPU time 82.93 seconds
Started Mar 21 02:20:29 PM PDT 24
Finished Mar 21 02:21:52 PM PDT 24
Peak memory 257236 kb
Host smart-cb8cd20f-a4ef-466c-b35d-d7e1e387dd47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889176363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.1889176363
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.218025863
Short name T160
Test name
Test status
Simulation time 4787487116 ps
CPU time 71.66 seconds
Started Mar 21 02:20:44 PM PDT 24
Finished Mar 21 02:21:56 PM PDT 24
Peak memory 255920 kb
Host smart-112008e7-d9b9-4f50-9f8c-7504f2f4790d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218025863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idle
.218025863
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.1939624504
Short name T950
Test name
Test status
Simulation time 4469539821 ps
CPU time 14.28 seconds
Started Mar 21 02:20:30 PM PDT 24
Finished Mar 21 02:20:44 PM PDT 24
Peak memory 234704 kb
Host smart-4b4dfcc1-b171-4db1-ad1e-0660106ba335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939624504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.1939624504
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.713216787
Short name T34
Test name
Test status
Simulation time 419637114 ps
CPU time 3.65 seconds
Started Mar 21 02:20:30 PM PDT 24
Finished Mar 21 02:20:34 PM PDT 24
Peak memory 218276 kb
Host smart-cf7d58bd-516b-4876-b030-c35dc0355388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713216787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.713216787
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.364733543
Short name T169
Test name
Test status
Simulation time 4030763673 ps
CPU time 4.12 seconds
Started Mar 21 02:20:31 PM PDT 24
Finished Mar 21 02:20:35 PM PDT 24
Peak memory 224340 kb
Host smart-ca9fb93d-2913-4a31-9ae8-92bc6ab1669b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364733543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.364733543
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.1137198978
Short name T220
Test name
Test status
Simulation time 29491437985 ps
CPU time 6.06 seconds
Started Mar 21 02:20:30 PM PDT 24
Finished Mar 21 02:20:36 PM PDT 24
Peak memory 233564 kb
Host smart-fc28ec85-ab46-49ff-b354-42731424cd29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137198978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.1137198978
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.4114236009
Short name T883
Test name
Test status
Simulation time 1699392868 ps
CPU time 11.05 seconds
Started Mar 21 02:20:28 PM PDT 24
Finished Mar 21 02:20:40 PM PDT 24
Peak memory 225588 kb
Host smart-f058e3ae-06d5-40b1-bfe1-d828d4d40bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114236009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.4114236009
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.3833950480
Short name T945
Test name
Test status
Simulation time 185254924 ps
CPU time 3.62 seconds
Started Mar 21 02:20:28 PM PDT 24
Finished Mar 21 02:20:32 PM PDT 24
Peak memory 222724 kb
Host smart-115ccdc2-52de-4890-a89d-4c4b081a74ea
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3833950480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.3833950480
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.288048419
Short name T133
Test name
Test status
Simulation time 288233019 ps
CPU time 1.17 seconds
Started Mar 21 02:20:40 PM PDT 24
Finished Mar 21 02:20:41 PM PDT 24
Peak memory 206960 kb
Host smart-d9976e46-bb35-41cf-8597-1041f10b140a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288048419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stres
s_all.288048419
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.1161578483
Short name T269
Test name
Test status
Simulation time 19542968544 ps
CPU time 35.54 seconds
Started Mar 21 02:20:29 PM PDT 24
Finished Mar 21 02:21:05 PM PDT 24
Peak memory 216444 kb
Host smart-5ed204f6-5112-46a6-a642-c71eefa35076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161578483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.1161578483
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.3767159973
Short name T318
Test name
Test status
Simulation time 1329548474 ps
CPU time 5.21 seconds
Started Mar 21 02:20:31 PM PDT 24
Finished Mar 21 02:20:36 PM PDT 24
Peak memory 216112 kb
Host smart-3e64ddcb-3b14-4221-a90b-564f90431715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767159973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.3767159973
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.2863447907
Short name T377
Test name
Test status
Simulation time 46761812 ps
CPU time 1.42 seconds
Started Mar 21 02:21:31 PM PDT 24
Finished Mar 21 02:21:33 PM PDT 24
Peak memory 216108 kb
Host smart-e7f531c1-552b-417e-a9ee-7601c22428a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863447907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.2863447907
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.1252990711
Short name T408
Test name
Test status
Simulation time 44998789 ps
CPU time 0.84 seconds
Started Mar 21 02:20:42 PM PDT 24
Finished Mar 21 02:20:43 PM PDT 24
Peak memory 205504 kb
Host smart-725d8260-282f-48bb-b192-c4c28e6ccaf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252990711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.1252990711
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.411936241
Short name T891
Test name
Test status
Simulation time 1035020916 ps
CPU time 10.28 seconds
Started Mar 21 02:20:30 PM PDT 24
Finished Mar 21 02:20:41 PM PDT 24
Peak memory 228116 kb
Host smart-a0a92534-cda6-4583-a863-32004c2f6eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411936241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.411936241
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.4152481730
Short name T288
Test name
Test status
Simulation time 26870171 ps
CPU time 0.73 seconds
Started Mar 21 02:20:43 PM PDT 24
Finished Mar 21 02:20:44 PM PDT 24
Peak memory 204712 kb
Host smart-971d1247-a09b-48fb-9236-a0d0e03c85fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152481730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
4152481730
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.689040095
Short name T211
Test name
Test status
Simulation time 301031421 ps
CPU time 3.11 seconds
Started Mar 21 02:20:41 PM PDT 24
Finished Mar 21 02:20:44 PM PDT 24
Peak memory 235176 kb
Host smart-10974e30-6636-406c-a975-c9acde095fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689040095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.689040095
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.3089608340
Short name T929
Test name
Test status
Simulation time 15705240 ps
CPU time 0.8 seconds
Started Mar 21 02:20:42 PM PDT 24
Finished Mar 21 02:20:43 PM PDT 24
Peak memory 206336 kb
Host smart-9bc3cffa-d071-4457-ba4a-1d104fac5ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089608340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.3089608340
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.1978589095
Short name T823
Test name
Test status
Simulation time 21829925105 ps
CPU time 139.84 seconds
Started Mar 21 02:20:42 PM PDT 24
Finished Mar 21 02:23:02 PM PDT 24
Peak memory 265452 kb
Host smart-972cba16-a3c5-447b-8494-dd7e6027d1d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978589095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.1978589095
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.789317184
Short name T673
Test name
Test status
Simulation time 8409215070 ps
CPU time 52.69 seconds
Started Mar 21 02:20:41 PM PDT 24
Finished Mar 21 02:21:33 PM PDT 24
Peak memory 249080 kb
Host smart-37ee34fa-964c-4048-86c0-6214d4b9712b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789317184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.789317184
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.692910861
Short name T926
Test name
Test status
Simulation time 28951862912 ps
CPU time 60.91 seconds
Started Mar 21 02:20:40 PM PDT 24
Finished Mar 21 02:21:42 PM PDT 24
Peak memory 250016 kb
Host smart-36167802-2750-4676-bb53-10fb69e073e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692910861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idle
.692910861
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.3859589346
Short name T266
Test name
Test status
Simulation time 4230514629 ps
CPU time 29.16 seconds
Started Mar 21 02:20:41 PM PDT 24
Finished Mar 21 02:21:11 PM PDT 24
Peak memory 224424 kb
Host smart-29320646-fd69-4849-bb96-e9ff4a25c841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859589346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.3859589346
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.1573325570
Short name T714
Test name
Test status
Simulation time 595407812 ps
CPU time 4.69 seconds
Started Mar 21 02:20:41 PM PDT 24
Finished Mar 21 02:20:45 PM PDT 24
Peak memory 233572 kb
Host smart-26dd8e8e-e08e-49ec-a172-b46472af4acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573325570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.1573325570
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.911976801
Short name T862
Test name
Test status
Simulation time 16001744029 ps
CPU time 24.97 seconds
Started Mar 21 02:20:41 PM PDT 24
Finished Mar 21 02:21:06 PM PDT 24
Peak memory 221932 kb
Host smart-5928d738-b7ec-4f82-bdb6-6337501d7bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911976801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.911976801
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.518771829
Short name T682
Test name
Test status
Simulation time 2530389263 ps
CPU time 13.45 seconds
Started Mar 21 02:20:41 PM PDT 24
Finished Mar 21 02:20:55 PM PDT 24
Peak memory 240176 kb
Host smart-2700fc1f-a6ee-45f2-aa47-1e773c0ed0f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518771829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap
.518771829
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.3522271780
Short name T788
Test name
Test status
Simulation time 450703531 ps
CPU time 5.31 seconds
Started Mar 21 02:20:42 PM PDT 24
Finished Mar 21 02:20:47 PM PDT 24
Peak memory 233544 kb
Host smart-65168962-2bfb-491d-a2a2-faa415469483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522271780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.3522271780
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.838984233
Short name T122
Test name
Test status
Simulation time 3473001954 ps
CPU time 7.02 seconds
Started Mar 21 02:20:45 PM PDT 24
Finished Mar 21 02:20:52 PM PDT 24
Peak memory 222792 kb
Host smart-b8ba0cd8-2c7a-471d-8198-644825c50de8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=838984233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dire
ct.838984233
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.1822630364
Short name T55
Test name
Test status
Simulation time 55431699 ps
CPU time 1.05 seconds
Started Mar 21 02:20:42 PM PDT 24
Finished Mar 21 02:20:43 PM PDT 24
Peak memory 206808 kb
Host smart-4deba70b-baa9-4612-9e60-a16287673573
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822630364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.1822630364
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.3519394759
Short name T270
Test name
Test status
Simulation time 1348519136 ps
CPU time 19.72 seconds
Started Mar 21 02:20:42 PM PDT 24
Finished Mar 21 02:21:02 PM PDT 24
Peak memory 216116 kb
Host smart-eb8a7bf5-8fe7-4792-8c3c-e3b7cd920314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519394759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.3519394759
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.3321043131
Short name T411
Test name
Test status
Simulation time 3858860140 ps
CPU time 8.19 seconds
Started Mar 21 02:20:41 PM PDT 24
Finished Mar 21 02:20:49 PM PDT 24
Peak memory 216212 kb
Host smart-2a93b67b-1d16-4940-8359-5649e7d108ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321043131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.3321043131
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.3886174672
Short name T543
Test name
Test status
Simulation time 157469683 ps
CPU time 2.08 seconds
Started Mar 21 02:20:41 PM PDT 24
Finished Mar 21 02:20:44 PM PDT 24
Peak memory 216092 kb
Host smart-41bf8470-3c39-4b27-8921-9aa47acc0f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886174672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.3886174672
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.715644407
Short name T314
Test name
Test status
Simulation time 293908514 ps
CPU time 0.92 seconds
Started Mar 21 02:20:41 PM PDT 24
Finished Mar 21 02:20:42 PM PDT 24
Peak memory 205596 kb
Host smart-782c27e3-9a4e-47b5-a68b-3d8b7e61569b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715644407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.715644407
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.4242291112
Short name T506
Test name
Test status
Simulation time 15674701666 ps
CPU time 11.98 seconds
Started Mar 21 02:20:42 PM PDT 24
Finished Mar 21 02:20:54 PM PDT 24
Peak memory 240684 kb
Host smart-63bb9761-a065-41a8-a2b0-7c862b3052e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242291112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.4242291112
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.4097031833
Short name T53
Test name
Test status
Simulation time 41435760 ps
CPU time 0.8 seconds
Started Mar 21 02:20:54 PM PDT 24
Finished Mar 21 02:20:55 PM PDT 24
Peak memory 205592 kb
Host smart-1686d6ed-bf38-4d19-94bd-be0178e46982
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097031833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
4097031833
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.871834953
Short name T658
Test name
Test status
Simulation time 139297694 ps
CPU time 2.57 seconds
Started Mar 21 02:20:42 PM PDT 24
Finished Mar 21 02:20:45 PM PDT 24
Peak memory 218588 kb
Host smart-af4ee0c9-9df2-4782-837d-157c7378024d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871834953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.871834953
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.2488496284
Short name T390
Test name
Test status
Simulation time 33954506 ps
CPU time 0.76 seconds
Started Mar 21 02:20:40 PM PDT 24
Finished Mar 21 02:20:41 PM PDT 24
Peak memory 206664 kb
Host smart-bfd150bc-3083-4dbd-9a3a-d760550fb4d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488496284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.2488496284
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.638197566
Short name T8
Test name
Test status
Simulation time 5160513299 ps
CPU time 28.91 seconds
Started Mar 21 02:20:51 PM PDT 24
Finished Mar 21 02:21:20 PM PDT 24
Peak memory 236060 kb
Host smart-4b85c911-5dbc-43e1-b8eb-c4694dc8f4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638197566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.638197566
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.3813804698
Short name T44
Test name
Test status
Simulation time 38516922973 ps
CPU time 85.88 seconds
Started Mar 21 02:20:54 PM PDT 24
Finished Mar 21 02:22:20 PM PDT 24
Peak memory 252744 kb
Host smart-e1321311-6c7e-45f3-8451-9707ebd7a343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813804698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.3813804698
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.3000169104
Short name T679
Test name
Test status
Simulation time 9346433046 ps
CPU time 37.13 seconds
Started Mar 21 02:20:53 PM PDT 24
Finished Mar 21 02:21:30 PM PDT 24
Peak memory 249088 kb
Host smart-4692b824-3389-4c90-881e-29285432783c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000169104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.3000169104
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.2401392945
Short name T123
Test name
Test status
Simulation time 28140924912 ps
CPU time 28.78 seconds
Started Mar 21 02:20:54 PM PDT 24
Finished Mar 21 02:21:23 PM PDT 24
Peak memory 233248 kb
Host smart-edd2e6ba-ef68-42ed-84a5-ac25983619f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401392945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.2401392945
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.1833251937
Short name T185
Test name
Test status
Simulation time 3030136230 ps
CPU time 6.06 seconds
Started Mar 21 02:20:40 PM PDT 24
Finished Mar 21 02:20:46 PM PDT 24
Peak memory 234044 kb
Host smart-720d80d5-0330-4ab0-8030-621c7023ad2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833251937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.1833251937
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.718242186
Short name T919
Test name
Test status
Simulation time 10037814809 ps
CPU time 30.37 seconds
Started Mar 21 02:20:44 PM PDT 24
Finished Mar 21 02:21:14 PM PDT 24
Peak memory 228148 kb
Host smart-fc592293-1aba-4d21-b898-7b6cc31915cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718242186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.718242186
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.3504199670
Short name T248
Test name
Test status
Simulation time 9275955298 ps
CPU time 28.59 seconds
Started Mar 21 02:20:45 PM PDT 24
Finished Mar 21 02:21:13 PM PDT 24
Peak memory 233552 kb
Host smart-6b7e7ab4-ac79-45d1-9d31-fcd49431b323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504199670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.3504199670
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.382532601
Short name T720
Test name
Test status
Simulation time 2396864857 ps
CPU time 9.14 seconds
Started Mar 21 02:20:42 PM PDT 24
Finished Mar 21 02:20:51 PM PDT 24
Peak memory 233544 kb
Host smart-5251a3cf-cf17-443e-a352-30f6fdbd0fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382532601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.382532601
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.3650998190
Short name T827
Test name
Test status
Simulation time 217943909 ps
CPU time 4.13 seconds
Started Mar 21 02:20:50 PM PDT 24
Finished Mar 21 02:20:54 PM PDT 24
Peak memory 221924 kb
Host smart-31e26fec-ed29-49b7-8974-86d294bb602d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3650998190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.3650998190
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.2440701104
Short name T699
Test name
Test status
Simulation time 9907763814 ps
CPU time 35.35 seconds
Started Mar 21 02:20:41 PM PDT 24
Finished Mar 21 02:21:17 PM PDT 24
Peak memory 216208 kb
Host smart-6b930ad0-c8ed-4e44-b0c3-b16c50266593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440701104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2440701104
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.454816890
Short name T773
Test name
Test status
Simulation time 3741486416 ps
CPU time 5.73 seconds
Started Mar 21 02:20:42 PM PDT 24
Finished Mar 21 02:20:48 PM PDT 24
Peak memory 216188 kb
Host smart-c71f2474-9820-4596-8ec6-5f146362e7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454816890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.454816890
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.2197129463
Short name T310
Test name
Test status
Simulation time 52441640 ps
CPU time 1.08 seconds
Started Mar 21 02:20:42 PM PDT 24
Finished Mar 21 02:20:43 PM PDT 24
Peak memory 206584 kb
Host smart-224ddba1-8b3b-4564-bea2-d4601ae64b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197129463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.2197129463
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.4180958740
Short name T798
Test name
Test status
Simulation time 79906758 ps
CPU time 0.99 seconds
Started Mar 21 02:20:41 PM PDT 24
Finished Mar 21 02:20:42 PM PDT 24
Peak memory 206624 kb
Host smart-c5d6d327-9011-4ab6-bfac-44aeb0b98766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180958740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.4180958740
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.1922620779
Short name T162
Test name
Test status
Simulation time 24668437936 ps
CPU time 26.22 seconds
Started Mar 21 02:20:43 PM PDT 24
Finished Mar 21 02:21:09 PM PDT 24
Peak memory 235568 kb
Host smart-400164e1-c84a-4694-8a5c-80a521ac197b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922620779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.1922620779
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.1108943496
Short name T657
Test name
Test status
Simulation time 13991386 ps
CPU time 0.7 seconds
Started Mar 21 02:20:52 PM PDT 24
Finished Mar 21 02:20:53 PM PDT 24
Peak memory 205272 kb
Host smart-9c5e026c-11bb-45ef-8b65-079cc9e83b78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108943496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
1108943496
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.3564033413
Short name T767
Test name
Test status
Simulation time 122196389 ps
CPU time 2.9 seconds
Started Mar 21 02:20:50 PM PDT 24
Finished Mar 21 02:20:53 PM PDT 24
Peak memory 224356 kb
Host smart-2e510896-63fd-4bcc-91b6-19776c811fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564033413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.3564033413
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.770991538
Short name T370
Test name
Test status
Simulation time 16095983 ps
CPU time 0.81 seconds
Started Mar 21 02:20:51 PM PDT 24
Finished Mar 21 02:20:52 PM PDT 24
Peak memory 206368 kb
Host smart-fabf2b04-3c52-4be1-b16d-a7c9fad93f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770991538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.770991538
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.3303800656
Short name T909
Test name
Test status
Simulation time 8884203486 ps
CPU time 44.16 seconds
Started Mar 21 02:20:53 PM PDT 24
Finished Mar 21 02:21:37 PM PDT 24
Peak memory 240832 kb
Host smart-9a9f7dc9-2eaf-4eaa-b6fd-a075de0d6f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303800656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.3303800656
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.975557890
Short name T661
Test name
Test status
Simulation time 4484445334 ps
CPU time 45.85 seconds
Started Mar 21 02:20:52 PM PDT 24
Finished Mar 21 02:21:38 PM PDT 24
Peak memory 250216 kb
Host smart-3d05cde4-66b1-47ad-abd6-113f0186abcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975557890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.975557890
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.3895147120
Short name T675
Test name
Test status
Simulation time 173906669869 ps
CPU time 700.91 seconds
Started Mar 21 02:20:50 PM PDT 24
Finished Mar 21 02:32:31 PM PDT 24
Peak memory 252180 kb
Host smart-834bf7e7-c2bb-4afa-b224-f681fd414636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895147120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.3895147120
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.497414474
Short name T501
Test name
Test status
Simulation time 1945363031 ps
CPU time 15.78 seconds
Started Mar 21 02:20:53 PM PDT 24
Finished Mar 21 02:21:09 PM PDT 24
Peak memory 224336 kb
Host smart-db04bcd8-3a6f-4ba4-bb74-868905b389fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497414474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.497414474
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.1372471970
Short name T795
Test name
Test status
Simulation time 12531201948 ps
CPU time 10.81 seconds
Started Mar 21 02:20:53 PM PDT 24
Finished Mar 21 02:21:04 PM PDT 24
Peak memory 220188 kb
Host smart-adc642a1-13cc-4042-b516-aa6ab88f8c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372471970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.1372471970
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.4077562168
Short name T911
Test name
Test status
Simulation time 28051111345 ps
CPU time 33.79 seconds
Started Mar 21 02:20:53 PM PDT 24
Finished Mar 21 02:21:27 PM PDT 24
Peak memory 240604 kb
Host smart-d6e933fe-091b-48ef-9abd-d17ba06da69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077562168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.4077562168
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.1129926090
Short name T931
Test name
Test status
Simulation time 787553090 ps
CPU time 7.66 seconds
Started Mar 21 02:20:51 PM PDT 24
Finished Mar 21 02:20:58 PM PDT 24
Peak memory 234576 kb
Host smart-66d7c949-3606-4f33-8416-324a7f7d5e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129926090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.1129926090
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.3279974772
Short name T607
Test name
Test status
Simulation time 5008405277 ps
CPU time 13.86 seconds
Started Mar 21 02:20:50 PM PDT 24
Finished Mar 21 02:21:04 PM PDT 24
Peak memory 218412 kb
Host smart-3e42c3ee-8221-4fa9-8556-310991696c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279974772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3279974772
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.2184912970
Short name T711
Test name
Test status
Simulation time 359131905 ps
CPU time 3.33 seconds
Started Mar 21 02:20:53 PM PDT 24
Finished Mar 21 02:20:56 PM PDT 24
Peak memory 220156 kb
Host smart-d9acdf1c-9406-4c86-b928-18d1dceeaefa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2184912970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.2184912970
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.4147561211
Short name T748
Test name
Test status
Simulation time 40822626535 ps
CPU time 391.66 seconds
Started Mar 21 02:20:54 PM PDT 24
Finished Mar 21 02:27:25 PM PDT 24
Peak memory 266012 kb
Host smart-78454e45-696f-4acc-957c-7dce390c1ded
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147561211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.4147561211
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.3800758949
Short name T574
Test name
Test status
Simulation time 5397855092 ps
CPU time 24.37 seconds
Started Mar 21 02:20:50 PM PDT 24
Finished Mar 21 02:21:15 PM PDT 24
Peak memory 216136 kb
Host smart-d88ee9a2-9059-41aa-9e76-aa7a13fbd9f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800758949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.3800758949
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.335735061
Short name T702
Test name
Test status
Simulation time 4699735104 ps
CPU time 12.57 seconds
Started Mar 21 02:20:52 PM PDT 24
Finished Mar 21 02:21:05 PM PDT 24
Peak memory 216164 kb
Host smart-d5e49c82-f61c-41c5-b3d9-44db300728a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335735061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.335735061
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.1290248926
Short name T515
Test name
Test status
Simulation time 195057470 ps
CPU time 0.91 seconds
Started Mar 21 02:20:56 PM PDT 24
Finished Mar 21 02:20:57 PM PDT 24
Peak memory 206232 kb
Host smart-8e07d453-08a7-4b34-8a46-3b2676133ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290248926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.1290248926
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.716181955
Short name T346
Test name
Test status
Simulation time 264892799 ps
CPU time 0.9 seconds
Started Mar 21 02:20:49 PM PDT 24
Finished Mar 21 02:20:50 PM PDT 24
Peak memory 205668 kb
Host smart-967dacb0-65a5-4dd4-a2b4-092b6583d3fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716181955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.716181955
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.1446820069
Short name T890
Test name
Test status
Simulation time 953916278 ps
CPU time 6.95 seconds
Started Mar 21 02:20:51 PM PDT 24
Finished Mar 21 02:20:58 PM PDT 24
Peak memory 221304 kb
Host smart-141e90cb-2f71-46b9-90a3-d1d2b2b7d798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446820069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.1446820069
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.1880495973
Short name T737
Test name
Test status
Simulation time 43745503 ps
CPU time 0.75 seconds
Started Mar 21 02:16:38 PM PDT 24
Finished Mar 21 02:16:39 PM PDT 24
Peak memory 205260 kb
Host smart-e09e5047-7243-4b6f-9e0b-67c61896fcb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880495973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.1
880495973
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.3430782215
Short name T719
Test name
Test status
Simulation time 462258237 ps
CPU time 4.03 seconds
Started Mar 21 02:16:37 PM PDT 24
Finished Mar 21 02:16:41 PM PDT 24
Peak memory 233204 kb
Host smart-c6141865-c981-42dc-b4b9-0d9594da28b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430782215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.3430782215
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.520887594
Short name T844
Test name
Test status
Simulation time 113599609 ps
CPU time 0.78 seconds
Started Mar 21 02:16:27 PM PDT 24
Finished Mar 21 02:16:28 PM PDT 24
Peak memory 205324 kb
Host smart-82ef5b37-5abf-42e2-82dd-c1b09685ba19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520887594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.520887594
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.2009065405
Short name T254
Test name
Test status
Simulation time 204686701842 ps
CPU time 459.85 seconds
Started Mar 21 02:16:37 PM PDT 24
Finished Mar 21 02:24:17 PM PDT 24
Peak memory 265392 kb
Host smart-4bb61abf-6d0a-4db3-be8a-a7b05c52f8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009065405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.2009065405
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.924405025
Short name T839
Test name
Test status
Simulation time 21479359517 ps
CPU time 127.97 seconds
Started Mar 21 02:16:39 PM PDT 24
Finished Mar 21 02:18:47 PM PDT 24
Peak memory 235116 kb
Host smart-09b8faeb-de9c-48ee-a52b-32d629c14830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924405025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.924405025
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.4134610291
Short name T236
Test name
Test status
Simulation time 56180050674 ps
CPU time 141.17 seconds
Started Mar 21 02:16:40 PM PDT 24
Finished Mar 21 02:19:01 PM PDT 24
Peak memory 257240 kb
Host smart-3c36208e-6e22-4726-8418-eb6e2b6ff71f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134610291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.4134610291
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.1509233768
Short name T470
Test name
Test status
Simulation time 44857791845 ps
CPU time 26.04 seconds
Started Mar 21 02:16:38 PM PDT 24
Finished Mar 21 02:17:04 PM PDT 24
Peak memory 240796 kb
Host smart-1da13b39-3744-478f-8331-8cc454bb9d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509233768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.1509233768
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.1103812663
Short name T733
Test name
Test status
Simulation time 4782813546 ps
CPU time 14.44 seconds
Started Mar 21 02:16:37 PM PDT 24
Finished Mar 21 02:16:51 PM PDT 24
Peak memory 224388 kb
Host smart-961a5bff-d3dc-427c-afea-749d8a3d832f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103812663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.1103812663
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.1601797888
Short name T683
Test name
Test status
Simulation time 2734880077 ps
CPU time 5.62 seconds
Started Mar 21 02:16:40 PM PDT 24
Finished Mar 21 02:16:45 PM PDT 24
Peak memory 232684 kb
Host smart-219ba536-0190-4d94-8108-ebec654a258a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601797888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.1601797888
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.1498508445
Short name T567
Test name
Test status
Simulation time 997721298 ps
CPU time 5.12 seconds
Started Mar 21 02:16:38 PM PDT 24
Finished Mar 21 02:16:43 PM PDT 24
Peak memory 233512 kb
Host smart-2928bf22-adb0-493e-ba75-8bdad33f9b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498508445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.1498508445
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.784597164
Short name T825
Test name
Test status
Simulation time 590762786 ps
CPU time 7.04 seconds
Started Mar 21 02:16:39 PM PDT 24
Finished Mar 21 02:16:46 PM PDT 24
Peak memory 236900 kb
Host smart-6188f7d8-d51c-4e2e-8d46-0b4744a77aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784597164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.784597164
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_ram_cfg.3906039234
Short name T299
Test name
Test status
Simulation time 26126052 ps
CPU time 0.75 seconds
Started Mar 21 02:16:27 PM PDT 24
Finished Mar 21 02:16:28 PM PDT 24
Peak memory 216108 kb
Host smart-d3513dd4-4373-4831-82dc-97d52c83f13d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906039234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_ram_cfg.3906039234
Directory /workspace/3.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.3013284238
Short name T925
Test name
Test status
Simulation time 2864730510 ps
CPU time 7.05 seconds
Started Mar 21 02:16:37 PM PDT 24
Finished Mar 21 02:16:45 PM PDT 24
Peak memory 222680 kb
Host smart-172d989d-9e55-44ed-9d35-a430f1eef528
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3013284238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.3013284238
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.2377739793
Short name T64
Test name
Test status
Simulation time 304314822 ps
CPU time 1.18 seconds
Started Mar 21 02:16:45 PM PDT 24
Finished Mar 21 02:16:46 PM PDT 24
Peak memory 236420 kb
Host smart-218d7c23-ddc8-4e49-95c3-11c69c608ec9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377739793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.2377739793
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.3420402217
Short name T221
Test name
Test status
Simulation time 867772888858 ps
CPU time 396.91 seconds
Started Mar 21 02:16:36 PM PDT 24
Finished Mar 21 02:23:13 PM PDT 24
Peak memory 253228 kb
Host smart-74e0ea99-fc58-40fb-adfd-fcca378f6a51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420402217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.3420402217
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.2482086396
Short name T540
Test name
Test status
Simulation time 14978031962 ps
CPU time 44.69 seconds
Started Mar 21 02:16:23 PM PDT 24
Finished Mar 21 02:17:08 PM PDT 24
Peak memory 216184 kb
Host smart-848016e0-57c6-47a0-a8ee-654550cbe318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482086396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.2482086396
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.3876184057
Short name T829
Test name
Test status
Simulation time 2148652962 ps
CPU time 5.73 seconds
Started Mar 21 02:16:28 PM PDT 24
Finished Mar 21 02:16:34 PM PDT 24
Peak memory 216096 kb
Host smart-0317a064-5b32-4935-b60b-e78ba0c85d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876184057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.3876184057
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.4064140581
Short name T892
Test name
Test status
Simulation time 15082099 ps
CPU time 0.76 seconds
Started Mar 21 02:16:26 PM PDT 24
Finished Mar 21 02:16:27 PM PDT 24
Peak memory 205588 kb
Host smart-cf33e299-f8f4-447a-af77-2cb75e8f7f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064140581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.4064140581
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.694677623
Short name T485
Test name
Test status
Simulation time 550735761 ps
CPU time 0.94 seconds
Started Mar 21 02:16:27 PM PDT 24
Finished Mar 21 02:16:28 PM PDT 24
Peak memory 206548 kb
Host smart-f0b18ffc-0ebf-45e8-a3f7-55776db52deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694677623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.694677623
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.2826106459
Short name T652
Test name
Test status
Simulation time 4512045481 ps
CPU time 8.68 seconds
Started Mar 21 02:16:37 PM PDT 24
Finished Mar 21 02:16:46 PM PDT 24
Peak memory 233804 kb
Host smart-0ef35de6-5ca7-4fa6-83ec-431967c3fe22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826106459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.2826106459
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.789864622
Short name T659
Test name
Test status
Simulation time 52721766 ps
CPU time 0.73 seconds
Started Mar 21 02:21:00 PM PDT 24
Finished Mar 21 02:21:01 PM PDT 24
Peak memory 205272 kb
Host smart-4b6ca7ba-e719-4eda-8fe8-88030c747104
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789864622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.789864622
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.2070246431
Short name T563
Test name
Test status
Simulation time 137035308 ps
CPU time 2.5 seconds
Started Mar 21 02:20:52 PM PDT 24
Finished Mar 21 02:20:55 PM PDT 24
Peak memory 233288 kb
Host smart-35131c33-e5bc-41e5-929e-56e386bcff38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070246431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.2070246431
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.3324601266
Short name T316
Test name
Test status
Simulation time 50322946 ps
CPU time 0.74 seconds
Started Mar 21 02:20:51 PM PDT 24
Finished Mar 21 02:20:52 PM PDT 24
Peak memory 205520 kb
Host smart-7e2686ed-7136-4c80-a856-4998a558d168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324601266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.3324601266
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.2885490751
Short name T210
Test name
Test status
Simulation time 39067811171 ps
CPU time 56.01 seconds
Started Mar 21 02:20:52 PM PDT 24
Finished Mar 21 02:21:49 PM PDT 24
Peak memory 238800 kb
Host smart-ed975c8a-9a77-43b0-a647-d201e99951fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885490751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.2885490751
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.2109825733
Short name T542
Test name
Test status
Simulation time 4645615498 ps
CPU time 42.63 seconds
Started Mar 21 02:20:52 PM PDT 24
Finished Mar 21 02:21:35 PM PDT 24
Peak memory 236472 kb
Host smart-f52aadac-0dc1-41c5-826b-2f83099efce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109825733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.2109825733
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.585402703
Short name T832
Test name
Test status
Simulation time 95646826765 ps
CPU time 93.36 seconds
Started Mar 21 02:20:51 PM PDT 24
Finished Mar 21 02:22:25 PM PDT 24
Peak memory 249104 kb
Host smart-d74e7567-5231-47ec-8ab3-7b12f66287c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585402703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idle
.585402703
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.3898083992
Short name T416
Test name
Test status
Simulation time 179448302 ps
CPU time 6.3 seconds
Started Mar 21 02:20:53 PM PDT 24
Finished Mar 21 02:20:59 PM PDT 24
Peak memory 224348 kb
Host smart-dadeb126-914a-4961-b204-b7617b15769c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898083992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.3898083992
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.1014615417
Short name T872
Test name
Test status
Simulation time 345567256 ps
CPU time 2.78 seconds
Started Mar 21 02:20:53 PM PDT 24
Finished Mar 21 02:20:56 PM PDT 24
Peak memory 216240 kb
Host smart-3e05fc08-0cb2-401b-945d-fbee52d776bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014615417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.1014615417
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.2224903681
Short name T541
Test name
Test status
Simulation time 1267863271 ps
CPU time 4.5 seconds
Started Mar 21 02:20:52 PM PDT 24
Finished Mar 21 02:20:57 PM PDT 24
Peak memory 229784 kb
Host smart-224cb9a6-dad0-4a45-922a-437ec73fa218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224903681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.2224903681
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.2039156867
Short name T250
Test name
Test status
Simulation time 49247719460 ps
CPU time 35.59 seconds
Started Mar 21 02:20:54 PM PDT 24
Finished Mar 21 02:21:30 PM PDT 24
Peak memory 229292 kb
Host smart-97469637-24bb-44ba-a450-b46dd3a1bba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039156867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.2039156867
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.1329690765
Short name T613
Test name
Test status
Simulation time 2013226125 ps
CPU time 6.96 seconds
Started Mar 21 02:20:54 PM PDT 24
Finished Mar 21 02:21:01 PM PDT 24
Peak memory 219120 kb
Host smart-aa84ef2a-2546-4f09-adab-8f8f4b4cc05f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1329690765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.1329690765
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.196573496
Short name T149
Test name
Test status
Simulation time 229293033197 ps
CPU time 340.86 seconds
Started Mar 21 02:21:01 PM PDT 24
Finished Mar 21 02:26:42 PM PDT 24
Peak memory 273672 kb
Host smart-971e726b-70cf-42e4-93d8-77b46c47ee2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196573496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stres
s_all.196573496
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.1666813258
Short name T342
Test name
Test status
Simulation time 3749091407 ps
CPU time 30.68 seconds
Started Mar 21 02:20:51 PM PDT 24
Finished Mar 21 02:21:22 PM PDT 24
Peak memory 216228 kb
Host smart-413c9f96-f797-4c1b-a97b-b85c2849bca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666813258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.1666813258
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.1565070114
Short name T728
Test name
Test status
Simulation time 6465736510 ps
CPU time 22.21 seconds
Started Mar 21 02:20:52 PM PDT 24
Finished Mar 21 02:21:15 PM PDT 24
Peak memory 216188 kb
Host smart-c0c6cc34-c0d8-490c-9863-f7382b5e012d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565070114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.1565070114
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.910170535
Short name T323
Test name
Test status
Simulation time 91360906 ps
CPU time 2.34 seconds
Started Mar 21 02:20:53 PM PDT 24
Finished Mar 21 02:20:56 PM PDT 24
Peak memory 216120 kb
Host smart-657ed0d9-e7c5-4e2b-b8d9-5528d3807152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910170535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.910170535
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.2702205259
Short name T503
Test name
Test status
Simulation time 27738789 ps
CPU time 0.73 seconds
Started Mar 21 02:20:54 PM PDT 24
Finished Mar 21 02:20:55 PM PDT 24
Peak memory 205616 kb
Host smart-fb8a6073-e068-40e2-bf7f-a452419f26d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702205259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.2702205259
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.232141682
Short name T206
Test name
Test status
Simulation time 4676367280 ps
CPU time 18.13 seconds
Started Mar 21 02:20:50 PM PDT 24
Finished Mar 21 02:21:08 PM PDT 24
Peak memory 218656 kb
Host smart-3c622784-e968-459d-a5d0-454f2a717d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232141682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.232141682
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.2421505867
Short name T462
Test name
Test status
Simulation time 14867192 ps
CPU time 0.74 seconds
Started Mar 21 02:21:05 PM PDT 24
Finished Mar 21 02:21:06 PM PDT 24
Peak memory 205236 kb
Host smart-2a2f27d7-460a-4c16-a89b-a16dc5b70059
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421505867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
2421505867
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.1718651208
Short name T386
Test name
Test status
Simulation time 218541452 ps
CPU time 2.79 seconds
Started Mar 21 02:20:59 PM PDT 24
Finished Mar 21 02:21:02 PM PDT 24
Peak memory 217224 kb
Host smart-05994b0a-bb98-4485-82e0-c73ab1088bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718651208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.1718651208
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.3129472464
Short name T790
Test name
Test status
Simulation time 201876869 ps
CPU time 0.84 seconds
Started Mar 21 02:21:03 PM PDT 24
Finished Mar 21 02:21:04 PM PDT 24
Peak memory 206336 kb
Host smart-6e45dbd1-cde2-4ba2-b167-88a210c69182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129472464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.3129472464
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.2160660005
Short name T949
Test name
Test status
Simulation time 7432866228 ps
CPU time 75.45 seconds
Started Mar 21 02:20:59 PM PDT 24
Finished Mar 21 02:22:15 PM PDT 24
Peak memory 250028 kb
Host smart-010666d2-ed26-4d34-aa73-75791762a53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160660005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.2160660005
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.2688950076
Short name T42
Test name
Test status
Simulation time 127952537475 ps
CPU time 223.24 seconds
Started Mar 21 02:20:58 PM PDT 24
Finished Mar 21 02:24:41 PM PDT 24
Peak memory 254232 kb
Host smart-4fe5c870-6ec5-44c3-90b4-a2c00b92d8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688950076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.2688950076
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.2105255182
Short name T769
Test name
Test status
Simulation time 152322136510 ps
CPU time 285.86 seconds
Started Mar 21 02:21:01 PM PDT 24
Finished Mar 21 02:25:47 PM PDT 24
Peak memory 259784 kb
Host smart-14b437ec-0bab-41e4-b20d-75cebd54727d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105255182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.2105255182
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.3948895770
Short name T761
Test name
Test status
Simulation time 1508469862 ps
CPU time 16.06 seconds
Started Mar 21 02:21:04 PM PDT 24
Finished Mar 21 02:21:21 PM PDT 24
Peak memory 252008 kb
Host smart-6fe7618d-0633-4158-8b87-2b42d14ce8c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948895770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.3948895770
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.4256064967
Short name T686
Test name
Test status
Simulation time 307242889 ps
CPU time 3.41 seconds
Started Mar 21 02:20:58 PM PDT 24
Finished Mar 21 02:21:02 PM PDT 24
Peak memory 218292 kb
Host smart-6d1ea2d2-dc5f-4b15-98af-7b5563cc704e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256064967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.4256064967
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.1809684921
Short name T877
Test name
Test status
Simulation time 97258120519 ps
CPU time 61.2 seconds
Started Mar 21 02:21:05 PM PDT 24
Finished Mar 21 02:22:06 PM PDT 24
Peak memory 234964 kb
Host smart-d956cb09-b086-4fca-bf62-07e31cd8e60a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809684921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.1809684921
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.151803599
Short name T821
Test name
Test status
Simulation time 669002909 ps
CPU time 5.8 seconds
Started Mar 21 02:21:00 PM PDT 24
Finished Mar 21 02:21:06 PM PDT 24
Peak memory 217256 kb
Host smart-034a9b54-d6b7-4450-9b8e-5a9db73ccdd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151803599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap
.151803599
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.3273233723
Short name T389
Test name
Test status
Simulation time 2279192270 ps
CPU time 3.33 seconds
Started Mar 21 02:21:00 PM PDT 24
Finished Mar 21 02:21:03 PM PDT 24
Peak memory 217760 kb
Host smart-eb9fda51-9306-4491-b94c-36ab5b024c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273233723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.3273233723
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.1564264146
Short name T758
Test name
Test status
Simulation time 542884308 ps
CPU time 5.13 seconds
Started Mar 21 02:21:05 PM PDT 24
Finished Mar 21 02:21:10 PM PDT 24
Peak memory 221488 kb
Host smart-94cfefcb-d800-4d98-9c8f-65deea61b203
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1564264146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.1564264146
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.2469605650
Short name T252
Test name
Test status
Simulation time 120189099665 ps
CPU time 268.24 seconds
Started Mar 21 02:21:01 PM PDT 24
Finished Mar 21 02:25:29 PM PDT 24
Peak memory 273092 kb
Host smart-8e074c32-2e1a-4f5c-938a-89a605aea068
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469605650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.2469605650
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.3146906359
Short name T2
Test name
Test status
Simulation time 27248642568 ps
CPU time 39.11 seconds
Started Mar 21 02:21:00 PM PDT 24
Finished Mar 21 02:21:39 PM PDT 24
Peak memory 216232 kb
Host smart-1ef4e70b-51c6-44b8-a5a2-f331234cbcb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146906359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.3146906359
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.1927149294
Short name T360
Test name
Test status
Simulation time 4603615342 ps
CPU time 15.85 seconds
Started Mar 21 02:21:05 PM PDT 24
Finished Mar 21 02:21:21 PM PDT 24
Peak memory 216184 kb
Host smart-17f34484-d686-4b58-a658-83c7fe79e4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927149294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.1927149294
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.1334928147
Short name T900
Test name
Test status
Simulation time 268257294 ps
CPU time 8.96 seconds
Started Mar 21 02:20:58 PM PDT 24
Finished Mar 21 02:21:08 PM PDT 24
Peak memory 216256 kb
Host smart-8df145ad-c438-42b3-9310-523a2a01fc9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334928147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.1334928147
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.1965051404
Short name T789
Test name
Test status
Simulation time 108522334 ps
CPU time 1.06 seconds
Started Mar 21 02:21:00 PM PDT 24
Finished Mar 21 02:21:01 PM PDT 24
Peak memory 206624 kb
Host smart-f5c2cac3-ccd9-4bbc-a608-0afa45c43e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965051404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.1965051404
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.3339026247
Short name T437
Test name
Test status
Simulation time 15190261792 ps
CPU time 42.79 seconds
Started Mar 21 02:21:00 PM PDT 24
Finished Mar 21 02:21:43 PM PDT 24
Peak memory 238796 kb
Host smart-f2d5b9db-b71f-466d-84ed-99a6516f49ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339026247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.3339026247
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.1028312744
Short name T282
Test name
Test status
Simulation time 17431180 ps
CPU time 0.71 seconds
Started Mar 21 02:21:09 PM PDT 24
Finished Mar 21 02:21:10 PM PDT 24
Peak memory 205624 kb
Host smart-d9c6f231-75be-4984-88a1-19ece7ff1168
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028312744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
1028312744
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.4136907681
Short name T763
Test name
Test status
Simulation time 324530804 ps
CPU time 3.92 seconds
Started Mar 21 02:21:09 PM PDT 24
Finished Mar 21 02:21:13 PM PDT 24
Peak memory 234364 kb
Host smart-32e08749-f273-4110-aa21-6bd7f9cf09d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136907681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.4136907681
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.644935422
Short name T369
Test name
Test status
Simulation time 53092965 ps
CPU time 0.79 seconds
Started Mar 21 02:20:57 PM PDT 24
Finished Mar 21 02:20:58 PM PDT 24
Peak memory 206652 kb
Host smart-5da3a182-37fe-422a-88b2-0e3410d23375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644935422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.644935422
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.2328711823
Short name T663
Test name
Test status
Simulation time 2199306197 ps
CPU time 40.02 seconds
Started Mar 21 02:21:06 PM PDT 24
Finished Mar 21 02:21:47 PM PDT 24
Peak memory 240616 kb
Host smart-b44d3aa2-6eb3-4c4d-9ca2-4605fc20aaa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328711823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.2328711823
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.2827291860
Short name T918
Test name
Test status
Simulation time 158404201268 ps
CPU time 284.43 seconds
Started Mar 21 02:21:13 PM PDT 24
Finished Mar 21 02:25:58 PM PDT 24
Peak memory 256296 kb
Host smart-daa2154e-5377-4d3e-8f89-a4064325048e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827291860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.2827291860
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.2064471352
Short name T339
Test name
Test status
Simulation time 120254903409 ps
CPU time 209.91 seconds
Started Mar 21 02:21:10 PM PDT 24
Finished Mar 21 02:24:40 PM PDT 24
Peak memory 248972 kb
Host smart-9e7ac6b2-5af6-4b52-bb46-423346ae3d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064471352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.2064471352
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.139020535
Short name T263
Test name
Test status
Simulation time 2143463273 ps
CPU time 7.4 seconds
Started Mar 21 02:21:09 PM PDT 24
Finished Mar 21 02:21:16 PM PDT 24
Peak memory 234180 kb
Host smart-6acf0671-6ddb-4f4a-9b4c-f1bcba204a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139020535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.139020535
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.2494748502
Short name T915
Test name
Test status
Simulation time 3226015248 ps
CPU time 10.45 seconds
Started Mar 21 02:21:07 PM PDT 24
Finished Mar 21 02:21:18 PM PDT 24
Peak memory 220892 kb
Host smart-24839ca5-62c1-4855-9a44-3291b3c855e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494748502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.2494748502
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.941614699
Short name T644
Test name
Test status
Simulation time 676850052 ps
CPU time 10.78 seconds
Started Mar 21 02:21:08 PM PDT 24
Finished Mar 21 02:21:19 PM PDT 24
Peak memory 233284 kb
Host smart-2eca6484-6034-4800-85a7-9f456ffb5d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941614699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.941614699
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.1154763127
Short name T24
Test name
Test status
Simulation time 2207972939 ps
CPU time 10.08 seconds
Started Mar 21 02:21:09 PM PDT 24
Finished Mar 21 02:21:19 PM PDT 24
Peak memory 248968 kb
Host smart-9866a255-5e7f-4860-915d-e07848f0a445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154763127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.1154763127
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.2978680290
Short name T953
Test name
Test status
Simulation time 1070075315 ps
CPU time 4.19 seconds
Started Mar 21 02:21:07 PM PDT 24
Finished Mar 21 02:21:11 PM PDT 24
Peak memory 219288 kb
Host smart-e60318ac-f619-4ab5-9dfe-e11cd3987eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978680290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.2978680290
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.3689695756
Short name T965
Test name
Test status
Simulation time 4982494575 ps
CPU time 4.44 seconds
Started Mar 21 02:21:10 PM PDT 24
Finished Mar 21 02:21:15 PM PDT 24
Peak memory 222964 kb
Host smart-f76cd63e-e478-412d-b4ee-d52c5065bee7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3689695756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.3689695756
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.259609467
Short name T894
Test name
Test status
Simulation time 61295270846 ps
CPU time 169.48 seconds
Started Mar 21 02:21:10 PM PDT 24
Finished Mar 21 02:24:00 PM PDT 24
Peak memory 252992 kb
Host smart-90f42457-d537-4ed6-ae0d-55d3e570877f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259609467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stres
s_all.259609467
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.3231327799
Short name T347
Test name
Test status
Simulation time 4135592113 ps
CPU time 12.63 seconds
Started Mar 21 02:20:57 PM PDT 24
Finished Mar 21 02:21:10 PM PDT 24
Peak memory 216244 kb
Host smart-2620acbb-03bd-4db1-8365-5e9e1faf2ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231327799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.3231327799
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.1393712917
Short name T585
Test name
Test status
Simulation time 37713346744 ps
CPU time 25.27 seconds
Started Mar 21 02:20:59 PM PDT 24
Finished Mar 21 02:21:25 PM PDT 24
Peak memory 216132 kb
Host smart-fb24edba-ca64-4fd0-b253-7ac2373551cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393712917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.1393712917
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.672908801
Short name T888
Test name
Test status
Simulation time 223567956 ps
CPU time 3.63 seconds
Started Mar 21 02:20:59 PM PDT 24
Finished Mar 21 02:21:03 PM PDT 24
Peak memory 216044 kb
Host smart-2c63cec2-2463-4d8c-999a-b0663789d6f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672908801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.672908801
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.390980693
Short name T688
Test name
Test status
Simulation time 85363069 ps
CPU time 0.93 seconds
Started Mar 21 02:21:01 PM PDT 24
Finished Mar 21 02:21:03 PM PDT 24
Peak memory 205592 kb
Host smart-e2b29fc8-c90c-4d44-b4f3-ea5aa9269478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390980693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.390980693
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.729926947
Short name T619
Test name
Test status
Simulation time 6324418874 ps
CPU time 21.07 seconds
Started Mar 21 02:21:11 PM PDT 24
Finished Mar 21 02:21:32 PM PDT 24
Peak memory 240780 kb
Host smart-09b2e501-a390-43e8-bbe5-6bf230f0c5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729926947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.729926947
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.479286994
Short name T324
Test name
Test status
Simulation time 51234042 ps
CPU time 0.7 seconds
Started Mar 21 02:21:19 PM PDT 24
Finished Mar 21 02:21:20 PM PDT 24
Peak memory 204692 kb
Host smart-4241a17e-2227-48a3-978a-24d68a2d75d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479286994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.479286994
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.1338234648
Short name T599
Test name
Test status
Simulation time 139391928 ps
CPU time 2.16 seconds
Started Mar 21 02:21:17 PM PDT 24
Finished Mar 21 02:21:20 PM PDT 24
Peak memory 224308 kb
Host smart-e37a1216-cf8d-4e30-a125-703dd362c123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338234648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.1338234648
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.132289497
Short name T539
Test name
Test status
Simulation time 15329806 ps
CPU time 0.76 seconds
Started Mar 21 02:21:08 PM PDT 24
Finished Mar 21 02:21:09 PM PDT 24
Peak memory 205632 kb
Host smart-10ad0968-9b74-4329-a8c1-fe14e9a80005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132289497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.132289497
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.2309854052
Short name T881
Test name
Test status
Simulation time 44410523635 ps
CPU time 210.78 seconds
Started Mar 21 02:21:17 PM PDT 24
Finished Mar 21 02:24:48 PM PDT 24
Peak memory 263812 kb
Host smart-ce16ebf9-bb0b-4e2d-a375-3b0c44365f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309854052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.2309854052
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.1740045900
Short name T18
Test name
Test status
Simulation time 5892978679 ps
CPU time 61.47 seconds
Started Mar 21 02:21:18 PM PDT 24
Finished Mar 21 02:22:20 PM PDT 24
Peak memory 238660 kb
Host smart-df8ea09f-cef5-4c4d-8ff7-3398909e0dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740045900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.1740045900
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.3103777595
Short name T188
Test name
Test status
Simulation time 6286495589 ps
CPU time 11.5 seconds
Started Mar 21 02:21:18 PM PDT 24
Finished Mar 21 02:21:30 PM PDT 24
Peak memory 237356 kb
Host smart-f72e6a29-0736-45ce-b867-2f027dd418dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103777595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.3103777595
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.3646582990
Short name T557
Test name
Test status
Simulation time 230122843 ps
CPU time 3.79 seconds
Started Mar 21 02:21:08 PM PDT 24
Finished Mar 21 02:21:12 PM PDT 24
Peak memory 219492 kb
Host smart-59c1577e-d179-442e-a1f3-33868e30d7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646582990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.3646582990
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.1207100998
Short name T779
Test name
Test status
Simulation time 315198167 ps
CPU time 6.36 seconds
Started Mar 21 02:21:17 PM PDT 24
Finished Mar 21 02:21:23 PM PDT 24
Peak memory 234016 kb
Host smart-ccf4d9d5-4be9-41d7-bde1-573b1e68a2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207100998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.1207100998
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.3588805134
Short name T6
Test name
Test status
Simulation time 972201548 ps
CPU time 4.95 seconds
Started Mar 21 02:21:12 PM PDT 24
Finished Mar 21 02:21:17 PM PDT 24
Peak memory 234156 kb
Host smart-c1aae75f-a584-42d0-97b4-1429c4bd8441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588805134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.3588805134
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.3798574154
Short name T783
Test name
Test status
Simulation time 23629528460 ps
CPU time 19.48 seconds
Started Mar 21 02:21:08 PM PDT 24
Finished Mar 21 02:21:28 PM PDT 24
Peak memory 216628 kb
Host smart-8137c4fd-6ec6-4b07-acfd-770db2b2b28b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798574154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.3798574154
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.796348199
Short name T527
Test name
Test status
Simulation time 3415345968 ps
CPU time 3.73 seconds
Started Mar 21 02:21:17 PM PDT 24
Finished Mar 21 02:21:21 PM PDT 24
Peak memory 218984 kb
Host smart-28687248-62de-4972-858c-ce2afa696637
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=796348199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dire
ct.796348199
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.1759367233
Short name T498
Test name
Test status
Simulation time 1478228015 ps
CPU time 13.83 seconds
Started Mar 21 02:21:09 PM PDT 24
Finished Mar 21 02:21:23 PM PDT 24
Peak memory 216168 kb
Host smart-eca46f2a-fedc-4da2-8751-716dd91d297b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759367233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.1759367233
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.2092660469
Short name T747
Test name
Test status
Simulation time 5308182964 ps
CPU time 8.17 seconds
Started Mar 21 02:21:11 PM PDT 24
Finished Mar 21 02:21:19 PM PDT 24
Peak memory 216160 kb
Host smart-c5200b2a-f3fb-4c0f-9278-09528481157f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092660469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.2092660469
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.332621239
Short name T403
Test name
Test status
Simulation time 350208259 ps
CPU time 1.83 seconds
Started Mar 21 02:21:09 PM PDT 24
Finished Mar 21 02:21:11 PM PDT 24
Peak memory 216032 kb
Host smart-0b4de47a-d8b1-4e11-a85a-22f29ad87a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332621239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.332621239
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.2909330221
Short name T433
Test name
Test status
Simulation time 25859473 ps
CPU time 0.72 seconds
Started Mar 21 02:21:13 PM PDT 24
Finished Mar 21 02:21:14 PM PDT 24
Peak memory 205608 kb
Host smart-296dc55e-6c27-4b14-b70b-8f12939e0a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909330221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.2909330221
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.4293742144
Short name T691
Test name
Test status
Simulation time 9506800678 ps
CPU time 30.62 seconds
Started Mar 21 02:21:16 PM PDT 24
Finished Mar 21 02:21:46 PM PDT 24
Peak memory 240752 kb
Host smart-bfce2033-9d70-41bd-b28e-ab823e65956a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293742144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.4293742144
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.3384396789
Short name T290
Test name
Test status
Simulation time 21995571 ps
CPU time 0.73 seconds
Started Mar 21 02:21:30 PM PDT 24
Finished Mar 21 02:21:30 PM PDT 24
Peak memory 204612 kb
Host smart-d5c88f0f-311e-4544-bae8-e4db8d792194
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384396789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
3384396789
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.410644168
Short name T560
Test name
Test status
Simulation time 249968119 ps
CPU time 2.86 seconds
Started Mar 21 02:21:18 PM PDT 24
Finished Mar 21 02:21:21 PM PDT 24
Peak memory 233760 kb
Host smart-ffc6d577-6438-4b03-984d-575e8c154908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410644168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.410644168
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.465420261
Short name T513
Test name
Test status
Simulation time 64319157 ps
CPU time 0.78 seconds
Started Mar 21 02:21:19 PM PDT 24
Finished Mar 21 02:21:20 PM PDT 24
Peak memory 206312 kb
Host smart-a92d8466-bf8b-4fa7-9c5a-83213c231cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465420261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.465420261
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.1219698023
Short name T695
Test name
Test status
Simulation time 37692119716 ps
CPU time 151.44 seconds
Started Mar 21 02:21:26 PM PDT 24
Finished Mar 21 02:23:57 PM PDT 24
Peak memory 240772 kb
Host smart-17ea611c-fd5f-411d-9911-b01c229a0271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219698023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.1219698023
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.1779047228
Short name T577
Test name
Test status
Simulation time 7497692415 ps
CPU time 21.96 seconds
Started Mar 21 02:21:19 PM PDT 24
Finished Mar 21 02:21:41 PM PDT 24
Peak memory 253480 kb
Host smart-87aebe15-87ac-433c-8a13-5e26a9330a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779047228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.1779047228
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.1812781309
Short name T86
Test name
Test status
Simulation time 2351109025 ps
CPU time 9.02 seconds
Started Mar 21 02:21:20 PM PDT 24
Finished Mar 21 02:21:29 PM PDT 24
Peak memory 233916 kb
Host smart-c17a27ef-8a3d-4c63-a871-ea924a4d1c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812781309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.1812781309
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.1794547804
Short name T849
Test name
Test status
Simulation time 38067903953 ps
CPU time 26.33 seconds
Started Mar 21 02:21:22 PM PDT 24
Finished Mar 21 02:21:48 PM PDT 24
Peak memory 233740 kb
Host smart-9ed6c6c7-acea-41b9-8001-99128b18cd77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794547804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.1794547804
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.4116436312
Short name T157
Test name
Test status
Simulation time 8693323991 ps
CPU time 17.15 seconds
Started Mar 21 02:21:20 PM PDT 24
Finished Mar 21 02:21:38 PM PDT 24
Peak memory 228224 kb
Host smart-e9d388c2-db34-4883-aa9c-b839e6ce294e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116436312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.4116436312
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.3811164007
Short name T69
Test name
Test status
Simulation time 1675443909 ps
CPU time 6.61 seconds
Started Mar 21 02:21:17 PM PDT 24
Finished Mar 21 02:21:24 PM PDT 24
Peak memory 218292 kb
Host smart-d111e7d0-b763-4590-9a75-21c82b468bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811164007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.3811164007
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.724387801
Short name T739
Test name
Test status
Simulation time 1184795910 ps
CPU time 5.46 seconds
Started Mar 21 02:21:27 PM PDT 24
Finished Mar 21 02:21:32 PM PDT 24
Peak memory 222116 kb
Host smart-e1b33b41-42f1-45a2-870d-f5454cc757d5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=724387801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dire
ct.724387801
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.283633010
Short name T649
Test name
Test status
Simulation time 76233534319 ps
CPU time 355.68 seconds
Started Mar 21 02:21:27 PM PDT 24
Finished Mar 21 02:27:23 PM PDT 24
Peak memory 255020 kb
Host smart-7e6d8b6d-741f-42e6-b6bb-b17f18475bd9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283633010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stres
s_all.283633010
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.2215854652
Short name T71
Test name
Test status
Simulation time 19459515650 ps
CPU time 26.93 seconds
Started Mar 21 02:21:17 PM PDT 24
Finished Mar 21 02:21:44 PM PDT 24
Peak memory 216172 kb
Host smart-ba9dffd5-e068-41dd-9927-2c4a238c994a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215854652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.2215854652
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.690763084
Short name T384
Test name
Test status
Simulation time 4660319572 ps
CPU time 14.04 seconds
Started Mar 21 02:21:20 PM PDT 24
Finished Mar 21 02:21:34 PM PDT 24
Peak memory 216216 kb
Host smart-a23b39e5-d6a0-413f-9053-a1d147718758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690763084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.690763084
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.1092582235
Short name T276
Test name
Test status
Simulation time 45975079 ps
CPU time 1.6 seconds
Started Mar 21 02:21:17 PM PDT 24
Finished Mar 21 02:21:19 PM PDT 24
Peak memory 216284 kb
Host smart-f43e675d-a611-4862-b86e-4040b2f0b559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092582235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.1092582235
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.239843577
Short name T487
Test name
Test status
Simulation time 51115807 ps
CPU time 0.73 seconds
Started Mar 21 02:21:20 PM PDT 24
Finished Mar 21 02:21:21 PM PDT 24
Peak memory 205672 kb
Host smart-34e78cbb-a42c-42df-ae82-9565525ba209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239843577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.239843577
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.111279326
Short name T594
Test name
Test status
Simulation time 113501223 ps
CPU time 2.57 seconds
Started Mar 21 02:21:16 PM PDT 24
Finished Mar 21 02:21:18 PM PDT 24
Peak memory 218404 kb
Host smart-5dbc9bb0-69fa-4c26-9d09-d77254ed921a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111279326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.111279326
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.1097114909
Short name T368
Test name
Test status
Simulation time 13260985 ps
CPU time 0.77 seconds
Started Mar 21 02:21:43 PM PDT 24
Finished Mar 21 02:21:44 PM PDT 24
Peak memory 205228 kb
Host smart-635d5ee5-1ccc-4a88-8d5e-c9275a36c20a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097114909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
1097114909
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.1490443358
Short name T343
Test name
Test status
Simulation time 189479549 ps
CPU time 3.94 seconds
Started Mar 21 02:21:29 PM PDT 24
Finished Mar 21 02:21:33 PM PDT 24
Peak memory 233808 kb
Host smart-b75c9fa1-22f7-4276-8888-80db64d54e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490443358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.1490443358
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.2041561017
Short name T298
Test name
Test status
Simulation time 33060947 ps
CPU time 0.81 seconds
Started Mar 21 02:21:28 PM PDT 24
Finished Mar 21 02:21:29 PM PDT 24
Peak memory 206304 kb
Host smart-5079c505-6d8d-454f-8caa-a3bf3c240047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041561017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.2041561017
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.1512457276
Short name T194
Test name
Test status
Simulation time 34137040951 ps
CPU time 57.07 seconds
Started Mar 21 02:21:29 PM PDT 24
Finished Mar 21 02:22:27 PM PDT 24
Peak memory 239584 kb
Host smart-9751beef-b599-4c90-923a-2f1f001f4f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512457276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.1512457276
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.930863433
Short name T170
Test name
Test status
Simulation time 5457759053 ps
CPU time 102.14 seconds
Started Mar 21 02:21:30 PM PDT 24
Finished Mar 21 02:23:12 PM PDT 24
Peak memory 255776 kb
Host smart-3353dcec-07ca-47d1-a445-030432eca1a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930863433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.930863433
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_intercept.683548186
Short name T106
Test name
Test status
Simulation time 3459587055 ps
CPU time 7.26 seconds
Started Mar 21 02:21:30 PM PDT 24
Finished Mar 21 02:21:37 PM PDT 24
Peak memory 233032 kb
Host smart-c076c3e2-58a8-414f-828c-034f22ed52f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683548186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.683548186
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.1970220533
Short name T438
Test name
Test status
Simulation time 456378583 ps
CPU time 8.59 seconds
Started Mar 21 02:21:29 PM PDT 24
Finished Mar 21 02:21:38 PM PDT 24
Peak memory 231776 kb
Host smart-b151a4ed-0b71-41bd-acbc-140287bc8c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970220533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.1970220533
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.401332516
Short name T660
Test name
Test status
Simulation time 333474670 ps
CPU time 4.8 seconds
Started Mar 21 02:21:29 PM PDT 24
Finished Mar 21 02:21:34 PM PDT 24
Peak memory 216596 kb
Host smart-424f00ee-9b66-47aa-8ee5-2552efbbb8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401332516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap
.401332516
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.811931358
Short name T904
Test name
Test status
Simulation time 369876666 ps
CPU time 3.06 seconds
Started Mar 21 02:21:29 PM PDT 24
Finished Mar 21 02:21:33 PM PDT 24
Peak memory 218580 kb
Host smart-ea01f044-8576-4aff-a3a0-cc40e9546284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811931358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.811931358
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.492835083
Short name T303
Test name
Test status
Simulation time 497631229 ps
CPU time 3.42 seconds
Started Mar 21 02:21:31 PM PDT 24
Finished Mar 21 02:21:35 PM PDT 24
Peak memory 218572 kb
Host smart-8b554ac2-048c-48ab-a5a3-0378ca34ea8d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=492835083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dire
ct.492835083
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.607454007
Short name T274
Test name
Test status
Simulation time 5407801896 ps
CPU time 29.73 seconds
Started Mar 21 02:21:27 PM PDT 24
Finished Mar 21 02:21:57 PM PDT 24
Peak memory 216064 kb
Host smart-b8f1db35-5620-4221-9ebb-80614765fe0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607454007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.607454007
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.1788775907
Short name T558
Test name
Test status
Simulation time 3474659881 ps
CPU time 7.79 seconds
Started Mar 21 02:21:28 PM PDT 24
Finished Mar 21 02:21:36 PM PDT 24
Peak memory 216192 kb
Host smart-c3203d79-903e-4ce5-8845-518b56d44083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788775907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.1788775907
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.2280415825
Short name T578
Test name
Test status
Simulation time 574162140 ps
CPU time 11.32 seconds
Started Mar 21 02:21:29 PM PDT 24
Finished Mar 21 02:21:40 PM PDT 24
Peak memory 216244 kb
Host smart-5ad9c66d-8b95-44cd-934e-e0d41b744a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280415825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.2280415825
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.2315382779
Short name T764
Test name
Test status
Simulation time 34910749 ps
CPU time 0.83 seconds
Started Mar 21 02:21:29 PM PDT 24
Finished Mar 21 02:21:30 PM PDT 24
Peak memory 205588 kb
Host smart-dca5926d-8411-435a-985b-46fed9994344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315382779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.2315382779
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.2489781583
Short name T184
Test name
Test status
Simulation time 301846976 ps
CPU time 4.84 seconds
Started Mar 21 02:21:30 PM PDT 24
Finished Mar 21 02:21:35 PM PDT 24
Peak memory 217156 kb
Host smart-677b164d-606c-40e9-bdc6-6f3a73cce87c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489781583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.2489781583
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.1779171019
Short name T582
Test name
Test status
Simulation time 18184190 ps
CPU time 0.71 seconds
Started Mar 21 02:21:43 PM PDT 24
Finished Mar 21 02:21:44 PM PDT 24
Peak memory 205264 kb
Host smart-c137cfb8-3a65-4ab9-9863-2892fd026360
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779171019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
1779171019
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.3582664851
Short name T214
Test name
Test status
Simulation time 1039272446 ps
CPU time 5.61 seconds
Started Mar 21 02:21:43 PM PDT 24
Finished Mar 21 02:21:49 PM PDT 24
Peak memory 233004 kb
Host smart-9e5f6042-19a0-4c14-89aa-5b81b4890159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582664851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.3582664851
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.3387950054
Short name T397
Test name
Test status
Simulation time 15314589 ps
CPU time 0.77 seconds
Started Mar 21 02:21:44 PM PDT 24
Finished Mar 21 02:21:45 PM PDT 24
Peak memory 205308 kb
Host smart-b954d142-9d43-4ce4-8367-3c34016df407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387950054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.3387950054
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.3818860485
Short name T249
Test name
Test status
Simulation time 101422465510 ps
CPU time 215.56 seconds
Started Mar 21 02:21:43 PM PDT 24
Finished Mar 21 02:25:19 PM PDT 24
Peak memory 250984 kb
Host smart-ad5f51b0-3046-4d26-b74d-1a7a49c8969c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818860485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.3818860485
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.804170718
Short name T912
Test name
Test status
Simulation time 9653121318 ps
CPU time 121.48 seconds
Started Mar 21 02:21:43 PM PDT 24
Finished Mar 21 02:23:45 PM PDT 24
Peak memory 249124 kb
Host smart-24abd4b7-7932-4c39-81ad-1c361c180bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804170718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.804170718
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.4277693669
Short name T43
Test name
Test status
Simulation time 32982455974 ps
CPU time 74.68 seconds
Started Mar 21 02:21:43 PM PDT 24
Finished Mar 21 02:22:58 PM PDT 24
Peak memory 249072 kb
Host smart-31d7ba05-c3f5-4297-b280-27d995e1d78e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277693669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.4277693669
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.1982420291
Short name T445
Test name
Test status
Simulation time 1901057122 ps
CPU time 10.66 seconds
Started Mar 21 02:21:45 PM PDT 24
Finished Mar 21 02:21:56 PM PDT 24
Peak memory 247736 kb
Host smart-67d3f32a-a960-4380-858c-d028621daecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982420291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.1982420291
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.4273481261
Short name T168
Test name
Test status
Simulation time 431389280 ps
CPU time 4.47 seconds
Started Mar 21 02:21:44 PM PDT 24
Finished Mar 21 02:21:48 PM PDT 24
Peak memory 219872 kb
Host smart-57f5dc2b-79a6-4c5d-9cb5-063c2e15feaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273481261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.4273481261
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.298066981
Short name T327
Test name
Test status
Simulation time 20482781726 ps
CPU time 18.92 seconds
Started Mar 21 02:21:44 PM PDT 24
Finished Mar 21 02:22:03 PM PDT 24
Peak memory 232652 kb
Host smart-0d39c192-c1af-4e52-a493-c7e57b3d2898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298066981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.298066981
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.2244613669
Short name T223
Test name
Test status
Simulation time 2432521481 ps
CPU time 10.58 seconds
Started Mar 21 02:21:44 PM PDT 24
Finished Mar 21 02:21:55 PM PDT 24
Peak memory 233640 kb
Host smart-0c43561a-5e13-426a-99a2-05c8733c0a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244613669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.2244613669
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.2184911406
Short name T293
Test name
Test status
Simulation time 191160385 ps
CPU time 4.14 seconds
Started Mar 21 02:21:42 PM PDT 24
Finished Mar 21 02:21:46 PM PDT 24
Peak memory 235212 kb
Host smart-8f29de29-cd21-4822-82c5-faf09b3c07ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184911406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.2184911406
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.590914097
Short name T126
Test name
Test status
Simulation time 11400132061 ps
CPU time 5.15 seconds
Started Mar 21 02:21:43 PM PDT 24
Finished Mar 21 02:21:48 PM PDT 24
Peak memory 218664 kb
Host smart-b212e9e6-54bf-45be-b4f6-1c2b03642209
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=590914097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dire
ct.590914097
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.49771033
Short name T407
Test name
Test status
Simulation time 95810670 ps
CPU time 1.07 seconds
Started Mar 21 02:21:43 PM PDT 24
Finished Mar 21 02:21:45 PM PDT 24
Peak memory 206644 kb
Host smart-900c4c11-0d9b-4916-9872-634b8f4cf742
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49771033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stress
_all.49771033
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.3601966626
Short name T374
Test name
Test status
Simulation time 1003883535 ps
CPU time 12.41 seconds
Started Mar 21 02:21:42 PM PDT 24
Finished Mar 21 02:21:54 PM PDT 24
Peak memory 216144 kb
Host smart-cddb32f0-2cfc-4ee8-a30e-da2dab9ddce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601966626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.3601966626
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.2157106121
Short name T566
Test name
Test status
Simulation time 71213084 ps
CPU time 1.39 seconds
Started Mar 21 02:21:43 PM PDT 24
Finished Mar 21 02:21:44 PM PDT 24
Peak memory 206780 kb
Host smart-7e60ce4c-229d-44a3-a13f-8d50863f021d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157106121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.2157106121
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.2508818076
Short name T866
Test name
Test status
Simulation time 13178239 ps
CPU time 0.77 seconds
Started Mar 21 02:21:44 PM PDT 24
Finished Mar 21 02:21:45 PM PDT 24
Peak memory 205616 kb
Host smart-5341cda2-b99f-48af-a2bf-b33fa7678199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508818076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.2508818076
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.1884077329
Short name T509
Test name
Test status
Simulation time 37355284 ps
CPU time 0.89 seconds
Started Mar 21 02:21:46 PM PDT 24
Finished Mar 21 02:21:47 PM PDT 24
Peak memory 206596 kb
Host smart-b5fc2332-4c10-4a65-81c4-7cfc0605c8f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884077329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.1884077329
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.3971377452
Short name T198
Test name
Test status
Simulation time 6089687241 ps
CPU time 16.55 seconds
Started Mar 21 02:21:42 PM PDT 24
Finished Mar 21 02:21:58 PM PDT 24
Peak memory 227208 kb
Host smart-c3c4823c-907b-44be-8c03-7bf894f37c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971377452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.3971377452
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.3284633308
Short name T934
Test name
Test status
Simulation time 15806979 ps
CPU time 0.74 seconds
Started Mar 21 02:21:58 PM PDT 24
Finished Mar 21 02:21:58 PM PDT 24
Peak memory 205280 kb
Host smart-457c2c97-3cd7-4e39-9901-80fcc8fe5d46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284633308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
3284633308
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.2327942842
Short name T807
Test name
Test status
Simulation time 54345481 ps
CPU time 2.92 seconds
Started Mar 21 02:21:54 PM PDT 24
Finished Mar 21 02:21:57 PM PDT 24
Peak memory 234204 kb
Host smart-67886245-f8f3-4b69-96c8-2030ac9910c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327942842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.2327942842
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.3135950805
Short name T401
Test name
Test status
Simulation time 78014076 ps
CPU time 0.77 seconds
Started Mar 21 02:21:44 PM PDT 24
Finished Mar 21 02:21:45 PM PDT 24
Peak memory 205604 kb
Host smart-2f92f792-56dd-42cb-a097-935264aa4731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135950805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.3135950805
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.2909652879
Short name T530
Test name
Test status
Simulation time 103525228216 ps
CPU time 161.43 seconds
Started Mar 21 02:22:00 PM PDT 24
Finished Mar 21 02:24:42 PM PDT 24
Peak memory 257244 kb
Host smart-3b58984d-1eb5-4dce-a713-84a831a8abeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909652879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.2909652879
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.3103523319
Short name T500
Test name
Test status
Simulation time 16496202002 ps
CPU time 140.89 seconds
Started Mar 21 02:21:57 PM PDT 24
Finished Mar 21 02:24:18 PM PDT 24
Peak memory 239744 kb
Host smart-c28485d1-70e2-4ce4-ac13-250808a64089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103523319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.3103523319
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.3537810147
Short name T740
Test name
Test status
Simulation time 8483893436 ps
CPU time 47.15 seconds
Started Mar 21 02:21:54 PM PDT 24
Finished Mar 21 02:22:42 PM PDT 24
Peak memory 249124 kb
Host smart-ddcc51b2-a150-41c3-abd3-e55703b79e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537810147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.3537810147
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.3092107014
Short name T743
Test name
Test status
Simulation time 1821255581 ps
CPU time 11 seconds
Started Mar 21 02:21:55 PM PDT 24
Finished Mar 21 02:22:06 PM PDT 24
Peak memory 239996 kb
Host smart-737062e0-225a-45da-bd3d-52a88fbd68da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092107014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.3092107014
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.40128572
Short name T930
Test name
Test status
Simulation time 16544582458 ps
CPU time 11.45 seconds
Started Mar 21 02:21:43 PM PDT 24
Finished Mar 21 02:21:55 PM PDT 24
Peak memory 233584 kb
Host smart-e8924ffe-0b31-4bb0-a836-01e884275c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40128572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.40128572
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.1710342834
Short name T845
Test name
Test status
Simulation time 606366728 ps
CPU time 7.68 seconds
Started Mar 21 02:21:43 PM PDT 24
Finished Mar 21 02:21:51 PM PDT 24
Peak memory 227012 kb
Host smart-ed24c7a5-3327-474f-8956-f306e61ef47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710342834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.1710342834
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.4059032148
Short name T593
Test name
Test status
Simulation time 426647311 ps
CPU time 5.49 seconds
Started Mar 21 02:21:42 PM PDT 24
Finished Mar 21 02:21:48 PM PDT 24
Peak memory 232900 kb
Host smart-7efbaeef-8c22-4715-848f-3957457e1cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059032148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.4059032148
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.1256716043
Short name T633
Test name
Test status
Simulation time 44146590596 ps
CPU time 23.52 seconds
Started Mar 21 02:21:43 PM PDT 24
Finished Mar 21 02:22:07 PM PDT 24
Peak memory 226836 kb
Host smart-319c0044-e4e0-41d6-a46f-f61eba705f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256716043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.1256716043
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.2387027709
Short name T35
Test name
Test status
Simulation time 1207116526 ps
CPU time 4.23 seconds
Started Mar 21 02:21:57 PM PDT 24
Finished Mar 21 02:22:01 PM PDT 24
Peak memory 219912 kb
Host smart-caa45cf1-ec8f-423c-ae7f-46157f16abad
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2387027709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.2387027709
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.802710630
Short name T272
Test name
Test status
Simulation time 61016445511 ps
CPU time 79.19 seconds
Started Mar 21 02:21:42 PM PDT 24
Finished Mar 21 02:23:02 PM PDT 24
Peak memory 216136 kb
Host smart-7e5eb9d8-7116-4740-94b7-3670fb6d3be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802710630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.802710630
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.2236376286
Short name T286
Test name
Test status
Simulation time 14868307023 ps
CPU time 13.02 seconds
Started Mar 21 02:21:43 PM PDT 24
Finished Mar 21 02:21:56 PM PDT 24
Peak memory 216116 kb
Host smart-50a7f381-efaf-47c6-a214-f93c567c2296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236376286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.2236376286
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.3273538752
Short name T713
Test name
Test status
Simulation time 15925077 ps
CPU time 0.81 seconds
Started Mar 21 02:21:44 PM PDT 24
Finished Mar 21 02:21:44 PM PDT 24
Peak memory 205612 kb
Host smart-f8dcbf31-b0cd-4f1e-966e-51a6bc807436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273538752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.3273538752
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.325984491
Short name T415
Test name
Test status
Simulation time 345899380 ps
CPU time 1 seconds
Started Mar 21 02:21:41 PM PDT 24
Finished Mar 21 02:21:42 PM PDT 24
Peak memory 206592 kb
Host smart-d99d1b71-d971-457c-bbf5-aaa6b3d673f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325984491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.325984491
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.3715407900
Short name T837
Test name
Test status
Simulation time 2871207170 ps
CPU time 10.88 seconds
Started Mar 21 02:21:43 PM PDT 24
Finished Mar 21 02:21:54 PM PDT 24
Peak memory 237816 kb
Host smart-985e84a1-131d-4e2d-b45e-bc38a9310dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715407900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.3715407900
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.799230528
Short name T468
Test name
Test status
Simulation time 31104951 ps
CPU time 0.69 seconds
Started Mar 21 02:21:57 PM PDT 24
Finished Mar 21 02:21:57 PM PDT 24
Peak memory 205220 kb
Host smart-b28ae8ae-839f-489a-b606-63750e255c9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799230528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.799230528
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.1879733974
Short name T336
Test name
Test status
Simulation time 619784162 ps
CPU time 3.23 seconds
Started Mar 21 02:21:57 PM PDT 24
Finished Mar 21 02:22:01 PM PDT 24
Peak memory 218212 kb
Host smart-0979860a-1fb0-42cc-bc16-fdfd8bf0c8b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879733974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.1879733974
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.1024499309
Short name T962
Test name
Test status
Simulation time 24610990 ps
CPU time 0.81 seconds
Started Mar 21 02:21:57 PM PDT 24
Finished Mar 21 02:21:58 PM PDT 24
Peak memory 206296 kb
Host smart-840d675b-c583-4364-98f0-869172461432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024499309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.1024499309
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.2554716656
Short name T697
Test name
Test status
Simulation time 15012825000 ps
CPU time 69.67 seconds
Started Mar 21 02:21:57 PM PDT 24
Finished Mar 21 02:23:06 PM PDT 24
Peak memory 234800 kb
Host smart-63aecaf8-38ea-4da4-b5a2-9a6b7b067722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554716656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.2554716656
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.1083434999
Short name T429
Test name
Test status
Simulation time 14750537171 ps
CPU time 60.64 seconds
Started Mar 21 02:21:57 PM PDT 24
Finished Mar 21 02:22:57 PM PDT 24
Peak memory 229384 kb
Host smart-7cdaa430-44b1-4dd9-97a1-ea57c12cc5ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083434999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.1083434999
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.1257781800
Short name T941
Test name
Test status
Simulation time 86492196796 ps
CPU time 158.14 seconds
Started Mar 21 02:21:56 PM PDT 24
Finished Mar 21 02:24:35 PM PDT 24
Peak memory 273296 kb
Host smart-5b49a11d-974a-4b3e-b214-4da5f351918d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257781800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.1257781800
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.857998040
Short name T870
Test name
Test status
Simulation time 45250420582 ps
CPU time 54.16 seconds
Started Mar 21 02:21:56 PM PDT 24
Finished Mar 21 02:22:51 PM PDT 24
Peak memory 247712 kb
Host smart-c73d63f9-f85f-4e13-b8dc-15650a30458c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857998040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.857998040
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.3771634705
Short name T824
Test name
Test status
Simulation time 3488641061 ps
CPU time 8.86 seconds
Started Mar 21 02:21:57 PM PDT 24
Finished Mar 21 02:22:06 PM PDT 24
Peak memory 233208 kb
Host smart-fa6b3f4a-ccc4-4fd9-b4dd-e18538d8abba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771634705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.3771634705
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.2944777513
Short name T196
Test name
Test status
Simulation time 1561384320 ps
CPU time 7.4 seconds
Started Mar 21 02:22:00 PM PDT 24
Finished Mar 21 02:22:08 PM PDT 24
Peak memory 235284 kb
Host smart-ea0231c8-d6b6-461d-9fd9-99b0f72318df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944777513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.2944777513
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.1578952055
Short name T447
Test name
Test status
Simulation time 246067316 ps
CPU time 4.72 seconds
Started Mar 21 02:21:56 PM PDT 24
Finished Mar 21 02:22:01 PM PDT 24
Peak memory 240692 kb
Host smart-7dfaa714-7056-4b01-a784-0f46f426f41b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578952055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.1578952055
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.4079423742
Short name T491
Test name
Test status
Simulation time 198239498 ps
CPU time 3.51 seconds
Started Mar 21 02:21:57 PM PDT 24
Finished Mar 21 02:22:00 PM PDT 24
Peak memory 218272 kb
Host smart-c6558463-0bf9-4e98-b081-0c9b056c072d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079423742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.4079423742
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.3525795187
Short name T341
Test name
Test status
Simulation time 1650932033 ps
CPU time 6.21 seconds
Started Mar 21 02:21:55 PM PDT 24
Finished Mar 21 02:22:02 PM PDT 24
Peak memory 222476 kb
Host smart-a413c3ba-2819-4f39-9396-eb81eaccfb5a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3525795187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.3525795187
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.3378600034
Short name T394
Test name
Test status
Simulation time 285998542046 ps
CPU time 433.93 seconds
Started Mar 21 02:21:55 PM PDT 24
Finished Mar 21 02:29:09 PM PDT 24
Peak memory 263520 kb
Host smart-59cee9f8-9dcb-4daf-a6b4-e96dc9382566
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378600034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.3378600034
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.2174082181
Short name T496
Test name
Test status
Simulation time 798198735 ps
CPU time 13.32 seconds
Started Mar 21 02:21:56 PM PDT 24
Finished Mar 21 02:22:09 PM PDT 24
Peak memory 216112 kb
Host smart-3dcb50e1-6d17-4389-bdc8-a329ac2b7571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174082181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.2174082181
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.1323310618
Short name T942
Test name
Test status
Simulation time 240568358 ps
CPU time 2.08 seconds
Started Mar 21 02:22:00 PM PDT 24
Finished Mar 21 02:22:02 PM PDT 24
Peak memory 216012 kb
Host smart-3a587ec7-b5a6-470a-b46f-97a9486b374f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323310618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.1323310618
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.3763541939
Short name T353
Test name
Test status
Simulation time 97344757 ps
CPU time 2.19 seconds
Started Mar 21 02:21:57 PM PDT 24
Finished Mar 21 02:21:59 PM PDT 24
Peak memory 207924 kb
Host smart-fe67c591-8898-4de0-a148-2a43fb90c544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763541939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.3763541939
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.4085847329
Short name T291
Test name
Test status
Simulation time 77018674 ps
CPU time 1.03 seconds
Started Mar 21 02:21:55 PM PDT 24
Finished Mar 21 02:21:57 PM PDT 24
Peak memory 206648 kb
Host smart-ea6e5ba4-b9b4-4a32-b008-562d0f0fc8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085847329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.4085847329
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.824754438
Short name T546
Test name
Test status
Simulation time 2268430621 ps
CPU time 16.33 seconds
Started Mar 21 02:21:58 PM PDT 24
Finished Mar 21 02:22:15 PM PDT 24
Peak memory 237700 kb
Host smart-bd8aeefd-d29a-40f5-b2d9-51fcedc05487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824754438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.824754438
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.685089993
Short name T52
Test name
Test status
Simulation time 25668001 ps
CPU time 0.75 seconds
Started Mar 21 02:21:56 PM PDT 24
Finished Mar 21 02:21:57 PM PDT 24
Peak memory 205616 kb
Host smart-ece2426c-c410-4c65-ae16-69ef354e9737
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685089993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.685089993
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.183944037
Short name T504
Test name
Test status
Simulation time 1502167648 ps
CPU time 3.58 seconds
Started Mar 21 02:21:55 PM PDT 24
Finished Mar 21 02:21:59 PM PDT 24
Peak memory 233028 kb
Host smart-0538d7b8-a8f6-4ad1-909e-a5cf5e61e670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183944037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.183944037
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.1065694067
Short name T626
Test name
Test status
Simulation time 96770008 ps
CPU time 0.8 seconds
Started Mar 21 02:21:57 PM PDT 24
Finished Mar 21 02:21:58 PM PDT 24
Peak memory 206336 kb
Host smart-1f6ba3a2-dd11-4873-afe6-c29603c26a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065694067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.1065694067
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.4165493295
Short name T247
Test name
Test status
Simulation time 40824393752 ps
CPU time 94.68 seconds
Started Mar 21 02:21:57 PM PDT 24
Finished Mar 21 02:23:32 PM PDT 24
Peak memory 257160 kb
Host smart-53eb7dbe-dac6-4e6b-8c76-2284d85711b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165493295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.4165493295
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.2563201802
Short name T262
Test name
Test status
Simulation time 21643050606 ps
CPU time 162.82 seconds
Started Mar 21 02:21:57 PM PDT 24
Finished Mar 21 02:24:40 PM PDT 24
Peak memory 256136 kb
Host smart-bb40bb35-768a-454c-81c4-4fe6c24c386d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563201802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.2563201802
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.2174183436
Short name T158
Test name
Test status
Simulation time 64690782598 ps
CPU time 141.63 seconds
Started Mar 21 02:21:57 PM PDT 24
Finished Mar 21 02:24:18 PM PDT 24
Peak memory 255132 kb
Host smart-96e03174-5af5-4f03-84e9-5e49e08566fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174183436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.2174183436
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.3327164410
Short name T650
Test name
Test status
Simulation time 8547781753 ps
CPU time 30.14 seconds
Started Mar 21 02:21:55 PM PDT 24
Finished Mar 21 02:22:26 PM PDT 24
Peak memory 237596 kb
Host smart-9c8b6e13-9dfe-4969-b809-5ea5d60f5f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327164410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.3327164410
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.2942527456
Short name T707
Test name
Test status
Simulation time 1810825328 ps
CPU time 6.1 seconds
Started Mar 21 02:21:57 PM PDT 24
Finished Mar 21 02:22:03 PM PDT 24
Peak memory 219864 kb
Host smart-3eb0e259-a4cd-40fa-822b-c1ef9705616e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942527456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.2942527456
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.3812492596
Short name T398
Test name
Test status
Simulation time 292770504 ps
CPU time 3.22 seconds
Started Mar 21 02:21:56 PM PDT 24
Finished Mar 21 02:22:00 PM PDT 24
Peak memory 218232 kb
Host smart-5dd79647-2ac4-491c-8a98-6dd751d19f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812492596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.3812492596
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.187729550
Short name T731
Test name
Test status
Simulation time 2734045613 ps
CPU time 12.71 seconds
Started Mar 21 02:21:58 PM PDT 24
Finished Mar 21 02:22:10 PM PDT 24
Peak memory 238960 kb
Host smart-702b3072-3bf6-4645-b1e4-ab7f4887aced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187729550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap
.187729550
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.3692912344
Short name T192
Test name
Test status
Simulation time 977192486 ps
CPU time 7.6 seconds
Started Mar 21 02:21:56 PM PDT 24
Finished Mar 21 02:22:04 PM PDT 24
Peak memory 224376 kb
Host smart-2889f6af-4d66-4991-b95f-82dedd24bbe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692912344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.3692912344
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.3555925880
Short name T634
Test name
Test status
Simulation time 170393314 ps
CPU time 3.77 seconds
Started Mar 21 02:21:59 PM PDT 24
Finished Mar 21 02:22:03 PM PDT 24
Peak memory 222572 kb
Host smart-dcef2924-7d50-48a3-b1e0-3092da4de289
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3555925880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.3555925880
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.2674523685
Short name T340
Test name
Test status
Simulation time 1300684343 ps
CPU time 5.89 seconds
Started Mar 21 02:21:54 PM PDT 24
Finished Mar 21 02:22:00 PM PDT 24
Peak memory 217620 kb
Host smart-607bc607-1b50-44a0-a062-4f6a6ef69f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674523685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.2674523685
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.1569734567
Short name T84
Test name
Test status
Simulation time 2847529078 ps
CPU time 5.93 seconds
Started Mar 21 02:21:55 PM PDT 24
Finished Mar 21 02:22:01 PM PDT 24
Peak memory 216072 kb
Host smart-4b1ae695-e2b1-4b4b-85b5-83ca1ec0e3f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569734567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.1569734567
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.2870444138
Short name T322
Test name
Test status
Simulation time 35573852 ps
CPU time 1.17 seconds
Started Mar 21 02:21:57 PM PDT 24
Finished Mar 21 02:21:58 PM PDT 24
Peak memory 207216 kb
Host smart-5639f93d-2568-4c83-9e32-e114e53db24a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870444138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.2870444138
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.2750156649
Short name T575
Test name
Test status
Simulation time 92734463 ps
CPU time 0.92 seconds
Started Mar 21 02:21:57 PM PDT 24
Finished Mar 21 02:21:58 PM PDT 24
Peak memory 206640 kb
Host smart-e7b419ad-7252-4d60-b80a-2919648b4c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750156649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.2750156649
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.3648882632
Short name T454
Test name
Test status
Simulation time 1693655679 ps
CPU time 8.74 seconds
Started Mar 21 02:21:57 PM PDT 24
Finished Mar 21 02:22:06 PM PDT 24
Peak memory 249096 kb
Host smart-d52a1de9-f443-4b68-947b-389d9d56458a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648882632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.3648882632
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.2355900889
Short name T723
Test name
Test status
Simulation time 26857638 ps
CPU time 0.69 seconds
Started Mar 21 02:17:00 PM PDT 24
Finished Mar 21 02:17:01 PM PDT 24
Peak memory 205256 kb
Host smart-7b7ed587-0faa-40eb-93b8-f017b1cf9ab6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355900889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.2
355900889
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.626821939
Short name T430
Test name
Test status
Simulation time 221860346 ps
CPU time 3.59 seconds
Started Mar 21 02:16:59 PM PDT 24
Finished Mar 21 02:17:03 PM PDT 24
Peak memory 224376 kb
Host smart-98ca0379-449c-4eb3-89c6-ba04cf21c66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626821939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.626821939
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.2511584917
Short name T893
Test name
Test status
Simulation time 13001550 ps
CPU time 0.77 seconds
Started Mar 21 02:16:48 PM PDT 24
Finished Mar 21 02:16:49 PM PDT 24
Peak memory 205304 kb
Host smart-0c6c9d45-7df6-4815-a332-61d2b9a29caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511584917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.2511584917
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.4058647730
Short name T625
Test name
Test status
Simulation time 24592487759 ps
CPU time 129.82 seconds
Started Mar 21 02:16:57 PM PDT 24
Finished Mar 21 02:19:07 PM PDT 24
Peak memory 240780 kb
Host smart-f97bc117-0a73-4ff5-bf23-c97aa4c2a89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058647730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.4058647730
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.1320041498
Short name T588
Test name
Test status
Simulation time 27248173100 ps
CPU time 207.53 seconds
Started Mar 21 02:16:57 PM PDT 24
Finished Mar 21 02:20:25 PM PDT 24
Peak memory 248412 kb
Host smart-725fe8b1-aa6b-44dd-a1ac-1608c6f69571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320041498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.1320041498
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.3285533895
Short name T41
Test name
Test status
Simulation time 17771199107 ps
CPU time 152.89 seconds
Started Mar 21 02:16:59 PM PDT 24
Finished Mar 21 02:19:32 PM PDT 24
Peak memory 249076 kb
Host smart-f1f7ea3d-91b4-4ac6-9e46-c8e2e7278af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285533895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.3285533895
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.419665689
Short name T442
Test name
Test status
Simulation time 259472015 ps
CPU time 6.95 seconds
Started Mar 21 02:16:58 PM PDT 24
Finished Mar 21 02:17:06 PM PDT 24
Peak memory 223740 kb
Host smart-c5555037-a87d-4137-8c78-6dbe27b5f5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419665689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.419665689
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.3026529739
Short name T681
Test name
Test status
Simulation time 631899249 ps
CPU time 4.59 seconds
Started Mar 21 02:16:49 PM PDT 24
Finished Mar 21 02:16:54 PM PDT 24
Peak memory 233568 kb
Host smart-932ef43d-b963-4d0c-935d-aece0dd7c896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026529739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.3026529739
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.2517264460
Short name T722
Test name
Test status
Simulation time 15545179620 ps
CPU time 46.87 seconds
Started Mar 21 02:16:50 PM PDT 24
Finished Mar 21 02:17:37 PM PDT 24
Peak memory 218280 kb
Host smart-94984f18-ca9b-40ca-9478-5b7d5a6356e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517264460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.2517264460
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.1279016101
Short name T913
Test name
Test status
Simulation time 44514235912 ps
CPU time 19.04 seconds
Started Mar 21 02:16:49 PM PDT 24
Finished Mar 21 02:17:08 PM PDT 24
Peak memory 227424 kb
Host smart-52c067ad-ea0b-4114-ba07-864809b274e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279016101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.1279016101
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.3067838983
Short name T208
Test name
Test status
Simulation time 611791403 ps
CPU time 3.75 seconds
Started Mar 21 02:16:49 PM PDT 24
Finished Mar 21 02:16:53 PM PDT 24
Peak memory 218632 kb
Host smart-e5b1b33c-3a2b-45d5-afa1-634145b823f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067838983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.3067838983
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_ram_cfg.2080809537
Short name T665
Test name
Test status
Simulation time 22514515 ps
CPU time 0.76 seconds
Started Mar 21 02:16:50 PM PDT 24
Finished Mar 21 02:16:51 PM PDT 24
Peak memory 216084 kb
Host smart-e10e40da-6d38-4a01-b0d5-ce747abd8be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080809537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_ram_cfg.2080809537
Directory /workspace/4.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.706964057
Short name T72
Test name
Test status
Simulation time 598916946 ps
CPU time 3.95 seconds
Started Mar 21 02:16:57 PM PDT 24
Finished Mar 21 02:17:02 PM PDT 24
Peak memory 222200 kb
Host smart-f7d6c2d8-8170-49f2-986d-111b1c1fec18
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=706964057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_direc
t.706964057
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.330452309
Short name T65
Test name
Test status
Simulation time 125464262 ps
CPU time 1.12 seconds
Started Mar 21 02:16:56 PM PDT 24
Finished Mar 21 02:16:58 PM PDT 24
Peak memory 234804 kb
Host smart-d0adf992-caaa-4ced-909a-44919e63288d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330452309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.330452309
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.112456322
Short name T135
Test name
Test status
Simulation time 112703646122 ps
CPU time 546.07 seconds
Started Mar 21 02:16:58 PM PDT 24
Finished Mar 21 02:26:04 PM PDT 24
Peak memory 284496 kb
Host smart-7c724421-9025-4967-afde-ef157439f38d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112456322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress
_all.112456322
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.3088334975
Short name T277
Test name
Test status
Simulation time 4520458445 ps
CPU time 38.07 seconds
Started Mar 21 02:16:48 PM PDT 24
Finished Mar 21 02:17:26 PM PDT 24
Peak memory 216208 kb
Host smart-90483ed8-29ed-4b0a-b12b-c82152bfc160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088334975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.3088334975
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.292993883
Short name T334
Test name
Test status
Simulation time 506025601 ps
CPU time 4.2 seconds
Started Mar 21 02:16:50 PM PDT 24
Finished Mar 21 02:16:54 PM PDT 24
Peak memory 216080 kb
Host smart-ae5b65a5-cf9c-4c77-8599-9db6934bcea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292993883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.292993883
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.1998818535
Short name T597
Test name
Test status
Simulation time 326946924 ps
CPU time 2.48 seconds
Started Mar 21 02:16:49 PM PDT 24
Finished Mar 21 02:16:51 PM PDT 24
Peak memory 216124 kb
Host smart-7812c806-1c37-47ba-b8e1-fce7de05e739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998818535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.1998818535
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.999433461
Short name T421
Test name
Test status
Simulation time 359246414 ps
CPU time 0.92 seconds
Started Mar 21 02:16:48 PM PDT 24
Finished Mar 21 02:16:49 PM PDT 24
Peak memory 206580 kb
Host smart-bd15ce7b-5315-4ef1-8c59-c176e4534368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999433461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.999433461
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.3874452432
Short name T847
Test name
Test status
Simulation time 949952095 ps
CPU time 5.71 seconds
Started Mar 21 02:16:58 PM PDT 24
Finished Mar 21 02:17:04 PM PDT 24
Peak memory 224368 kb
Host smart-ca5aefe4-c931-4409-9047-097b95a85e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874452432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.3874452432
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.1596970606
Short name T897
Test name
Test status
Simulation time 14937656 ps
CPU time 0.72 seconds
Started Mar 21 02:22:07 PM PDT 24
Finished Mar 21 02:22:08 PM PDT 24
Peak memory 205232 kb
Host smart-48b3a5ab-a6fa-43f8-95db-a69fa2e2a380
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596970606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
1596970606
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.3873187597
Short name T639
Test name
Test status
Simulation time 1048174042 ps
CPU time 4.67 seconds
Started Mar 21 02:22:11 PM PDT 24
Finished Mar 21 02:22:16 PM PDT 24
Peak memory 235828 kb
Host smart-e17a6653-e134-4f0d-9298-fcc14295e692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873187597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.3873187597
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.686545105
Short name T325
Test name
Test status
Simulation time 122594768 ps
CPU time 0.74 seconds
Started Mar 21 02:21:56 PM PDT 24
Finished Mar 21 02:21:56 PM PDT 24
Peak memory 205268 kb
Host smart-9f1ea8bf-ecc7-42f3-94bd-f56e0ec0405b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686545105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.686545105
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.3307573121
Short name T573
Test name
Test status
Simulation time 2225723912 ps
CPU time 10.57 seconds
Started Mar 21 02:22:08 PM PDT 24
Finished Mar 21 02:22:19 PM PDT 24
Peak memory 234160 kb
Host smart-1953972e-42f9-421b-9ab1-05dc1cb4af6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307573121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.3307573121
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.2753088094
Short name T335
Test name
Test status
Simulation time 231937964197 ps
CPU time 133.8 seconds
Started Mar 21 02:22:05 PM PDT 24
Finished Mar 21 02:24:20 PM PDT 24
Peak memory 265456 kb
Host smart-c402bef9-a01b-4e2f-9e01-45d191c34d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753088094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.2753088094
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.3126402416
Short name T372
Test name
Test status
Simulation time 2575521703 ps
CPU time 15.32 seconds
Started Mar 21 02:22:09 PM PDT 24
Finished Mar 21 02:22:24 PM PDT 24
Peak memory 246104 kb
Host smart-33065af2-8832-44b2-b51b-703cbd4bd1e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126402416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.3126402416
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.3528173140
Short name T672
Test name
Test status
Simulation time 29068734756 ps
CPU time 9.99 seconds
Started Mar 21 02:22:06 PM PDT 24
Finished Mar 21 02:22:18 PM PDT 24
Peak memory 233412 kb
Host smart-3bfc2933-2f74-4319-8ac0-7b3a0105749d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528173140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.3528173140
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.424714787
Short name T598
Test name
Test status
Simulation time 1532011958 ps
CPU time 5.89 seconds
Started Mar 21 02:22:07 PM PDT 24
Finished Mar 21 02:22:13 PM PDT 24
Peak memory 240768 kb
Host smart-cc9709bf-189d-4268-8350-98260939f527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424714787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.424714787
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.3272195786
Short name T550
Test name
Test status
Simulation time 466324991 ps
CPU time 4.35 seconds
Started Mar 21 02:22:05 PM PDT 24
Finished Mar 21 02:22:10 PM PDT 24
Peak memory 232892 kb
Host smart-a87bcbc9-0c51-4b14-b4ec-a7f976a99b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272195786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.3272195786
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.2763035501
Short name T819
Test name
Test status
Simulation time 38211276402 ps
CPU time 22.28 seconds
Started Mar 21 02:21:57 PM PDT 24
Finished Mar 21 02:22:19 PM PDT 24
Peak memory 223320 kb
Host smart-57b34493-7b2f-437a-a6e9-8e22acccfa8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763035501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2763035501
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.2816255673
Short name T645
Test name
Test status
Simulation time 1215643290 ps
CPU time 5.13 seconds
Started Mar 21 02:22:07 PM PDT 24
Finished Mar 21 02:22:13 PM PDT 24
Peak memory 222652 kb
Host smart-ce8584d8-ab2a-418b-afd6-bc4aec94b0fc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2816255673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.2816255673
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.2678726437
Short name T137
Test name
Test status
Simulation time 110958128260 ps
CPU time 772.62 seconds
Started Mar 21 02:22:06 PM PDT 24
Finished Mar 21 02:34:59 PM PDT 24
Peak memory 270668 kb
Host smart-26edad1b-2f3e-4d4e-968f-203f68d4c564
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678726437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.2678726437
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.1824052523
Short name T734
Test name
Test status
Simulation time 4839941669 ps
CPU time 27.85 seconds
Started Mar 21 02:21:56 PM PDT 24
Finished Mar 21 02:22:24 PM PDT 24
Peak memory 216164 kb
Host smart-4e12bb24-daaa-481f-a236-24c79220ad01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824052523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.1824052523
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.3183652399
Short name T590
Test name
Test status
Simulation time 1408113029 ps
CPU time 3.99 seconds
Started Mar 21 02:21:57 PM PDT 24
Finished Mar 21 02:22:01 PM PDT 24
Peak memory 216068 kb
Host smart-66f3b3b3-fc2c-4fe5-9a05-a7c2a6f3abca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183652399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.3183652399
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.1507419660
Short name T671
Test name
Test status
Simulation time 140668075 ps
CPU time 2.65 seconds
Started Mar 21 02:21:59 PM PDT 24
Finished Mar 21 02:22:02 PM PDT 24
Peak memory 216136 kb
Host smart-cbab9c03-5833-412c-be98-433575d06c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507419660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.1507419660
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.3077638555
Short name T12
Test name
Test status
Simulation time 332293900 ps
CPU time 0.87 seconds
Started Mar 21 02:21:56 PM PDT 24
Finished Mar 21 02:21:57 PM PDT 24
Peak memory 205596 kb
Host smart-df74e07f-613c-4a13-b558-adfc3b993de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077638555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.3077638555
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.2882131311
Short name T477
Test name
Test status
Simulation time 689540053 ps
CPU time 5.26 seconds
Started Mar 21 02:22:11 PM PDT 24
Finished Mar 21 02:22:16 PM PDT 24
Peak memory 238652 kb
Host smart-accd973f-7081-47e7-ae54-c345268993ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882131311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.2882131311
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.4213940652
Short name T621
Test name
Test status
Simulation time 13691057 ps
CPU time 0.71 seconds
Started Mar 21 02:22:11 PM PDT 24
Finished Mar 21 02:22:11 PM PDT 24
Peak memory 205268 kb
Host smart-0333fc3d-a2af-43ff-a823-935f31640aae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213940652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
4213940652
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.2886706106
Short name T939
Test name
Test status
Simulation time 930109692 ps
CPU time 3.76 seconds
Started Mar 21 02:22:06 PM PDT 24
Finished Mar 21 02:22:10 PM PDT 24
Peak memory 218512 kb
Host smart-283d9151-605d-41ac-8b1a-b81e9aa3355c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886706106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.2886706106
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.3262292937
Short name T576
Test name
Test status
Simulation time 31591517 ps
CPU time 0.9 seconds
Started Mar 21 02:22:09 PM PDT 24
Finished Mar 21 02:22:10 PM PDT 24
Peak memory 206280 kb
Host smart-88874eeb-04a2-4dc4-8315-69a9d49e3ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262292937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.3262292937
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.639714548
Short name T328
Test name
Test status
Simulation time 2685310364 ps
CPU time 15.72 seconds
Started Mar 21 02:22:07 PM PDT 24
Finished Mar 21 02:22:24 PM PDT 24
Peak memory 224384 kb
Host smart-962d0d28-60ac-469b-ba08-20c34390a659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639714548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.639714548
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.2737223762
Short name T418
Test name
Test status
Simulation time 7841722368 ps
CPU time 93.71 seconds
Started Mar 21 02:22:08 PM PDT 24
Finished Mar 21 02:23:42 PM PDT 24
Peak memory 254796 kb
Host smart-e28af389-6b32-4f4d-acd9-72d793de2206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737223762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.2737223762
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.94941521
Short name T854
Test name
Test status
Simulation time 49652886703 ps
CPU time 74.89 seconds
Started Mar 21 02:22:07 PM PDT 24
Finished Mar 21 02:23:23 PM PDT 24
Peak memory 234760 kb
Host smart-d57aa0bc-9f2f-4360-96dc-3f86bb0e1fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94941521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idle.94941521
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.2870175541
Short name T840
Test name
Test status
Simulation time 4059833059 ps
CPU time 25.55 seconds
Started Mar 21 02:22:08 PM PDT 24
Finished Mar 21 02:22:34 PM PDT 24
Peak memory 233784 kb
Host smart-40f3c137-e22e-41b6-86bd-e8e2055fbf18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870175541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.2870175541
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.475002015
Short name T564
Test name
Test status
Simulation time 2470506649 ps
CPU time 9.03 seconds
Started Mar 21 02:22:05 PM PDT 24
Finished Mar 21 02:22:15 PM PDT 24
Peak memory 217800 kb
Host smart-33036f5f-bc6b-4b96-852a-726f1310d14a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475002015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.475002015
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.1975387784
Short name T701
Test name
Test status
Simulation time 754410059 ps
CPU time 5.95 seconds
Started Mar 21 02:22:07 PM PDT 24
Finished Mar 21 02:22:14 PM PDT 24
Peak memory 232536 kb
Host smart-6e0d3012-0ec3-4e61-9c48-943a07d40629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975387784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.1975387784
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.1112829987
Short name T505
Test name
Test status
Simulation time 1089769881 ps
CPU time 9.12 seconds
Started Mar 21 02:22:09 PM PDT 24
Finished Mar 21 02:22:18 PM PDT 24
Peak memory 237524 kb
Host smart-5e89fe48-32a2-414c-97d2-bd955de375ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112829987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.1112829987
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.3033743122
Short name T685
Test name
Test status
Simulation time 20744001318 ps
CPU time 16.22 seconds
Started Mar 21 02:22:08 PM PDT 24
Finished Mar 21 02:22:25 PM PDT 24
Peak memory 217632 kb
Host smart-eaefa0e2-f94a-4871-9b33-376cb21a617f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033743122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.3033743122
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.598468608
Short name T744
Test name
Test status
Simulation time 5645286338 ps
CPU time 5.92 seconds
Started Mar 21 02:22:09 PM PDT 24
Finished Mar 21 02:22:15 PM PDT 24
Peak memory 220080 kb
Host smart-939b927c-3ca7-4ca1-98b0-5b86f8d87a0a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=598468608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dire
ct.598468608
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.2597191743
Short name T50
Test name
Test status
Simulation time 75767072321 ps
CPU time 400.25 seconds
Started Mar 21 02:22:08 PM PDT 24
Finished Mar 21 02:28:49 PM PDT 24
Peak memory 271788 kb
Host smart-ec96ba10-4674-46bd-a83f-285ea42a92c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597191743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.2597191743
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.985291747
Short name T508
Test name
Test status
Simulation time 3690796456 ps
CPU time 21.16 seconds
Started Mar 21 02:22:05 PM PDT 24
Finished Mar 21 02:22:27 PM PDT 24
Peak memory 220248 kb
Host smart-03cb31a9-ade3-4d3f-ad21-99db2f3f28c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985291747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.985291747
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.1310080249
Short name T775
Test name
Test status
Simulation time 4364065066 ps
CPU time 13.45 seconds
Started Mar 21 02:22:06 PM PDT 24
Finished Mar 21 02:22:20 PM PDT 24
Peak memory 216212 kb
Host smart-a0a61590-328d-475c-a9a5-290be55358d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310080249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.1310080249
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.2684003321
Short name T604
Test name
Test status
Simulation time 1090004419 ps
CPU time 8.19 seconds
Started Mar 21 02:22:07 PM PDT 24
Finished Mar 21 02:22:16 PM PDT 24
Peak memory 216096 kb
Host smart-1d2040ce-6d6c-46bf-98c9-49a0a714d36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684003321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.2684003321
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.3016306793
Short name T603
Test name
Test status
Simulation time 80482214 ps
CPU time 0.92 seconds
Started Mar 21 02:22:08 PM PDT 24
Finished Mar 21 02:22:09 PM PDT 24
Peak memory 205528 kb
Host smart-64f819c0-f563-4405-b3bf-655f11e6ba1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016306793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.3016306793
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.278374638
Short name T172
Test name
Test status
Simulation time 2143023500 ps
CPU time 8.59 seconds
Started Mar 21 02:22:11 PM PDT 24
Finished Mar 21 02:22:20 PM PDT 24
Peak memory 218240 kb
Host smart-213dce20-75eb-4244-9a53-5f802cba5d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278374638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.278374638
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.2419375865
Short name T620
Test name
Test status
Simulation time 13143103 ps
CPU time 0.71 seconds
Started Mar 21 02:22:22 PM PDT 24
Finished Mar 21 02:22:23 PM PDT 24
Peak memory 205596 kb
Host smart-afe250b3-8fd2-4d79-a668-f93223bb49f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419375865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
2419375865
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.42503193
Short name T956
Test name
Test status
Simulation time 224221724 ps
CPU time 3.35 seconds
Started Mar 21 02:22:19 PM PDT 24
Finished Mar 21 02:22:22 PM PDT 24
Peak memory 219568 kb
Host smart-06aab3f2-e75e-443a-b18a-ae4abb265c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42503193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.42503193
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.315211875
Short name T786
Test name
Test status
Simulation time 22632636 ps
CPU time 0.82 seconds
Started Mar 21 02:22:20 PM PDT 24
Finished Mar 21 02:22:21 PM PDT 24
Peak memory 206364 kb
Host smart-46a89e2e-57ae-46b4-a7fd-234f5bbb71a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315211875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.315211875
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.827813121
Short name T493
Test name
Test status
Simulation time 201823364717 ps
CPU time 216.35 seconds
Started Mar 21 02:22:23 PM PDT 24
Finished Mar 21 02:26:00 PM PDT 24
Peak memory 257232 kb
Host smart-3f2274c4-48ac-430e-a00a-6daf3f5dcacc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827813121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.827813121
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.4213263542
Short name T947
Test name
Test status
Simulation time 100211273543 ps
CPU time 181.28 seconds
Started Mar 21 02:22:23 PM PDT 24
Finished Mar 21 02:25:24 PM PDT 24
Peak memory 250112 kb
Host smart-cf1a525a-862b-4813-a8f9-a4cc88fed3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213263542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.4213263542
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.2943905796
Short name T772
Test name
Test status
Simulation time 790605687 ps
CPU time 9.69 seconds
Started Mar 21 02:22:18 PM PDT 24
Finished Mar 21 02:22:28 PM PDT 24
Peak memory 233720 kb
Host smart-75221825-715e-4b09-b6f8-96ff3398a0ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943905796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.2943905796
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.4143432876
Short name T871
Test name
Test status
Simulation time 74949245 ps
CPU time 2.48 seconds
Started Mar 21 02:22:19 PM PDT 24
Finished Mar 21 02:22:21 PM PDT 24
Peak memory 232488 kb
Host smart-b1715140-8776-4e9a-8e5d-e5a41d54fac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143432876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.4143432876
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.1045715461
Short name T638
Test name
Test status
Simulation time 785916597 ps
CPU time 7.81 seconds
Started Mar 21 02:22:20 PM PDT 24
Finished Mar 21 02:22:28 PM PDT 24
Peak memory 237840 kb
Host smart-68729089-e2b1-4849-af39-d3075c5cfe86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045715461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.1045715461
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.3430257190
Short name T584
Test name
Test status
Simulation time 571634871 ps
CPU time 4.05 seconds
Started Mar 21 02:22:21 PM PDT 24
Finished Mar 21 02:22:25 PM PDT 24
Peak memory 233396 kb
Host smart-0f55a99f-e700-499f-8b3e-6c35a9fc7429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430257190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.3430257190
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.1901091951
Short name T375
Test name
Test status
Simulation time 719276319 ps
CPU time 5.61 seconds
Started Mar 21 02:22:19 PM PDT 24
Finished Mar 21 02:22:25 PM PDT 24
Peak memory 233632 kb
Host smart-ff777214-6876-42a3-97b5-9b9e8d3f675d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901091951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1901091951
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.1585502727
Short name T422
Test name
Test status
Simulation time 1336794445 ps
CPU time 5.48 seconds
Started Mar 21 02:22:22 PM PDT 24
Finished Mar 21 02:22:27 PM PDT 24
Peak memory 218652 kb
Host smart-ed77854a-55f8-480d-ba65-66d1f0eb71cd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1585502727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.1585502727
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.924212344
Short name T45
Test name
Test status
Simulation time 306129651423 ps
CPU time 834.4 seconds
Started Mar 21 02:22:24 PM PDT 24
Finished Mar 21 02:36:18 PM PDT 24
Peak memory 289780 kb
Host smart-1f885031-fbdd-41f6-9bdc-ce8c97123455
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924212344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stres
s_all.924212344
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.88492040
Short name T344
Test name
Test status
Simulation time 2215319450 ps
CPU time 28.98 seconds
Started Mar 21 02:22:22 PM PDT 24
Finished Mar 21 02:22:51 PM PDT 24
Peak memory 219864 kb
Host smart-8974a069-e57f-42fa-815f-33e308af8ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88492040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.88492040
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.2669343302
Short name T517
Test name
Test status
Simulation time 1895032547 ps
CPU time 7.81 seconds
Started Mar 21 02:22:20 PM PDT 24
Finished Mar 21 02:22:28 PM PDT 24
Peak memory 216048 kb
Host smart-218d35ac-af66-4741-88c9-930e6c126f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669343302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.2669343302
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.61147685
Short name T305
Test name
Test status
Simulation time 197753921 ps
CPU time 1.19 seconds
Started Mar 21 02:22:20 PM PDT 24
Finished Mar 21 02:22:21 PM PDT 24
Peak memory 216096 kb
Host smart-59bf1200-9426-464e-a042-c63676420ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61147685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.61147685
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.1397807890
Short name T641
Test name
Test status
Simulation time 76002671 ps
CPU time 0.98 seconds
Started Mar 21 02:22:20 PM PDT 24
Finished Mar 21 02:22:21 PM PDT 24
Peak memory 206616 kb
Host smart-6b89be8f-df6f-41e4-a51d-d356d9efed65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397807890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.1397807890
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.1011313633
Short name T382
Test name
Test status
Simulation time 10865116610 ps
CPU time 13.01 seconds
Started Mar 21 02:22:20 PM PDT 24
Finished Mar 21 02:22:33 PM PDT 24
Peak memory 233304 kb
Host smart-ac5ad3a3-173a-4e38-82a2-fca370cd9219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011313633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.1011313633
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.3903757834
Short name T510
Test name
Test status
Simulation time 30930745 ps
CPU time 0.72 seconds
Started Mar 21 02:22:24 PM PDT 24
Finished Mar 21 02:22:25 PM PDT 24
Peak memory 204712 kb
Host smart-8f398366-d64e-4630-8b86-cf9abbfe119c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903757834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
3903757834
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.259352353
Short name T216
Test name
Test status
Simulation time 905036409 ps
CPU time 3.98 seconds
Started Mar 21 02:22:24 PM PDT 24
Finished Mar 21 02:22:28 PM PDT 24
Peak memory 235156 kb
Host smart-63228176-f4df-402f-8bef-c40e30101291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259352353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.259352353
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.1058627444
Short name T828
Test name
Test status
Simulation time 59959851 ps
CPU time 0.78 seconds
Started Mar 21 02:22:22 PM PDT 24
Finished Mar 21 02:22:23 PM PDT 24
Peak memory 205260 kb
Host smart-9e13d5a9-20f7-4b15-9bb6-7a44dfebfe43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058627444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.1058627444
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.1198792253
Short name T37
Test name
Test status
Simulation time 55170868988 ps
CPU time 137.48 seconds
Started Mar 21 02:22:21 PM PDT 24
Finished Mar 21 02:24:39 PM PDT 24
Peak memory 270644 kb
Host smart-2433fc49-88bd-4cde-a9f4-8d65b795a0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198792253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.1198792253
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.4237308737
Short name T796
Test name
Test status
Simulation time 16451374295 ps
CPU time 140.88 seconds
Started Mar 21 02:22:21 PM PDT 24
Finished Mar 21 02:24:42 PM PDT 24
Peak memory 249316 kb
Host smart-f58059cc-2a4f-4118-a144-04cc3f473add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237308737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.4237308737
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.3239136933
Short name T144
Test name
Test status
Simulation time 2962330886 ps
CPU time 62.39 seconds
Started Mar 21 02:22:21 PM PDT 24
Finished Mar 21 02:23:24 PM PDT 24
Peak memory 250420 kb
Host smart-dad48031-c9f0-4ec9-bf48-d622c4c6fc14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239136933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.3239136933
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.1373792557
Short name T521
Test name
Test status
Simulation time 1700237712 ps
CPU time 14.71 seconds
Started Mar 21 02:22:21 PM PDT 24
Finished Mar 21 02:22:36 PM PDT 24
Peak memory 248680 kb
Host smart-24741258-0965-4421-b4f1-79df14e918f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373792557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.1373792557
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.799790108
Short name T937
Test name
Test status
Simulation time 3915450431 ps
CPU time 14.75 seconds
Started Mar 21 02:22:23 PM PDT 24
Finished Mar 21 02:22:38 PM PDT 24
Peak memory 233648 kb
Host smart-9e3b52cc-103f-4b48-8155-b5777dd62552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799790108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.799790108
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.4283630247
Short name T155
Test name
Test status
Simulation time 90438296958 ps
CPU time 63.52 seconds
Started Mar 21 02:22:24 PM PDT 24
Finished Mar 21 02:23:27 PM PDT 24
Peak memory 240140 kb
Host smart-59db22fd-1992-451d-8220-2a2c62e70bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283630247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.4283630247
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.271533657
Short name T787
Test name
Test status
Simulation time 2106974711 ps
CPU time 5.73 seconds
Started Mar 21 02:22:22 PM PDT 24
Finished Mar 21 02:22:28 PM PDT 24
Peak memory 224308 kb
Host smart-c0e063b5-af68-4e06-99fd-5de1d8f6c1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271533657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap
.271533657
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.3633306161
Short name T664
Test name
Test status
Simulation time 824313464 ps
CPU time 6.52 seconds
Started Mar 21 02:22:23 PM PDT 24
Finished Mar 21 02:22:29 PM PDT 24
Peak memory 232872 kb
Host smart-5caef32a-dc54-4528-9211-cdc5d10f8551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633306161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.3633306161
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.334263215
Short name T306
Test name
Test status
Simulation time 3016690827 ps
CPU time 8.22 seconds
Started Mar 21 02:22:24 PM PDT 24
Finished Mar 21 02:22:33 PM PDT 24
Peak memory 219684 kb
Host smart-86befb01-8de3-4ca0-b3fc-e5709f1131ec
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=334263215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dire
ct.334263215
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.1636749012
Short name T666
Test name
Test status
Simulation time 12161584320 ps
CPU time 26.56 seconds
Started Mar 21 02:22:19 PM PDT 24
Finished Mar 21 02:22:46 PM PDT 24
Peak memory 216204 kb
Host smart-156aacae-7895-46fe-ae96-23b260e1dcbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636749012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.1636749012
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.305776613
Short name T938
Test name
Test status
Simulation time 199432937 ps
CPU time 1.33 seconds
Started Mar 21 02:22:22 PM PDT 24
Finished Mar 21 02:22:24 PM PDT 24
Peak memory 206676 kb
Host smart-610fc349-481f-45d1-b470-ac8bf88fac76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305776613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.305776613
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.3112892340
Short name T358
Test name
Test status
Simulation time 20498484 ps
CPU time 0.82 seconds
Started Mar 21 02:22:25 PM PDT 24
Finished Mar 21 02:22:25 PM PDT 24
Peak memory 206612 kb
Host smart-6dce847f-0fdc-4dca-ac41-5ca47e4a27c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112892340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.3112892340
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.3594646181
Short name T289
Test name
Test status
Simulation time 75142931 ps
CPU time 0.9 seconds
Started Mar 21 02:22:21 PM PDT 24
Finished Mar 21 02:22:22 PM PDT 24
Peak memory 205596 kb
Host smart-68918cec-8f28-468a-81fd-005d34c667d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594646181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.3594646181
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.593390066
Short name T200
Test name
Test status
Simulation time 653865298 ps
CPU time 6.83 seconds
Started Mar 21 02:22:22 PM PDT 24
Finished Mar 21 02:22:29 PM PDT 24
Peak memory 233140 kb
Host smart-ade3c29b-63a5-4c75-9b49-0aa6873b93d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593390066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.593390066
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.2811677054
Short name T385
Test name
Test status
Simulation time 12896500 ps
CPU time 0.76 seconds
Started Mar 21 02:22:38 PM PDT 24
Finished Mar 21 02:22:38 PM PDT 24
Peak memory 205340 kb
Host smart-a0e443d0-8d59-42e3-9610-dd3c28f76bb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811677054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
2811677054
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.2481123304
Short name T406
Test name
Test status
Simulation time 256373744 ps
CPU time 2.89 seconds
Started Mar 21 02:22:32 PM PDT 24
Finished Mar 21 02:22:35 PM PDT 24
Peak memory 233616 kb
Host smart-8902f6af-e786-4f76-a368-c6bc24351c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481123304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.2481123304
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.3051797770
Short name T448
Test name
Test status
Simulation time 21079865 ps
CPU time 0.85 seconds
Started Mar 21 02:22:28 PM PDT 24
Finished Mar 21 02:22:28 PM PDT 24
Peak memory 206360 kb
Host smart-dda32c64-db29-4425-8c03-5e4832b89742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051797770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.3051797770
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.2453427128
Short name T242
Test name
Test status
Simulation time 156226479668 ps
CPU time 199.13 seconds
Started Mar 21 02:22:32 PM PDT 24
Finished Mar 21 02:25:51 PM PDT 24
Peak memory 249000 kb
Host smart-c7b5473e-8c46-4300-add9-3205ee26b481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453427128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.2453427128
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.2697961286
Short name T225
Test name
Test status
Simulation time 63310843903 ps
CPU time 276.46 seconds
Started Mar 21 02:22:37 PM PDT 24
Finished Mar 21 02:27:13 PM PDT 24
Peak memory 255000 kb
Host smart-332b59fb-2de8-4bf9-9ed5-b3349da43406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697961286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.2697961286
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.2668424980
Short name T529
Test name
Test status
Simulation time 23354525658 ps
CPU time 164.4 seconds
Started Mar 21 02:22:31 PM PDT 24
Finished Mar 21 02:25:16 PM PDT 24
Peak memory 249968 kb
Host smart-56a9b9ea-92e4-4a88-969e-4d6ae6e3909f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668424980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.2668424980
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.2648733453
Short name T762
Test name
Test status
Simulation time 7348751408 ps
CPU time 22.47 seconds
Started Mar 21 02:22:31 PM PDT 24
Finished Mar 21 02:22:54 PM PDT 24
Peak memory 239608 kb
Host smart-d9251cb4-7647-4c13-a035-b8401a980dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648733453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.2648733453
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.2446366801
Short name T948
Test name
Test status
Simulation time 2504060954 ps
CPU time 4.34 seconds
Started Mar 21 02:22:28 PM PDT 24
Finished Mar 21 02:22:33 PM PDT 24
Peak memory 233568 kb
Host smart-78408f9e-db9b-46a8-89d1-877a151ec450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446366801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.2446366801
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.232342108
Short name T227
Test name
Test status
Simulation time 13876852653 ps
CPU time 47 seconds
Started Mar 21 02:22:29 PM PDT 24
Finished Mar 21 02:23:16 PM PDT 24
Peak memory 256832 kb
Host smart-7d5ccf95-bdb4-4388-bd3f-db63ec1520eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232342108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.232342108
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.2038525861
Short name T712
Test name
Test status
Simulation time 116611472 ps
CPU time 2.7 seconds
Started Mar 21 02:22:31 PM PDT 24
Finished Mar 21 02:22:33 PM PDT 24
Peak memory 233536 kb
Host smart-5fee3d07-f224-4832-8649-c124018228a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038525861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.2038525861
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.2311061052
Short name T313
Test name
Test status
Simulation time 5518927579 ps
CPU time 9.95 seconds
Started Mar 21 02:22:30 PM PDT 24
Finished Mar 21 02:22:40 PM PDT 24
Peak memory 232608 kb
Host smart-4fea0ad8-4fc0-43bd-9c03-b3362633327b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311061052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.2311061052
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.2372206702
Short name T466
Test name
Test status
Simulation time 334558631 ps
CPU time 4.46 seconds
Started Mar 21 02:22:32 PM PDT 24
Finished Mar 21 02:22:36 PM PDT 24
Peak memory 222668 kb
Host smart-00b32173-1ee6-4166-9a3a-01b7002c6659
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2372206702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.2372206702
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.3801244525
Short name T873
Test name
Test status
Simulation time 17528501008 ps
CPU time 16.9 seconds
Started Mar 21 02:22:31 PM PDT 24
Finished Mar 21 02:22:48 PM PDT 24
Peak memory 216092 kb
Host smart-70a140e1-102d-425d-86b4-37761a4c7083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801244525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.3801244525
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.2954984886
Short name T648
Test name
Test status
Simulation time 13762272747 ps
CPU time 6.02 seconds
Started Mar 21 02:22:29 PM PDT 24
Finished Mar 21 02:22:36 PM PDT 24
Peak memory 216128 kb
Host smart-66dd9a82-91ee-4726-9e9a-9466391d272d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954984886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.2954984886
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.876700347
Short name T13
Test name
Test status
Simulation time 139516145 ps
CPU time 1.67 seconds
Started Mar 21 02:22:31 PM PDT 24
Finished Mar 21 02:22:33 PM PDT 24
Peak memory 216028 kb
Host smart-b61b60d9-7392-485a-b2a2-8f5c52c20606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876700347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.876700347
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.2562062842
Short name T579
Test name
Test status
Simulation time 422071633 ps
CPU time 1.04 seconds
Started Mar 21 02:22:31 PM PDT 24
Finished Mar 21 02:22:32 PM PDT 24
Peak memory 205624 kb
Host smart-836e8ad5-c077-48f7-9689-168e448328bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562062842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.2562062842
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.2821889881
Short name T916
Test name
Test status
Simulation time 861282876 ps
CPU time 6.89 seconds
Started Mar 21 02:22:30 PM PDT 24
Finished Mar 21 02:22:37 PM PDT 24
Peak memory 221412 kb
Host smart-0964d1d9-472d-40a6-9817-cc31afee0d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821889881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.2821889881
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.4284560146
Short name T806
Test name
Test status
Simulation time 13798258 ps
CPU time 0.73 seconds
Started Mar 21 02:22:37 PM PDT 24
Finished Mar 21 02:22:37 PM PDT 24
Peak memory 205240 kb
Host smart-7655e63c-ec88-40e9-b7bd-2244f3ac2f06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284560146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
4284560146
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.3427079671
Short name T822
Test name
Test status
Simulation time 64209630 ps
CPU time 2.17 seconds
Started Mar 21 02:22:30 PM PDT 24
Finished Mar 21 02:22:33 PM PDT 24
Peak memory 218500 kb
Host smart-c23d6699-dc77-4edb-89d7-dcb14e4bbfd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427079671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3427079671
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.2015687212
Short name T440
Test name
Test status
Simulation time 14565798 ps
CPU time 0.75 seconds
Started Mar 21 02:22:31 PM PDT 24
Finished Mar 21 02:22:32 PM PDT 24
Peak memory 205312 kb
Host smart-923aac13-4526-43ec-b30e-af5f9578a277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015687212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.2015687212
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.3513623021
Short name T281
Test name
Test status
Simulation time 16319761678 ps
CPU time 74.98 seconds
Started Mar 21 02:22:38 PM PDT 24
Finished Mar 21 02:23:53 PM PDT 24
Peak memory 224472 kb
Host smart-69ddc992-e333-4fa8-abef-48c41170fb59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513623021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.3513623021
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.582282
Short name T165
Test name
Test status
Simulation time 305813844310 ps
CPU time 534.65 seconds
Started Mar 21 02:22:36 PM PDT 24
Finished Mar 21 02:31:31 PM PDT 24
Peak memory 272744 kb
Host smart-4a80649e-67f5-47b5-8b19-efc5fe052fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.582282
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.969193136
Short name T492
Test name
Test status
Simulation time 16596902601 ps
CPU time 31.5 seconds
Started Mar 21 02:22:36 PM PDT 24
Finished Mar 21 02:23:08 PM PDT 24
Peak memory 237072 kb
Host smart-c1c294fd-d586-4de8-9634-db17826b5088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969193136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idle
.969193136
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_intercept.3052678951
Short name T366
Test name
Test status
Simulation time 5113615336 ps
CPU time 6.45 seconds
Started Mar 21 02:22:32 PM PDT 24
Finished Mar 21 02:22:38 PM PDT 24
Peak memory 233140 kb
Host smart-33fb36ac-57a0-4d08-93df-3ebdb30ae2a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052678951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.3052678951
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.894086506
Short name T784
Test name
Test status
Simulation time 184873422 ps
CPU time 3.51 seconds
Started Mar 21 02:22:30 PM PDT 24
Finished Mar 21 02:22:34 PM PDT 24
Peak memory 224296 kb
Host smart-ac5d7d0a-58b7-4848-a6b9-2ebf6739a1d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894086506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.894086506
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.2431094237
Short name T655
Test name
Test status
Simulation time 20131696514 ps
CPU time 14.42 seconds
Started Mar 21 02:22:32 PM PDT 24
Finished Mar 21 02:22:47 PM PDT 24
Peak memory 235360 kb
Host smart-85079c8c-07dc-471b-9ca8-87d872c11540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431094237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.2431094237
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.58287817
Short name T777
Test name
Test status
Simulation time 4290061828 ps
CPU time 16.19 seconds
Started Mar 21 02:22:33 PM PDT 24
Finished Mar 21 02:22:49 PM PDT 24
Peak memory 217976 kb
Host smart-be9f9809-1af5-4819-b29d-6d96d3df5da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58287817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.58287817
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.2989757572
Short name T718
Test name
Test status
Simulation time 1890415110 ps
CPU time 4.3 seconds
Started Mar 21 02:22:36 PM PDT 24
Finished Mar 21 02:22:41 PM PDT 24
Peak memory 218668 kb
Host smart-913f1b02-498d-42ff-8997-dafde00e94cd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2989757572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.2989757572
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.769948897
Short name T141
Test name
Test status
Simulation time 41656832 ps
CPU time 0.96 seconds
Started Mar 21 02:22:39 PM PDT 24
Finished Mar 21 02:22:40 PM PDT 24
Peak memory 206748 kb
Host smart-bcf3c153-6c18-442e-897e-a1ba49960360
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769948897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stres
s_all.769948897
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.2248546433
Short name T698
Test name
Test status
Simulation time 2413140979 ps
CPU time 12.76 seconds
Started Mar 21 02:22:38 PM PDT 24
Finished Mar 21 02:22:50 PM PDT 24
Peak memory 216196 kb
Host smart-38ddb63a-eb56-46c6-b441-21f35524dfc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248546433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.2248546433
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.1904528548
Short name T38
Test name
Test status
Simulation time 27866975464 ps
CPU time 12.34 seconds
Started Mar 21 02:22:33 PM PDT 24
Finished Mar 21 02:22:45 PM PDT 24
Peak memory 216228 kb
Host smart-9f6f0b4c-0c10-4ca9-8ef4-9524aec9dd66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904528548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.1904528548
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.3296527415
Short name T608
Test name
Test status
Simulation time 1324594220 ps
CPU time 2.23 seconds
Started Mar 21 02:22:31 PM PDT 24
Finished Mar 21 02:22:34 PM PDT 24
Peak memory 216108 kb
Host smart-f5f17c12-ba3a-439f-86b2-ae653a4811b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296527415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.3296527415
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.3717857125
Short name T820
Test name
Test status
Simulation time 66174236 ps
CPU time 0.83 seconds
Started Mar 21 02:22:31 PM PDT 24
Finished Mar 21 02:22:32 PM PDT 24
Peak memory 205876 kb
Host smart-17140fc5-1126-445e-a488-935e53323b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717857125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.3717857125
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.1493930856
Short name T231
Test name
Test status
Simulation time 102965731 ps
CPU time 2.38 seconds
Started Mar 21 02:22:31 PM PDT 24
Finished Mar 21 02:22:34 PM PDT 24
Peak memory 217696 kb
Host smart-d0ac59f7-0637-4ffa-930e-14e57c7f1c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493930856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.1493930856
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.472784234
Short name T940
Test name
Test status
Simulation time 14573681 ps
CPU time 0.73 seconds
Started Mar 21 02:22:39 PM PDT 24
Finished Mar 21 02:22:40 PM PDT 24
Peak memory 204688 kb
Host smart-7a0d427a-8e74-4a91-8a79-d41736576f17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472784234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.472784234
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.4066840614
Short name T502
Test name
Test status
Simulation time 3464916619 ps
CPU time 4.7 seconds
Started Mar 21 02:22:37 PM PDT 24
Finished Mar 21 02:22:42 PM PDT 24
Peak memory 218460 kb
Host smart-9a9fa1c5-02c5-45c1-afcc-e68183db63aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066840614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.4066840614
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.183207527
Short name T319
Test name
Test status
Simulation time 36292141 ps
CPU time 0.8 seconds
Started Mar 21 02:22:38 PM PDT 24
Finished Mar 21 02:22:39 PM PDT 24
Peak memory 206696 kb
Host smart-1033c220-c6d9-4584-bbd4-0beea7fe15a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183207527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.183207527
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.2887659728
Short name T27
Test name
Test status
Simulation time 25876271589 ps
CPU time 125.24 seconds
Started Mar 21 02:22:39 PM PDT 24
Finished Mar 21 02:24:45 PM PDT 24
Peak memory 260040 kb
Host smart-e853399f-f881-4d56-9252-9966607a89af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887659728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.2887659728
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.346837836
Short name T879
Test name
Test status
Simulation time 34608644495 ps
CPU time 263.59 seconds
Started Mar 21 02:22:37 PM PDT 24
Finished Mar 21 02:27:01 PM PDT 24
Peak memory 252864 kb
Host smart-c02ab7ff-dcb2-4c8a-a03b-9f038956667e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346837836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle
.346837836
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.804954616
Short name T637
Test name
Test status
Simulation time 1323219528 ps
CPU time 15.62 seconds
Started Mar 21 02:22:38 PM PDT 24
Finished Mar 21 02:22:53 PM PDT 24
Peak memory 238052 kb
Host smart-81bb4f38-b07b-4f40-8f1b-65df44a9238e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804954616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.804954616
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.2522732418
Short name T618
Test name
Test status
Simulation time 188405319 ps
CPU time 2.94 seconds
Started Mar 21 02:22:37 PM PDT 24
Finished Mar 21 02:22:40 PM PDT 24
Peak memory 234240 kb
Host smart-1d7e29f1-2db6-4d79-beb5-975e80057da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522732418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.2522732418
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.2842694074
Short name T388
Test name
Test status
Simulation time 69317375652 ps
CPU time 47.22 seconds
Started Mar 21 02:22:37 PM PDT 24
Finished Mar 21 02:23:25 PM PDT 24
Peak memory 240008 kb
Host smart-466bc8f8-7fc0-4203-b9e2-67270accd9ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842694074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.2842694074
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.2553650707
Short name T224
Test name
Test status
Simulation time 791036883 ps
CPU time 4.47 seconds
Started Mar 21 02:22:38 PM PDT 24
Finished Mar 21 02:22:42 PM PDT 24
Peak memory 233532 kb
Host smart-d7d19808-36fb-4579-9945-9dd883d2da3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553650707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.2553650707
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.505604249
Short name T230
Test name
Test status
Simulation time 697719467 ps
CPU time 3.11 seconds
Started Mar 21 02:22:38 PM PDT 24
Finished Mar 21 02:22:41 PM PDT 24
Peak memory 232940 kb
Host smart-4d763128-bfb3-4c33-a59d-b82a917d2e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505604249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.505604249
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.3492884998
Short name T518
Test name
Test status
Simulation time 1460727392 ps
CPU time 6.67 seconds
Started Mar 21 02:22:38 PM PDT 24
Finished Mar 21 02:22:45 PM PDT 24
Peak memory 222072 kb
Host smart-0c6a9ec5-00b8-4ef1-b0dc-a5ecc1bf94b6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3492884998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.3492884998
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.1197047715
Short name T600
Test name
Test status
Simulation time 179412242 ps
CPU time 0.97 seconds
Started Mar 21 02:22:38 PM PDT 24
Finished Mar 21 02:22:39 PM PDT 24
Peak memory 206436 kb
Host smart-c1fa628e-2fb0-4737-a610-e2ecf03f7cc9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197047715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.1197047715
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.3372592393
Short name T85
Test name
Test status
Simulation time 14591983053 ps
CPU time 41.59 seconds
Started Mar 21 02:22:37 PM PDT 24
Finished Mar 21 02:23:19 PM PDT 24
Peak memory 216164 kb
Host smart-68c6798c-1ba3-46fa-97a6-5138332e25cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372592393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.3372592393
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2415474246
Short name T815
Test name
Test status
Simulation time 14935637644 ps
CPU time 24.18 seconds
Started Mar 21 02:22:39 PM PDT 24
Finished Mar 21 02:23:03 PM PDT 24
Peak memory 216192 kb
Host smart-1466dc7d-9270-4311-90aa-e5f5a2acbf79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415474246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2415474246
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.3311363454
Short name T801
Test name
Test status
Simulation time 43948982 ps
CPU time 1.01 seconds
Started Mar 21 02:22:38 PM PDT 24
Finished Mar 21 02:22:39 PM PDT 24
Peak memory 207764 kb
Host smart-729bebed-ce11-4c5b-b838-f490693c095b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311363454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.3311363454
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.2843512083
Short name T545
Test name
Test status
Simulation time 97914503 ps
CPU time 1.05 seconds
Started Mar 21 02:22:38 PM PDT 24
Finished Mar 21 02:22:39 PM PDT 24
Peak memory 205628 kb
Host smart-4fbc7280-85e6-4581-a335-39de19949936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843512083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.2843512083
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.1730749468
Short name T191
Test name
Test status
Simulation time 1123813015 ps
CPU time 9.15 seconds
Started Mar 21 02:22:37 PM PDT 24
Finished Mar 21 02:22:46 PM PDT 24
Peak memory 237708 kb
Host smart-8a35038d-d581-40c4-a4ec-ad46fb9076d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730749468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.1730749468
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.1514979212
Short name T781
Test name
Test status
Simulation time 22955208 ps
CPU time 0.71 seconds
Started Mar 21 02:22:46 PM PDT 24
Finished Mar 21 02:22:47 PM PDT 24
Peak memory 205244 kb
Host smart-490ab7f9-8a5f-4c88-85f5-1edfda346649
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514979212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
1514979212
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.2838580608
Short name T317
Test name
Test status
Simulation time 724299262 ps
CPU time 2.78 seconds
Started Mar 21 02:22:49 PM PDT 24
Finished Mar 21 02:22:52 PM PDT 24
Peak memory 233020 kb
Host smart-37abbdfe-8151-4e84-97a1-defb1c534dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838580608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.2838580608
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.896899027
Short name T300
Test name
Test status
Simulation time 16077338 ps
CPU time 0.77 seconds
Started Mar 21 02:22:38 PM PDT 24
Finished Mar 21 02:22:39 PM PDT 24
Peak memory 205660 kb
Host smart-6621e117-dd66-4bb3-9b27-d9d1747ac5c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896899027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.896899027
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.3705351013
Short name T535
Test name
Test status
Simulation time 4759221278 ps
CPU time 34.9 seconds
Started Mar 21 02:22:49 PM PDT 24
Finished Mar 21 02:23:24 PM PDT 24
Peak memory 254792 kb
Host smart-b830fa78-c94c-4ed7-adc8-a7378f941e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705351013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.3705351013
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.2382406679
Short name T258
Test name
Test status
Simulation time 61325339132 ps
CPU time 105.68 seconds
Started Mar 21 02:22:50 PM PDT 24
Finished Mar 21 02:24:37 PM PDT 24
Peak memory 235152 kb
Host smart-3d5f192f-ac72-44a2-a75b-07d953dbb429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382406679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.2382406679
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.3841360669
Short name T151
Test name
Test status
Simulation time 42734331082 ps
CPU time 118.57 seconds
Started Mar 21 02:22:53 PM PDT 24
Finished Mar 21 02:24:52 PM PDT 24
Peak memory 261944 kb
Host smart-51233240-8102-4896-8329-040ad95ea1a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841360669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.3841360669
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.208150261
Short name T419
Test name
Test status
Simulation time 13900577840 ps
CPU time 26.39 seconds
Started Mar 21 02:22:48 PM PDT 24
Finished Mar 21 02:23:15 PM PDT 24
Peak memory 240812 kb
Host smart-1ab287eb-cd9f-4100-b2d0-0ac0e9df4f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208150261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.208150261
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.1883242003
Short name T609
Test name
Test status
Simulation time 804638397 ps
CPU time 5.71 seconds
Started Mar 21 02:22:48 PM PDT 24
Finished Mar 21 02:22:53 PM PDT 24
Peak memory 217540 kb
Host smart-cd03a184-9333-4094-ad3e-a8bf902d7a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883242003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.1883242003
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.2306478240
Short name T551
Test name
Test status
Simulation time 14731400781 ps
CPU time 12.02 seconds
Started Mar 21 02:22:50 PM PDT 24
Finished Mar 21 02:23:02 PM PDT 24
Peak memory 226556 kb
Host smart-21f9a4aa-ea24-4389-8a76-c76d94c0ec71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306478240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.2306478240
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.96859021
Short name T29
Test name
Test status
Simulation time 9948000009 ps
CPU time 17.29 seconds
Started Mar 21 02:22:46 PM PDT 24
Finished Mar 21 02:23:03 PM PDT 24
Peak memory 233704 kb
Host smart-867893fc-49f2-4311-b888-6e313727e7ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96859021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap.96859021
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.1386200320
Short name T7
Test name
Test status
Simulation time 245428204 ps
CPU time 2.73 seconds
Started Mar 21 02:22:47 PM PDT 24
Finished Mar 21 02:22:50 PM PDT 24
Peak memory 233360 kb
Host smart-a0bdc121-836f-4685-b4dc-affeec541eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386200320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.1386200320
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.1340109376
Short name T359
Test name
Test status
Simulation time 222895532 ps
CPU time 3.98 seconds
Started Mar 21 02:22:49 PM PDT 24
Finished Mar 21 02:22:53 PM PDT 24
Peak memory 221964 kb
Host smart-1f17d985-8207-4670-9af7-2ac228f0972f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1340109376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.1340109376
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.154700752
Short name T859
Test name
Test status
Simulation time 40242439483 ps
CPU time 418.3 seconds
Started Mar 21 02:22:48 PM PDT 24
Finished Mar 21 02:29:46 PM PDT 24
Peak memory 287140 kb
Host smart-8c5b3fff-f2eb-4e82-bf64-c86466e6c62f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154700752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stres
s_all.154700752
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.4116145689
Short name T571
Test name
Test status
Simulation time 10320775123 ps
CPU time 52.4 seconds
Started Mar 21 02:22:39 PM PDT 24
Finished Mar 21 02:23:32 PM PDT 24
Peak memory 216144 kb
Host smart-f2146794-1367-4749-99ed-dfc1af41d4b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116145689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.4116145689
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.1758482685
Short name T799
Test name
Test status
Simulation time 2578858485 ps
CPU time 11.32 seconds
Started Mar 21 02:22:41 PM PDT 24
Finished Mar 21 02:22:53 PM PDT 24
Peak memory 216104 kb
Host smart-b6a34149-ec29-4591-b996-739287b7cc80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758482685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.1758482685
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.3549993011
Short name T596
Test name
Test status
Simulation time 264516642 ps
CPU time 5.95 seconds
Started Mar 21 02:22:54 PM PDT 24
Finished Mar 21 02:23:00 PM PDT 24
Peak memory 216196 kb
Host smart-658db54d-4b04-4f91-937c-35f939e45791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549993011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.3549993011
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.1780166546
Short name T936
Test name
Test status
Simulation time 66923201 ps
CPU time 0.86 seconds
Started Mar 21 02:22:48 PM PDT 24
Finished Mar 21 02:22:50 PM PDT 24
Peak memory 205604 kb
Host smart-7cfc0241-77f9-484e-b68e-881dd8cd3195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780166546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.1780166546
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.3804368373
Short name T706
Test name
Test status
Simulation time 917188139 ps
CPU time 3.89 seconds
Started Mar 21 02:22:48 PM PDT 24
Finished Mar 21 02:22:52 PM PDT 24
Peak memory 236384 kb
Host smart-bc46a179-6e15-4d24-80da-faf9f0ea4db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804368373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.3804368373
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.840573701
Short name T523
Test name
Test status
Simulation time 18977758 ps
CPU time 0.69 seconds
Started Mar 21 02:22:47 PM PDT 24
Finished Mar 21 02:22:48 PM PDT 24
Peak memory 205220 kb
Host smart-d3e13465-0367-4da4-9820-7558ed340937
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840573701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.840573701
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.300287150
Short name T755
Test name
Test status
Simulation time 586924321 ps
CPU time 4.41 seconds
Started Mar 21 02:22:51 PM PDT 24
Finished Mar 21 02:22:56 PM PDT 24
Peak memory 233596 kb
Host smart-838d8919-4fa2-45a8-a405-4effe34a94a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300287150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.300287150
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.3903049830
Short name T921
Test name
Test status
Simulation time 200768973 ps
CPU time 0.8 seconds
Started Mar 21 02:22:54 PM PDT 24
Finished Mar 21 02:22:55 PM PDT 24
Peak memory 205732 kb
Host smart-a70994ec-b8f0-4710-ace7-82515a83cbdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903049830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.3903049830
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.3846673512
Short name T889
Test name
Test status
Simulation time 36892474223 ps
CPU time 64.91 seconds
Started Mar 21 02:22:50 PM PDT 24
Finished Mar 21 02:23:56 PM PDT 24
Peak memory 240680 kb
Host smart-0c641068-0405-42e5-bcd9-0ea2ed9051d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846673512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.3846673512
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.1160382745
Short name T457
Test name
Test status
Simulation time 34583255114 ps
CPU time 59.56 seconds
Started Mar 21 02:22:51 PM PDT 24
Finished Mar 21 02:23:51 PM PDT 24
Peak memory 256412 kb
Host smart-cc1dbfb0-0ac4-409a-98e3-57a13bf1a551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160382745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.1160382745
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.3470308756
Short name T173
Test name
Test status
Simulation time 15884155725 ps
CPU time 152.65 seconds
Started Mar 21 02:22:51 PM PDT 24
Finished Mar 21 02:25:24 PM PDT 24
Peak memory 272940 kb
Host smart-d916b8bb-4d8b-4a9c-aa94-e6de366c0158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470308756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.3470308756
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_intercept.1498342875
Short name T771
Test name
Test status
Simulation time 4427129108 ps
CPU time 8.87 seconds
Started Mar 21 02:22:51 PM PDT 24
Finished Mar 21 02:23:00 PM PDT 24
Peak memory 233488 kb
Host smart-ec21988b-750f-4f68-973f-3790ff67388a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498342875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.1498342875
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.3203554608
Short name T717
Test name
Test status
Simulation time 2917807947 ps
CPU time 6.3 seconds
Started Mar 21 02:22:49 PM PDT 24
Finished Mar 21 02:22:55 PM PDT 24
Peak memory 233188 kb
Host smart-ebd401fd-0304-4af0-b417-1bf2f7991049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203554608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.3203554608
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.1770749358
Short name T853
Test name
Test status
Simulation time 10022417003 ps
CPU time 16.64 seconds
Started Mar 21 02:22:47 PM PDT 24
Finished Mar 21 02:23:04 PM PDT 24
Peak memory 224348 kb
Host smart-a87afe83-1d78-40e1-bdbd-f77e642cdccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770749358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.1770749358
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.3738169592
Short name T166
Test name
Test status
Simulation time 4266020993 ps
CPU time 15.19 seconds
Started Mar 21 02:22:49 PM PDT 24
Finished Mar 21 02:23:04 PM PDT 24
Peak memory 233564 kb
Host smart-19581042-bce9-41f0-b29e-f5aed0a90908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738169592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.3738169592
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.1085933605
Short name T337
Test name
Test status
Simulation time 13532172480 ps
CPU time 4.57 seconds
Started Mar 21 02:22:50 PM PDT 24
Finished Mar 21 02:22:55 PM PDT 24
Peak memory 218732 kb
Host smart-3e6a2f8d-7ef1-448e-8561-427592e0ac2c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1085933605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.1085933605
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.3776413305
Short name T721
Test name
Test status
Simulation time 409836755120 ps
CPU time 510.73 seconds
Started Mar 21 02:22:53 PM PDT 24
Finished Mar 21 02:31:24 PM PDT 24
Peak memory 265504 kb
Host smart-af3bf9e8-056f-4f64-be62-e5a78b97753e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776413305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.3776413305
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.693173104
Short name T267
Test name
Test status
Simulation time 927104552 ps
CPU time 9.51 seconds
Started Mar 21 02:22:46 PM PDT 24
Finished Mar 21 02:22:56 PM PDT 24
Peak memory 216112 kb
Host smart-657ea3c0-75cf-477b-97a2-8a1567cdaa06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693173104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.693173104
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.1438734774
Short name T522
Test name
Test status
Simulation time 6172660716 ps
CPU time 12.37 seconds
Started Mar 21 02:22:48 PM PDT 24
Finished Mar 21 02:23:00 PM PDT 24
Peak memory 216108 kb
Host smart-f458d9fa-2724-4af3-a279-14541e2193a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438734774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.1438734774
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.942501339
Short name T587
Test name
Test status
Simulation time 298453482 ps
CPU time 10.78 seconds
Started Mar 21 02:22:49 PM PDT 24
Finished Mar 21 02:23:00 PM PDT 24
Peak memory 216052 kb
Host smart-4ac60e40-b7d9-4a9a-a575-08c8b5095136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942501339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.942501339
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.2111006927
Short name T354
Test name
Test status
Simulation time 71181876 ps
CPU time 0.89 seconds
Started Mar 21 02:22:49 PM PDT 24
Finished Mar 21 02:22:50 PM PDT 24
Peak memory 205596 kb
Host smart-a13303bd-5f9d-4c03-86ab-e96d2cb9e92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111006927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.2111006927
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.2206890338
Short name T876
Test name
Test status
Simulation time 2926832635 ps
CPU time 11.29 seconds
Started Mar 21 02:22:50 PM PDT 24
Finished Mar 21 02:23:01 PM PDT 24
Peak memory 233972 kb
Host smart-88f8a455-6022-4fdb-834f-a8083a959570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206890338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.2206890338
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.3375115842
Short name T624
Test name
Test status
Simulation time 37065234 ps
CPU time 0.77 seconds
Started Mar 21 02:23:00 PM PDT 24
Finished Mar 21 02:23:01 PM PDT 24
Peak memory 205584 kb
Host smart-46c0dd67-9c44-4125-96f3-cef9fdcb64ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375115842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
3375115842
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.2163390753
Short name T654
Test name
Test status
Simulation time 2405239013 ps
CPU time 3.96 seconds
Started Mar 21 02:22:58 PM PDT 24
Finished Mar 21 02:23:02 PM PDT 24
Peak memory 218932 kb
Host smart-8bfff791-3ed7-4291-ba3d-1d1bf895ab4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163390753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.2163390753
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.3513752729
Short name T617
Test name
Test status
Simulation time 21054458 ps
CPU time 0.77 seconds
Started Mar 21 02:22:48 PM PDT 24
Finished Mar 21 02:22:49 PM PDT 24
Peak memory 205312 kb
Host smart-7def050b-6178-4dba-bdb7-2705ce0f3dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513752729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.3513752729
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.3190719110
Short name T40
Test name
Test status
Simulation time 3287749467 ps
CPU time 62.91 seconds
Started Mar 21 02:23:03 PM PDT 24
Finished Mar 21 02:24:07 PM PDT 24
Peak memory 255104 kb
Host smart-523d5bca-6aec-4f79-bfc1-263166c15e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190719110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.3190719110
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.4243875398
Short name T207
Test name
Test status
Simulation time 158800773599 ps
CPU time 266.63 seconds
Started Mar 21 02:23:01 PM PDT 24
Finished Mar 21 02:27:28 PM PDT 24
Peak memory 252416 kb
Host smart-d9cacefe-bd64-4616-8e2a-fc5fe53682f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243875398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.4243875398
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.4028474231
Short name T51
Test name
Test status
Simulation time 12391944360 ps
CPU time 96.6 seconds
Started Mar 21 02:23:02 PM PDT 24
Finished Mar 21 02:24:38 PM PDT 24
Peak memory 232664 kb
Host smart-b1e43183-a339-4bdf-9493-ff78ec7eabd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028474231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.4028474231
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.3584727344
Short name T105
Test name
Test status
Simulation time 1102057768 ps
CPU time 17.06 seconds
Started Mar 21 02:22:59 PM PDT 24
Finished Mar 21 02:23:16 PM PDT 24
Peak memory 234704 kb
Host smart-a8590b2f-9b07-4d8e-a8ba-4fa4ae2255d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584727344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.3584727344
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.798044891
Short name T627
Test name
Test status
Simulation time 514166034 ps
CPU time 5.15 seconds
Started Mar 21 02:22:59 PM PDT 24
Finished Mar 21 02:23:05 PM PDT 24
Peak memory 233456 kb
Host smart-5daa5341-2974-4800-8dd4-bf7f29286c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798044891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.798044891
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.3538434455
Short name T811
Test name
Test status
Simulation time 11030614165 ps
CPU time 14.01 seconds
Started Mar 21 02:23:00 PM PDT 24
Finished Mar 21 02:23:14 PM PDT 24
Peak memory 232592 kb
Host smart-e995ef5a-6826-482d-9c20-de1caa91bba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538434455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.3538434455
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.3103138232
Short name T914
Test name
Test status
Simulation time 2735801522 ps
CPU time 5.68 seconds
Started Mar 21 02:23:01 PM PDT 24
Finished Mar 21 02:23:07 PM PDT 24
Peak memory 233596 kb
Host smart-cc445220-923c-4620-853e-62e0f5181169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103138232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.3103138232
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.1779199456
Short name T73
Test name
Test status
Simulation time 646404983 ps
CPU time 6.36 seconds
Started Mar 21 02:22:57 PM PDT 24
Finished Mar 21 02:23:04 PM PDT 24
Peak memory 233332 kb
Host smart-d5b38f36-7be3-41ee-bf13-8c36bd0d6416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779199456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.1779199456
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.872585555
Short name T443
Test name
Test status
Simulation time 461957363 ps
CPU time 3.17 seconds
Started Mar 21 02:23:01 PM PDT 24
Finished Mar 21 02:23:04 PM PDT 24
Peak memory 218588 kb
Host smart-882235ce-61b6-4002-811a-014b5ec67464
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=872585555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dire
ct.872585555
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.394498882
Short name T241
Test name
Test status
Simulation time 157612758961 ps
CPU time 387.98 seconds
Started Mar 21 02:22:59 PM PDT 24
Finished Mar 21 02:29:28 PM PDT 24
Peak memory 265940 kb
Host smart-2cbcf034-1240-4ee4-a216-d88c538f4745
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394498882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stres
s_all.394498882
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.3013460732
Short name T860
Test name
Test status
Simulation time 1649046032 ps
CPU time 10.2 seconds
Started Mar 21 02:22:59 PM PDT 24
Finished Mar 21 02:23:10 PM PDT 24
Peak memory 216104 kb
Host smart-84e0e9f3-175c-4063-958b-fc8bd2bd7f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013460732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.3013460732
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.2308335317
Short name T680
Test name
Test status
Simulation time 29255642587 ps
CPU time 20.62 seconds
Started Mar 21 02:22:51 PM PDT 24
Finished Mar 21 02:23:12 PM PDT 24
Peak memory 216184 kb
Host smart-5a2c8b76-80b5-4bc0-bb8b-cfb448d82eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308335317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.2308335317
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.1117003148
Short name T612
Test name
Test status
Simulation time 129075350 ps
CPU time 2.06 seconds
Started Mar 21 02:23:01 PM PDT 24
Finished Mar 21 02:23:03 PM PDT 24
Peak memory 216132 kb
Host smart-abef34fd-1e1e-4cb6-8a65-46df014ff3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117003148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.1117003148
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.3985912501
Short name T746
Test name
Test status
Simulation time 161089440 ps
CPU time 0.87 seconds
Started Mar 21 02:22:58 PM PDT 24
Finished Mar 21 02:22:59 PM PDT 24
Peak memory 206624 kb
Host smart-5bfba5c7-49ba-4adf-ad6b-5b7787913e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985912501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3985912501
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.2557895884
Short name T217
Test name
Test status
Simulation time 7749993153 ps
CPU time 11.74 seconds
Started Mar 21 02:22:58 PM PDT 24
Finished Mar 21 02:23:10 PM PDT 24
Peak memory 223284 kb
Host smart-421a44bc-9aa5-474a-a84d-7ebd338e6ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557895884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.2557895884
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.2785535632
Short name T396
Test name
Test status
Simulation time 33841263 ps
CPU time 0.7 seconds
Started Mar 21 02:17:09 PM PDT 24
Finished Mar 21 02:17:10 PM PDT 24
Peak memory 204620 kb
Host smart-77c61816-3bfe-4061-99e2-9dd20cec901b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785535632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.2
785535632
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.3124448170
Short name T460
Test name
Test status
Simulation time 3644623006 ps
CPU time 4.41 seconds
Started Mar 21 02:17:09 PM PDT 24
Finished Mar 21 02:17:14 PM PDT 24
Peak memory 218540 kb
Host smart-6e3dec07-9b0c-43d3-8485-6d2a53734604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124448170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.3124448170
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.559934827
Short name T432
Test name
Test status
Simulation time 20518582 ps
CPU time 0.82 seconds
Started Mar 21 02:16:57 PM PDT 24
Finished Mar 21 02:16:58 PM PDT 24
Peak memory 206356 kb
Host smart-a75b8f98-c6a0-40c7-aacd-0f7595aa8e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559934827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.559934827
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.2473681883
Short name T163
Test name
Test status
Simulation time 52716878982 ps
CPU time 81.32 seconds
Started Mar 21 02:17:08 PM PDT 24
Finished Mar 21 02:18:29 PM PDT 24
Peak memory 272552 kb
Host smart-2b0aed28-878e-4f3c-93c5-ce8ed6f9faa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473681883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.2473681883
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.352620483
Short name T830
Test name
Test status
Simulation time 6890078196 ps
CPU time 42.24 seconds
Started Mar 21 02:17:08 PM PDT 24
Finished Mar 21 02:17:51 PM PDT 24
Peak memory 235972 kb
Host smart-61783f25-b3a2-4d56-a642-b69a63e05d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352620483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.352620483
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.1630169002
Short name T753
Test name
Test status
Simulation time 20857894107 ps
CPU time 65.65 seconds
Started Mar 21 02:17:07 PM PDT 24
Finished Mar 21 02:18:13 PM PDT 24
Peak memory 235588 kb
Host smart-7b0634e5-6299-48f3-ac87-3e9142e4dde8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630169002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.1630169002
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.1870520443
Short name T265
Test name
Test status
Simulation time 42181873652 ps
CPU time 45.54 seconds
Started Mar 21 02:17:11 PM PDT 24
Finished Mar 21 02:17:56 PM PDT 24
Peak memory 239244 kb
Host smart-e0b71b64-b247-4964-a56b-f61d8a9efe37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870520443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.1870520443
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.603505412
Short name T741
Test name
Test status
Simulation time 81501004 ps
CPU time 2.35 seconds
Started Mar 21 02:17:07 PM PDT 24
Finished Mar 21 02:17:09 PM PDT 24
Peak memory 216528 kb
Host smart-1cce5361-432c-47ff-bbb0-a4407cae8342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603505412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.603505412
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.3792733077
Short name T36
Test name
Test status
Simulation time 11377285123 ps
CPU time 34.91 seconds
Started Mar 21 02:17:09 PM PDT 24
Finished Mar 21 02:17:44 PM PDT 24
Peak memory 235104 kb
Host smart-5416ad20-69aa-4859-b5dd-563d2f4a8998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792733077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.3792733077
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.1730868265
Short name T572
Test name
Test status
Simulation time 5414620061 ps
CPU time 16.89 seconds
Started Mar 21 02:17:07 PM PDT 24
Finished Mar 21 02:17:24 PM PDT 24
Peak memory 234456 kb
Host smart-0fbcc2bc-7e98-48bb-8788-2811794dcb33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730868265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.1730868265
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.568924707
Short name T757
Test name
Test status
Simulation time 3032746963 ps
CPU time 4.14 seconds
Started Mar 21 02:17:07 PM PDT 24
Finished Mar 21 02:17:12 PM PDT 24
Peak memory 224416 kb
Host smart-0c11570f-f94a-44dd-8864-6a7b07b885bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568924707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.568924707
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_ram_cfg.3212578345
Short name T62
Test name
Test status
Simulation time 36245509 ps
CPU time 0.76 seconds
Started Mar 21 02:16:58 PM PDT 24
Finished Mar 21 02:16:59 PM PDT 24
Peak memory 216108 kb
Host smart-6b594318-e64f-4b81-b43a-3fe508c2168c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212578345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_ram_cfg.3212578345
Directory /workspace/5.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.1208063975
Short name T5
Test name
Test status
Simulation time 2017590132 ps
CPU time 7.72 seconds
Started Mar 21 02:17:09 PM PDT 24
Finished Mar 21 02:17:17 PM PDT 24
Peak memory 219780 kb
Host smart-75699cdb-ec58-40c4-a73c-933cc632e95b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1208063975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.1208063975
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.1546740327
Short name T946
Test name
Test status
Simulation time 1496312912838 ps
CPU time 560.13 seconds
Started Mar 21 02:17:10 PM PDT 24
Finished Mar 21 02:26:30 PM PDT 24
Peak memory 281064 kb
Host smart-7967bf3f-a120-4ac2-b9ba-a339c24b2bcc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546740327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.1546740327
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.1563426170
Short name T486
Test name
Test status
Simulation time 5789604530 ps
CPU time 20.23 seconds
Started Mar 21 02:17:10 PM PDT 24
Finished Mar 21 02:17:31 PM PDT 24
Peak memory 216392 kb
Host smart-4410f1aa-b146-4ff7-8af4-9b9359abcc63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563426170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.1563426170
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.1876335080
Short name T676
Test name
Test status
Simulation time 3434864609 ps
CPU time 13.57 seconds
Started Mar 21 02:16:59 PM PDT 24
Finished Mar 21 02:17:13 PM PDT 24
Peak memory 216200 kb
Host smart-b322ea88-c0ba-413c-9e58-7f1296c8ba0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876335080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.1876335080
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.800262047
Short name T351
Test name
Test status
Simulation time 592825686 ps
CPU time 10.32 seconds
Started Mar 21 02:17:09 PM PDT 24
Finished Mar 21 02:17:19 PM PDT 24
Peak memory 216172 kb
Host smart-82c050a5-3e2a-4803-b28c-2737fbeeb517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800262047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.800262047
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.4015235637
Short name T705
Test name
Test status
Simulation time 172196914 ps
CPU time 0.94 seconds
Started Mar 21 02:17:06 PM PDT 24
Finished Mar 21 02:17:08 PM PDT 24
Peak memory 206612 kb
Host smart-e9812fc6-6135-4602-af08-aff770eb50a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015235637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.4015235637
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.2336001236
Short name T332
Test name
Test status
Simulation time 2074666087 ps
CPU time 9.16 seconds
Started Mar 21 02:17:07 PM PDT 24
Finished Mar 21 02:17:16 PM PDT 24
Peak memory 239112 kb
Host smart-fe6c318e-99ae-497a-92f0-c1484864360b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336001236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.2336001236
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.1693561207
Short name T534
Test name
Test status
Simulation time 37230454 ps
CPU time 0.69 seconds
Started Mar 21 02:17:25 PM PDT 24
Finished Mar 21 02:17:26 PM PDT 24
Peak memory 204684 kb
Host smart-2c72879c-b2d8-44eb-b14e-8cb1ff344221
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693561207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.1
693561207
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.1821336695
Short name T495
Test name
Test status
Simulation time 303914219 ps
CPU time 3.07 seconds
Started Mar 21 02:17:24 PM PDT 24
Finished Mar 21 02:17:28 PM PDT 24
Peak memory 218620 kb
Host smart-6f3ec973-66b7-45b4-b7fb-2ba8ad1d37d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821336695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.1821336695
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.2925168412
Short name T400
Test name
Test status
Simulation time 36853855 ps
CPU time 0.8 seconds
Started Mar 21 02:17:10 PM PDT 24
Finished Mar 21 02:17:11 PM PDT 24
Peak memory 206676 kb
Host smart-f6806fa3-30ca-4af1-985b-5ad43a0420c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925168412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.2925168412
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.2146196903
Short name T253
Test name
Test status
Simulation time 250440148038 ps
CPU time 387.65 seconds
Started Mar 21 02:17:26 PM PDT 24
Finished Mar 21 02:23:54 PM PDT 24
Peak memory 260112 kb
Host smart-25b435fa-de98-4caf-ab67-d80a41e335f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146196903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.2146196903
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.4016023787
Short name T404
Test name
Test status
Simulation time 125903996969 ps
CPU time 248.62 seconds
Started Mar 21 02:17:26 PM PDT 24
Finished Mar 21 02:21:35 PM PDT 24
Peak memory 257516 kb
Host smart-52389a3a-7a33-44bf-94c3-89c6289529f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016023787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.4016023787
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.4052985979
Short name T373
Test name
Test status
Simulation time 45999822862 ps
CPU time 24.83 seconds
Started Mar 21 02:17:26 PM PDT 24
Finished Mar 21 02:17:51 PM PDT 24
Peak memory 256644 kb
Host smart-e579fc65-761d-4106-b90d-78efe17e4744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052985979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.4052985979
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.2112962464
Short name T213
Test name
Test status
Simulation time 4729300932 ps
CPU time 5.62 seconds
Started Mar 21 02:17:24 PM PDT 24
Finished Mar 21 02:17:31 PM PDT 24
Peak memory 224400 kb
Host smart-87103219-ec37-4f7d-aacf-97f8b994166d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112962464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.2112962464
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.3254751628
Short name T76
Test name
Test status
Simulation time 244593795 ps
CPU time 3.09 seconds
Started Mar 21 02:17:26 PM PDT 24
Finished Mar 21 02:17:30 PM PDT 24
Peak memory 224332 kb
Host smart-7eb7a590-600f-4380-8df1-eee188826000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254751628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.3254751628
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.941701654
Short name T350
Test name
Test status
Simulation time 307008833 ps
CPU time 2.5 seconds
Started Mar 21 02:17:25 PM PDT 24
Finished Mar 21 02:17:28 PM PDT 24
Peak memory 232572 kb
Host smart-e8a7cab1-9017-4174-9cba-c97176050bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941701654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.
941701654
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.295116831
Short name T352
Test name
Test status
Simulation time 3460968304 ps
CPU time 8.26 seconds
Started Mar 21 02:17:09 PM PDT 24
Finished Mar 21 02:17:18 PM PDT 24
Peak memory 226668 kb
Host smart-c9f13832-5705-4bf6-81de-8ba9a5af7df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295116831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.295116831
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_ram_cfg.2330957781
Short name T473
Test name
Test status
Simulation time 17375094 ps
CPU time 0.77 seconds
Started Mar 21 02:17:09 PM PDT 24
Finished Mar 21 02:17:10 PM PDT 24
Peak memory 216080 kb
Host smart-98c278d1-b433-4f47-97a6-21a9c1e29df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330957781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_ram_cfg.2330957781
Directory /workspace/6.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.3264953932
Short name T903
Test name
Test status
Simulation time 1402877472 ps
CPU time 5 seconds
Started Mar 21 02:17:24 PM PDT 24
Finished Mar 21 02:17:30 PM PDT 24
Peak memory 218656 kb
Host smart-7ef565fa-eecd-4638-b47a-3aca77185cf8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3264953932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.3264953932
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.2775216809
Short name T138
Test name
Test status
Simulation time 168849656 ps
CPU time 1 seconds
Started Mar 21 02:17:27 PM PDT 24
Finished Mar 21 02:17:28 PM PDT 24
Peak memory 206508 kb
Host smart-402435a5-844d-44ac-8b34-a055bde349f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775216809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.2775216809
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.3149220305
Short name T778
Test name
Test status
Simulation time 15269830489 ps
CPU time 83.95 seconds
Started Mar 21 02:17:09 PM PDT 24
Finished Mar 21 02:18:34 PM PDT 24
Peak memory 216184 kb
Host smart-ef87452c-c9f5-4e16-adda-fe49bd058c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149220305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.3149220305
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.250249374
Short name T453
Test name
Test status
Simulation time 7926190734 ps
CPU time 22.75 seconds
Started Mar 21 02:17:08 PM PDT 24
Finished Mar 21 02:17:31 PM PDT 24
Peak memory 216028 kb
Host smart-b5862f47-6e67-4f22-918c-d68ea5670ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250249374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.250249374
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.2014635388
Short name T464
Test name
Test status
Simulation time 62590086 ps
CPU time 1.21 seconds
Started Mar 21 02:17:07 PM PDT 24
Finished Mar 21 02:17:09 PM PDT 24
Peak memory 207060 kb
Host smart-32cbedea-ce7a-4acd-b89d-0c8374a9eb95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014635388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.2014635388
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.2942051756
Short name T393
Test name
Test status
Simulation time 417296728 ps
CPU time 1.07 seconds
Started Mar 21 02:17:12 PM PDT 24
Finished Mar 21 02:17:13 PM PDT 24
Peak memory 206692 kb
Host smart-02810800-4c6a-4747-86dc-2977198d110f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942051756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.2942051756
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.3764855408
Short name T834
Test name
Test status
Simulation time 1462581008 ps
CPU time 5.96 seconds
Started Mar 21 02:17:25 PM PDT 24
Finished Mar 21 02:17:31 PM PDT 24
Peak memory 233788 kb
Host smart-d1fab385-9264-407b-ba1a-0df950a9c5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764855408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.3764855408
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.4172659572
Short name T611
Test name
Test status
Simulation time 19968847 ps
CPU time 0.7 seconds
Started Mar 21 02:17:35 PM PDT 24
Finished Mar 21 02:17:36 PM PDT 24
Peak memory 205600 kb
Host smart-cff26631-243f-475c-8c03-a48761de1454
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172659572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.4
172659572
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.4026840085
Short name T434
Test name
Test status
Simulation time 1046650981 ps
CPU time 3.04 seconds
Started Mar 21 02:17:38 PM PDT 24
Finished Mar 21 02:17:43 PM PDT 24
Peak memory 218660 kb
Host smart-956a953a-ae98-423e-b227-23c346ca5dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026840085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.4026840085
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.1251282559
Short name T326
Test name
Test status
Simulation time 54974357 ps
CPU time 0.78 seconds
Started Mar 21 02:17:24 PM PDT 24
Finished Mar 21 02:17:25 PM PDT 24
Peak memory 206340 kb
Host smart-94432b03-8d46-4d89-b2e9-f660d444e644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251282559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.1251282559
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.2475203896
Short name T943
Test name
Test status
Simulation time 150405617951 ps
CPU time 367.88 seconds
Started Mar 21 02:17:38 PM PDT 24
Finished Mar 21 02:23:48 PM PDT 24
Peak memory 266292 kb
Host smart-ebd240d7-47ae-4e9b-ad31-ec0ff6c97738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475203896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.2475203896
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.543278870
Short name T804
Test name
Test status
Simulation time 86097682316 ps
CPU time 318.92 seconds
Started Mar 21 02:17:36 PM PDT 24
Finished Mar 21 02:22:56 PM PDT 24
Peak memory 256640 kb
Host smart-a065e506-61a6-4a83-b0d6-006cd8187389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543278870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.543278870
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.126271263
Short name T674
Test name
Test status
Simulation time 2772304963 ps
CPU time 24.53 seconds
Started Mar 21 02:17:36 PM PDT 24
Finished Mar 21 02:18:01 PM PDT 24
Peak memory 251752 kb
Host smart-c07ec5e7-c8e8-412f-8daf-c3493a4d8f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126271263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.
126271263
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.3574104174
Short name T264
Test name
Test status
Simulation time 4974071290 ps
CPU time 27.5 seconds
Started Mar 21 02:17:35 PM PDT 24
Finished Mar 21 02:18:03 PM PDT 24
Peak memory 233720 kb
Host smart-c0aa665d-c095-4000-98ae-71929579cb22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574104174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.3574104174
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.4125924550
Short name T234
Test name
Test status
Simulation time 276976899 ps
CPU time 3.18 seconds
Started Mar 21 02:17:35 PM PDT 24
Finished Mar 21 02:17:39 PM PDT 24
Peak memory 218556 kb
Host smart-8cfe4a90-7346-4dc0-83c0-0d1334fd5bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125924550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.4125924550
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.3691422359
Short name T186
Test name
Test status
Simulation time 733857645 ps
CPU time 7.44 seconds
Started Mar 21 02:17:39 PM PDT 24
Finished Mar 21 02:17:48 PM PDT 24
Peak memory 233980 kb
Host smart-d9681add-fcea-4402-b767-8162449c42f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691422359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.3691422359
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.1136000367
Short name T463
Test name
Test status
Simulation time 11945154693 ps
CPU time 20.19 seconds
Started Mar 21 02:17:38 PM PDT 24
Finished Mar 21 02:18:00 PM PDT 24
Peak memory 228420 kb
Host smart-e8d87e19-2f8b-4a9b-9bc3-c3b61bd64833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136000367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.1136000367
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.94939940
Short name T204
Test name
Test status
Simulation time 2452926557 ps
CPU time 4.84 seconds
Started Mar 21 02:17:34 PM PDT 24
Finished Mar 21 02:17:40 PM PDT 24
Peak memory 218456 kb
Host smart-30c20a09-3202-49aa-bb6e-d7f603c15c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94939940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.94939940
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_ram_cfg.3696764397
Short name T667
Test name
Test status
Simulation time 17266906 ps
CPU time 0.79 seconds
Started Mar 21 02:17:25 PM PDT 24
Finished Mar 21 02:17:26 PM PDT 24
Peak memory 216100 kb
Host smart-d4bfc943-6a82-4e36-97a0-ad71c62914d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696764397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_ram_cfg.3696764397
Directory /workspace/7.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.4181821699
Short name T858
Test name
Test status
Simulation time 594230555 ps
CPU time 4.08 seconds
Started Mar 21 02:17:38 PM PDT 24
Finished Mar 21 02:17:44 PM PDT 24
Peak memory 218984 kb
Host smart-a74bafa8-e02c-4c70-8eae-c912992437f2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4181821699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.4181821699
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.2996790805
Short name T132
Test name
Test status
Simulation time 41714563803 ps
CPU time 130.88 seconds
Started Mar 21 02:17:34 PM PDT 24
Finished Mar 21 02:19:46 PM PDT 24
Peak memory 265036 kb
Host smart-2a76384c-10e3-42b9-89c1-d2ec807d7e1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996790805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.2996790805
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.1930528480
Short name T528
Test name
Test status
Simulation time 4157298950 ps
CPU time 31.86 seconds
Started Mar 21 02:17:37 PM PDT 24
Finished Mar 21 02:18:09 PM PDT 24
Peak memory 217700 kb
Host smart-80623b6f-cdd5-4d8c-833a-08a711481d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930528480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.1930528480
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.2255516487
Short name T651
Test name
Test status
Simulation time 4268868816 ps
CPU time 12.42 seconds
Started Mar 21 02:17:39 PM PDT 24
Finished Mar 21 02:17:53 PM PDT 24
Peak memory 216232 kb
Host smart-5f3a371a-69fc-4719-8dce-0a711190086c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255516487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.2255516487
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.3135493127
Short name T292
Test name
Test status
Simulation time 603398716 ps
CPU time 5.87 seconds
Started Mar 21 02:17:39 PM PDT 24
Finished Mar 21 02:17:47 PM PDT 24
Peak memory 216132 kb
Host smart-3365eb8e-5aa1-49da-a5f7-043fab337e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135493127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.3135493127
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.2221902651
Short name T556
Test name
Test status
Simulation time 17669160 ps
CPU time 0.7 seconds
Started Mar 21 02:17:34 PM PDT 24
Finished Mar 21 02:17:36 PM PDT 24
Peak memory 205604 kb
Host smart-b66cbbcf-c276-4359-b5ed-a9fbc82945d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221902651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.2221902651
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.967226802
Short name T175
Test name
Test status
Simulation time 3539727324 ps
CPU time 16.37 seconds
Started Mar 21 02:17:50 PM PDT 24
Finished Mar 21 02:18:06 PM PDT 24
Peak memory 234944 kb
Host smart-0af9eba5-771b-4a6f-b302-6717c9fb0e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967226802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.967226802
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.2538147206
Short name T592
Test name
Test status
Simulation time 13784580 ps
CPU time 0.7 seconds
Started Mar 21 02:17:44 PM PDT 24
Finished Mar 21 02:17:45 PM PDT 24
Peak memory 205284 kb
Host smart-084a60c8-9e72-4a7c-a53d-a5764a3d776f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538147206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.2
538147206
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.578577806
Short name T218
Test name
Test status
Simulation time 138541501 ps
CPU time 3.27 seconds
Started Mar 21 02:17:46 PM PDT 24
Finished Mar 21 02:17:50 PM PDT 24
Peak memory 235392 kb
Host smart-d3fbcfdb-99dd-4787-b228-7c0cac57ec2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578577806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.578577806
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.421044030
Short name T378
Test name
Test status
Simulation time 58536923 ps
CPU time 0.76 seconds
Started Mar 21 02:17:38 PM PDT 24
Finished Mar 21 02:17:39 PM PDT 24
Peak memory 205304 kb
Host smart-3bc5813e-3b9b-482c-a4ef-f1ac1dd66787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421044030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.421044030
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.1038028216
Short name T212
Test name
Test status
Simulation time 302130287503 ps
CPU time 362.86 seconds
Started Mar 21 02:17:53 PM PDT 24
Finished Mar 21 02:23:56 PM PDT 24
Peak memory 265156 kb
Host smart-07909ef7-2188-41e0-a8fc-baa5a50fd824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038028216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.1038028216
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.1609289625
Short name T179
Test name
Test status
Simulation time 41170498111 ps
CPU time 159.28 seconds
Started Mar 21 02:17:51 PM PDT 24
Finished Mar 21 02:20:30 PM PDT 24
Peak memory 261080 kb
Host smart-98c1833f-ca72-4fcc-ab67-1d5b37ad17f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609289625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.1609289625
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.3974225022
Short name T581
Test name
Test status
Simulation time 4409924655 ps
CPU time 56.61 seconds
Started Mar 21 02:17:55 PM PDT 24
Finished Mar 21 02:18:52 PM PDT 24
Peak memory 249492 kb
Host smart-e95fa84e-06d6-4f23-a736-e43ad60796f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974225022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.3974225022
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.2252699278
Short name T183
Test name
Test status
Simulation time 7088762851 ps
CPU time 16.71 seconds
Started Mar 21 02:17:48 PM PDT 24
Finished Mar 21 02:18:05 PM PDT 24
Peak memory 245084 kb
Host smart-0851388e-9b0d-46e1-a955-14b68b28f3e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252699278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.2252699278
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.2821401284
Short name T171
Test name
Test status
Simulation time 379469158 ps
CPU time 3.76 seconds
Started Mar 21 02:17:45 PM PDT 24
Finished Mar 21 02:17:49 PM PDT 24
Peak memory 219452 kb
Host smart-418d4bd6-a649-424d-96a8-7322b5519f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821401284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.2821401284
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.1812936905
Short name T215
Test name
Test status
Simulation time 500691223 ps
CPU time 5.62 seconds
Started Mar 21 02:17:49 PM PDT 24
Finished Mar 21 02:17:54 PM PDT 24
Peak memory 233244 kb
Host smart-11374963-5173-4652-bc41-8079d37e3078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812936905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.1812936905
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.4124765186
Short name T361
Test name
Test status
Simulation time 2459234059 ps
CPU time 13.27 seconds
Started Mar 21 02:17:53 PM PDT 24
Finished Mar 21 02:18:07 PM PDT 24
Peak memory 229080 kb
Host smart-be25ce54-23b0-4789-a29f-3cb59ecfc129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124765186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.4124765186
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.25001273
Short name T379
Test name
Test status
Simulation time 5895592757 ps
CPU time 6.42 seconds
Started Mar 21 02:17:46 PM PDT 24
Finished Mar 21 02:17:52 PM PDT 24
Peak memory 216580 kb
Host smart-acb75565-b2d3-48ce-a4f5-fb93fae92d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25001273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.25001273
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_ram_cfg.3280097308
Short name T554
Test name
Test status
Simulation time 53862346 ps
CPU time 0.81 seconds
Started Mar 21 02:17:38 PM PDT 24
Finished Mar 21 02:17:39 PM PDT 24
Peak memory 216084 kb
Host smart-d7373dd0-407a-43c4-9633-fb2bb0ab68ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280097308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_ram_cfg.3280097308
Directory /workspace/8.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.3893445518
Short name T304
Test name
Test status
Simulation time 548405922 ps
CPU time 4.08 seconds
Started Mar 21 02:17:48 PM PDT 24
Finished Mar 21 02:17:53 PM PDT 24
Peak memory 222172 kb
Host smart-948fb59f-0ee0-44c7-90e2-3148c3a0634e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3893445518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.3893445518
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.2066410624
Short name T19
Test name
Test status
Simulation time 41197392778 ps
CPU time 292.78 seconds
Started Mar 21 02:17:48 PM PDT 24
Finished Mar 21 02:22:41 PM PDT 24
Peak memory 257168 kb
Host smart-1a9712f8-699e-4ba3-be2a-745439f3af62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066410624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.2066410624
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.193244486
Short name T905
Test name
Test status
Simulation time 4246702772 ps
CPU time 23.91 seconds
Started Mar 21 02:17:36 PM PDT 24
Finished Mar 21 02:18:01 PM PDT 24
Peak memory 216252 kb
Host smart-ce8e8d0b-0c27-4916-91ad-acc15547ca09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193244486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.193244486
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.1467907738
Short name T730
Test name
Test status
Simulation time 6910607727 ps
CPU time 15.42 seconds
Started Mar 21 02:17:38 PM PDT 24
Finished Mar 21 02:17:53 PM PDT 24
Peak memory 216156 kb
Host smart-0956bec3-8aa5-450a-be59-b4ec86bbbfde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467907738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.1467907738
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.3077667794
Short name T441
Test name
Test status
Simulation time 395182790 ps
CPU time 1.13 seconds
Started Mar 21 02:17:40 PM PDT 24
Finished Mar 21 02:17:42 PM PDT 24
Peak memory 206600 kb
Host smart-df9b3bcc-d4f3-4a9c-af41-82d0e9b2af3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077667794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.3077667794
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.3466638791
Short name T294
Test name
Test status
Simulation time 83610504 ps
CPU time 0.81 seconds
Started Mar 21 02:17:36 PM PDT 24
Finished Mar 21 02:17:37 PM PDT 24
Peak memory 205556 kb
Host smart-b0099c96-34d7-4c3a-96bf-134631a76f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466638791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.3466638791
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.368243105
Short name T640
Test name
Test status
Simulation time 695415146 ps
CPU time 6.85 seconds
Started Mar 21 02:17:53 PM PDT 24
Finished Mar 21 02:18:00 PM PDT 24
Peak memory 233756 kb
Host smart-f6f26d98-d06a-446a-865e-e879c32ead3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368243105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.368243105
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.1749949757
Short name T920
Test name
Test status
Simulation time 46955723 ps
CPU time 0.71 seconds
Started Mar 21 02:17:56 PM PDT 24
Finished Mar 21 02:17:57 PM PDT 24
Peak memory 205288 kb
Host smart-2f370405-72e4-443c-b318-3898e6417fb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749949757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.1
749949757
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.2444672222
Short name T203
Test name
Test status
Simulation time 208043935 ps
CPU time 4.35 seconds
Started Mar 21 02:17:57 PM PDT 24
Finished Mar 21 02:18:01 PM PDT 24
Peak memory 234256 kb
Host smart-b41a99d0-f578-47a7-9e95-02310a71e2aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444672222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.2444672222
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.4079701330
Short name T482
Test name
Test status
Simulation time 110256148 ps
CPU time 0.77 seconds
Started Mar 21 02:17:47 PM PDT 24
Finished Mar 21 02:17:48 PM PDT 24
Peak memory 205660 kb
Host smart-76ed1e1a-ce40-4456-8f7d-c709f1d21073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079701330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.4079701330
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.2571021349
Short name T471
Test name
Test status
Simulation time 21204709876 ps
CPU time 75.54 seconds
Started Mar 21 02:17:58 PM PDT 24
Finished Mar 21 02:19:14 PM PDT 24
Peak memory 265392 kb
Host smart-3c552ea1-1d7d-4409-ad2d-542b362955af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571021349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.2571021349
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.398933400
Short name T917
Test name
Test status
Simulation time 218595331851 ps
CPU time 287.18 seconds
Started Mar 21 02:17:58 PM PDT 24
Finished Mar 21 02:22:45 PM PDT 24
Peak memory 263168 kb
Host smart-1b46850f-ba42-47cf-a516-5886ba3e7313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398933400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.398933400
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.326288999
Short name T257
Test name
Test status
Simulation time 2973260349 ps
CPU time 56.03 seconds
Started Mar 21 02:17:54 PM PDT 24
Finished Mar 21 02:18:50 PM PDT 24
Peak memory 255656 kb
Host smart-07050833-9238-4bf1-9783-3ad5f32e5efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326288999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.
326288999
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.4134144081
Short name T770
Test name
Test status
Simulation time 16256925465 ps
CPU time 31 seconds
Started Mar 21 02:17:56 PM PDT 24
Finished Mar 21 02:18:27 PM PDT 24
Peak memory 239044 kb
Host smart-0567f539-5e08-4e0d-ab4c-f67da7a6ce66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134144081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.4134144081
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.295153206
Short name T935
Test name
Test status
Simulation time 1937407505 ps
CPU time 7.54 seconds
Started Mar 21 02:17:55 PM PDT 24
Finished Mar 21 02:18:03 PM PDT 24
Peak memory 218724 kb
Host smart-2b559ff0-83cc-4314-8ac1-3e818b1886c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295153206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.295153206
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.2725444617
Short name T694
Test name
Test status
Simulation time 37051117094 ps
CPU time 37.04 seconds
Started Mar 21 02:17:57 PM PDT 24
Finished Mar 21 02:18:34 PM PDT 24
Peak memory 236300 kb
Host smart-538d134c-b13d-43a4-b0a6-43c5a6e27eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725444617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.2725444617
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.1913289306
Short name T152
Test name
Test status
Simulation time 12439529335 ps
CPU time 9.18 seconds
Started Mar 21 02:17:54 PM PDT 24
Finished Mar 21 02:18:03 PM PDT 24
Peak memory 218548 kb
Host smart-3f993944-b398-4c9f-b771-f3cc94f8c37b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913289306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.1913289306
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.1506454771
Short name T167
Test name
Test status
Simulation time 1255188265 ps
CPU time 4.97 seconds
Started Mar 21 02:17:57 PM PDT 24
Finished Mar 21 02:18:02 PM PDT 24
Peak memory 217816 kb
Host smart-04e845d8-af31-489a-858e-5e88d06ec573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506454771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.1506454771
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_ram_cfg.1806077698
Short name T61
Test name
Test status
Simulation time 24125071 ps
CPU time 0.74 seconds
Started Mar 21 02:17:48 PM PDT 24
Finished Mar 21 02:17:49 PM PDT 24
Peak memory 216096 kb
Host smart-4b8bd344-01b0-4321-9765-8865511cd0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806077698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_ram_cfg.1806077698
Directory /workspace/9.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.2951527088
Short name T646
Test name
Test status
Simulation time 2512911434 ps
CPU time 8.87 seconds
Started Mar 21 02:17:56 PM PDT 24
Finished Mar 21 02:18:05 PM PDT 24
Peak memory 219036 kb
Host smart-844e24d2-5a40-4dba-be5c-558a15d249ee
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2951527088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.2951527088
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.2259291345
Short name T928
Test name
Test status
Simulation time 97965928 ps
CPU time 1.05 seconds
Started Mar 21 02:17:56 PM PDT 24
Finished Mar 21 02:17:58 PM PDT 24
Peak memory 206624 kb
Host smart-8e1da5a2-6aff-4a8a-8e04-c1b697a0cabf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259291345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.2259291345
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.3310301387
Short name T838
Test name
Test status
Simulation time 13103130951 ps
CPU time 47.82 seconds
Started Mar 21 02:17:56 PM PDT 24
Finished Mar 21 02:18:44 PM PDT 24
Peak memory 220952 kb
Host smart-9742dcfe-d6ef-4c34-b8b9-cbc7cdf5eb6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310301387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.3310301387
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.3888262220
Short name T283
Test name
Test status
Simulation time 2432748990 ps
CPU time 9 seconds
Started Mar 21 02:17:46 PM PDT 24
Finished Mar 21 02:17:56 PM PDT 24
Peak memory 216124 kb
Host smart-bc94fa51-f80d-4eaa-a9ab-92d963b28ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888262220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.3888262220
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.2191146370
Short name T275
Test name
Test status
Simulation time 64779414 ps
CPU time 3.12 seconds
Started Mar 21 02:17:56 PM PDT 24
Finished Mar 21 02:18:00 PM PDT 24
Peak memory 216048 kb
Host smart-093e8677-bb6b-4764-96a8-8880d4ea5c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191146370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2191146370
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.1400053500
Short name T520
Test name
Test status
Simulation time 113431078 ps
CPU time 1.07 seconds
Started Mar 21 02:17:56 PM PDT 24
Finished Mar 21 02:17:57 PM PDT 24
Peak memory 206548 kb
Host smart-45bd62a1-36a4-4b2c-9833-c70952ed01ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400053500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1400053500
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.4150324185
Short name T902
Test name
Test status
Simulation time 1550803179 ps
CPU time 11.21 seconds
Started Mar 21 02:17:59 PM PDT 24
Finished Mar 21 02:18:10 PM PDT 24
Peak memory 237788 kb
Host smart-88186561-21c6-42af-8474-4706f3caaead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150324185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.4150324185
Directory /workspace/9.spi_device_upload/latest
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