Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5818455	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

6206868

1

T1

1117

T2

20

T3

878

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	7710131	1			T1	1		T2	1		T3	2
values[0x0]	2156193	1			T1	673		T2	17		T3	440
values[0x1]	2158999	1			T1	680		T2	10		T3	439

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4216405	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

7808918

1

T1

1179

T2

23

T3

879

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	46028	1			T3	12		T5	829		T6	2
valid_sources[0x01]	54543	1			T5	4		T7	156		T9	2
valid_sources[0x02]	49422	1			T3	8		T5	60		T6	14
valid_sources[0x03]	44495	1			T5	18		T7	159		T9	7
valid_sources[0x04]	45790	1			T3	9		T5	66		T7	155
valid_sources[0x05]	47266	1			T5	5		T7	122		T10	55
valid_sources[0x06]	44904	1			T5	18		T6	3		T7	142
valid_sources[0x07]	43957	1			T3	5		T5	6		T6	2
valid_sources[0x08]	49342	1			T5	150		T7	153		T9	7
valid_sources[0x09]	48165	1			T5	27		T7	162		T10	61
valid_sources[0x0a]	46943	1			T5	164		T7	168		T9	1
valid_sources[0x0b]	43613	1			T5	22		T7	174		T10	51
valid_sources[0x0c]	53495	1			T5	186		T7	140		T10	60
valid_sources[0x0d]	45443	1			T5	464		T6	9		T7	183
valid_sources[0x0e]	44504	1			T5	11		T6	14		T7	147
valid_sources[0x0f]	49319	1			T5	127		T7	140		T10	50
valid_sources[0x10]	48005	1			T5	67		T7	157		T10	52
valid_sources[0x11]	48430	1			T5	200		T6	1		T7	132
valid_sources[0x12]	49738	1			T3	3		T5	111		T6	7
valid_sources[0x13]	44871	1			T3	16		T5	13		T7	169
valid_sources[0x14]	44870	1			T5	175		T6	8		T7	179
valid_sources[0x15]	45639	1			T5	91		T7	160		T10	63
valid_sources[0x16]	48591	1			T5	67		T6	5		T7	134
valid_sources[0x17]	47387	1			T3	16		T5	149		T7	142
valid_sources[0x18]	48315	1			T3	4		T5	69		T7	154
valid_sources[0x19]	46361	1			T5	9		T7	151		T9	71
valid_sources[0x1a]	48359	1			T5	95		T7	149		T9	1
valid_sources[0x1b]	50964	1			T5	67		T6	2		T7	143
valid_sources[0x1c]	50348	1			T5	92		T7	142		T10	54
valid_sources[0x1d]	43791	1			T3	1		T5	199		T7	135
valid_sources[0x1e]	45037	1			T3	3		T5	9		T7	150
valid_sources[0x1f]	46705	1			T3	31		T5	65		T7	136
valid_sources[0x20]	45239	1			T3	14		T5	71		T6	24
valid_sources[0x21]	48310	1			T5	119		T7	160		T9	1
valid_sources[0x22]	51091	1			T5	110		T6	16		T7	174
valid_sources[0x23]	45510	1			T3	2		T5	50		T7	197
valid_sources[0x24]	48942	1			T3	6		T5	224		T6	1
valid_sources[0x25]	48858	1			T3	1		T5	497		T6	9
valid_sources[0x26]	45774	1			T1	1354		T3	11		T5	81
valid_sources[0x27]	45263	1			T5	232		T7	196		T9	2
valid_sources[0x28]	48897	1			T5	173		T6	1		T7	129
valid_sources[0x29]	46859	1			T5	128		T7	132		T10	38
valid_sources[0x2a]	45504	1			T3	2		T5	279		T6	4
valid_sources[0x2b]	48541	1			T3	5		T5	11		T7	141
valid_sources[0x2c]	47230	1			T5	5		T7	161		T9	3
valid_sources[0x2d]	47164	1			T5	204		T6	25		T7	181
valid_sources[0x2e]	46319	1			T5	502		T6	10		T7	165
valid_sources[0x2f]	45186	1			T5	227		T7	129		T10	70
valid_sources[0x30]	50385	1			T3	6		T5	603		T7	113
valid_sources[0x31]	44185	1			T3	6		T5	45		T7	164
valid_sources[0x32]	46013	1			T3	3		T5	7		T6	1
valid_sources[0x33]	46698	1			T5	48		T6	1		T7	144
valid_sources[0x34]	45322	1			T3	13		T5	8		T7	164
valid_sources[0x35]	47284	1			T3	20		T5	18		T7	170
valid_sources[0x36]	47009	1			T5	211		T6	2		T7	143
valid_sources[0x37]	44307	1			T5	3		T7	165		T9	1
valid_sources[0x38]	45590	1			T3	3		T5	5		T6	16
valid_sources[0x39]	47988	1			T5	17		T6	1		T7	143
valid_sources[0x3a]	47295	1			T5	551		T7	183		T9	1
valid_sources[0x3b]	46856	1			T5	27		T6	10		T7	132
valid_sources[0x3c]	48666	1			T5	52		T7	147		T9	47
valid_sources[0x3d]	44217	1			T3	8		T5	152		T7	167
valid_sources[0x3e]	45443	1			T3	3		T5	52		T7	159
valid_sources[0x3f]	45772	1			T5	122		T7	139		T9	3
valid_sources[0x40]	51097	1			T5	239		T7	148		T9	21
valid_sources[0x41]	44844	1			T5	9		T7	142		T9	1
valid_sources[0x42]	48468	1			T3	6		T5	28		T6	1
valid_sources[0x43]	45557	1			T5	130		T7	146		T9	1
valid_sources[0x44]	46984	1			T5	30		T7	159		T10	56
valid_sources[0x45]	47268	1			T5	47		T7	180		T10	54
valid_sources[0x46]	46252	1			T3	3		T5	15		T7	154
valid_sources[0x47]	50261	1			T3	2		T5	10		T7	143
valid_sources[0x48]	45171	1			T5	40		T7	134		T9	12
valid_sources[0x49]	49044	1			T5	187		T7	152		T10	49
valid_sources[0x4a]	49615	1			T3	4		T5	76		T6	12
valid_sources[0x4b]	44615	1			T3	24		T5	134		T6	2
valid_sources[0x4c]	49037	1			T3	6		T5	97		T7	162
valid_sources[0x4d]	49535	1			T5	475		T7	148		T9	30
valid_sources[0x4e]	45763	1			T3	38		T5	75		T7	121
valid_sources[0x4f]	46384	1			T3	10		T5	169		T7	148
valid_sources[0x50]	44142	1			T5	1235		T7	160		T9	1
valid_sources[0x51]	46631	1			T3	4		T5	3		T6	1
valid_sources[0x52]	45002	1			T3	14		T5	12		T7	154
valid_sources[0x53]	47158	1			T5	145		T6	7		T7	171
valid_sources[0x54]	45922	1			T5	36		T7	133		T9	83
valid_sources[0x55]	45786	1			T5	19		T7	138		T8	1
valid_sources[0x56]	50583	1			T3	4		T5	98		T7	142
valid_sources[0x57]	46033	1			T5	93		T7	142		T10	57
valid_sources[0x58]	43582	1			T3	22		T5	7		T6	3
valid_sources[0x59]	45811	1			T5	61		T6	7		T7	145
valid_sources[0x5a]	46133	1			T3	14		T5	37		T6	7
valid_sources[0x5b]	44259	1			T3	1		T5	98		T7	193
valid_sources[0x5c]	45126	1			T5	1		T6	3		T7	169
valid_sources[0x5d]	44947	1			T5	22		T7	157		T9	48
valid_sources[0x5e]	45691	1			T5	29		T7	152		T10	68
valid_sources[0x5f]	50273	1			T5	909		T6	12		T7	132
valid_sources[0x60]	46213	1			T5	317		T7	173		T9	8
valid_sources[0x61]	48799	1			T5	120		T6	14		T7	179
valid_sources[0x62]	44526	1			T5	119		T7	180		T9	4
valid_sources[0x63]	52222	1			T5	578		T7	197		T9	2
valid_sources[0x64]	44908	1			T3	12		T5	38		T7	152
valid_sources[0x65]	49620	1			T3	11		T5	118		T7	139
valid_sources[0x66]	45215	1			T5	216		T7	144		T9	6
valid_sources[0x67]	45045	1			T5	71		T7	195		T9	1
valid_sources[0x68]	44868	1			T3	6		T5	227		T7	134
valid_sources[0x69]	44793	1			T3	13		T5	22		T7	175
valid_sources[0x6a]	44962	1			T5	47		T6	12		T7	151
valid_sources[0x6b]	45472	1			T3	6		T5	84		T6	5
valid_sources[0x6c]	48781	1			T5	204		T6	10		T7	127
valid_sources[0x6d]	47631	1			T5	84		T6	50		T7	159
valid_sources[0x6e]	43810	1			T5	295		T7	134		T10	52
valid_sources[0x6f]	48444	1			T5	946		T7	175		T10	37
valid_sources[0x70]	47425	1			T3	22		T5	3		T7	171
valid_sources[0x71]	49178	1			T3	4		T5	28		T6	1
valid_sources[0x72]	45141	1			T3	4		T5	48		T7	129
valid_sources[0x73]	49939	1			T5	38		T7	205		T10	49
valid_sources[0x74]	45120	1			T3	1		T5	26		T6	4
valid_sources[0x75]	47757	1			T3	3		T5	42		T6	3
valid_sources[0x76]	45471	1			T5	25		T7	171		T9	1
valid_sources[0x77]	46300	1			T5	22		T6	2		T7	171
valid_sources[0x78]	48508	1			T5	60		T7	158		T10	62
valid_sources[0x79]	46979	1			T5	57		T6	14		T7	141
valid_sources[0x7a]	47441	1			T3	4		T5	48		T7	166
valid_sources[0x7b]	45119	1			T5	232		T7	154		T10	54
valid_sources[0x7c]	44770	1			T5	83		T7	149		T10	53
valid_sources[0x7d]	46230	1			T5	15		T7	147		T9	24
valid_sources[0x7e]	49805	1			T5	47		T6	35		T7	165
valid_sources[0x7f]	48940	1			T5	75		T6	8		T7	166
valid_sources[0x80]	52079	1			T5	63		T6	6		T7	153

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

2344082

1

T1

1

T2

1

T3

1

values[0x0]

all_enables

biggest_size

1946223

1

T1

553

T2

12

T3

440

values[0x1]

all_enables

biggest_size

1916563

1

T1

563

T2

7

T3

437