Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

5839783

1

T1

237

T2

8

T3

3

full_word

6208112

1

T1

1117

T2

20

T3

878

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	12047415	1			T1	1354		T2	28		T3	881
auto[TlIntgErrCmd]	153	1			T47	2		T81	4		T82	9
auto[TlIntgErrData]	177	1			T47	10		T81	5		T82	12
auto[TlIntgErrBoth]	150	1			T47	8		T81	1		T82	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7713514

1

T1

1

T2

1

T3

2

auto[1]

4334381

1

T1

1353

T2

27

T3

879

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	5368971	1			T3	1		T4	1		T5	9118
auto[TlIntgErrNone]	partial	auto[1]	470383	1			T1	237		T2	8		T3	2
auto[TlIntgErrNone]	full_word	auto[0]	2344321	1			T1	1		T2	1		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	3863740	1			T1	1116		T2	19		T3	877
auto[TlIntgErrCmd]	partial	auto[0]	62	1			T81	2		T82	1		T95	4
auto[TlIntgErrCmd]	partial	auto[1]	78	1			T47	1		T81	2		T82	6
auto[TlIntgErrCmd]	full_word	auto[0]	11	1			T47	1		T82	2		T96	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T95	2		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	73	1			T47	5		T81	3		T82	4
auto[TlIntgErrData]	partial	auto[1]	81	1			T47	5		T81	1		T82	6
auto[TlIntgErrData]	full_word	auto[0]	19	1			T81	1		T82	2		T95	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T95	1		T143	1		T144	1
auto[TlIntgErrBoth]	partial	auto[0]	51	1			T47	1		T82	6		T95	3
auto[TlIntgErrBoth]	partial	auto[1]	84	1			T47	6		T81	1		T82	2
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T82	1		T126	1		T145	1
auto[TlIntgErrBoth]	full_word	auto[1]	9	1			T47	1		T95	2		T145	1