Unified Coverage Report :: Module :: prim_generic_ram_1r1w

Module : prim_generic_ram_1r1w

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_ram_1r1w

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	704608520	3624773	0	0
gen_wmask[1].MaskCheckPortA_A	704608520	3624773	0	0
gen_wmask[2].MaskCheckPortA_A	704608520	3624773	0	0
gen_wmask[3].MaskCheckPortA_A	704608520	3624773	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704608520	3624773	0	0
T3	11916	832	0	0
T4	736914	0	0	0
T5	1755896	21395	0	0
T6	29220	832	0	0
T7	447139	9749	0	0
T8	1284	0	0	0
T9	392030	8762	0	0
T10	888017	6782	0	0
T11	39689	832	0	0
T12	34922	832	0	0
T13	5087	832	0	0
T14	23040	832	0	0
T15	0	4241	0	0
T16	2603	0	0	0
T19	0	12059	0	0
T23	0	75	0	0
T24	0	5123	0	0
T25	0	5137	0	0
T26	0	8543	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704608520	3624773	0	0
T3	11916	832	0	0
T4	736914	0	0	0
T5	1755896	21395	0	0
T6	29220	832	0	0
T7	447139	9749	0	0
T8	1284	0	0	0
T9	392030	8762	0	0
T10	888017	6782	0	0
T11	39689	832	0	0
T12	34922	832	0	0
T13	5087	832	0	0
T14	23040	832	0	0
T15	0	4241	0	0
T16	2603	0	0	0
T19	0	12059	0	0
T23	0	75	0	0
T24	0	5123	0	0
T25	0	5137	0	0
T26	0	8543	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704608520	3624773	0	0
T3	11916	832	0	0
T4	736914	0	0	0
T5	1755896	21395	0	0
T6	29220	832	0	0
T7	447139	9749	0	0
T8	1284	0	0	0
T9	392030	8762	0	0
T10	888017	6782	0	0
T11	39689	832	0	0
T12	34922	832	0	0
T13	5087	832	0	0
T14	23040	832	0	0
T15	0	4241	0	0
T16	2603	0	0	0
T19	0	12059	0	0
T23	0	75	0	0
T24	0	5123	0	0
T25	0	5137	0	0
T26	0	8543	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704608520	3624773	0	0
T3	11916	832	0	0
T4	736914	0	0	0
T5	1755896	21395	0	0
T6	29220	832	0	0
T7	447139	9749	0	0
T8	1284	0	0	0
T9	392030	8762	0	0
T10	888017	6782	0	0
T11	39689	832	0	0
T12	34922	832	0	0
T13	5087	832	0	0
T14	23040	832	0	0
T15	0	4241	0	0
T16	2603	0	0	0
T19	0	12059	0	0
T23	0	75	0	0
T24	0	5123	0	0
T25	0	5137	0	0
T26	0	8543	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			==> MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	524299363	2387279	0	0
gen_wmask[1].MaskCheckPortA_A	524299363	2387279	0	0
gen_wmask[2].MaskCheckPortA_A	524299363	2387279	0	0
gen_wmask[3].MaskCheckPortA_A	524299363	2387279	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524299363	2387279	0	0
T3	11916	832	0	0
T4	736914	0	0	0
T5	965802	17717	0	0
T6	27156	832	0	0
T7	167978	3956	0	0
T8	1284	0	0	0
T9	105357	4396	0	0
T10	710655	2321	0	0
T11	23403	832	0	0
T12	0	832	0	0
T13	0	832	0	0
T14	0	832	0	0
T16	2171	0	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524299363	2387279	0	0
T3	11916	832	0	0
T4	736914	0	0	0
T5	965802	17717	0	0
T6	27156	832	0	0
T7	167978	3956	0	0
T8	1284	0	0	0
T9	105357	4396	0	0
T10	710655	2321	0	0
T11	23403	832	0	0
T12	0	832	0	0
T13	0	832	0	0
T14	0	832	0	0
T16	2171	0	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524299363	2387279	0	0
T3	11916	832	0	0
T4	736914	0	0	0
T5	965802	17717	0	0
T6	27156	832	0	0
T7	167978	3956	0	0
T8	1284	0	0	0
T9	105357	4396	0	0
T10	710655	2321	0	0
T11	23403	832	0	0
T12	0	832	0	0
T13	0	832	0	0
T14	0	832	0	0
T16	2171	0	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524299363	2387279	0	0
T3	11916	832	0	0
T4	736914	0	0	0
T5	965802	17717	0	0
T6	27156	832	0	0
T7	167978	3956	0	0
T8	1284	0	0	0
T9	105357	4396	0	0
T10	710655	2321	0	0
T11	23403	832	0	0
T12	0	832	0	0
T13	0	832	0	0
T14	0	832	0	0
T16	2171	0	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	180309157	1237494	0	0
gen_wmask[1].MaskCheckPortA_A	180309157	1237494	0	0
gen_wmask[2].MaskCheckPortA_A	180309157	1237494	0	0
gen_wmask[3].MaskCheckPortA_A	180309157	1237494	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180309157	1237494	0	0
T5	790094	3678	0	0
T6	2064	0	0	0
T7	279161	5793	0	0
T9	286673	4366	0	0
T10	177362	4461	0	0
T11	16286	0	0	0
T12	34922	0	0	0
T13	5087	0	0	0
T14	23040	0	0	0
T15	0	4241	0	0
T16	432	0	0	0
T19	0	12059	0	0
T23	0	75	0	0
T24	0	5123	0	0
T25	0	5137	0	0
T26	0	8543	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180309157	1237494	0	0
T5	790094	3678	0	0
T6	2064	0	0	0
T7	279161	5793	0	0
T9	286673	4366	0	0
T10	177362	4461	0	0
T11	16286	0	0	0
T12	34922	0	0	0
T13	5087	0	0	0
T14	23040	0	0	0
T15	0	4241	0	0
T16	432	0	0	0
T19	0	12059	0	0
T23	0	75	0	0
T24	0	5123	0	0
T25	0	5137	0	0
T26	0	8543	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180309157	1237494	0	0
T5	790094	3678	0	0
T6	2064	0	0	0
T7	279161	5793	0	0
T9	286673	4366	0	0
T10	177362	4461	0	0
T11	16286	0	0	0
T12	34922	0	0	0
T13	5087	0	0	0
T14	23040	0	0	0
T15	0	4241	0	0
T16	432	0	0	0
T19	0	12059	0	0
T23	0	75	0	0
T24	0	5123	0	0
T25	0	5137	0	0
T26	0	8543	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180309157	1237494	0	0
T5	790094	3678	0	0
T6	2064	0	0	0
T7	279161	5793	0	0
T9	286673	4366	0	0
T10	177362	4461	0	0
T11	16286	0	0	0
T12	34922	0	0	0
T13	5087	0	0	0
T14	23040	0	0	0
T15	0	4241	0	0
T16	432	0	0	0
T19	0	12059	0	0
T23	0	75	0	0
T24	0	5123	0	0
T25	0	5137	0	0
T26	0	8543	0	0