Unified Coverage Report :: Module :: prim_pulse_sync

Module : prim_pulse_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_flash_readbuf_watermark_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_flash_readbuf_flip_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_upload.u_payloadptr_clr_psync	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.69	94.25	84.31	96.94		87.50	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.69	94.25	84.31	96.94		87.50	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_upload.u_payloadptr_clr_psync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.37	100.00	86.11		100.00	95.74	100.00	u_upload

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T9
1	0	Covered	T5,T7,T9
1	1	Covered	T5,T7,T9

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T9
1	0	Covered	T5,T7,T9
1	1	Covered	T5,T7,T9

---

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1572898089	3350	0	0
SrcPulseCheck_M	540927471	3350	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1572898089	3350	0	0
T5	965802	21	0	0
T6	27156	0	0	0
T7	167978	2	0	0
T8	1284	0	0	0
T9	105357	9	0	0
T10	710655	0	0	0
T11	70209	7	0	0
T12	641565	0	0	0
T13	75532	0	0	0
T14	145456	0	0	0
T15	769884	13	0	0
T16	2171	0	0	0
T17	328292	0	0	0
T18	2598	0	0	0
T19	1368884	29	0	0
T23	3886	0	0	0
T24	0	5	0	0
T25	0	4	0	0
T26	0	18	0	0
T32	1266644	0	0	0
T33	0	19	0	0
T34	0	7	0	0
T35	0	2	0	0
T36	0	15	0	0
T117	0	7	0	0
T118	0	8	0	0
T119	0	4	0	0
T120	0	7	0	0
T121	0	7	0	0
T122	0	7	0	0
T123	0	7	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	540927471	3350	0	0
T5	790094	21	0	0
T6	2064	0	0	0
T7	279161	2	0	0
T9	286673	9	0	0
T10	177362	0	0	0
T11	48858	7	0	0
T12	104766	0	0	0
T13	15261	0	0	0
T14	69120	0	0	0
T15	1267144	13	0	0
T16	432	0	0	0
T17	285324	0	0	0
T19	279478	29	0	0
T23	4432	0	0	0
T24	445398	5	0	0
T25	0	4	0	0
T26	0	18	0	0
T32	210060	0	0	0
T33	0	19	0	0
T34	0	7	0	0
T35	0	2	0	0
T36	0	15	0	0
T117	0	7	0	0
T118	0	8	0	0
T119	0	4	0	0
T120	0	7	0	0
T121	0	7	0	0
T122	0	7	0	0
T123	0	7	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T33,T34
1	0	Covered	T11,T33,T34
1	1	Covered	T11,T33,T34

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T33,T34
1	0	Covered	T11,T33,T34
1	1	Covered	T11,T33,T34

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	524299363	410	0	0
SrcPulseCheck_M	180309157	410	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524299363	410	0	0
T11	23403	2	0	0
T12	213855	0	0	0
T13	37766	0	0	0
T14	72728	0	0	0
T15	384942	0	0	0
T17	164146	0	0	0
T18	866	0	0	0
T19	684442	0	0	0
T23	1943	0	0	0
T32	633322	0	0	0
T33	0	10	0	0
T34	0	2	0	0
T117	0	2	0	0
T118	0	4	0	0
T119	0	2	0	0
T120	0	2	0	0
T121	0	2	0	0
T122	0	2	0	0
T123	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	180309157	410	0	0
T11	16286	2	0	0
T12	34922	0	0	0
T13	5087	0	0	0
T14	23040	0	0	0
T15	633572	0	0	0
T17	142662	0	0	0
T19	139739	0	0	0
T23	2216	0	0	0
T24	222699	0	0	0
T32	105030	0	0	0
T33	0	10	0	0
T34	0	2	0	0
T117	0	2	0	0
T118	0	4	0	0
T119	0	2	0	0
T120	0	2	0	0
T121	0	2	0	0
T122	0	2	0	0
T123	0	2	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T33,T34
1	0	Covered	T11,T33,T34
1	1	Covered	T11,T33,T34

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T33,T34
1	0	Covered	T11,T33,T34
1	1	Covered	T11,T33,T34

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	524299363	591	0	0
SrcPulseCheck_M	180309157	591	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524299363	591	0	0
T11	23403	5	0	0
T12	213855	0	0	0
T13	37766	0	0	0
T14	72728	0	0	0
T15	384942	0	0	0
T17	164146	0	0	0
T18	866	0	0	0
T19	684442	0	0	0
T23	1943	0	0	0
T32	633322	0	0	0
T33	0	9	0	0
T34	0	5	0	0
T117	0	5	0	0
T118	0	4	0	0
T119	0	2	0	0
T120	0	5	0	0
T121	0	5	0	0
T122	0	5	0	0
T123	0	5	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	180309157	591	0	0
T11	16286	5	0	0
T12	34922	0	0	0
T13	5087	0	0	0
T14	23040	0	0	0
T15	633572	0	0	0
T17	142662	0	0	0
T19	139739	0	0	0
T23	2216	0	0	0
T24	222699	0	0	0
T32	105030	0	0	0
T33	0	9	0	0
T34	0	5	0	0
T117	0	5	0	0
T118	0	4	0	0
T119	0	2	0	0
T120	0	5	0	0
T121	0	5	0	0
T122	0	5	0	0
T123	0	5	0	0

Line Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T9
1	0	Covered	T5,T7,T9
1	1	Covered	T5,T7,T9

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T9
1	0	Covered	T5,T7,T9
1	1	Covered	T5,T7,T9

---

Branch Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	524299363	2349	0	0
SrcPulseCheck_M	180309157	2349	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524299363	2349	0	0
T5	965802	21	0	0
T6	27156	0	0	0
T7	167978	2	0	0
T8	1284	0	0	0
T9	105357	9	0	0
T10	710655	0	0	0
T11	23403	0	0	0
T12	213855	0	0	0
T15	0	13	0	0
T16	2171	0	0	0
T18	866	0	0	0
T19	0	29	0	0
T24	0	5	0	0
T25	0	4	0	0
T26	0	18	0	0
T35	0	2	0	0
T36	0	15	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	180309157	2349	0	0
T5	790094	21	0	0
T6	2064	0	0	0
T7	279161	2	0	0
T9	286673	9	0	0
T10	177362	0	0	0
T11	16286	0	0	0
T12	34922	0	0	0
T13	5087	0	0	0
T14	23040	0	0	0
T15	0	13	0	0
T16	432	0	0	0
T19	0	29	0	0
T24	0	5	0	0
T25	0	4	0	0
T26	0	18	0	0
T35	0	2	0	0
T36	0	15	0	0