Unified Coverage Report :: Module Instance :: tb.dut.u_readcmd.u_readsram.u_sram_fifo

Module Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.18	100.00	72.73			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.33	95.00	75.00			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.77	98.25	100.00		100.00	90.62	100.00	u_readsram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Module Instance : tb.dut.u_readcmd.u_readsram.u_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.45	100.00	81.82			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	100.00	87.50			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.77	98.25	100.00		100.00	90.62	100.00	u_readsram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
62.10	85.71	31.25			71.43	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.62	84.62	42.31			55.56	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	63.15	84.00	60.00			45.45

Module Instance : tb.dut.u_spi_tpm.u_sram_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.32	100.00	77.27			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.11	95.00	78.12			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.66	99.29	91.20		91.67	96.13	100.00	u_spi_tpm

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Module Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.06	100.00	56.25			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.96	100.00	65.38			94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	90.30	100.00	80.00			90.91

Module Instance : tb.dut.u_tlul2sram_egress.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.85	95.00	73.08			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
78.16	94.03	62.07			70.83	85.71	u_tlul2sram_egress

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Module Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.67	80.00	31.25			71.43	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.09	82.50	42.31			55.56	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
78.16	94.03	62.07			70.83	85.71	u_tlul2sram_egress

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	63.15	84.00	60.00			45.45

Module Instance : tb.dut.u_tlul2sram_egress.u_rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
61.67	86.67	33.33			66.67	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.29	85.00	41.18			55.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
78.16	94.03	62.07			70.83	85.71	u_tlul2sram_egress

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	63.15	84.00	60.00			45.45

Module Instance : tb.dut.u_tlul2sram_ingress.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.85	95.00	73.08			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.44	94.03	72.41			83.33	100.00	u_tlul2sram_ingress

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Line Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

	Total	Covered	Percent
Conditions	22	16	72.73
Logical	22	16	72.73
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T5,T6

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T6
1	0	Not Covered
1	1	Covered	T3,T5,T7

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T5,T6
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T3,T5,T7

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T3,T5,T7
1	1	0	Not Covered
1	1	1	Covered	T3,T5,T7

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T7

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T5,T7

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T7
1	0	Covered	T3,T5,T7
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	130	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T5,T6
0	0	Covered	T3,T5,T6

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	180309157	27357553	0	0
DepthKnown_A	180309157	138980773	0	0
RvalidKnown_A	180309157	138980773	0	0
WreadyKnown_A	180309157	138980773	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	180309157	27357553	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180309157	27357553	0	0
T3	4228	3978	0	0
T4	135291	0	0	0
T5	790094	61949	0	0
T6	2064	0	0	0
T7	279161	11347	0	0
T9	286673	25909	0	0
T10	177362	0	0	0
T11	16286	15036	0	0
T12	34922	6846	0	0
T14	0	4100	0	0
T15	0	139959	0	0
T16	432	0	0	0
T19	0	230000	0	0
T32	0	9936	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180309157	138980773	0	0
T3	4228	4228	0	0
T4	135291	0	0	0
T5	790094	646730	0	0
T6	2064	2064	0	0
T7	279161	109275	0	0
T9	286673	194857	0	0
T10	177362	0	0	0
T11	16286	16286	0	0
T12	34922	34670	0	0
T13	0	4576	0	0
T14	0	23040	0	0
T15	0	609785	0	0
T16	432	0	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180309157	138980773	0	0
T3	4228	4228	0	0
T4	135291	0	0	0
T5	790094	646730	0	0
T6	2064	2064	0	0
T7	279161	109275	0	0
T9	286673	194857	0	0
T10	177362	0	0	0
T11	16286	16286	0	0
T12	34922	34670	0	0
T13	0	4576	0	0
T14	0	23040	0	0
T15	0	609785	0	0
T16	432	0	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180309157	138980773	0	0
T3	4228	4228	0	0
T4	135291	0	0	0
T5	790094	646730	0	0
T6	2064	2064	0	0
T7	279161	109275	0	0
T9	286673	194857	0	0
T10	177362	0	0	0
T11	16286	16286	0	0
T12	34922	34670	0	0
T13	0	4576	0	0
T14	0	23040	0	0
T15	0	609785	0	0
T16	432	0	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	180309157	27357553	0	0
T3	4228	3978	0	0
T4	135291	0	0	0
T5	790094	61949	0	0
T6	2064	0	0	0
T7	279161	11347	0	0
T9	286673	25909	0	0
T10	177362	0	0	0
T11	16286	15036	0	0
T12	34922	6846	0	0
T14	0	4100	0	0
T15	0	139959	0	0
T16	432	0	0	0
T19	0	230000	0	0
T32	0	9936	0	0

Line Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo

	Total	Covered	Percent
Conditions	22	18	81.82
Logical	22	18	81.82
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T5,T6

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T6
1	0	Not Covered
1	1	Covered	T3,T5,T7

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T5,T6
1	0	1	Covered	T3,T5,T7
1	1	0	Not Covered
1	1	1	Covered	T3,T5,T7

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T3,T5,T7
1	1	0	Not Covered
1	1	1	Covered	T3,T5,T7

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T7

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T5,T7

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T7
1	0	Covered	T3,T5,T7
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	130	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T5,T6
0	0	Covered	T3,T5,T6

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	180309157	28749465	0	0
DepthKnown_A	180309157	138980773	0	0
RvalidKnown_A	180309157	138980773	0	0
WreadyKnown_A	180309157	138980773	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	180309157	28749465	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180309157	28749465	0	0
T3	4228	4100	0	0
T4	135291	0	0	0
T5	790094	64355	0	0
T6	2064	0	0	0
T7	279161	12396	0	0
T9	286673	26876	0	0
T10	177362	0	0	0
T11	16286	15990	0	0
T12	34922	7414	0	0
T14	0	4224	0	0
T15	0	148154	0	0
T16	432	0	0	0
T19	0	242482	0	0
T32	0	10246	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180309157	138980773	0	0
T3	4228	4228	0	0
T4	135291	0	0	0
T5	790094	646730	0	0
T6	2064	2064	0	0
T7	279161	109275	0	0
T9	286673	194857	0	0
T10	177362	0	0	0
T11	16286	16286	0	0
T12	34922	34670	0	0
T13	0	4576	0	0
T14	0	23040	0	0
T15	0	609785	0	0
T16	432	0	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180309157	138980773	0	0
T3	4228	4228	0	0
T4	135291	0	0	0
T5	790094	646730	0	0
T6	2064	2064	0	0
T7	279161	109275	0	0
T9	286673	194857	0	0
T10	177362	0	0	0
T11	16286	16286	0	0
T12	34922	34670	0	0
T13	0	4576	0	0
T14	0	23040	0	0
T15	0	609785	0	0
T16	432	0	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180309157	138980773	0	0
T3	4228	4228	0	0
T4	135291	0	0	0
T5	790094	646730	0	0
T6	2064	2064	0	0
T7	279161	109275	0	0
T9	286673	194857	0	0
T10	177362	0	0	0
T11	16286	16286	0	0
T12	34922	34670	0	0
T13	0	4576	0	0
T14	0	23040	0	0
T15	0	609785	0	0
T16	432	0	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	180309157	28749465	0	0
T3	4228	4100	0	0
T4	135291	0	0	0
T5	790094	64355	0	0
T6	2064	0	0	0
T7	279161	12396	0	0
T9	286673	26876	0	0
T10	177362	0	0	0
T11	16286	15990	0	0
T12	34922	7414	0	0
T14	0	4224	0	0
T15	0	148154	0	0
T16	432	0	0	0
T19	0	242482	0	0
T32	0	10246	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	12	85.71
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	1	50.00
CONT_ASSIGN	133	1	0	0.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	0	1
			MISSING_ELSE
133	0	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

	Total	Covered	Percent
Conditions	16	5	31.25
Logical	16	5	31.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T5,T6

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T6
1	0	Not Covered
1	1	Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T5,T6
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
Branches		7	5	71.43
TERNARY	138	2	1	50.00
IF	69	3	3	100.00
IF	123	2	1	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T5,T6
0	0	Covered	T3,T5,T6

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	3	60.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	3	60.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	180309157	0	0	0
DepthKnown_A	180309157	138980773	0	0
RvalidKnown_A	180309157	138980773	0	0
WreadyKnown_A	180309157	138980773	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	180309157	0	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180309157	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180309157	138980773	0	0
T3	4228	4228	0	0
T4	135291	0	0	0
T5	790094	646730	0	0
T6	2064	2064	0	0
T7	279161	109275	0	0
T9	286673	194857	0	0
T10	177362	0	0	0
T11	16286	16286	0	0
T12	34922	34670	0	0
T13	0	4576	0	0
T14	0	23040	0	0
T15	0	609785	0	0
T16	432	0	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180309157	138980773	0	0
T3	4228	4228	0	0
T4	135291	0	0	0
T5	790094	646730	0	0
T6	2064	2064	0	0
T7	279161	109275	0	0
T9	286673	194857	0	0
T10	177362	0	0	0
T11	16286	16286	0	0
T12	34922	34670	0	0
T13	0	4576	0	0
T14	0	23040	0	0
T15	0	609785	0	0
T16	432	0	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180309157	138980773	0	0
T3	4228	4228	0	0
T4	135291	0	0	0
T5	790094	646730	0	0
T6	2064	2064	0	0
T7	279161	109275	0	0
T9	286673	194857	0	0
T10	177362	0	0	0
T11	16286	16286	0	0
T12	34922	34670	0	0
T13	0	4576	0	0
T14	0	23040	0	0
T15	0	609785	0	0
T16	432	0	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	180309157	0	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo

	Total	Covered	Percent
Conditions	22	17	77.27
Logical	22	17	77.27
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Not Covered
1	1	Covered	T5,T7,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T5,T7,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T7,T9
1	0	1	Covered	T5,T7,T9
1	1	0	Not Covered
1	1	1	Covered	T5,T7,T9

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T9

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T7,T9

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T9
1	0	Covered	T5,T7,T9
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	130	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	180309157	8397410	0	0
DepthKnown_A	180309157	39554651	0	0
RvalidKnown_A	180309157	39554651	0	0
WreadyKnown_A	180309157	39554651	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	180309157	8397410	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180309157	8397410	0	0
T5	790094	33339	0	0
T6	2064	0	0	0
T7	279161	71546	0	0
T9	286673	7250	0	0
T10	177362	72082	0	0
T11	16286	0	0	0
T12	34922	0	0	0
T13	5087	0	0	0
T14	23040	0	0	0
T15	0	6527	0	0
T16	432	0	0	0
T19	0	93602	0	0
T23	0	409	0	0
T24	0	69080	0	0
T25	0	65044	0	0
T26	0	37294	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180309157	39554651	0	0
T1	130638	122888	0	0
T2	7248	7248	0	0
T3	4228	0	0	0
T4	135291	125336	0	0
T5	790094	133528	0	0
T6	2064	0	0	0
T7	279161	162880	0	0
T9	286673	89976	0	0
T10	177362	170024	0	0
T15	0	21080	0	0
T16	432	432	0	0
T17	0	135576	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180309157	39554651	0	0
T1	130638	122888	0	0
T2	7248	7248	0	0
T3	4228	0	0	0
T4	135291	125336	0	0
T5	790094	133528	0	0
T6	2064	0	0	0
T7	279161	162880	0	0
T9	286673	89976	0	0
T10	177362	170024	0	0
T15	0	21080	0	0
T16	432	432	0	0
T17	0	135576	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180309157	39554651	0	0
T1	130638	122888	0	0
T2	7248	7248	0	0
T3	4228	0	0	0
T4	135291	125336	0	0
T5	790094	133528	0	0
T6	2064	0	0	0
T7	279161	162880	0	0
T9	286673	89976	0	0
T10	177362	170024	0	0
T15	0	21080	0	0
T16	432	432	0	0
T17	0	135576	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	180309157	8397410	0	0
T5	790094	33339	0	0
T6	2064	0	0	0
T7	279161	71546	0	0
T9	286673	7250	0	0
T10	177362	72082	0	0
T11	16286	0	0	0
T12	34922	0	0	0
T13	5087	0	0	0
T14	23040	0	0	0
T15	0	6527	0	0
T16	432	0	0	0
T19	0	93602	0	0
T23	0	409	0	0
T24	0	69080	0	0
T25	0	65044	0	0
T26	0	37294	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

	Total	Covered	Percent
Conditions	16	9	56.25
Logical	16	9	56.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Not Covered
1	1	Covered	T5,T7,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T5,T7,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T5,T7,T9

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T5,T7,T9
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T7,T9

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	180309157	269903	0	0
DepthKnown_A	180309157	39554651	0	0
RvalidKnown_A	180309157	39554651	0	0
WreadyKnown_A	180309157	39554651	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	180309157	269903	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180309157	269903	0	0
T5	790094	1077	0	0
T6	2064	0	0	0
T7	279161	2292	0	0
T9	286673	236	0	0
T10	177362	2321	0	0
T11	16286	0	0	0
T12	34922	0	0	0
T13	5087	0	0	0
T14	23040	0	0	0
T15	0	214	0	0
T16	432	0	0	0
T19	0	3016	0	0
T23	0	14	0	0
T24	0	2220	0	0
T25	0	2098	0	0
T26	0	1196	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180309157	39554651	0	0
T1	130638	122888	0	0
T2	7248	7248	0	0
T3	4228	0	0	0
T4	135291	125336	0	0
T5	790094	133528	0	0
T6	2064	0	0	0
T7	279161	162880	0	0
T9	286673	89976	0	0
T10	177362	170024	0	0
T15	0	21080	0	0
T16	432	432	0	0
T17	0	135576	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180309157	39554651	0	0
T1	130638	122888	0	0
T2	7248	7248	0	0
T3	4228	0	0	0
T4	135291	125336	0	0
T5	790094	133528	0	0
T6	2064	0	0	0
T7	279161	162880	0	0
T9	286673	89976	0	0
T10	177362	170024	0	0
T15	0	21080	0	0
T16	432	432	0	0
T17	0	135576	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180309157	39554651	0	0
T1	130638	122888	0	0
T2	7248	7248	0	0
T3	4228	0	0	0
T4	135291	125336	0	0
T5	790094	133528	0	0
T6	2064	0	0	0
T7	279161	162880	0	0
T9	286673	89976	0	0
T10	177362	170024	0	0
T15	0	21080	0	0
T16	432	432	0	0
T17	0	135576	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	180309157	269903	0	0
T5	790094	1077	0	0
T6	2064	0	0	0
T7	279161	2292	0	0
T9	286673	236	0	0
T10	177362	2321	0	0
T11	16286	0	0	0
T12	34922	0	0	0
T13	5087	0	0	0
T14	23040	0	0	0
T15	0	214	0	0
T16	432	0	0	0
T19	0	3016	0	0
T23	0	14	0	0
T24	0	2220	0	0
T25	0	2098	0	0
T26	0	1196	0	0

Line Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T5,T6

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T3,T5,T6

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T3,T5,T6
1	1	0	Not Covered
1	1	1	Covered	T3,T5,T6

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T3,T5,T6
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	524299363	3437918	0	0
DepthKnown_A	524299363	524214495	0	0
RvalidKnown_A	524299363	524214495	0	0
WreadyKnown_A	524299363	524214495	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	524299363	3437918	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524299363	3437918	0	0
T3	11916	832	0	0
T4	736914	0	0	0
T5	965802	50042	0	0
T6	27156	3733	0	0
T7	167978	1664	0	0
T8	1284	0	0	0
T9	105357	4160	0	0
T10	710655	0	0	0
T11	23403	832	0	0
T12	0	832	0	0
T13	0	832	0	0
T14	0	832	0	0
T15	0	13447	0	0
T16	2171	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524299363	524214495	0	0
T1	579186	579130	0	0
T2	3400	3305	0	0
T3	11916	11823	0	0
T4	736914	736845	0	0
T5	965802	965731	0	0
T6	27156	27073	0	0
T7	167978	167970	0	0
T8	1284	1206	0	0
T9	105357	105266	0	0
T10	710655	710558	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524299363	524214495	0	0
T1	579186	579130	0	0
T2	3400	3305	0	0
T3	11916	11823	0	0
T4	736914	736845	0	0
T5	965802	965731	0	0
T6	27156	27073	0	0
T7	167978	167970	0	0
T8	1284	1206	0	0
T9	105357	105266	0	0
T10	710655	710558	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524299363	524214495	0	0
T1	579186	579130	0	0
T2	3400	3305	0	0
T3	11916	11823	0	0
T4	736914	736845	0	0
T5	965802	965731	0	0
T6	27156	27073	0	0
T7	167978	167970	0	0
T8	1284	1206	0	0
T9	105357	105266	0	0
T10	710655	710558	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	524299363	3437918	0	0
T3	11916	832	0	0
T4	736914	0	0	0
T5	965802	50042	0	0
T6	27156	3733	0	0
T7	167978	1664	0	0
T8	1284	0	0	0
T9	105357	4160	0	0
T10	710655	0	0	0
T11	23403	832	0	0
T12	0	832	0	0
T13	0	832	0	0
T14	0	832	0	0
T15	0	13447	0	0
T16	2171	0	0	0

Line Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	12	80.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	0	0.00
ALWAYS	111	2	1	50.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	0	0.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	0	1
111	1	1
112	0	1
			MISSING_ELSE
116	1	1
133	0	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo

	Total	Covered	Percent
Conditions	16	5	31.25
Logical	16	5	31.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	5	71.43
TERNARY	138	2	1	50.00
IF	69	3	3	100.00
IF	123	2	1	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	3	60.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	3	60.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	524299363	0	0	0
DepthKnown_A	524299363	524214495	0	0
RvalidKnown_A	524299363	524214495	0	0
WreadyKnown_A	524299363	524214495	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	524299363	0	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524299363	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524299363	524214495	0	0
T1	579186	579130	0	0
T2	3400	3305	0	0
T3	11916	11823	0	0
T4	736914	736845	0	0
T5	965802	965731	0	0
T6	27156	27073	0	0
T7	167978	167970	0	0
T8	1284	1206	0	0
T9	105357	105266	0	0
T10	710655	710558	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524299363	524214495	0	0
T1	579186	579130	0	0
T2	3400	3305	0	0
T3	11916	11823	0	0
T4	736914	736845	0	0
T5	965802	965731	0	0
T6	27156	27073	0	0
T7	167978	167970	0	0
T8	1284	1206	0	0
T9	105357	105266	0	0
T10	710655	710558	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524299363	524214495	0	0
T1	579186	579130	0	0
T2	3400	3305	0	0
T3	11916	11823	0	0
T4	736914	736845	0	0
T5	965802	965731	0	0
T6	27156	27073	0	0
T7	167978	167970	0	0
T8	1284	1206	0	0
T9	105357	105266	0	0
T10	710655	710558	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	524299363	0	0	0

Line Coverage for Instance : tb.dut.u_tlul2sram_egress.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	13	86.67
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	0	0.00
ALWAYS	111	2	1	50.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	0	1
111	1	1
112	0	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul2sram_egress.u_rspfifo

	Total	Covered	Percent
Conditions	24	8	33.33
Logical	24	8	33.33
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul2sram_egress.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	6	66.67
TERNARY	130	2	1	50.00
TERNARY	138	2	1	50.00
IF	69	3	3	100.00
IF	111	2	1	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul2sram_egress.u_rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	3	60.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	3	60.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	524299363	0	0	0
DepthKnown_A	524299363	524214495	0	0
RvalidKnown_A	524299363	524214495	0	0
WreadyKnown_A	524299363	524214495	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	524299363	0	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524299363	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524299363	524214495	0	0
T1	579186	579130	0	0
T2	3400	3305	0	0
T3	11916	11823	0	0
T4	736914	736845	0	0
T5	965802	965731	0	0
T6	27156	27073	0	0
T7	167978	167970	0	0
T8	1284	1206	0	0
T9	105357	105266	0	0
T10	710655	710558	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524299363	524214495	0	0
T1	579186	579130	0	0
T2	3400	3305	0	0
T3	11916	11823	0	0
T4	736914	736845	0	0
T5	965802	965731	0	0
T6	27156	27073	0	0
T7	167978	167970	0	0
T8	1284	1206	0	0
T9	105357	105266	0	0
T10	710655	710558	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524299363	524214495	0	0
T1	579186	579130	0	0
T2	3400	3305	0	0
T3	11916	11823	0	0
T4	736914	736845	0	0
T5	965802	965731	0	0
T6	27156	27073	0	0
T7	167978	167970	0	0
T8	1284	1206	0	0
T9	105357	105266	0	0
T10	710655	710558	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	524299363	0	0	0

Line Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T5,T7,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T5,T7,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T5,T15,T19
1	1	0	Not Covered
1	1	1	Covered	T5,T7,T9

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T5,T7,T9
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T7,T9

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	524299363	467475	0	0
DepthKnown_A	524299363	524214495	0	0
RvalidKnown_A	524299363	524214495	0	0
WreadyKnown_A	524299363	524214495	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	524299363	467475	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524299363	467475	0	0
T5	965802	3768	0	0
T6	27156	0	0	0
T7	167978	1494	0	0
T8	1284	0	0	0
T9	105357	471	0	0
T10	710655	1150	0	0
T11	23403	0	0	0
T12	213855	0	0	0
T15	0	1486	0	0
T16	2171	0	0	0
T18	866	0	0	0
T19	0	9821	0	0
T23	0	82	0	0
T24	0	1307	0	0
T25	0	3738	0	0
T26	0	5621	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524299363	524214495	0	0
T1	579186	579130	0	0
T2	3400	3305	0	0
T3	11916	11823	0	0
T4	736914	736845	0	0
T5	965802	965731	0	0
T6	27156	27073	0	0
T7	167978	167970	0	0
T8	1284	1206	0	0
T9	105357	105266	0	0
T10	710655	710558	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524299363	524214495	0	0
T1	579186	579130	0	0
T2	3400	3305	0	0
T3	11916	11823	0	0
T4	736914	736845	0	0
T5	965802	965731	0	0
T6	27156	27073	0	0
T7	167978	167970	0	0
T8	1284	1206	0	0
T9	105357	105266	0	0
T10	710655	710558	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524299363	524214495	0	0
T1	579186	579130	0	0
T2	3400	3305	0	0
T3	11916	11823	0	0
T4	736914	736845	0	0
T5	965802	965731	0	0
T6	27156	27073	0	0
T7	167978	167970	0	0
T8	1284	1206	0	0
T9	105357	105266	0	0
T10	710655	710558	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	524299363	467475	0	0
T5	965802	3768	0	0
T6	27156	0	0	0
T7	167978	1494	0	0
T8	1284	0	0	0
T9	105357	471	0	0
T10	710655	1150	0	0
T11	23403	0	0	0
T12	213855	0	0	0
T15	0	1486	0	0
T16	2171	0	0	0
T18	866	0	0	0
T19	0	9821	0	0
T23	0	82	0	0
T24	0	1307	0	0
T25	0	3738	0	0
T26	0	5621	0	0