Unified Coverage Report :: Module Instance :: tb.dut.u_tlul2sram_ingress.u_sramreqfifo

Module Instance : tb.dut.u_tlul2sram_ingress.u_sramreqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.62	100.00	62.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.89	95.00	69.23			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.44	94.03	72.41			83.33	100.00	u_tlul2sram_ingress

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Module Instance : tb.dut.u_tlul2sram_ingress.u_rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.12	95.00	76.47			85.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.44	94.03	72.41			83.33	100.00	u_tlul2sram_ingress

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Module Instance : tb.dut.u_sys_sram_arbiter.u_req_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.06	100.00	56.25			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.96	100.00	65.38			94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	90.30	100.00	80.00			90.91

Module Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_sramreqfifo

	Total	Covered	Percent
Conditions	16	10	62.50
Logical	16	10	62.50
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T5,T7,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T5,T7,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T5,T7,T9

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T5,T7,T9
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T7,T9

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	524299363	205712	0	0
DepthKnown_A	524299363	524214495	0	0
RvalidKnown_A	524299363	524214495	0	0
WreadyKnown_A	524299363	524214495	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	524299363	205712	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524299363	205712	0	0
T5	965802	859	0	0
T6	27156	0	0	0
T7	167978	1494	0	0
T8	1284	0	0	0
T9	105357	471	0	0
T10	710655	1150	0	0
T11	23403	0	0	0
T12	213855	0	0	0
T15	0	484	0	0
T16	2171	0	0	0
T18	866	0	0	0
T19	0	2160	0	0
T23	0	19	0	0
T24	0	1307	0	0
T25	0	1200	0	0
T26	0	1235	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524299363	524214495	0	0
T1	579186	579130	0	0
T2	3400	3305	0	0
T3	11916	11823	0	0
T4	736914	736845	0	0
T5	965802	965731	0	0
T6	27156	27073	0	0
T7	167978	167970	0	0
T8	1284	1206	0	0
T9	105357	105266	0	0
T10	710655	710558	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524299363	524214495	0	0
T1	579186	579130	0	0
T2	3400	3305	0	0
T3	11916	11823	0	0
T4	736914	736845	0	0
T5	965802	965731	0	0
T6	27156	27073	0	0
T7	167978	167970	0	0
T8	1284	1206	0	0
T9	105357	105266	0	0
T10	710655	710558	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524299363	524214495	0	0
T1	579186	579130	0	0
T2	3400	3305	0	0
T3	11916	11823	0	0
T4	736914	736845	0	0
T5	965802	965731	0	0
T6	27156	27073	0	0
T7	167978	167970	0	0
T8	1284	1206	0	0
T9	105357	105266	0	0
T10	710655	710558	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	524299363	205712	0	0
T5	965802	859	0	0
T6	27156	0	0	0
T7	167978	1494	0	0
T8	1284	0	0	0
T9	105357	471	0	0
T10	710655	1150	0	0
T11	23403	0	0	0
T12	213855	0	0	0
T15	0	484	0	0
T16	2171	0	0	0
T18	866	0	0	0
T19	0	2160	0	0
T23	0	19	0	0
T24	0	1307	0	0
T25	0	1200	0	0
T26	0	1235	0	0

Line Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_rspfifo

	Total	Covered	Percent
Conditions	24	18	75.00
Logical	24	18	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T15,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T5,T7,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T5,T7,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T5,T15,T19
1	1	0	Not Covered
1	1	1	Covered	T5,T7,T9

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T9

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T7,T9

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T5,T15,T19
1	0	Covered	T5,T7,T9
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T5,T7,T9
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T7,T9

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	524299363	467475	0	0
DepthKnown_A	524299363	524214495	0	0
RvalidKnown_A	524299363	524214495	0	0
WreadyKnown_A	524299363	524214495	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	524299363	467475	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524299363	467475	0	0
T5	965802	3768	0	0
T6	27156	0	0	0
T7	167978	1494	0	0
T8	1284	0	0	0
T9	105357	471	0	0
T10	710655	1150	0	0
T11	23403	0	0	0
T12	213855	0	0	0
T15	0	1486	0	0
T16	2171	0	0	0
T18	866	0	0	0
T19	0	9821	0	0
T23	0	82	0	0
T24	0	1307	0	0
T25	0	3738	0	0
T26	0	5621	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524299363	524214495	0	0
T1	579186	579130	0	0
T2	3400	3305	0	0
T3	11916	11823	0	0
T4	736914	736845	0	0
T5	965802	965731	0	0
T6	27156	27073	0	0
T7	167978	167970	0	0
T8	1284	1206	0	0
T9	105357	105266	0	0
T10	710655	710558	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524299363	524214495	0	0
T1	579186	579130	0	0
T2	3400	3305	0	0
T3	11916	11823	0	0
T4	736914	736845	0	0
T5	965802	965731	0	0
T6	27156	27073	0	0
T7	167978	167970	0	0
T8	1284	1206	0	0
T9	105357	105266	0	0
T10	710655	710558	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524299363	524214495	0	0
T1	579186	579130	0	0
T2	3400	3305	0	0
T3	11916	11823	0	0
T4	736914	736845	0	0
T5	965802	965731	0	0
T6	27156	27073	0	0
T7	167978	167970	0	0
T8	1284	1206	0	0
T9	105357	105266	0	0
T10	710655	710558	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	524299363	467475	0	0
T5	965802	3768	0	0
T6	27156	0	0	0
T7	167978	1494	0	0
T8	1284	0	0	0
T9	105357	471	0	0
T10	710655	1150	0	0
T11	23403	0	0	0
T12	213855	0	0	0
T15	0	1486	0	0
T16	2171	0	0	0
T18	866	0	0	0
T19	0	9821	0	0
T23	0	82	0	0
T24	0	1307	0	0
T25	0	3738	0	0
T26	0	5621	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.u_req_fifo

	Total	Covered	Percent
Conditions	16	9	56.25
Logical	16	9	56.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T5,T7,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T5,T7,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T5,T7,T9

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T5,T7,T9
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T7,T9

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.u_req_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	524299363	209820	0	0
DepthKnown_A	524299363	524214495	0	0
RvalidKnown_A	524299363	524214495	0	0
WreadyKnown_A	524299363	524214495	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	524299363	209820	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524299363	209820	0	0
T5	965802	897	0	0
T6	27156	0	0	0
T7	167978	1498	0	0
T8	1284	0	0	0
T9	105357	489	0	0
T10	710655	1150	0	0
T11	23403	0	0	0
T12	213855	0	0	0
T15	0	503	0	0
T16	2171	0	0	0
T18	866	0	0	0
T19	0	2212	0	0
T23	0	19	0	0
T24	0	1316	0	0
T25	0	1208	0	0
T26	0	1264	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524299363	524214495	0	0
T1	579186	579130	0	0
T2	3400	3305	0	0
T3	11916	11823	0	0
T4	736914	736845	0	0
T5	965802	965731	0	0
T6	27156	27073	0	0
T7	167978	167970	0	0
T8	1284	1206	0	0
T9	105357	105266	0	0
T10	710655	710558	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524299363	524214495	0	0
T1	579186	579130	0	0
T2	3400	3305	0	0
T3	11916	11823	0	0
T4	736914	736845	0	0
T5	965802	965731	0	0
T6	27156	27073	0	0
T7	167978	167970	0	0
T8	1284	1206	0	0
T9	105357	105266	0	0
T10	710655	710558	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524299363	524214495	0	0
T1	579186	579130	0	0
T2	3400	3305	0	0
T3	11916	11823	0	0
T4	736914	736845	0	0
T5	965802	965731	0	0
T6	27156	27073	0	0
T7	167978	167970	0	0
T8	1284	1206	0	0
T9	105357	105266	0	0
T10	710655	710558	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	524299363	209820	0	0
T5	965802	897	0	0
T6	27156	0	0	0
T7	167978	1498	0	0
T8	1284	0	0	0
T9	105357	489	0	0
T10	710655	1150	0	0
T11	23403	0	0	0
T12	213855	0	0	0
T15	0	503	0	0
T16	2171	0	0	0
T18	866	0	0	0
T19	0	2212	0	0
T23	0	19	0	0
T24	0	1316	0	0
T25	0	1208	0	0
T26	0	1264	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	526759775	14093053	0	0
DepthKnown_A	526759775	526623925	0	0
RvalidKnown_A	526759775	526623925	0	0
WreadyKnown_A	526759775	526623925	0	0
gen_passthru_fifo.paramCheckPass	1096	1096	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	14093053	0	0
T1	579186	1354	0	0
T2	3400	28	0	0
T3	11916	1712	0	0
T4	736914	1453	0	0
T5	965802	54326	0	0
T6	27156	879	0	0
T7	167978	40659	0	0
T8	1284	1	0	0
T9	105357	10018	0	0
T10	710655	14863	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	526623925	0	0
T1	579186	579130	0	0
T2	3400	3305	0	0
T3	11916	11823	0	0
T4	736914	736845	0	0
T5	965802	965731	0	0
T6	27156	27073	0	0
T7	167978	167970	0	0
T8	1284	1206	0	0
T9	105357	105266	0	0
T10	710655	710558	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	526623925	0	0
T1	579186	579130	0	0
T2	3400	3305	0	0
T3	11916	11823	0	0
T4	736914	736845	0	0
T5	965802	965731	0	0
T6	27156	27073	0	0
T7	167978	167970	0	0
T8	1284	1206	0	0
T9	105357	105266	0	0
T10	710655	710558	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	526623925	0	0
T1	579186	579130	0	0
T2	3400	3305	0	0
T3	11916	11823	0	0
T4	736914	736845	0	0
T5	965802	965731	0	0
T6	27156	27073	0	0
T7	167978	167970	0	0
T8	1284	1206	0	0
T9	105357	105266	0	0
T10	710655	710558	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1096	1096	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	526759775	27007026	0	0
DepthKnown_A	526759775	526623925	0	0
RvalidKnown_A	526759775	526623925	0	0
WreadyKnown_A	526759775	526623925	0	0
gen_passthru_fifo.paramCheckPass	1096	1096	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	27007026	0	0
T1	579186	6004	0	0
T2	3400	117	0	0
T3	11916	992	0	0
T4	736914	4507	0	0
T5	965802	138531	0	0
T6	27156	3966	0	0
T7	167978	39619	0	0
T8	1284	1	0	0
T9	105357	7366	0	0
T10	710655	14837	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	526623925	0	0
T1	579186	579130	0	0
T2	3400	3305	0	0
T3	11916	11823	0	0
T4	736914	736845	0	0
T5	965802	965731	0	0
T6	27156	27073	0	0
T7	167978	167970	0	0
T8	1284	1206	0	0
T9	105357	105266	0	0
T10	710655	710558	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	526623925	0	0
T1	579186	579130	0	0
T2	3400	3305	0	0
T3	11916	11823	0	0
T4	736914	736845	0	0
T5	965802	965731	0	0
T6	27156	27073	0	0
T7	167978	167970	0	0
T8	1284	1206	0	0
T9	105357	105266	0	0
T10	710655	710558	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	526623925	0	0
T1	579186	579130	0	0
T2	3400	3305	0	0
T3	11916	11823	0	0
T4	736914	736845	0	0
T5	965802	965731	0	0
T6	27156	27073	0	0
T7	167978	167970	0	0
T8	1284	1206	0	0
T9	105357	105266	0	0
T10	710655	710558	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1096	1096	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	526759775	3235839	0	0
DepthKnown_A	526759775	526623925	0	0
RvalidKnown_A	526759775	526623925	0	0
WreadyKnown_A	526759775	526623925	0	0
gen_passthru_fifo.paramCheckPass	1096	1096	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	3235839	0	0
T3	11916	1663	0	0
T4	736914	0	0	0
T5	965802	24138	0	0
T6	27156	832	0	0
T7	167978	2495	0	0
T8	1284	0	0	0
T9	105357	6653	0	0
T10	710655	0	0	0
T11	23403	832	0	0
T12	0	1663	0	0
T13	0	1663	0	0
T14	0	1663	0	0
T15	0	14141	0	0
T16	2171	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	526623925	0	0
T1	579186	579130	0	0
T2	3400	3305	0	0
T3	11916	11823	0	0
T4	736914	736845	0	0
T5	965802	965731	0	0
T6	27156	27073	0	0
T7	167978	167970	0	0
T8	1284	1206	0	0
T9	105357	105266	0	0
T10	710655	710558	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	526623925	0	0
T1	579186	579130	0	0
T2	3400	3305	0	0
T3	11916	11823	0	0
T4	736914	736845	0	0
T5	965802	965731	0	0
T6	27156	27073	0	0
T7	167978	167970	0	0
T8	1284	1206	0	0
T9	105357	105266	0	0
T10	710655	710558	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	526623925	0	0
T1	579186	579130	0	0
T2	3400	3305	0	0
T3	11916	11823	0	0
T4	736914	736845	0	0
T5	965802	965731	0	0
T6	27156	27073	0	0
T7	167978	167970	0	0
T8	1284	1206	0	0
T9	105357	105266	0	0
T10	710655	710558	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1096	1096	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	526759775	3468791	0	0
DepthKnown_A	526759775	526623925	0	0
RvalidKnown_A	526759775	526623925	0	0
WreadyKnown_A	526759775	526623925	0	0
gen_passthru_fifo.paramCheckPass	1096	1096	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	3468791	0	0
T3	11916	832	0	0
T4	736914	0	0	0
T5	965802	50042	0	0
T6	27156	3733	0	0
T7	167978	1664	0	0
T8	1284	0	0	0
T9	105357	4160	0	0
T10	710655	0	0	0
T11	23403	832	0	0
T12	0	832	0	0
T13	0	832	0	0
T14	0	832	0	0
T15	0	13447	0	0
T16	2171	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	526623925	0	0
T1	579186	579130	0	0
T2	3400	3305	0	0
T3	11916	11823	0	0
T4	736914	736845	0	0
T5	965802	965731	0	0
T6	27156	27073	0	0
T7	167978	167970	0	0
T8	1284	1206	0	0
T9	105357	105266	0	0
T10	710655	710558	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	526623925	0	0
T1	579186	579130	0	0
T2	3400	3305	0	0
T3	11916	11823	0	0
T4	736914	736845	0	0
T5	965802	965731	0	0
T6	27156	27073	0	0
T7	167978	167970	0	0
T8	1284	1206	0	0
T9	105357	105266	0	0
T10	710655	710558	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	526623925	0	0
T1	579186	579130	0	0
T2	3400	3305	0	0
T3	11916	11823	0	0
T4	736914	736845	0	0
T5	965802	965731	0	0
T6	27156	27073	0	0
T7	167978	167970	0	0
T8	1284	1206	0	0
T9	105357	105266	0	0
T10	710655	710558	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1096	1096	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	526759775	212670	0	0
DepthKnown_A	526759775	526623925	0	0
RvalidKnown_A	526759775	526623925	0	0
WreadyKnown_A	526759775	526623925	0	0
gen_passthru_fifo.paramCheckPass	1096	1096	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	212670	0	0
T5	965802	859	0	0
T6	27156	0	0	0
T7	167978	1495	0	0
T8	1284	0	0	0
T9	105357	471	0	0
T10	710655	1150	0	0
T11	23403	0	0	0
T12	213855	0	0	0
T15	0	484	0	0
T16	2171	0	0	0
T18	866	0	0	0
T19	0	2160	0	0
T23	0	19	0	0
T24	0	1307	0	0
T25	0	1200	0	0
T26	0	1235	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	526623925	0	0
T1	579186	579130	0	0
T2	3400	3305	0	0
T3	11916	11823	0	0
T4	736914	736845	0	0
T5	965802	965731	0	0
T6	27156	27073	0	0
T7	167978	167970	0	0
T8	1284	1206	0	0
T9	105357	105266	0	0
T10	710655	710558	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	526623925	0	0
T1	579186	579130	0	0
T2	3400	3305	0	0
T3	11916	11823	0	0
T4	736914	736845	0	0
T5	965802	965731	0	0
T6	27156	27073	0	0
T7	167978	167970	0	0
T8	1284	1206	0	0
T9	105357	105266	0	0
T10	710655	710558	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	526623925	0	0
T1	579186	579130	0	0
T2	3400	3305	0	0
T3	11916	11823	0	0
T4	736914	736845	0	0
T5	965802	965731	0	0
T6	27156	27073	0	0
T7	167978	167970	0	0
T8	1284	1206	0	0
T9	105357	105266	0	0
T10	710655	710558	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1096	1096	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	526759775	477442	0	0
DepthKnown_A	526759775	526623925	0	0
RvalidKnown_A	526759775	526623925	0	0
WreadyKnown_A	526759775	526623925	0	0
gen_passthru_fifo.paramCheckPass	1096	1096	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	477442	0	0
T5	965802	3768	0	0
T6	27156	0	0	0
T7	167978	1494	0	0
T8	1284	0	0	0
T9	105357	471	0	0
T10	710655	1150	0	0
T11	23403	0	0	0
T12	213855	0	0	0
T15	0	1486	0	0
T16	2171	0	0	0
T18	866	0	0	0
T19	0	9821	0	0
T23	0	82	0	0
T24	0	1307	0	0
T25	0	3738	0	0
T26	0	5621	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	526623925	0	0
T1	579186	579130	0	0
T2	3400	3305	0	0
T3	11916	11823	0	0
T4	736914	736845	0	0
T5	965802	965731	0	0
T6	27156	27073	0	0
T7	167978	167970	0	0
T8	1284	1206	0	0
T9	105357	105266	0	0
T10	710655	710558	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	526623925	0	0
T1	579186	579130	0	0
T2	3400	3305	0	0
T3	11916	11823	0	0
T4	736914	736845	0	0
T5	965802	965731	0	0
T6	27156	27073	0	0
T7	167978	167970	0	0
T8	1284	1206	0	0
T9	105357	105266	0	0
T10	710655	710558	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	526623925	0	0
T1	579186	579130	0	0
T2	3400	3305	0	0
T3	11916	11823	0	0
T4	736914	736845	0	0
T5	965802	965731	0	0
T6	27156	27073	0	0
T7	167978	167970	0	0
T8	1284	1206	0	0
T9	105357	105266	0	0
T10	710655	710558	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1096	1096	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0