Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	526759775	10356644	0	0
DepthKnown_A	526759775	526623925	0	0
RvalidKnown_A	526759775	526623925	0	0
WreadyKnown_A	526759775	526623925	0	0
gen_passthru_fifo.paramCheckPass	1096	1096	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	10356644	0	0
T1	579186	1354	0	0
T2	3400	28	0	0
T3	11916	49	0	0
T4	736914	1453	0	0
T5	965802	21865	0	0
T6	27156	47	0	0
T7	167978	36624	0	0
T8	1284	1	0	0
T9	105357	2805	0	0
T10	710655	13709	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	526623925	0	0
T1	579186	579130	0	0
T2	3400	3305	0	0
T3	11916	11823	0	0
T4	736914	736845	0	0
T5	965802	965731	0	0
T6	27156	27073	0	0
T7	167978	167970	0	0
T8	1284	1206	0	0
T9	105357	105266	0	0
T10	710655	710558	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	526623925	0	0
T1	579186	579130	0	0
T2	3400	3305	0	0
T3	11916	11823	0	0
T4	736914	736845	0	0
T5	965802	965731	0	0
T6	27156	27073	0	0
T7	167978	167970	0	0
T8	1284	1206	0	0
T9	105357	105266	0	0
T10	710655	710558	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	526623925	0	0
T1	579186	579130	0	0
T2	3400	3305	0	0
T3	11916	11823	0	0
T4	736914	736845	0	0
T5	965802	965731	0	0
T6	27156	27073	0	0
T7	167978	167970	0	0
T8	1284	1206	0	0
T9	105357	105266	0	0
T10	710655	710558	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1096	1096	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	526759775	23060793	0	0
DepthKnown_A	526759775	526623925	0	0
RvalidKnown_A	526759775	526623925	0	0
WreadyKnown_A	526759775	526623925	0	0
gen_passthru_fifo.paramCheckPass	1096	1096	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	23060793	0	0
T1	579186	6004	0	0
T2	3400	117	0	0
T3	11916	160	0	0
T4	736914	4507	0	0
T5	965802	84721	0	0
T6	27156	233	0	0
T7	167978	36461	0	0
T8	1284	1	0	0
T9	105357	2735	0	0
T10	710655	13687	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	526623925	0	0
T1	579186	579130	0	0
T2	3400	3305	0	0
T3	11916	11823	0	0
T4	736914	736845	0	0
T5	965802	965731	0	0
T6	27156	27073	0	0
T7	167978	167970	0	0
T8	1284	1206	0	0
T9	105357	105266	0	0
T10	710655	710558	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	526623925	0	0
T1	579186	579130	0	0
T2	3400	3305	0	0
T3	11916	11823	0	0
T4	736914	736845	0	0
T5	965802	965731	0	0
T6	27156	27073	0	0
T7	167978	167970	0	0
T8	1284	1206	0	0
T9	105357	105266	0	0
T10	710655	710558	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	526623925	0	0
T1	579186	579130	0	0
T2	3400	3305	0	0
T3	11916	11823	0	0
T4	736914	736845	0	0
T5	965802	965731	0	0
T6	27156	27073	0	0
T7	167978	167970	0	0
T8	1284	1206	0	0
T9	105357	105266	0	0
T10	710655	710558	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1096	1096	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0