Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T9
1	0	Covered	T5,T7,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T5,T7,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T9
1	0	Covered	T5,T7,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T6
1	0	Unreachable
1	1	Covered	T5,T7,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T9
1	0	Covered	T3,T5,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T3,T5,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T5,T6
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	884917677	702749919	0	0
CheckNGreaterZero_A	2766	2766	0	0
GntImpliesReady_A	884917677	4129839	0	0
GntImpliesValid_A	884917677	4129839	0	0
GrantKnown_A	884917677	702749919	0	0
IdxKnown_A	884917677	702749919	0	0
IndexIsCorrect_A	884917677	4129839	0	0
LockArbDecision_A	884917677	0	0	0
NoReadyValidNoGrant_A	884917677	0	0	0
ReadyAndValidImplyGrant_A	884917677	4129839	0	0
ReqAndReadyImplyGrant_A	884917677	4129839	0	0
ReqImpliesValid_A	884917677	4129839	0	0
ReqStaysHighUntilGranted0_M	884917677	0	0	0
RoundRobin_A	884917677	7	0	922
ValidKnown_A	884917677	702749919	0	0
gen_data_port_assertion.DataFlow_A	884917677	4129839	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	884917677	702749919	0	0
T1	709824	702018	0	0
T2	10648	10553	0	0
T3	20372	16051	0	0
T4	1007496	862181	0	0
T5	2545990	1745989	0	0
T6	31284	29137	0	0
T7	726300	440125	0	0
T8	1284	1206	0	0
T9	678703	390099	0	0
T10	1065379	880582	0	0
T11	16286	16286	0	0
T12	34922	34670	0	0
T13	0	4576	0	0
T14	0	23040	0	0
T15	0	630865	0	0
T16	864	432	0	0
T17	0	135576	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2766	2766	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	884917677	4129839	0	0
T3	11916	832	0	0
T4	736914	0	0	0
T5	2545990	23457	0	0
T6	31284	832	0	0
T7	726300	13773	0	0
T8	1284	0	0	0
T9	678703	9505	0	0
T10	1065379	10474	0	0
T11	55975	832	0	0
T12	69844	832	0	0
T13	10174	832	0	0
T14	46080	832	0	0
T15	0	4474	0	0
T16	3035	0	0	0
T19	0	15337	0	0
T23	0	90	0	0
T24	0	7539	0	0
T25	0	7413	0	0
T26	0	9849	0	0
T35	0	4	0	0
T36	0	1647	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	884917677	4129839	0	0
T3	11916	832	0	0
T4	736914	0	0	0
T5	2545990	23457	0	0
T6	31284	832	0	0
T7	726300	13773	0	0
T8	1284	0	0	0
T9	678703	9505	0	0
T10	1065379	10474	0	0
T11	55975	832	0	0
T12	69844	832	0	0
T13	10174	832	0	0
T14	46080	832	0	0
T15	0	4474	0	0
T16	3035	0	0	0
T19	0	15337	0	0
T23	0	90	0	0
T24	0	7539	0	0
T25	0	7413	0	0
T26	0	9849	0	0
T35	0	4	0	0
T36	0	1647	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	884917677	702749919	0	0
T1	709824	702018	0	0
T2	10648	10553	0	0
T3	20372	16051	0	0
T4	1007496	862181	0	0
T5	2545990	1745989	0	0
T6	31284	29137	0	0
T7	726300	440125	0	0
T8	1284	1206	0	0
T9	678703	390099	0	0
T10	1065379	880582	0	0
T11	16286	16286	0	0
T12	34922	34670	0	0
T13	0	4576	0	0
T14	0	23040	0	0
T15	0	630865	0	0
T16	864	432	0	0
T17	0	135576	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	884917677	702749919	0	0
T1	709824	702018	0	0
T2	10648	10553	0	0
T3	20372	16051	0	0
T4	1007496	862181	0	0
T5	2545990	1745989	0	0
T6	31284	29137	0	0
T7	726300	440125	0	0
T8	1284	1206	0	0
T9	678703	390099	0	0
T10	1065379	880582	0	0
T11	16286	16286	0	0
T12	34922	34670	0	0
T13	0	4576	0	0
T14	0	23040	0	0
T15	0	630865	0	0
T16	864	432	0	0
T17	0	135576	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	884917677	4129839	0	0
T3	11916	832	0	0
T4	736914	0	0	0
T5	2545990	23457	0	0
T6	31284	832	0	0
T7	726300	13773	0	0
T8	1284	0	0	0
T9	678703	9505	0	0
T10	1065379	10474	0	0
T11	55975	832	0	0
T12	69844	832	0	0
T13	10174	832	0	0
T14	46080	832	0	0
T15	0	4474	0	0
T16	3035	0	0	0
T19	0	15337	0	0
T23	0	90	0	0
T24	0	7539	0	0
T25	0	7413	0	0
T26	0	9849	0	0
T35	0	4	0	0
T36	0	1647	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	884917677	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	884917677	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	884917677	4129839	0	0
T3	11916	832	0	0
T4	736914	0	0	0
T5	2545990	23457	0	0
T6	31284	832	0	0
T7	726300	13773	0	0
T8	1284	0	0	0
T9	678703	9505	0	0
T10	1065379	10474	0	0
T11	55975	832	0	0
T12	69844	832	0	0
T13	10174	832	0	0
T14	46080	832	0	0
T15	0	4474	0	0
T16	3035	0	0	0
T19	0	15337	0	0
T23	0	90	0	0
T24	0	7539	0	0
T25	0	7413	0	0
T26	0	9849	0	0
T35	0	4	0	0
T36	0	1647	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	884917677	4129839	0	0
T3	11916	832	0	0
T4	736914	0	0	0
T5	2545990	23457	0	0
T6	31284	832	0	0
T7	726300	13773	0	0
T8	1284	0	0	0
T9	678703	9505	0	0
T10	1065379	10474	0	0
T11	55975	832	0	0
T12	69844	832	0	0
T13	10174	832	0	0
T14	46080	832	0	0
T15	0	4474	0	0
T16	3035	0	0	0
T19	0	15337	0	0
T23	0	90	0	0
T24	0	7539	0	0
T25	0	7413	0	0
T26	0	9849	0	0
T35	0	4	0	0
T36	0	1647	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	884917677	4129839	0	0
T3	11916	832	0	0
T4	736914	0	0	0
T5	2545990	23457	0	0
T6	31284	832	0	0
T7	726300	13773	0	0
T8	1284	0	0	0
T9	678703	9505	0	0
T10	1065379	10474	0	0
T11	55975	832	0	0
T12	69844	832	0	0
T13	10174	832	0	0
T14	46080	832	0	0
T15	0	4474	0	0
T16	3035	0	0	0
T19	0	15337	0	0
T23	0	90	0	0
T24	0	7539	0	0
T25	0	7413	0	0
T26	0	9849	0	0
T35	0	4	0	0
T36	0	1647	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	884917677	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	884917677	7	0	922
T19	684442	1	0	1
T23	1943	0	0	1
T24	132609	0	0	1
T25	300499	0	0	1
T30	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	1386	0	0	1
T42	1023	0	0	1
T43	9922	0	0	1
T44	3514	0	0	1
T45	40205	0	0	1
T46	42862	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	884917677	702749919	0	0
T1	709824	702018	0	0
T2	10648	10553	0	0
T3	20372	16051	0	0
T4	1007496	862181	0	0
T5	2545990	1745989	0	0
T6	31284	29137	0	0
T7	726300	440125	0	0
T8	1284	1206	0	0
T9	678703	390099	0	0
T10	1065379	880582	0	0
T11	16286	16286	0	0
T12	34922	34670	0	0
T13	0	4576	0	0
T14	0	23040	0	0
T15	0	630865	0	0
T16	864	432	0	0
T17	0	135576	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	884917677	4129839	0	0
T3	11916	832	0	0
T4	736914	0	0	0
T5	2545990	23457	0	0
T6	31284	832	0	0
T7	726300	13773	0	0
T8	1284	0	0	0
T9	678703	9505	0	0
T10	1065379	10474	0	0
T11	55975	832	0	0
T12	69844	832	0	0
T13	10174	832	0	0
T14	46080	832	0	0
T15	0	4474	0	0
T16	3035	0	0	0
T19	0	15337	0	0
T23	0	90	0	0
T24	0	7539	0	0
T25	0	7413	0	0
T26	0	9849	0	0
T35	0	4	0	0
T36	0	1647	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T9
1	0	Covered	T5,T7,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T5,T7,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T7,T9
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	180309157	39554651	0	0
CheckNGreaterZero_A	922	922	0	0
GntImpliesReady_A	180309157	886301	0	0
GntImpliesValid_A	180309157	886301	0	0
GrantKnown_A	180309157	39554651	0	0
IdxKnown_A	180309157	39554651	0	0
IndexIsCorrect_A	180309157	886301	0	0
LockArbDecision_A	180309157	0	0	0
NoReadyValidNoGrant_A	180309157	0	0	0
ReadyAndValidImplyGrant_A	180309157	886301	0	0
ReqAndReadyImplyGrant_A	180309157	886301	0	0
ReqImpliesValid_A	180309157	886301	0	0
ReqStaysHighUntilGranted0_M	180309157	0	0	0
RoundRobin_A	180309157	0	0	0
ValidKnown_A	180309157	39554651	0	0
gen_data_port_assertion.DataFlow_A	180309157	886301	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180309157	39554651	0	0
T1	130638	122888	0	0
T2	7248	7248	0	0
T3	4228	0	0	0
T4	135291	125336	0	0
T5	790094	133528	0	0
T6	2064	0	0	0
T7	279161	162880	0	0
T9	286673	89976	0	0
T10	177362	170024	0	0
T15	0	21080	0	0
T16	432	432	0	0
T17	0	135576	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	922	922	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180309157	886301	0	0
T5	790094	3125	0	0
T6	2064	0	0	0
T7	279161	7803	0	0
T9	286673	835	0	0
T10	177362	7003	0	0
T11	16286	0	0	0
T12	34922	0	0	0
T13	5087	0	0	0
T14	23040	0	0	0
T15	0	995	0	0
T16	432	0	0	0
T19	0	8665	0	0
T23	0	90	0	0
T24	0	6506	0	0
T25	0	6696	0	0
T26	0	4817	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180309157	886301	0	0
T5	790094	3125	0	0
T6	2064	0	0	0
T7	279161	7803	0	0
T9	286673	835	0	0
T10	177362	7003	0	0
T11	16286	0	0	0
T12	34922	0	0	0
T13	5087	0	0	0
T14	23040	0	0	0
T15	0	995	0	0
T16	432	0	0	0
T19	0	8665	0	0
T23	0	90	0	0
T24	0	6506	0	0
T25	0	6696	0	0
T26	0	4817	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180309157	39554651	0	0
T1	130638	122888	0	0
T2	7248	7248	0	0
T3	4228	0	0	0
T4	135291	125336	0	0
T5	790094	133528	0	0
T6	2064	0	0	0
T7	279161	162880	0	0
T9	286673	89976	0	0
T10	177362	170024	0	0
T15	0	21080	0	0
T16	432	432	0	0
T17	0	135576	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180309157	39554651	0	0
T1	130638	122888	0	0
T2	7248	7248	0	0
T3	4228	0	0	0
T4	135291	125336	0	0
T5	790094	133528	0	0
T6	2064	0	0	0
T7	279161	162880	0	0
T9	286673	89976	0	0
T10	177362	170024	0	0
T15	0	21080	0	0
T16	432	432	0	0
T17	0	135576	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180309157	886301	0	0
T5	790094	3125	0	0
T6	2064	0	0	0
T7	279161	7803	0	0
T9	286673	835	0	0
T10	177362	7003	0	0
T11	16286	0	0	0
T12	34922	0	0	0
T13	5087	0	0	0
T14	23040	0	0	0
T15	0	995	0	0
T16	432	0	0	0
T19	0	8665	0	0
T23	0	90	0	0
T24	0	6506	0	0
T25	0	6696	0	0
T26	0	4817	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180309157	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180309157	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180309157	886301	0	0
T5	790094	3125	0	0
T6	2064	0	0	0
T7	279161	7803	0	0
T9	286673	835	0	0
T10	177362	7003	0	0
T11	16286	0	0	0
T12	34922	0	0	0
T13	5087	0	0	0
T14	23040	0	0	0
T15	0	995	0	0
T16	432	0	0	0
T19	0	8665	0	0
T23	0	90	0	0
T24	0	6506	0	0
T25	0	6696	0	0
T26	0	4817	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180309157	886301	0	0
T5	790094	3125	0	0
T6	2064	0	0	0
T7	279161	7803	0	0
T9	286673	835	0	0
T10	177362	7003	0	0
T11	16286	0	0	0
T12	34922	0	0	0
T13	5087	0	0	0
T14	23040	0	0	0
T15	0	995	0	0
T16	432	0	0	0
T19	0	8665	0	0
T23	0	90	0	0
T24	0	6506	0	0
T25	0	6696	0	0
T26	0	4817	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180309157	886301	0	0
T5	790094	3125	0	0
T6	2064	0	0	0
T7	279161	7803	0	0
T9	286673	835	0	0
T10	177362	7003	0	0
T11	16286	0	0	0
T12	34922	0	0	0
T13	5087	0	0	0
T14	23040	0	0	0
T15	0	995	0	0
T16	432	0	0	0
T19	0	8665	0	0
T23	0	90	0	0
T24	0	6506	0	0
T25	0	6696	0	0
T26	0	4817	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	180309157	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180309157	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180309157	39554651	0	0
T1	130638	122888	0	0
T2	7248	7248	0	0
T3	4228	0	0	0
T4	135291	125336	0	0
T5	790094	133528	0	0
T6	2064	0	0	0
T7	279161	162880	0	0
T9	286673	89976	0	0
T10	177362	170024	0	0
T15	0	21080	0	0
T16	432	432	0	0
T17	0	135576	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180309157	886301	0	0
T5	790094	3125	0	0
T6	2064	0	0	0
T7	279161	7803	0	0
T9	286673	835	0	0
T10	177362	7003	0	0
T11	16286	0	0	0
T12	34922	0	0	0
T13	5087	0	0	0
T14	23040	0	0	0
T15	0	995	0	0
T16	432	0	0	0
T19	0	8665	0	0
T23	0	90	0	0
T24	0	6506	0	0
T25	0	6696	0	0
T26	0	4817	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T9
1	0	Covered	T5,T7,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T6
1	0	Unreachable
1	1	Covered	T5,T7,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T7,T9
0	0	1	Unreachable
0	0	0	Covered	T3,T5,T6

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	180309157	138980773	0	0
CheckNGreaterZero_A	922	922	0	0
GntImpliesReady_A	180309157	646439	0	0
GntImpliesValid_A	180309157	646439	0	0
GrantKnown_A	180309157	138980773	0	0
IdxKnown_A	180309157	138980773	0	0
IndexIsCorrect_A	180309157	646439	0	0
LockArbDecision_A	180309157	0	0	0
NoReadyValidNoGrant_A	180309157	0	0	0
ReadyAndValidImplyGrant_A	180309157	646439	0	0
ReqAndReadyImplyGrant_A	180309157	646439	0	0
ReqImpliesValid_A	180309157	646439	0	0
ReqStaysHighUntilGranted0_M	180309157	0	0	0
RoundRobin_A	180309157	0	0	0
ValidKnown_A	180309157	138980773	0	0
gen_data_port_assertion.DataFlow_A	180309157	646439	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180309157	138980773	0	0
T3	4228	4228	0	0
T4	135291	0	0	0
T5	790094	646730	0	0
T6	2064	2064	0	0
T7	279161	109275	0	0
T9	286673	194857	0	0
T10	177362	0	0	0
T11	16286	16286	0	0
T12	34922	34670	0	0
T13	0	4576	0	0
T14	0	23040	0	0
T15	0	609785	0	0
T16	432	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	922	922	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180309157	646439	0	0
T5	790094	1718	0	0
T6	2064	0	0	0
T7	279161	516	0	0
T9	286673	3785	0	0
T10	177362	0	0	0
T11	16286	0	0	0
T12	34922	0	0	0
T13	5087	0	0	0
T14	23040	0	0	0
T15	0	3479	0	0
T16	432	0	0	0
T19	0	6672	0	0
T24	0	1033	0	0
T25	0	717	0	0
T26	0	5032	0	0
T35	0	4	0	0
T36	0	1647	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180309157	646439	0	0
T5	790094	1718	0	0
T6	2064	0	0	0
T7	279161	516	0	0
T9	286673	3785	0	0
T10	177362	0	0	0
T11	16286	0	0	0
T12	34922	0	0	0
T13	5087	0	0	0
T14	23040	0	0	0
T15	0	3479	0	0
T16	432	0	0	0
T19	0	6672	0	0
T24	0	1033	0	0
T25	0	717	0	0
T26	0	5032	0	0
T35	0	4	0	0
T36	0	1647	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180309157	138980773	0	0
T3	4228	4228	0	0
T4	135291	0	0	0
T5	790094	646730	0	0
T6	2064	2064	0	0
T7	279161	109275	0	0
T9	286673	194857	0	0
T10	177362	0	0	0
T11	16286	16286	0	0
T12	34922	34670	0	0
T13	0	4576	0	0
T14	0	23040	0	0
T15	0	609785	0	0
T16	432	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180309157	138980773	0	0
T3	4228	4228	0	0
T4	135291	0	0	0
T5	790094	646730	0	0
T6	2064	2064	0	0
T7	279161	109275	0	0
T9	286673	194857	0	0
T10	177362	0	0	0
T11	16286	16286	0	0
T12	34922	34670	0	0
T13	0	4576	0	0
T14	0	23040	0	0
T15	0	609785	0	0
T16	432	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180309157	646439	0	0
T5	790094	1718	0	0
T6	2064	0	0	0
T7	279161	516	0	0
T9	286673	3785	0	0
T10	177362	0	0	0
T11	16286	0	0	0
T12	34922	0	0	0
T13	5087	0	0	0
T14	23040	0	0	0
T15	0	3479	0	0
T16	432	0	0	0
T19	0	6672	0	0
T24	0	1033	0	0
T25	0	717	0	0
T26	0	5032	0	0
T35	0	4	0	0
T36	0	1647	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180309157	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180309157	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180309157	646439	0	0
T5	790094	1718	0	0
T6	2064	0	0	0
T7	279161	516	0	0
T9	286673	3785	0	0
T10	177362	0	0	0
T11	16286	0	0	0
T12	34922	0	0	0
T13	5087	0	0	0
T14	23040	0	0	0
T15	0	3479	0	0
T16	432	0	0	0
T19	0	6672	0	0
T24	0	1033	0	0
T25	0	717	0	0
T26	0	5032	0	0
T35	0	4	0	0
T36	0	1647	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180309157	646439	0	0
T5	790094	1718	0	0
T6	2064	0	0	0
T7	279161	516	0	0
T9	286673	3785	0	0
T10	177362	0	0	0
T11	16286	0	0	0
T12	34922	0	0	0
T13	5087	0	0	0
T14	23040	0	0	0
T15	0	3479	0	0
T16	432	0	0	0
T19	0	6672	0	0
T24	0	1033	0	0
T25	0	717	0	0
T26	0	5032	0	0
T35	0	4	0	0
T36	0	1647	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180309157	646439	0	0
T5	790094	1718	0	0
T6	2064	0	0	0
T7	279161	516	0	0
T9	286673	3785	0	0
T10	177362	0	0	0
T11	16286	0	0	0
T12	34922	0	0	0
T13	5087	0	0	0
T14	23040	0	0	0
T15	0	3479	0	0
T16	432	0	0	0
T19	0	6672	0	0
T24	0	1033	0	0
T25	0	717	0	0
T26	0	5032	0	0
T35	0	4	0	0
T36	0	1647	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	180309157	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180309157	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180309157	138980773	0	0
T3	4228	4228	0	0
T4	135291	0	0	0
T5	790094	646730	0	0
T6	2064	2064	0	0
T7	279161	109275	0	0
T9	286673	194857	0	0
T10	177362	0	0	0
T11	16286	16286	0	0
T12	34922	34670	0	0
T13	0	4576	0	0
T14	0	23040	0	0
T15	0	609785	0	0
T16	432	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180309157	646439	0	0
T5	790094	1718	0	0
T6	2064	0	0	0
T7	279161	516	0	0
T9	286673	3785	0	0
T10	177362	0	0	0
T11	16286	0	0	0
T12	34922	0	0	0
T13	5087	0	0	0
T14	23040	0	0	0
T15	0	3479	0	0
T16	432	0	0	0
T19	0	6672	0	0
T24	0	1033	0	0
T25	0	717	0	0
T26	0	5032	0	0
T35	0	4	0	0
T36	0	1647	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T9
1	0	Covered	T3,T5,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T3,T5,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T5,T6
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	524299363	524214495	0	0
CheckNGreaterZero_A	922	922	0	0
GntImpliesReady_A	524299363	2597099	0	0
GntImpliesValid_A	524299363	2597099	0	0
GrantKnown_A	524299363	524214495	0	0
IdxKnown_A	524299363	524214495	0	0
IndexIsCorrect_A	524299363	2597099	0	0
LockArbDecision_A	524299363	0	0	0
NoReadyValidNoGrant_A	524299363	0	0	0
ReadyAndValidImplyGrant_A	524299363	2597099	0	0
ReqAndReadyImplyGrant_A	524299363	2597099	0	0
ReqImpliesValid_A	524299363	2597099	0	0
ReqStaysHighUntilGranted0_M	524299363	0	0	0
RoundRobin_A	524299363	7	0	922
ValidKnown_A	524299363	524214495	0	0
gen_data_port_assertion.DataFlow_A	524299363	2597099	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524299363	524214495	0	0
T1	579186	579130	0	0
T2	3400	3305	0	0
T3	11916	11823	0	0
T4	736914	736845	0	0
T5	965802	965731	0	0
T6	27156	27073	0	0
T7	167978	167970	0	0
T8	1284	1206	0	0
T9	105357	105266	0	0
T10	710655	710558	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	922	922	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524299363	2597099	0	0
T3	11916	832	0	0
T4	736914	0	0	0
T5	965802	18614	0	0
T6	27156	832	0	0
T7	167978	5454	0	0
T8	1284	0	0	0
T9	105357	4885	0	0
T10	710655	3471	0	0
T11	23403	832	0	0
T12	0	832	0	0
T13	0	832	0	0
T14	0	832	0	0
T16	2171	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524299363	2597099	0	0
T3	11916	832	0	0
T4	736914	0	0	0
T5	965802	18614	0	0
T6	27156	832	0	0
T7	167978	5454	0	0
T8	1284	0	0	0
T9	105357	4885	0	0
T10	710655	3471	0	0
T11	23403	832	0	0
T12	0	832	0	0
T13	0	832	0	0
T14	0	832	0	0
T16	2171	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524299363	524214495	0	0
T1	579186	579130	0	0
T2	3400	3305	0	0
T3	11916	11823	0	0
T4	736914	736845	0	0
T5	965802	965731	0	0
T6	27156	27073	0	0
T7	167978	167970	0	0
T8	1284	1206	0	0
T9	105357	105266	0	0
T10	710655	710558	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524299363	524214495	0	0
T1	579186	579130	0	0
T2	3400	3305	0	0
T3	11916	11823	0	0
T4	736914	736845	0	0
T5	965802	965731	0	0
T6	27156	27073	0	0
T7	167978	167970	0	0
T8	1284	1206	0	0
T9	105357	105266	0	0
T10	710655	710558	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524299363	2597099	0	0
T3	11916	832	0	0
T4	736914	0	0	0
T5	965802	18614	0	0
T6	27156	832	0	0
T7	167978	5454	0	0
T8	1284	0	0	0
T9	105357	4885	0	0
T10	710655	3471	0	0
T11	23403	832	0	0
T12	0	832	0	0
T13	0	832	0	0
T14	0	832	0	0
T16	2171	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524299363	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524299363	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524299363	2597099	0	0
T3	11916	832	0	0
T4	736914	0	0	0
T5	965802	18614	0	0
T6	27156	832	0	0
T7	167978	5454	0	0
T8	1284	0	0	0
T9	105357	4885	0	0
T10	710655	3471	0	0
T11	23403	832	0	0
T12	0	832	0	0
T13	0	832	0	0
T14	0	832	0	0
T16	2171	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524299363	2597099	0	0
T3	11916	832	0	0
T4	736914	0	0	0
T5	965802	18614	0	0
T6	27156	832	0	0
T7	167978	5454	0	0
T8	1284	0	0	0
T9	105357	4885	0	0
T10	710655	3471	0	0
T11	23403	832	0	0
T12	0	832	0	0
T13	0	832	0	0
T14	0	832	0	0
T16	2171	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524299363	2597099	0	0
T3	11916	832	0	0
T4	736914	0	0	0
T5	965802	18614	0	0
T6	27156	832	0	0
T7	167978	5454	0	0
T8	1284	0	0	0
T9	105357	4885	0	0
T10	710655	3471	0	0
T11	23403	832	0	0
T12	0	832	0	0
T13	0	832	0	0
T14	0	832	0	0
T16	2171	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	524299363	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524299363	7	0	922
T19	684442	1	0	1
T23	1943	0	0	1
T24	132609	0	0	1
T25	300499	0	0	1
T30	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	1386	0	0	1
T42	1023	0	0	1
T43	9922	0	0	1
T44	3514	0	0	1
T45	40205	0	0	1
T46	42862	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524299363	524214495	0	0
T1	579186	579130	0	0
T2	3400	3305	0	0
T3	11916	11823	0	0
T4	736914	736845	0	0
T5	965802	965731	0	0
T6	27156	27073	0	0
T7	167978	167970	0	0
T8	1284	1206	0	0
T9	105357	105266	0	0
T10	710655	710558	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524299363	2597099	0	0
T3	11916	832	0	0
T4	736914	0	0	0
T5	965802	18614	0	0
T6	27156	832	0	0
T7	167978	5454	0	0
T8	1284	0	0	0
T9	105357	4885	0	0
T10	710655	3471	0	0
T11	23403	832	0	0
T12	0	832	0	0
T13	0	832	0	0
T14	0	832	0	0
T16	2171	0	0	0