Unified Coverage Report :: Module :: spi_device_csr_assert_fpv

Module : spi_device_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_spi_device_csr_assert_0/spi_device_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.spi_device_csr_assert	100.00						100.00

---

Module Instance : tb.dut.spi_device_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.69	94.25	84.31	96.94		87.50	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : spi_device_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	58	58	100.00	58	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	58	58	100.00	58	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	526759775	3946	0	0
addr_swap_data_rd_A	526759775	1513	0	0
addr_swap_mask_rd_A	526759775	1394	0	0
cfg_rd_A	526759775	1682	0	0
cmd_filter_0_rd_A	526759775	8355	0	0
cmd_filter_1_rd_A	526759775	7960	0	0
cmd_filter_2_rd_A	526759775	7557	0	0
cmd_filter_3_rd_A	526759775	7299	0	0
cmd_filter_4_rd_A	526759775	7182	0	0
cmd_filter_5_rd_A	526759775	7876	0	0
cmd_filter_6_rd_A	526759775	8689	0	0
cmd_filter_7_rd_A	526759775	7017	0	0
cmd_info_0_rd_A	526759775	3805	0	0
cmd_info_10_rd_A	526759775	3866	0	0
cmd_info_11_rd_A	526759775	4070	0	0
cmd_info_12_rd_A	526759775	3882	0	0
cmd_info_13_rd_A	526759775	3266	0	0
cmd_info_14_rd_A	526759775	3666	0	0
cmd_info_15_rd_A	526759775	3879	0	0
cmd_info_16_rd_A	526759775	4300	0	0
cmd_info_17_rd_A	526759775	3434	0	0
cmd_info_18_rd_A	526759775	4230	0	0
cmd_info_19_rd_A	526759775	3997	0	0
cmd_info_1_rd_A	526759775	3915	0	0
cmd_info_20_rd_A	526759775	3964	0	0
cmd_info_21_rd_A	526759775	4171	0	0
cmd_info_22_rd_A	526759775	3938	0	0
cmd_info_23_rd_A	526759775	3799	0	0
cmd_info_2_rd_A	526759775	3834	0	0
cmd_info_3_rd_A	526759775	3936	0	0
cmd_info_4_rd_A	526759775	3770	0	0
cmd_info_5_rd_A	526759775	4113	0	0
cmd_info_6_rd_A	526759775	4257	0	0
cmd_info_7_rd_A	526759775	4385	0	0
cmd_info_8_rd_A	526759775	3790	0	0
cmd_info_9_rd_A	526759775	4041	0	0
cmd_info_en4b_rd_A	526759775	1855	0	0
cmd_info_ex4b_rd_A	526759775	1795	0	0
cmd_info_wrdi_rd_A	526759775	1677	0	0
cmd_info_wren_rd_A	526759775	1822	0	0
intercept_en_rd_A	526759775	2102	0	0
intr_enable_rd_A	526759775	3594	0	0
jedec_cc_rd_A	526759775	1589	0	0
jedec_id_rd_A	526759775	1819	0	0
mailbox_addr_rd_A	526759775	1534	0	0
payload_swap_data_rd_A	526759775	1527	0	0
payload_swap_mask_rd_A	526759775	1378	0	0
read_threshold_rd_A	526759775	1615	0	0
tpm_access_0_rd_A	526759775	2201	0	0
tpm_access_1_rd_A	526759775	1602	0	0
tpm_cfg_rd_A	526759775	2246	0	0
tpm_did_vid_rd_A	526759775	1751	0	0
tpm_int_enable_rd_A	526759775	1433	0	0
tpm_int_status_rd_A	526759775	1448	0	0
tpm_int_vector_rd_A	526759775	1507	0	0
tpm_intf_capability_rd_A	526759775	1568	0	0
tpm_rid_rd_A	526759775	1549	0	0
tpm_sts_rd_A	526759775	1495	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	3946	0	0
T47	19745	2	0	0
T48	15581	4	0	0
T49	4060	18	0	0
T79	7033	140	0	0
T80	5259	228	0	0
T81	26480	1	0	0
T82	29173	2	0	0
T94	5946	3	0	0
T95	102979	6	0	0
T96	81993	6	0	0

addr_swap_data_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	1513	0	0
T48	15581	33	0	0
T70	3439	4	0	0
T94	5946	1	0	0
T95	102979	105	0	0
T98	71128	98	0	0
T101	10276	2	0	0
T102	9967	2	0	0
T124	12756	25	0	0
T125	4318	9	0	0
T126	93473	38	0	0

addr_swap_mask_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	1394	0	0
T48	15581	33	0	0
T70	3439	7	0	0
T94	5946	9	0	0
T95	102979	121	0	0
T98	71128	49	0	0
T101	10276	3	0	0
T102	9967	2	0	0
T124	12756	21	0	0
T125	4318	7	0	0
T126	93473	51	0	0

cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	1682	0	0
T48	15581	20	0	0
T70	3439	4	0	0
T94	5946	20	0	0
T95	102979	213	0	0
T98	71128	179	0	0
T101	10276	19	0	0
T102	9967	5	0	0
T124	12756	19	0	0
T125	4318	15	0	0
T126	93473	131	0	0

cmd_filter_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	8355	0	0
T48	15581	254	0	0
T70	3439	10	0	0
T94	5946	4	0	0
T95	102979	2361	0	0
T98	71128	1726	0	0
T102	9967	121	0	0
T106	8117	163	0	0
T124	12756	41	0	0
T125	4318	94	0	0
T126	93473	943	0	0

cmd_filter_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	7960	0	0
T48	15581	138	0	0
T79	7033	1	0	0
T94	5946	12	0	0
T95	102979	1864	0	0
T98	71128	1385	0	0
T101	10276	16	0	0
T102	9967	3	0	0
T124	12756	24	0	0
T125	4318	123	0	0
T126	93473	1124	0	0

cmd_filter_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	7557	0	0
T48	15581	232	0	0
T70	3439	1	0	0
T94	5946	141	0	0
T95	102979	1697	0	0
T98	71128	1180	0	0
T101	10276	83	0	0
T102	9967	78	0	0
T124	12756	32	0	0
T125	4318	121	0	0
T126	93473	1348	0	0

cmd_filter_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	7299	0	0
T48	15581	373	0	0
T70	3439	12	0	0
T94	5946	118	0	0
T95	102979	1119	0	0
T98	71128	1454	0	0
T101	10276	105	0	0
T102	9967	190	0	0
T124	12756	85	0	0
T125	4318	8	0	0
T126	93473	999	0	0

cmd_filter_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	7182	0	0
T48	15581	175	0	0
T70	3439	7	0	0
T94	5946	125	0	0
T95	102979	2242	0	0
T98	71128	983	0	0
T101	10276	17	0	0
T102	9967	3	0	0
T124	12756	31	0	0
T125	4318	124	0	0
T126	93473	608	0	0

cmd_filter_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	7876	0	0
T48	15581	228	0	0
T70	3439	12	0	0
T83	13418	2	0	0
T94	5946	15	0	0
T95	102979	2024	0	0
T98	71128	1064	0	0
T101	10276	168	0	0
T102	9967	157	0	0
T124	12756	35	0	0
T125	4318	2	0	0

cmd_filter_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	8689	0	0
T48	15581	143	0	0
T70	3439	5	0	0
T94	5946	110	0	0
T95	102979	2372	0	0
T98	71128	1361	0	0
T101	10276	209	0	0
T102	9967	171	0	0
T124	12756	20	0	0
T125	4318	7	0	0
T126	93473	1052	0	0

cmd_filter_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	7017	0	0
T48	15581	149	0	0
T70	3439	1	0	0
T94	5946	100	0	0
T95	102979	1584	0	0
T98	71128	1364	0	0
T101	10276	112	0	0
T102	9967	73	0	0
T124	12756	43	0	0
T125	4318	119	0	0
T126	93473	1087	0	0

cmd_info_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	3805	0	0
T48	15581	161	0	0
T70	3439	9	0	0
T94	5946	1	0	0
T95	102979	878	0	0
T98	71128	466	0	0
T101	10276	60	0	0
T102	9967	21	0	0
T124	12756	1	0	0
T125	4318	49	0	0
T126	93473	400	0	0

cmd_info_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	3866	0	0
T48	15581	123	0	0
T70	3439	7	0	0
T94	5946	82	0	0
T95	102979	799	0	0
T98	71128	527	0	0
T101	10276	39	0	0
T102	9967	78	0	0
T124	12756	36	0	0
T125	4318	6	0	0
T126	93473	391	0	0

cmd_info_11_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	4070	0	0
T48	15581	119	0	0
T70	3439	15	0	0
T94	5946	68	0	0
T95	102979	978	0	0
T98	71128	553	0	0
T101	10276	28	0	0
T102	9967	59	0	0
T124	12756	42	0	0
T125	4318	2	0	0
T126	93473	404	0	0

cmd_info_12_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	3882	0	0
T48	15581	107	0	0
T70	3439	9	0	0
T94	5946	11	0	0
T95	102979	975	0	0
T98	71128	301	0	0
T101	10276	54	0	0
T102	9967	52	0	0
T124	12756	54	0	0
T125	4318	1	0	0
T126	93473	441	0	0

cmd_info_13_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	3266	0	0
T48	15581	53	0	0
T70	3439	16	0	0
T94	5946	42	0	0
T95	102979	692	0	0
T98	71128	363	0	0
T101	10276	42	0	0
T102	9967	35	0	0
T124	12756	50	0	0
T125	4318	56	0	0
T126	93473	414	0	0

cmd_info_14_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	3666	0	0
T48	15581	62	0	0
T70	3439	1	0	0
T94	5946	6	0	0
T95	102979	955	0	0
T98	71128	456	0	0
T101	10276	68	0	0
T102	9967	26	0	0
T124	12756	42	0	0
T125	4318	3	0	0
T126	93473	343	0	0

cmd_info_15_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	3879	0	0
T48	15581	65	0	0
T70	3439	11	0	0
T94	5946	64	0	0
T95	102979	879	0	0
T98	71128	412	0	0
T101	10276	20	0	0
T102	9967	50	0	0
T106	8117	56	0	0
T125	4318	56	0	0
T126	93473	471	0	0

cmd_info_16_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	4300	0	0
T48	15581	12	0	0
T70	3439	10	0	0
T94	5946	6	0	0
T95	102979	887	0	0
T98	71128	563	0	0
T101	10276	84	0	0
T102	9967	30	0	0
T124	12756	33	0	0
T125	4318	4	0	0
T126	93473	606	0	0

cmd_info_17_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	3434	0	0
T48	15581	117	0	0
T70	3439	5	0	0
T94	5946	4	0	0
T95	102979	627	0	0
T98	71128	495	0	0
T101	10276	41	0	0
T102	9967	34	0	0
T124	12756	7	0	0
T125	4318	3	0	0
T126	93473	499	0	0

cmd_info_18_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	4230	0	0
T48	15581	70	0	0
T70	3439	14	0	0
T94	5946	12	0	0
T95	102979	1052	0	0
T98	71128	754	0	0
T101	10276	53	0	0
T102	9967	51	0	0
T124	12756	49	0	0
T125	4318	70	0	0
T126	93473	413	0	0

cmd_info_19_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	3997	0	0
T48	15581	140	0	0
T70	3439	3	0	0
T94	5946	47	0	0
T95	102979	916	0	0
T98	71128	369	0	0
T101	10276	31	0	0
T102	9967	45	0	0
T124	12756	39	0	0
T125	4318	48	0	0
T126	93473	563	0	0

cmd_info_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	3915	0	0
T48	15581	79	0	0
T70	3439	14	0	0
T94	5946	38	0	0
T95	102979	982	0	0
T98	71128	419	0	0
T101	10276	18	0	0
T102	9967	25	0	0
T124	12756	12	0	0
T125	4318	2	0	0
T126	93473	455	0	0

cmd_info_20_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	3964	0	0
T48	15581	73	0	0
T70	3439	12	0	0
T94	5946	4	0	0
T95	102979	1053	0	0
T98	71128	559	0	0
T101	10276	61	0	0
T102	9967	35	0	0
T124	12756	26	0	0
T125	4318	5	0	0
T126	93473	404	0	0

cmd_info_21_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	4171	0	0
T48	15581	93	0	0
T70	3439	5	0	0
T94	5946	3	0	0
T95	102979	914	0	0
T98	71128	543	0	0
T101	10276	68	0	0
T102	9967	62	0	0
T124	12756	33	0	0
T125	4318	54	0	0
T126	93473	469	0	0

cmd_info_22_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	3938	0	0
T48	15581	130	0	0
T70	3439	8	0	0
T94	5946	3	0	0
T95	102979	728	0	0
T98	71128	603	0	0
T101	10276	33	0	0
T102	9967	60	0	0
T124	12756	16	0	0
T125	4318	8	0	0
T126	93473	547	0	0

cmd_info_23_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	3799	0	0
T48	15581	112	0	0
T70	3439	11	0	0
T94	5946	53	0	0
T95	102979	799	0	0
T98	71128	535	0	0
T101	10276	23	0	0
T102	9967	22	0	0
T106	8117	80	0	0
T124	12756	19	0	0
T126	93473	380	0	0

cmd_info_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	3834	0	0
T48	15581	109	0	0
T70	3439	1	0	0
T94	5946	12	0	0
T95	102979	809	0	0
T98	71128	597	0	0
T101	10276	27	0	0
T102	9967	40	0	0
T124	12756	34	0	0
T125	4318	54	0	0
T126	93473	470	0	0

cmd_info_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	3936	0	0
T48	15581	50	0	0
T70	3439	6	0	0
T94	5946	45	0	0
T95	102979	922	0	0
T98	71128	514	0	0
T101	10276	54	0	0
T102	9967	15	0	0
T124	12756	40	0	0
T125	4318	1	0	0
T126	93473	480	0	0

cmd_info_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	3770	0	0
T48	15581	23	0	0
T70	3439	16	0	0
T94	5946	4	0	0
T95	102979	854	0	0
T98	71128	485	0	0
T101	10276	16	0	0
T102	9967	39	0	0
T124	12756	30	0	0
T125	4318	6	0	0
T126	93473	437	0	0

cmd_info_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	4113	0	0
T48	15581	58	0	0
T70	3439	5	0	0
T94	5946	9	0	0
T95	102979	1097	0	0
T98	71128	400	0	0
T101	10276	42	0	0
T102	9967	81	0	0
T124	12756	32	0	0
T125	4318	6	0	0
T126	93473	600	0	0

cmd_info_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	4257	0	0
T48	15581	95	0	0
T70	3439	10	0	0
T83	13418	8	0	0
T94	5946	45	0	0
T95	102979	970	0	0
T98	71128	454	0	0
T101	10276	79	0	0
T102	9967	49	0	0
T124	12756	14	0	0
T125	4318	55	0	0

cmd_info_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	4385	0	0
T48	15581	124	0	0
T70	3439	6	0	0
T94	5946	39	0	0
T95	102979	882	0	0
T98	71128	728	0	0
T101	10276	79	0	0
T102	9967	18	0	0
T124	12756	19	0	0
T125	4318	44	0	0
T126	93473	569	0	0

cmd_info_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	3790	0	0
T48	15581	154	0	0
T70	3439	5	0	0
T94	5946	60	0	0
T95	102979	669	0	0
T98	71128	472	0	0
T101	10276	49	0	0
T102	9967	36	0	0
T124	12756	26	0	0
T125	4318	10	0	0
T126	93473	526	0	0

cmd_info_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	4041	0	0
T48	15581	90	0	0
T70	3439	2	0	0
T94	5946	47	0	0
T95	102979	967	0	0
T98	71128	643	0	0
T101	10276	77	0	0
T102	9967	29	0	0
T124	12756	17	0	0
T125	4318	7	0	0
T126	93473	361	0	0

cmd_info_en4b_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	1855	0	0
T48	15581	30	0	0
T70	3439	7	0	0
T94	5946	8	0	0
T95	102979	187	0	0
T98	71128	68	0	0
T101	10276	12	0	0
T102	9967	1	0	0
T124	12756	30	0	0
T125	4318	14	0	0
T126	93473	91	0	0

cmd_info_ex4b_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	1795	0	0
T48	15581	34	0	0
T70	3439	12	0	0
T94	5946	6	0	0
T95	102979	187	0	0
T98	71128	129	0	0
T101	10276	5	0	0
T102	9967	11	0	0
T124	12756	26	0	0
T125	4318	1	0	0
T126	93473	153	0	0

cmd_info_wrdi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	1677	0	0
T48	15581	30	0	0
T70	3439	9	0	0
T94	5946	14	0	0
T95	102979	126	0	0
T98	71128	136	0	0
T101	10276	2	0	0
T106	8117	16	0	0
T124	12756	9	0	0
T126	93473	80	0	0
T127	9346	12	0	0

cmd_info_wren_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	1822	0	0
T48	15581	25	0	0
T70	3439	3	0	0
T94	5946	18	0	0
T95	102979	201	0	0
T98	71128	102	0	0
T101	10276	11	0	0
T102	9967	5	0	0
T124	12756	25	0	0
T125	4318	5	0	0
T126	93473	94	0	0

intercept_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	2102	0	0
T48	15581	62	0	0
T70	3439	9	0	0
T94	5946	26	0	0
T95	102979	284	0	0
T98	71128	169	0	0
T101	10276	18	0	0
T102	9967	1	0	0
T124	12756	25	0	0
T125	4318	9	0	0
T126	93473	185	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	3594	0	0
T19	684442	55	0	0
T23	1943	0	0	0
T24	132609	0	0	0
T25	300499	0	0	0
T41	1386	0	0	0
T42	1023	0	0	0
T43	9922	0	0	0
T44	3514	0	0	0
T45	40205	0	0	0
T46	42862	0	0	0
T69	0	37	0	0
T74	0	52	0	0
T128	0	67	0	0
T129	0	25	0	0
T130	0	34	0	0
T131	0	11	0	0
T132	0	16	0	0
T133	0	13	0	0
T134	0	44	0	0

jedec_cc_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	1589	0	0
T48	15581	31	0	0
T70	3439	10	0	0
T94	5946	9	0	0
T95	102979	147	0	0
T98	71128	87	0	0
T101	10276	7	0	0
T102	9967	1	0	0
T124	12756	33	0	0
T125	4318	5	0	0
T126	93473	69	0	0

jedec_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	1819	0	0
T48	15581	30	0	0
T70	3439	7	0	0
T94	5946	9	0	0
T95	102979	184	0	0
T98	71128	130	0	0
T101	10276	8	0	0
T102	9967	18	0	0
T124	12756	25	0	0
T125	4318	11	0	0
T126	93473	77	0	0

mailbox_addr_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	1534	0	0
T48	15581	17	0	0
T70	3439	11	0	0
T94	5946	9	0	0
T95	102979	95	0	0
T98	71128	65	0	0
T101	10276	14	0	0
T106	8117	9	0	0
T124	12756	35	0	0
T125	4318	1	0	0
T126	93473	55	0	0

payload_swap_data_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	1527	0	0
T48	15581	29	0	0
T70	3439	7	0	0
T94	5946	12	0	0
T95	102979	117	0	0
T98	71128	75	0	0
T102	9967	3	0	0
T106	8117	13	0	0
T124	12756	8	0	0
T125	4318	3	0	0
T126	93473	67	0	0

payload_swap_mask_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	1378	0	0
T48	15581	14	0	0
T70	3439	7	0	0
T94	5946	7	0	0
T95	102979	113	0	0
T98	71128	62	0	0
T101	10276	4	0	0
T106	8117	2	0	0
T124	12756	4	0	0
T125	4318	3	0	0
T126	93473	62	0	0

read_threshold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	1615	0	0
T48	15581	10	0	0
T70	3439	5	0	0
T94	5946	15	0	0
T95	102979	133	0	0
T98	71128	82	0	0
T106	8117	2	0	0
T124	12756	18	0	0
T125	4318	9	0	0
T126	93473	70	0	0
T127	9346	5	0	0

tpm_access_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	2201	0	0
T48	15581	30	0	0
T70	3439	5	0	0
T94	5946	22	0	0
T95	102979	394	0	0
T98	71128	177	0	0
T101	10276	17	0	0
T102	9967	18	0	0
T124	12756	35	0	0
T126	93473	142	0	0
T135	6202	7	0	0

tpm_access_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	1602	0	0
T48	15581	21	0	0
T70	3439	10	0	0
T83	13418	3	0	0
T94	5946	11	0	0
T95	102979	126	0	0
T98	71128	72	0	0
T101	10276	12	0	0
T102	9967	6	0	0
T124	12756	34	0	0
T125	4318	8	0	0

tpm_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	2246	0	0
T48	15581	23	0	0
T70	3439	13	0	0
T94	5946	15	0	0
T95	102979	402	0	0
T98	71128	188	0	0
T101	10276	32	0	0
T102	9967	5	0	0
T124	12756	10	0	0
T125	4318	8	0	0
T126	93473	181	0	0

tpm_did_vid_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	1751	0	0
T48	15581	16	0	0
T70	3439	2	0	0
T94	5946	10	0	0
T95	102979	153	0	0
T98	71128	111	0	0
T101	10276	8	0	0
T102	9967	16	0	0
T124	12756	36	0	0
T125	4318	15	0	0
T126	93473	97	0	0

tpm_int_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	1433	0	0
T48	15581	20	0	0
T70	3439	5	0	0
T94	5946	3	0	0
T95	102979	106	0	0
T98	71128	77	0	0
T101	10276	2	0	0
T102	9967	4	0	0
T124	12756	33	0	0
T125	4318	8	0	0
T126	93473	69	0	0

tpm_int_status_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	1448	0	0
T48	15581	19	0	0
T94	5946	11	0	0
T95	102979	124	0	0
T98	71128	66	0	0
T101	10276	7	0	0
T102	9967	2	0	0
T106	8117	3	0	0
T124	12756	44	0	0
T125	4318	5	0	0
T126	93473	39	0	0

tpm_int_vector_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	1507	0	0
T48	15581	38	0	0
T70	3439	3	0	0
T94	5946	3	0	0
T95	102979	127	0	0
T98	71128	60	0	0
T101	10276	6	0	0
T102	9967	5	0	0
T124	12756	24	0	0
T125	4318	2	0	0
T126	93473	57	0	0

tpm_intf_capability_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	1568	0	0
T48	15581	29	0	0
T70	3439	4	0	0
T94	5946	4	0	0
T95	102979	129	0	0
T98	71128	65	0	0
T101	10276	3	0	0
T102	9967	6	0	0
T124	12756	9	0	0
T125	4318	6	0	0
T126	93473	49	0	0

tpm_rid_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	1549	0	0
T48	15581	14	0	0
T70	3439	4	0	0
T94	5946	4	0	0
T95	102979	132	0	0
T98	71128	56	0	0
T101	10276	2	0	0
T102	9967	3	0	0
T124	12756	35	0	0
T125	4318	9	0	0
T126	93473	72	0	0

tpm_sts_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526759775	1495	0	0
T48	15581	38	0	0
T70	3439	3	0	0
T94	5946	4	0	0
T95	102979	101	0	0
T98	71128	84	0	0
T101	10276	6	0	0
T102	9967	8	0	0
T124	12756	38	0	0
T125	4318	9	0	0
T126	93473	64	0	0