| T816 |
/workspace/coverage/default/45.spi_device_flash_mode.1726818753 |
|
|
Mar 24 01:14:35 PM PDT 24 |
Mar 24 01:14:55 PM PDT 24 |
1780786609 ps |
| T817 |
/workspace/coverage/default/6.spi_device_tpm_sts_read.2966039895 |
|
|
Mar 24 01:12:54 PM PDT 24 |
Mar 24 01:12:55 PM PDT 24 |
132224538 ps |
| T818 |
/workspace/coverage/default/42.spi_device_intercept.2188267575 |
|
|
Mar 24 01:14:25 PM PDT 24 |
Mar 24 01:14:30 PM PDT 24 |
687960213 ps |
| T819 |
/workspace/coverage/default/13.spi_device_flash_all.4257697718 |
|
|
Mar 24 01:13:08 PM PDT 24 |
Mar 24 01:17:57 PM PDT 24 |
55217970331 ps |
| T820 |
/workspace/coverage/default/15.spi_device_tpm_all.1434883081 |
|
|
Mar 24 01:13:12 PM PDT 24 |
Mar 24 01:13:33 PM PDT 24 |
14123603895 ps |
| T821 |
/workspace/coverage/default/40.spi_device_tpm_all.1100933310 |
|
|
Mar 24 01:14:29 PM PDT 24 |
Mar 24 01:15:23 PM PDT 24 |
12013819627 ps |
| T822 |
/workspace/coverage/default/20.spi_device_tpm_read_hw_reg.1945684356 |
|
|
Mar 24 01:13:21 PM PDT 24 |
Mar 24 01:13:44 PM PDT 24 |
114938548040 ps |
| T823 |
/workspace/coverage/default/25.spi_device_alert_test.1505121210 |
|
|
Mar 24 01:13:40 PM PDT 24 |
Mar 24 01:13:41 PM PDT 24 |
12370297 ps |
| T824 |
/workspace/coverage/default/37.spi_device_flash_and_tpm.3420004913 |
|
|
Mar 24 01:14:27 PM PDT 24 |
Mar 24 01:19:10 PM PDT 24 |
79508126538 ps |
| T825 |
/workspace/coverage/default/9.spi_device_flash_and_tpm.467900669 |
|
|
Mar 24 01:12:46 PM PDT 24 |
Mar 24 01:13:34 PM PDT 24 |
7995794151 ps |
| T826 |
/workspace/coverage/default/37.spi_device_tpm_all.2198911403 |
|
|
Mar 24 01:14:10 PM PDT 24 |
Mar 24 01:14:42 PM PDT 24 |
4975146750 ps |
| T827 |
/workspace/coverage/default/17.spi_device_alert_test.1045561777 |
|
|
Mar 24 01:13:17 PM PDT 24 |
Mar 24 01:13:18 PM PDT 24 |
22586893 ps |
| T828 |
/workspace/coverage/default/10.spi_device_flash_all.3768491897 |
|
|
Mar 24 01:13:03 PM PDT 24 |
Mar 24 01:13:14 PM PDT 24 |
36272686936 ps |
| T829 |
/workspace/coverage/default/21.spi_device_read_buffer_direct.3731322164 |
|
|
Mar 24 01:13:26 PM PDT 24 |
Mar 24 01:13:33 PM PDT 24 |
2698496585 ps |
| T830 |
/workspace/coverage/default/24.spi_device_read_buffer_direct.469823 |
|
|
Mar 24 01:13:48 PM PDT 24 |
Mar 24 01:13:55 PM PDT 24 |
2982124584 ps |
| T56 |
/workspace/coverage/default/1.spi_device_sec_cm.3488849780 |
|
|
Mar 24 01:12:48 PM PDT 24 |
Mar 24 01:12:50 PM PDT 24 |
519247080 ps |
| T831 |
/workspace/coverage/default/5.spi_device_pass_cmd_filtering.806719049 |
|
|
Mar 24 01:12:52 PM PDT 24 |
Mar 24 01:13:14 PM PDT 24 |
45122758545 ps |
| T832 |
/workspace/coverage/default/2.spi_device_intercept.456559592 |
|
|
Mar 24 01:12:45 PM PDT 24 |
Mar 24 01:12:51 PM PDT 24 |
576649642 ps |
| T833 |
/workspace/coverage/default/36.spi_device_flash_all.1696198832 |
|
|
Mar 24 01:14:20 PM PDT 24 |
Mar 24 01:15:29 PM PDT 24 |
48159289912 ps |
| T233 |
/workspace/coverage/default/40.spi_device_flash_all.1474306711 |
|
|
Mar 24 01:14:31 PM PDT 24 |
Mar 24 01:20:13 PM PDT 24 |
288061280471 ps |
| T834 |
/workspace/coverage/default/27.spi_device_tpm_sts_read.963114151 |
|
|
Mar 24 01:13:56 PM PDT 24 |
Mar 24 01:13:57 PM PDT 24 |
126141176 ps |
| T835 |
/workspace/coverage/default/24.spi_device_pass_addr_payload_swap.3205139061 |
|
|
Mar 24 01:13:32 PM PDT 24 |
Mar 24 01:13:44 PM PDT 24 |
1246586173 ps |
| T836 |
/workspace/coverage/default/44.spi_device_csb_read.1395055305 |
|
|
Mar 24 01:14:30 PM PDT 24 |
Mar 24 01:14:31 PM PDT 24 |
33701833 ps |
| T837 |
/workspace/coverage/default/47.spi_device_intercept.4111913027 |
|
|
Mar 24 01:14:49 PM PDT 24 |
Mar 24 01:14:56 PM PDT 24 |
777450486 ps |
| T838 |
/workspace/coverage/default/15.spi_device_intercept.510898539 |
|
|
Mar 24 01:13:07 PM PDT 24 |
Mar 24 01:13:12 PM PDT 24 |
156037357 ps |
| T839 |
/workspace/coverage/default/47.spi_device_alert_test.2542676249 |
|
|
Mar 24 01:14:43 PM PDT 24 |
Mar 24 01:14:44 PM PDT 24 |
52616210 ps |
| T840 |
/workspace/coverage/default/37.spi_device_read_buffer_direct.2784271182 |
|
|
Mar 24 01:14:14 PM PDT 24 |
Mar 24 01:14:17 PM PDT 24 |
104995626 ps |
| T841 |
/workspace/coverage/default/47.spi_device_flash_all.4151658067 |
|
|
Mar 24 01:14:43 PM PDT 24 |
Mar 24 01:15:31 PM PDT 24 |
48602668290 ps |
| T842 |
/workspace/coverage/default/21.spi_device_intercept.1284377567 |
|
|
Mar 24 01:13:38 PM PDT 24 |
Mar 24 01:13:48 PM PDT 24 |
4245524978 ps |
| T843 |
/workspace/coverage/default/1.spi_device_tpm_sts_read.3805183095 |
|
|
Mar 24 01:12:36 PM PDT 24 |
Mar 24 01:12:37 PM PDT 24 |
72620813 ps |
| T844 |
/workspace/coverage/default/41.spi_device_flash_mode.840128110 |
|
|
Mar 24 01:14:37 PM PDT 24 |
Mar 24 01:14:57 PM PDT 24 |
762129146 ps |
| T39 |
/workspace/coverage/default/14.spi_device_flash_and_tpm.3135034219 |
|
|
Mar 24 01:13:15 PM PDT 24 |
Mar 24 01:14:07 PM PDT 24 |
6810994283 ps |
| T845 |
/workspace/coverage/default/8.spi_device_intercept.4038932441 |
|
|
Mar 24 01:12:50 PM PDT 24 |
Mar 24 01:12:56 PM PDT 24 |
3339418537 ps |
| T846 |
/workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.1758762769 |
|
|
Mar 24 01:13:33 PM PDT 24 |
Mar 24 01:15:56 PM PDT 24 |
34275720631 ps |
| T847 |
/workspace/coverage/default/16.spi_device_flash_and_tpm.2973898637 |
|
|
Mar 24 01:13:15 PM PDT 24 |
Mar 24 01:14:33 PM PDT 24 |
29947536151 ps |
| T848 |
/workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.2579357427 |
|
|
Mar 24 01:14:49 PM PDT 24 |
Mar 24 01:15:17 PM PDT 24 |
4736042729 ps |
| T849 |
/workspace/coverage/default/5.spi_device_tpm_all.257328601 |
|
|
Mar 24 01:12:49 PM PDT 24 |
Mar 24 01:12:58 PM PDT 24 |
2453683162 ps |
| T850 |
/workspace/coverage/default/16.spi_device_upload.3099343125 |
|
|
Mar 24 01:13:33 PM PDT 24 |
Mar 24 01:13:40 PM PDT 24 |
789313486 ps |
| T851 |
/workspace/coverage/default/38.spi_device_tpm_rw.4220218801 |
|
|
Mar 24 01:14:15 PM PDT 24 |
Mar 24 01:14:16 PM PDT 24 |
61543604 ps |
| T852 |
/workspace/coverage/default/31.spi_device_tpm_all.184275198 |
|
|
Mar 24 01:13:55 PM PDT 24 |
Mar 24 01:14:10 PM PDT 24 |
876431254 ps |
| T853 |
/workspace/coverage/default/18.spi_device_pass_cmd_filtering.755502735 |
|
|
Mar 24 01:13:16 PM PDT 24 |
Mar 24 01:13:20 PM PDT 24 |
953896279 ps |
| T854 |
/workspace/coverage/default/2.spi_device_stress_all.1306074371 |
|
|
Mar 24 01:12:41 PM PDT 24 |
Mar 24 01:12:42 PM PDT 24 |
88313679 ps |
| T855 |
/workspace/coverage/default/6.spi_device_pass_addr_payload_swap.4098895963 |
|
|
Mar 24 01:12:52 PM PDT 24 |
Mar 24 01:13:03 PM PDT 24 |
3478006886 ps |
| T856 |
/workspace/coverage/default/32.spi_device_flash_all.3274055985 |
|
|
Mar 24 01:13:54 PM PDT 24 |
Mar 24 01:14:31 PM PDT 24 |
18976994341 ps |
| T40 |
/workspace/coverage/default/40.spi_device_stress_all.4077904763 |
|
|
Mar 24 01:14:26 PM PDT 24 |
Mar 24 01:38:55 PM PDT 24 |
187618006327 ps |
| T857 |
/workspace/coverage/default/47.spi_device_pass_addr_payload_swap.161491427 |
|
|
Mar 24 01:14:41 PM PDT 24 |
Mar 24 01:14:53 PM PDT 24 |
1597115978 ps |
| T858 |
/workspace/coverage/default/30.spi_device_tpm_all.690837666 |
|
|
Mar 24 01:13:56 PM PDT 24 |
Mar 24 01:14:31 PM PDT 24 |
4199848264 ps |
| T859 |
/workspace/coverage/default/18.spi_device_read_buffer_direct.799505260 |
|
|
Mar 24 01:13:44 PM PDT 24 |
Mar 24 01:13:47 PM PDT 24 |
217047803 ps |
| T240 |
/workspace/coverage/default/33.spi_device_flash_and_tpm.3357538000 |
|
|
Mar 24 01:13:57 PM PDT 24 |
Mar 24 01:16:22 PM PDT 24 |
17062745266 ps |
| T860 |
/workspace/coverage/default/14.spi_device_mailbox.579795863 |
|
|
Mar 24 01:13:04 PM PDT 24 |
Mar 24 01:13:44 PM PDT 24 |
85861340410 ps |
| T861 |
/workspace/coverage/default/28.spi_device_stress_all.1956590851 |
|
|
Mar 24 01:13:45 PM PDT 24 |
Mar 24 01:13:46 PM PDT 24 |
51735119 ps |
| T212 |
/workspace/coverage/default/1.spi_device_flash_and_tpm.4290737962 |
|
|
Mar 24 01:12:40 PM PDT 24 |
Mar 24 01:15:13 PM PDT 24 |
57238900931 ps |
| T862 |
/workspace/coverage/default/30.spi_device_read_buffer_direct.1750505211 |
|
|
Mar 24 01:13:56 PM PDT 24 |
Mar 24 01:14:00 PM PDT 24 |
2317891231 ps |
| T863 |
/workspace/coverage/default/7.spi_device_alert_test.2359550019 |
|
|
Mar 24 01:12:54 PM PDT 24 |
Mar 24 01:12:54 PM PDT 24 |
21032588 ps |
| T864 |
/workspace/coverage/default/44.spi_device_pass_addr_payload_swap.68592273 |
|
|
Mar 24 01:14:36 PM PDT 24 |
Mar 24 01:14:40 PM PDT 24 |
390174856 ps |
| T865 |
/workspace/coverage/default/45.spi_device_flash_all.48712729 |
|
|
Mar 24 01:14:33 PM PDT 24 |
Mar 24 01:16:06 PM PDT 24 |
21098552645 ps |
| T241 |
/workspace/coverage/default/26.spi_device_flash_and_tpm.737628026 |
|
|
Mar 24 01:13:51 PM PDT 24 |
Mar 24 01:19:32 PM PDT 24 |
57025127604 ps |
| T866 |
/workspace/coverage/default/42.spi_device_tpm_rw.1286048124 |
|
|
Mar 24 01:14:37 PM PDT 24 |
Mar 24 01:14:39 PM PDT 24 |
315582717 ps |
| T867 |
/workspace/coverage/default/24.spi_device_tpm_all.224268082 |
|
|
Mar 24 01:13:49 PM PDT 24 |
Mar 24 01:14:01 PM PDT 24 |
8430488489 ps |
| T868 |
/workspace/coverage/default/24.spi_device_flash_all.3719922745 |
|
|
Mar 24 01:13:44 PM PDT 24 |
Mar 24 01:14:31 PM PDT 24 |
3101083830 ps |
| T869 |
/workspace/coverage/default/32.spi_device_cfg_cmd.350393160 |
|
|
Mar 24 01:13:53 PM PDT 24 |
Mar 24 01:13:58 PM PDT 24 |
928365571 ps |
| T870 |
/workspace/coverage/default/8.spi_device_tpm_sts_read.714980086 |
|
|
Mar 24 01:12:49 PM PDT 24 |
Mar 24 01:12:50 PM PDT 24 |
46764608 ps |
| T871 |
/workspace/coverage/default/5.spi_device_alert_test.2737542907 |
|
|
Mar 24 01:12:48 PM PDT 24 |
Mar 24 01:12:49 PM PDT 24 |
41241083 ps |
| T872 |
/workspace/coverage/default/35.spi_device_csb_read.4034302945 |
|
|
Mar 24 01:14:02 PM PDT 24 |
Mar 24 01:14:03 PM PDT 24 |
80977576 ps |
| T873 |
/workspace/coverage/default/10.spi_device_intercept.2084702815 |
|
|
Mar 24 01:13:01 PM PDT 24 |
Mar 24 01:13:05 PM PDT 24 |
3302153077 ps |
| T874 |
/workspace/coverage/default/21.spi_device_csb_read.392470638 |
|
|
Mar 24 01:13:42 PM PDT 24 |
Mar 24 01:13:43 PM PDT 24 |
12339595 ps |
| T213 |
/workspace/coverage/default/9.spi_device_flash_all.1581844237 |
|
|
Mar 24 01:12:52 PM PDT 24 |
Mar 24 01:14:08 PM PDT 24 |
8566366025 ps |
| T875 |
/workspace/coverage/default/38.spi_device_flash_all.906361451 |
|
|
Mar 24 01:14:13 PM PDT 24 |
Mar 24 01:15:23 PM PDT 24 |
17818227218 ps |
| T876 |
/workspace/coverage/default/38.spi_device_alert_test.124421482 |
|
|
Mar 24 01:14:12 PM PDT 24 |
Mar 24 01:14:13 PM PDT 24 |
158729121 ps |
| T877 |
/workspace/coverage/default/34.spi_device_mailbox.4243488502 |
|
|
Mar 24 01:14:01 PM PDT 24 |
Mar 24 01:14:41 PM PDT 24 |
28726277195 ps |
| T878 |
/workspace/coverage/default/16.spi_device_tpm_sts_read.1908406591 |
|
|
Mar 24 01:13:35 PM PDT 24 |
Mar 24 01:13:37 PM PDT 24 |
295210757 ps |
| T879 |
/workspace/coverage/default/35.spi_device_intercept.557923177 |
|
|
Mar 24 01:14:01 PM PDT 24 |
Mar 24 01:14:06 PM PDT 24 |
942585620 ps |
| T880 |
/workspace/coverage/default/31.spi_device_pass_addr_payload_swap.153959830 |
|
|
Mar 24 01:13:50 PM PDT 24 |
Mar 24 01:13:54 PM PDT 24 |
710134789 ps |
| T881 |
/workspace/coverage/default/21.spi_device_stress_all.492686121 |
|
|
Mar 24 01:13:32 PM PDT 24 |
Mar 24 01:13:34 PM PDT 24 |
460143591 ps |
| T882 |
/workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.1561306900 |
|
|
Mar 24 01:13:34 PM PDT 24 |
Mar 24 01:16:50 PM PDT 24 |
31378671137 ps |
| T883 |
/workspace/coverage/default/29.spi_device_flash_all.422606258 |
|
|
Mar 24 01:13:43 PM PDT 24 |
Mar 24 01:17:10 PM PDT 24 |
56131245919 ps |
| T884 |
/workspace/coverage/default/17.spi_device_flash_and_tpm.2560450963 |
|
|
Mar 24 01:13:43 PM PDT 24 |
Mar 24 01:16:50 PM PDT 24 |
14810145318 ps |
| T885 |
/workspace/coverage/default/15.spi_device_flash_mode.3396173894 |
|
|
Mar 24 01:13:03 PM PDT 24 |
Mar 24 01:13:19 PM PDT 24 |
1310399273 ps |
| T886 |
/workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.2112747688 |
|
|
Mar 24 01:13:38 PM PDT 24 |
Mar 24 01:13:52 PM PDT 24 |
3873950898 ps |
| T887 |
/workspace/coverage/default/45.spi_device_tpm_read_hw_reg.52826743 |
|
|
Mar 24 01:14:32 PM PDT 24 |
Mar 24 01:14:37 PM PDT 24 |
1842826197 ps |
| T888 |
/workspace/coverage/default/44.spi_device_upload.4273871969 |
|
|
Mar 24 01:14:29 PM PDT 24 |
Mar 24 01:14:36 PM PDT 24 |
2558764559 ps |
| T889 |
/workspace/coverage/default/9.spi_device_upload.78996553 |
|
|
Mar 24 01:12:55 PM PDT 24 |
Mar 24 01:13:09 PM PDT 24 |
4788111444 ps |
| T890 |
/workspace/coverage/default/3.spi_device_ram_cfg.790957428 |
|
|
Mar 24 01:12:35 PM PDT 24 |
Mar 24 01:12:36 PM PDT 24 |
32484155 ps |
| T891 |
/workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.3584640387 |
|
|
Mar 24 01:13:28 PM PDT 24 |
Mar 24 01:15:52 PM PDT 24 |
43892458215 ps |
| T892 |
/workspace/coverage/default/3.spi_device_cfg_cmd.3419308894 |
|
|
Mar 24 01:12:40 PM PDT 24 |
Mar 24 01:12:43 PM PDT 24 |
40132957 ps |
| T893 |
/workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.197692283 |
|
|
Mar 24 01:13:05 PM PDT 24 |
Mar 24 01:17:09 PM PDT 24 |
353819234810 ps |
| T894 |
/workspace/coverage/default/31.spi_device_cfg_cmd.2324196580 |
|
|
Mar 24 01:13:53 PM PDT 24 |
Mar 24 01:13:56 PM PDT 24 |
36238187 ps |
| T895 |
/workspace/coverage/default/13.spi_device_pass_cmd_filtering.914324734 |
|
|
Mar 24 01:13:04 PM PDT 24 |
Mar 24 01:13:12 PM PDT 24 |
1608399185 ps |
| T896 |
/workspace/coverage/default/19.spi_device_ram_cfg.3517798633 |
|
|
Mar 24 01:13:32 PM PDT 24 |
Mar 24 01:13:33 PM PDT 24 |
74984570 ps |
| T897 |
/workspace/coverage/default/19.spi_device_tpm_read_hw_reg.1168355412 |
|
|
Mar 24 01:13:22 PM PDT 24 |
Mar 24 01:13:29 PM PDT 24 |
3436585369 ps |
| T898 |
/workspace/coverage/default/12.spi_device_ram_cfg.418497555 |
|
|
Mar 24 01:13:00 PM PDT 24 |
Mar 24 01:13:05 PM PDT 24 |
19843830 ps |
| T899 |
/workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.1022764421 |
|
|
Mar 24 01:12:51 PM PDT 24 |
Mar 24 01:18:07 PM PDT 24 |
161371598755 ps |
| T900 |
/workspace/coverage/default/14.spi_device_intercept.3073105957 |
|
|
Mar 24 01:13:06 PM PDT 24 |
Mar 24 01:13:12 PM PDT 24 |
12624500490 ps |
| T901 |
/workspace/coverage/default/21.spi_device_tpm_sts_read.3218261168 |
|
|
Mar 24 01:13:45 PM PDT 24 |
Mar 24 01:13:46 PM PDT 24 |
191399666 ps |
| T902 |
/workspace/coverage/default/16.spi_device_csb_read.3210011072 |
|
|
Mar 24 01:13:14 PM PDT 24 |
Mar 24 01:13:15 PM PDT 24 |
23150712 ps |
| T903 |
/workspace/coverage/default/24.spi_device_csb_read.1686504057 |
|
|
Mar 24 01:13:44 PM PDT 24 |
Mar 24 01:13:44 PM PDT 24 |
127439247 ps |
| T904 |
/workspace/coverage/default/10.spi_device_tpm_all.3895051400 |
|
|
Mar 24 01:13:06 PM PDT 24 |
Mar 24 01:13:57 PM PDT 24 |
9766146809 ps |
| T905 |
/workspace/coverage/default/8.spi_device_csb_read.3106091770 |
|
|
Mar 24 01:12:51 PM PDT 24 |
Mar 24 01:12:52 PM PDT 24 |
21836403 ps |
| T906 |
/workspace/coverage/default/9.spi_device_read_buffer_direct.3557313894 |
|
|
Mar 24 01:12:51 PM PDT 24 |
Mar 24 01:12:55 PM PDT 24 |
378276725 ps |
| T76 |
/workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.3511023018 |
|
|
Mar 24 01:13:49 PM PDT 24 |
Mar 24 01:15:19 PM PDT 24 |
7798750462 ps |
| T907 |
/workspace/coverage/default/33.spi_device_tpm_read_hw_reg.602429758 |
|
|
Mar 24 01:14:04 PM PDT 24 |
Mar 24 01:14:09 PM PDT 24 |
1162601713 ps |
| T908 |
/workspace/coverage/default/49.spi_device_intercept.1212232160 |
|
|
Mar 24 01:14:47 PM PDT 24 |
Mar 24 01:14:55 PM PDT 24 |
5457499357 ps |
| T909 |
/workspace/coverage/default/38.spi_device_tpm_read_hw_reg.1777539322 |
|
|
Mar 24 01:14:12 PM PDT 24 |
Mar 24 01:14:26 PM PDT 24 |
2687751677 ps |
| T910 |
/workspace/coverage/default/47.spi_device_tpm_rw.1924940840 |
|
|
Mar 24 01:14:40 PM PDT 24 |
Mar 24 01:14:41 PM PDT 24 |
133436128 ps |
| T911 |
/workspace/coverage/default/3.spi_device_tpm_read_hw_reg.1662344113 |
|
|
Mar 24 01:12:46 PM PDT 24 |
Mar 24 01:12:56 PM PDT 24 |
1575170546 ps |
| T912 |
/workspace/coverage/default/11.spi_device_ram_cfg.82413861 |
|
|
Mar 24 01:13:03 PM PDT 24 |
Mar 24 01:13:05 PM PDT 24 |
16829244 ps |
| T913 |
/workspace/coverage/default/35.spi_device_mailbox.778401119 |
|
|
Mar 24 01:14:01 PM PDT 24 |
Mar 24 01:14:36 PM PDT 24 |
31249814683 ps |
| T914 |
/workspace/coverage/default/46.spi_device_intercept.4199954758 |
|
|
Mar 24 01:14:38 PM PDT 24 |
Mar 24 01:14:41 PM PDT 24 |
99113317 ps |
| T915 |
/workspace/coverage/default/15.spi_device_pass_cmd_filtering.466790944 |
|
|
Mar 24 01:13:03 PM PDT 24 |
Mar 24 01:13:07 PM PDT 24 |
1061008518 ps |
| T916 |
/workspace/coverage/default/17.spi_device_flash_all.2675227176 |
|
|
Mar 24 01:13:42 PM PDT 24 |
Mar 24 01:19:40 PM PDT 24 |
1438737919650 ps |
| T917 |
/workspace/coverage/default/29.spi_device_flash_mode.4183947487 |
|
|
Mar 24 01:13:47 PM PDT 24 |
Mar 24 01:13:54 PM PDT 24 |
789323270 ps |
| T918 |
/workspace/coverage/default/43.spi_device_mailbox.3033537994 |
|
|
Mar 24 01:14:26 PM PDT 24 |
Mar 24 01:14:33 PM PDT 24 |
928536277 ps |
| T919 |
/workspace/coverage/default/44.spi_device_flash_all.3508467163 |
|
|
Mar 24 01:14:30 PM PDT 24 |
Mar 24 01:16:04 PM PDT 24 |
27022520714 ps |
| T920 |
/workspace/coverage/default/1.spi_device_flash_all.104097983 |
|
|
Mar 24 01:12:43 PM PDT 24 |
Mar 24 01:14:28 PM PDT 24 |
46067627383 ps |
| T921 |
/workspace/coverage/default/6.spi_device_mailbox.4005656412 |
|
|
Mar 24 01:12:55 PM PDT 24 |
Mar 24 01:13:08 PM PDT 24 |
3773366832 ps |
| T922 |
/workspace/coverage/default/42.spi_device_flash_mode.2745668200 |
|
|
Mar 24 01:14:37 PM PDT 24 |
Mar 24 01:14:47 PM PDT 24 |
629361442 ps |
| T923 |
/workspace/coverage/default/39.spi_device_cfg_cmd.3728382807 |
|
|
Mar 24 01:14:32 PM PDT 24 |
Mar 24 01:14:35 PM PDT 24 |
70978320 ps |
| T924 |
/workspace/coverage/default/49.spi_device_pass_addr_payload_swap.2480944847 |
|
|
Mar 24 01:14:43 PM PDT 24 |
Mar 24 01:14:48 PM PDT 24 |
346122230 ps |
| T925 |
/workspace/coverage/default/30.spi_device_upload.1611028520 |
|
|
Mar 24 01:13:54 PM PDT 24 |
Mar 24 01:13:57 PM PDT 24 |
74385748 ps |
| T926 |
/workspace/coverage/default/0.spi_device_mailbox.4161252366 |
|
|
Mar 24 01:12:30 PM PDT 24 |
Mar 24 01:12:36 PM PDT 24 |
1111606633 ps |
| T927 |
/workspace/coverage/default/48.spi_device_cfg_cmd.2332240531 |
|
|
Mar 24 01:14:47 PM PDT 24 |
Mar 24 01:14:53 PM PDT 24 |
2794852237 ps |
| T928 |
/workspace/coverage/default/32.spi_device_pass_addr_payload_swap.4288221353 |
|
|
Mar 24 01:13:58 PM PDT 24 |
Mar 24 01:14:40 PM PDT 24 |
58459365040 ps |
| T929 |
/workspace/coverage/default/14.spi_device_ram_cfg.2924304909 |
|
|
Mar 24 01:13:06 PM PDT 24 |
Mar 24 01:13:07 PM PDT 24 |
27731259 ps |
| T930 |
/workspace/coverage/default/35.spi_device_upload.943550075 |
|
|
Mar 24 01:14:00 PM PDT 24 |
Mar 24 01:14:07 PM PDT 24 |
4696849201 ps |
| T931 |
/workspace/coverage/default/24.spi_device_flash_and_tpm.3236796517 |
|
|
Mar 24 01:13:38 PM PDT 24 |
Mar 24 01:13:58 PM PDT 24 |
1507160406 ps |
| T932 |
/workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.1368613769 |
|
|
Mar 24 01:12:46 PM PDT 24 |
Mar 24 01:14:44 PM PDT 24 |
57957460218 ps |
| T933 |
/workspace/coverage/default/20.spi_device_upload.3483898984 |
|
|
Mar 24 01:13:30 PM PDT 24 |
Mar 24 01:13:47 PM PDT 24 |
16466760335 ps |
| T934 |
/workspace/coverage/default/36.spi_device_pass_addr_payload_swap.2314591075 |
|
|
Mar 24 01:14:28 PM PDT 24 |
Mar 24 01:14:32 PM PDT 24 |
294826724 ps |
| T935 |
/workspace/coverage/default/16.spi_device_intercept.3599646372 |
|
|
Mar 24 01:13:41 PM PDT 24 |
Mar 24 01:13:43 PM PDT 24 |
320597490 ps |
| T936 |
/workspace/coverage/default/25.spi_device_flash_all.1880354990 |
|
|
Mar 24 01:13:54 PM PDT 24 |
Mar 24 01:15:09 PM PDT 24 |
21453789105 ps |
| T937 |
/workspace/coverage/default/44.spi_device_tpm_sts_read.3121461931 |
|
|
Mar 24 01:14:36 PM PDT 24 |
Mar 24 01:14:37 PM PDT 24 |
147319929 ps |
| T938 |
/workspace/coverage/default/12.spi_device_tpm_all.1511475396 |
|
|
Mar 24 01:13:02 PM PDT 24 |
Mar 24 01:13:05 PM PDT 24 |
232746321 ps |
| T939 |
/workspace/coverage/default/2.spi_device_flash_mode.2131431654 |
|
|
Mar 24 01:12:41 PM PDT 24 |
Mar 24 01:12:54 PM PDT 24 |
1666074373 ps |
| T940 |
/workspace/coverage/default/26.spi_device_tpm_all.3835354635 |
|
|
Mar 24 01:13:47 PM PDT 24 |
Mar 24 01:13:59 PM PDT 24 |
7808124996 ps |
| T941 |
/workspace/coverage/default/43.spi_device_alert_test.2537493524 |
|
|
Mar 24 01:14:30 PM PDT 24 |
Mar 24 01:14:32 PM PDT 24 |
37110608 ps |
| T942 |
/workspace/coverage/default/28.spi_device_pass_addr_payload_swap.2318095393 |
|
|
Mar 24 01:13:53 PM PDT 24 |
Mar 24 01:13:59 PM PDT 24 |
1144897770 ps |
| T943 |
/workspace/coverage/default/0.spi_device_alert_test.838765229 |
|
|
Mar 24 01:12:51 PM PDT 24 |
Mar 24 01:12:52 PM PDT 24 |
24495153 ps |
| T944 |
/workspace/coverage/default/5.spi_device_mailbox.2459035620 |
|
|
Mar 24 01:12:40 PM PDT 24 |
Mar 24 01:12:52 PM PDT 24 |
2859106103 ps |
| T945 |
/workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.507584949 |
|
|
Mar 24 01:12:46 PM PDT 24 |
Mar 24 01:16:34 PM PDT 24 |
129963814459 ps |
| T946 |
/workspace/coverage/default/20.spi_device_tpm_all.1896631076 |
|
|
Mar 24 01:13:28 PM PDT 24 |
Mar 24 01:13:40 PM PDT 24 |
6914819753 ps |
| T947 |
/workspace/coverage/default/29.spi_device_tpm_all.4266352249 |
|
|
Mar 24 01:13:45 PM PDT 24 |
Mar 24 01:14:43 PM PDT 24 |
10509274383 ps |
| T948 |
/workspace/coverage/default/4.spi_device_tpm_sts_read.2719993706 |
|
|
Mar 24 01:12:43 PM PDT 24 |
Mar 24 01:12:44 PM PDT 24 |
38417398 ps |
| T949 |
/workspace/coverage/default/29.spi_device_csb_read.2348981899 |
|
|
Mar 24 01:13:49 PM PDT 24 |
Mar 24 01:13:50 PM PDT 24 |
53550437 ps |
| T950 |
/workspace/coverage/default/3.spi_device_mailbox.3856193995 |
|
|
Mar 24 01:12:37 PM PDT 24 |
Mar 24 01:13:10 PM PDT 24 |
42917717268 ps |
| T951 |
/workspace/coverage/default/28.spi_device_pass_cmd_filtering.2402475260 |
|
|
Mar 24 01:13:52 PM PDT 24 |
Mar 24 01:14:01 PM PDT 24 |
6191663807 ps |
| T952 |
/workspace/coverage/default/12.spi_device_tpm_rw.2412088847 |
|
|
Mar 24 01:13:07 PM PDT 24 |
Mar 24 01:13:08 PM PDT 24 |
29101031 ps |
| T953 |
/workspace/coverage/default/25.spi_device_tpm_all.2107099686 |
|
|
Mar 24 01:13:42 PM PDT 24 |
Mar 24 01:14:07 PM PDT 24 |
4469061485 ps |
| T954 |
/workspace/coverage/default/38.spi_device_pass_cmd_filtering.1843871406 |
|
|
Mar 24 01:14:11 PM PDT 24 |
Mar 24 01:14:30 PM PDT 24 |
28158065371 ps |
| T955 |
/workspace/coverage/default/16.spi_device_flash_all.2962714242 |
|
|
Mar 24 01:13:29 PM PDT 24 |
Mar 24 01:13:59 PM PDT 24 |
3060508295 ps |
| T956 |
/workspace/coverage/default/43.spi_device_tpm_read_hw_reg.2207922228 |
|
|
Mar 24 01:14:30 PM PDT 24 |
Mar 24 01:14:45 PM PDT 24 |
21349049061 ps |
| T220 |
/workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.1194774942 |
|
|
Mar 24 01:14:26 PM PDT 24 |
Mar 24 01:17:37 PM PDT 24 |
19946553668 ps |
| T957 |
/workspace/coverage/default/34.spi_device_flash_mode.3159111668 |
|
|
Mar 24 01:14:01 PM PDT 24 |
Mar 24 01:14:20 PM PDT 24 |
4756390823 ps |
| T958 |
/workspace/coverage/default/3.spi_device_pass_cmd_filtering.4088034787 |
|
|
Mar 24 01:12:33 PM PDT 24 |
Mar 24 01:12:38 PM PDT 24 |
1994876126 ps |
| T959 |
/workspace/coverage/default/23.spi_device_intercept.4156426773 |
|
|
Mar 24 01:13:30 PM PDT 24 |
Mar 24 01:13:35 PM PDT 24 |
1309124871 ps |
| T960 |
/workspace/coverage/default/38.spi_device_flash_and_tpm.2426882284 |
|
|
Mar 24 01:14:33 PM PDT 24 |
Mar 24 01:15:34 PM PDT 24 |
3427234458 ps |
| T961 |
/workspace/coverage/default/30.spi_device_tpm_sts_read.2121721674 |
|
|
Mar 24 01:13:56 PM PDT 24 |
Mar 24 01:13:57 PM PDT 24 |
27751518 ps |
| T962 |
/workspace/coverage/default/34.spi_device_tpm_rw.2697035061 |
|
|
Mar 24 01:13:56 PM PDT 24 |
Mar 24 01:13:59 PM PDT 24 |
203299384 ps |
| T963 |
/workspace/coverage/default/40.spi_device_alert_test.302524304 |
|
|
Mar 24 01:14:25 PM PDT 24 |
Mar 24 01:14:26 PM PDT 24 |
98498123 ps |
| T964 |
/workspace/coverage/default/15.spi_device_cfg_cmd.3438128446 |
|
|
Mar 24 01:13:11 PM PDT 24 |
Mar 24 01:13:15 PM PDT 24 |
404126834 ps |
| T965 |
/workspace/coverage/default/44.spi_device_flash_and_tpm.3992531729 |
|
|
Mar 24 01:14:36 PM PDT 24 |
Mar 24 01:16:14 PM PDT 24 |
8184261156 ps |
| T966 |
/workspace/coverage/default/43.spi_device_flash_mode.2333137021 |
|
|
Mar 24 01:14:38 PM PDT 24 |
Mar 24 01:14:50 PM PDT 24 |
2362055270 ps |
| T967 |
/workspace/coverage/default/28.spi_device_flash_mode.2569905352 |
|
|
Mar 24 01:13:46 PM PDT 24 |
Mar 24 01:13:56 PM PDT 24 |
1945401337 ps |
| T968 |
/workspace/coverage/default/22.spi_device_tpm_all.2294675848 |
|
|
Mar 24 01:13:27 PM PDT 24 |
Mar 24 01:13:42 PM PDT 24 |
2320635479 ps |
| T969 |
/workspace/coverage/default/19.spi_device_tpm_all.175992362 |
|
|
Mar 24 01:13:22 PM PDT 24 |
Mar 24 01:13:30 PM PDT 24 |
907665588 ps |
| T970 |
/workspace/coverage/default/18.spi_device_flash_all.3491422530 |
|
|
Mar 24 01:13:22 PM PDT 24 |
Mar 24 01:16:35 PM PDT 24 |
75094437947 ps |
| T217 |
/workspace/coverage/default/39.spi_device_stress_all.122396216 |
|
|
Mar 24 01:14:26 PM PDT 24 |
Mar 24 01:16:51 PM PDT 24 |
11456808068 ps |
| T971 |
/workspace/coverage/default/34.spi_device_alert_test.3640311956 |
|
|
Mar 24 01:14:02 PM PDT 24 |
Mar 24 01:14:03 PM PDT 24 |
14608212 ps |
| T972 |
/workspace/coverage/default/49.spi_device_read_buffer_direct.952294302 |
|
|
Mar 24 01:14:49 PM PDT 24 |
Mar 24 01:14:53 PM PDT 24 |
513975200 ps |
| T973 |
/workspace/coverage/default/0.spi_device_pass_addr_payload_swap.1295881428 |
|
|
Mar 24 01:12:35 PM PDT 24 |
Mar 24 01:12:39 PM PDT 24 |
1274329514 ps |
| T974 |
/workspace/coverage/default/22.spi_device_csb_read.3818216562 |
|
|
Mar 24 01:13:28 PM PDT 24 |
Mar 24 01:13:30 PM PDT 24 |
19623557 ps |
| T975 |
/workspace/coverage/default/34.spi_device_pass_cmd_filtering.422396429 |
|
|
Mar 24 01:13:58 PM PDT 24 |
Mar 24 01:14:09 PM PDT 24 |
2626701982 ps |
| T976 |
/workspace/coverage/default/35.spi_device_tpm_rw.1364634082 |
|
|
Mar 24 01:14:02 PM PDT 24 |
Mar 24 01:14:03 PM PDT 24 |
18309605 ps |
| T99 |
/workspace/coverage/cover_reg_top/6.spi_device_csr_rw.724966620 |
|
|
Mar 24 12:36:56 PM PDT 24 |
Mar 24 12:36:59 PM PDT 24 |
85000661 ps |
| T977 |
/workspace/coverage/cover_reg_top/41.spi_device_intr_test.3867192823 |
|
|
Mar 24 12:36:59 PM PDT 24 |
Mar 24 12:37:01 PM PDT 24 |
53718421 ps |
| T978 |
/workspace/coverage/cover_reg_top/48.spi_device_intr_test.3826860044 |
|
|
Mar 24 12:37:18 PM PDT 24 |
Mar 24 12:37:22 PM PDT 24 |
106857103 ps |
| T100 |
/workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3257647648 |
|
|
Mar 24 12:36:48 PM PDT 24 |
Mar 24 12:36:50 PM PDT 24 |
162798960 ps |
| T979 |
/workspace/coverage/cover_reg_top/40.spi_device_intr_test.4188924300 |
|
|
Mar 24 12:37:30 PM PDT 24 |
Mar 24 12:37:36 PM PDT 24 |
45759330 ps |
| T101 |
/workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1294198787 |
|
|
Mar 24 12:37:09 PM PDT 24 |
Mar 24 12:37:14 PM PDT 24 |
102788814 ps |
| T47 |
/workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1114452825 |
|
|
Mar 24 12:37:06 PM PDT 24 |
Mar 24 12:37:23 PM PDT 24 |
340447513 ps |
| T980 |
/workspace/coverage/cover_reg_top/21.spi_device_intr_test.759787231 |
|
|
Mar 24 12:37:03 PM PDT 24 |
Mar 24 12:37:05 PM PDT 24 |
179065335 ps |
| T124 |
/workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1171401453 |
|
|
Mar 24 12:37:04 PM PDT 24 |
Mar 24 12:37:17 PM PDT 24 |
132907767 ps |
| T48 |
/workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3069898989 |
|
|
Mar 24 12:36:59 PM PDT 24 |
Mar 24 12:37:04 PM PDT 24 |
623302673 ps |
| T981 |
/workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1654067078 |
|
|
Mar 24 12:37:01 PM PDT 24 |
Mar 24 12:37:04 PM PDT 24 |
244221212 ps |
| T49 |
/workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.844296235 |
|
|
Mar 24 12:37:04 PM PDT 24 |
Mar 24 12:37:11 PM PDT 24 |
41879117 ps |
| T79 |
/workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1544862148 |
|
|
Mar 24 12:36:53 PM PDT 24 |
Mar 24 12:36:58 PM PDT 24 |
146535316 ps |
| T80 |
/workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2100193910 |
|
|
Mar 24 12:36:37 PM PDT 24 |
Mar 24 12:36:45 PM PDT 24 |
53140293 ps |
| T81 |
/workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2232534397 |
|
|
Mar 24 12:36:50 PM PDT 24 |
Mar 24 12:36:58 PM PDT 24 |
275877505 ps |
| T94 |
/workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.3468052409 |
|
|
Mar 24 12:37:02 PM PDT 24 |
Mar 24 12:37:04 PM PDT 24 |
121355966 ps |
| T70 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3537518923 |
|
|
Mar 24 12:36:52 PM PDT 24 |
Mar 24 12:36:55 PM PDT 24 |
143395409 ps |
| T982 |
/workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3796204441 |
|
|
Mar 24 12:37:06 PM PDT 24 |
Mar 24 12:37:09 PM PDT 24 |
38484500 ps |
| T82 |
/workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.4082512519 |
|
|
Mar 24 12:36:39 PM PDT 24 |
Mar 24 12:37:02 PM PDT 24 |
1215603909 ps |
| T95 |
/workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3336952982 |
|
|
Mar 24 12:37:10 PM PDT 24 |
Mar 24 12:37:35 PM PDT 24 |
1029823072 ps |
| T96 |
/workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.795078949 |
|
|
Mar 24 12:37:06 PM PDT 24 |
Mar 24 12:37:31 PM PDT 24 |
3416491223 ps |
| T983 |
/workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3616648383 |
|
|
Mar 24 12:36:41 PM PDT 24 |
Mar 24 12:37:08 PM PDT 24 |
1208885086 ps |
| T97 |
/workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2235945855 |
|
|
Mar 24 12:37:06 PM PDT 24 |
Mar 24 12:37:12 PM PDT 24 |
118837416 ps |
| T984 |
/workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2726611445 |
|
|
Mar 24 12:37:00 PM PDT 24 |
Mar 24 12:37:01 PM PDT 24 |
26373607 ps |
| T985 |
/workspace/coverage/cover_reg_top/18.spi_device_intr_test.3764567688 |
|
|
Mar 24 12:37:15 PM PDT 24 |
Mar 24 12:37:16 PM PDT 24 |
17011364 ps |
| T986 |
/workspace/coverage/cover_reg_top/43.spi_device_intr_test.440836131 |
|
|
Mar 24 12:37:10 PM PDT 24 |
Mar 24 12:37:12 PM PDT 24 |
53744540 ps |
| T98 |
/workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3190342436 |
|
|
Mar 24 12:36:47 PM PDT 24 |
Mar 24 12:37:04 PM PDT 24 |
1422595624 ps |
| T102 |
/workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2915818697 |
|
|
Mar 24 12:37:11 PM PDT 24 |
Mar 24 12:37:14 PM PDT 24 |
101725196 ps |
| T83 |
/workspace/coverage/cover_reg_top/12.spi_device_tl_errors.701033059 |
|
|
Mar 24 12:37:02 PM PDT 24 |
Mar 24 12:37:06 PM PDT 24 |
1917035200 ps |
| T103 |
/workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.210619444 |
|
|
Mar 24 12:36:53 PM PDT 24 |
Mar 24 12:37:10 PM PDT 24 |
212626534 ps |
| T104 |
/workspace/coverage/cover_reg_top/5.spi_device_csr_rw.4151053511 |
|
|
Mar 24 12:36:59 PM PDT 24 |
Mar 24 12:37:03 PM PDT 24 |
374178479 ps |
| T987 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3063940805 |
|
|
Mar 24 12:36:51 PM PDT 24 |
Mar 24 12:37:16 PM PDT 24 |
6031683754 ps |
| T84 |
/workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1025862682 |
|
|
Mar 24 12:37:05 PM PDT 24 |
Mar 24 12:37:14 PM PDT 24 |
664582525 ps |
| T988 |
/workspace/coverage/cover_reg_top/31.spi_device_intr_test.2407599659 |
|
|
Mar 24 12:37:17 PM PDT 24 |
Mar 24 12:37:23 PM PDT 24 |
12106498 ps |
| T85 |
/workspace/coverage/cover_reg_top/8.spi_device_tl_errors.4166306874 |
|
|
Mar 24 12:37:00 PM PDT 24 |
Mar 24 12:37:12 PM PDT 24 |
21448581 ps |
| T989 |
/workspace/coverage/cover_reg_top/36.spi_device_intr_test.684636806 |
|
|
Mar 24 12:37:05 PM PDT 24 |
Mar 24 12:37:11 PM PDT 24 |
39993286 ps |
| T87 |
/workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2402542655 |
|
|
Mar 24 12:36:55 PM PDT 24 |
Mar 24 12:37:04 PM PDT 24 |
57744327 ps |
| T990 |
/workspace/coverage/cover_reg_top/4.spi_device_intr_test.404493391 |
|
|
Mar 24 12:36:53 PM PDT 24 |
Mar 24 12:36:56 PM PDT 24 |
21567983 ps |
| T135 |
/workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1911431013 |
|
|
Mar 24 12:36:58 PM PDT 24 |
Mar 24 12:37:00 PM PDT 24 |
248177416 ps |
| T991 |
/workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1411833379 |
|
|
Mar 24 12:37:00 PM PDT 24 |
Mar 24 12:37:13 PM PDT 24 |
622854185 ps |
| T992 |
/workspace/coverage/cover_reg_top/17.spi_device_intr_test.1549870876 |
|
|
Mar 24 12:37:06 PM PDT 24 |
Mar 24 12:37:12 PM PDT 24 |
18774429 ps |
| T125 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3494749040 |
|
|
Mar 24 12:37:07 PM PDT 24 |
Mar 24 12:37:13 PM PDT 24 |
479913540 ps |
| T993 |
/workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2406952943 |
|
|
Mar 24 12:36:49 PM PDT 24 |
Mar 24 12:36:54 PM PDT 24 |
621962526 ps |
| T994 |
/workspace/coverage/cover_reg_top/9.spi_device_csr_rw.4059095895 |
|
|
Mar 24 12:37:22 PM PDT 24 |
Mar 24 12:37:24 PM PDT 24 |
38345251 ps |
| T995 |
/workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.935262157 |
|
|
Mar 24 12:37:15 PM PDT 24 |
Mar 24 12:37:18 PM PDT 24 |
523052785 ps |
| T996 |
/workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2420362209 |
|
|
Mar 24 12:36:37 PM PDT 24 |
Mar 24 12:36:54 PM PDT 24 |
2420855328 ps |
| T997 |
/workspace/coverage/cover_reg_top/2.spi_device_intr_test.2319012017 |
|
|
Mar 24 12:36:49 PM PDT 24 |
Mar 24 12:36:55 PM PDT 24 |
11152539 ps |
| T126 |
/workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2674759074 |
|
|
Mar 24 12:36:57 PM PDT 24 |
Mar 24 12:37:19 PM PDT 24 |
963629367 ps |
| T998 |
/workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2845131477 |
|
|
Mar 24 12:36:44 PM PDT 24 |
Mar 24 12:36:46 PM PDT 24 |
47949044 ps |
| T105 |
/workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.235833631 |
|
|
Mar 24 12:36:32 PM PDT 24 |
Mar 24 12:36:33 PM PDT 24 |
19793382 ps |
| T999 |
/workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.4203452776 |
|
|
Mar 24 12:37:02 PM PDT 24 |
Mar 24 12:37:04 PM PDT 24 |
102407182 ps |
| T1000 |
/workspace/coverage/cover_reg_top/26.spi_device_intr_test.1888352171 |
|
|
Mar 24 12:37:01 PM PDT 24 |
Mar 24 12:37:03 PM PDT 24 |
19754934 ps |
| T1001 |
/workspace/coverage/cover_reg_top/16.spi_device_intr_test.185838308 |
|
|
Mar 24 12:36:59 PM PDT 24 |
Mar 24 12:37:01 PM PDT 24 |
38892587 ps |
| T145 |
/workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1982832723 |
|
|
Mar 24 12:37:06 PM PDT 24 |
Mar 24 12:37:31 PM PDT 24 |
1951104136 ps |
| T1002 |
/workspace/coverage/cover_reg_top/35.spi_device_intr_test.2846410668 |
|
|
Mar 24 12:37:03 PM PDT 24 |
Mar 24 12:37:05 PM PDT 24 |
50735833 ps |
| T1003 |
/workspace/coverage/cover_reg_top/37.spi_device_intr_test.1390883702 |
|
|
Mar 24 12:37:00 PM PDT 24 |
Mar 24 12:37:01 PM PDT 24 |
13941216 ps |
| T1004 |
/workspace/coverage/cover_reg_top/47.spi_device_intr_test.97506383 |
|
|
Mar 24 12:37:07 PM PDT 24 |
Mar 24 12:37:15 PM PDT 24 |
13697844 ps |
| T88 |
/workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3669023373 |
|
|
Mar 24 12:37:09 PM PDT 24 |
Mar 24 12:37:15 PM PDT 24 |
124712247 ps |
| T1005 |
/workspace/coverage/cover_reg_top/34.spi_device_intr_test.1657894116 |
|
|
Mar 24 12:37:24 PM PDT 24 |
Mar 24 12:37:25 PM PDT 24 |
61753420 ps |
| T1006 |
/workspace/coverage/cover_reg_top/20.spi_device_intr_test.4140504643 |
|
|
Mar 24 12:37:11 PM PDT 24 |
Mar 24 12:37:12 PM PDT 24 |
12997884 ps |
| T106 |
/workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3987278443 |
|
|
Mar 24 12:37:02 PM PDT 24 |
Mar 24 12:37:04 PM PDT 24 |
338291522 ps |
| T127 |
/workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.4232255898 |
|
|
Mar 24 12:36:55 PM PDT 24 |
Mar 24 12:36:58 PM PDT 24 |
190749678 ps |
| T107 |
/workspace/coverage/cover_reg_top/16.spi_device_csr_rw.247075016 |
|
|
Mar 24 12:37:08 PM PDT 24 |
Mar 24 12:37:12 PM PDT 24 |
311659622 ps |
| T1007 |
/workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.4222326945 |
|
|
Mar 24 12:36:58 PM PDT 24 |
Mar 24 12:37:01 PM PDT 24 |
429209487 ps |
| T1008 |
/workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3592799822 |
|
|
Mar 24 12:36:46 PM PDT 24 |
Mar 24 12:36:54 PM PDT 24 |
99275359 ps |
| T1009 |
/workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3243678616 |
|
|
Mar 24 12:37:06 PM PDT 24 |
Mar 24 12:37:12 PM PDT 24 |
205402582 ps |
| T1010 |
/workspace/coverage/cover_reg_top/6.spi_device_intr_test.961980901 |
|
|
Mar 24 12:37:10 PM PDT 24 |
Mar 24 12:37:12 PM PDT 24 |
24053341 ps |
| T1011 |
/workspace/coverage/cover_reg_top/7.spi_device_tl_errors.4173050905 |
|
|
Mar 24 12:37:00 PM PDT 24 |
Mar 24 12:37:04 PM PDT 24 |
187611467 ps |
| T1012 |
/workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2334819842 |
|
|
Mar 24 12:36:43 PM PDT 24 |
Mar 24 12:36:51 PM PDT 24 |
42568778 ps |
| T1013 |
/workspace/coverage/cover_reg_top/44.spi_device_intr_test.1932560925 |
|
|
Mar 24 12:37:05 PM PDT 24 |
Mar 24 12:37:10 PM PDT 24 |
28222212 ps |
| T1014 |
/workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.926988512 |
|
|
Mar 24 12:36:59 PM PDT 24 |
Mar 24 12:37:37 PM PDT 24 |
5762575903 ps |
| T110 |
/workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3830286420 |
|
|
Mar 24 12:36:41 PM PDT 24 |
Mar 24 12:36:45 PM PDT 24 |
61320211 ps |
| T1015 |
/workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3154068540 |
|
|
Mar 24 12:37:10 PM PDT 24 |
Mar 24 12:37:16 PM PDT 24 |
226135277 ps |
| T108 |
/workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1636381515 |
|
|
Mar 24 12:36:59 PM PDT 24 |
Mar 24 12:37:02 PM PDT 24 |
101816668 ps |
| T1016 |
/workspace/coverage/cover_reg_top/4.spi_device_csr_rw.4241338175 |
|
|
Mar 24 12:37:00 PM PDT 24 |
Mar 24 12:37:02 PM PDT 24 |
54086323 ps |
| T1017 |
/workspace/coverage/cover_reg_top/13.spi_device_intr_test.3957023040 |
|
|
Mar 24 12:37:10 PM PDT 24 |
Mar 24 12:37:12 PM PDT 24 |
41462743 ps |
| T140 |
/workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1068807593 |
|
|
Mar 24 12:36:59 PM PDT 24 |
Mar 24 12:37:20 PM PDT 24 |
4274917971 ps |
| T1018 |
/workspace/coverage/cover_reg_top/7.spi_device_intr_test.4084322571 |
|
|
Mar 24 12:36:52 PM PDT 24 |
Mar 24 12:36:53 PM PDT 24 |
183105126 ps |