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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.95 98.30 94.34 98.61 89.36 97.00 95.84 98.17


Total test records in report: 1096
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
T86 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.350194865 Mar 24 12:37:07 PM PDT 24 Mar 24 12:37:13 PM PDT 24 182272095 ps
T1019 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1549017628 Mar 24 12:37:11 PM PDT 24 Mar 24 12:37:15 PM PDT 24 391453824 ps
T143 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.503530352 Mar 24 12:36:57 PM PDT 24 Mar 24 12:37:17 PM PDT 24 373850067 ps
T1020 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2499875850 Mar 24 12:36:55 PM PDT 24 Mar 24 12:36:56 PM PDT 24 21407055 ps
T1021 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3494650248 Mar 24 12:37:16 PM PDT 24 Mar 24 12:37:34 PM PDT 24 3234962597 ps
T1022 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.4206965271 Mar 24 12:36:49 PM PDT 24 Mar 24 12:36:53 PM PDT 24 133302252 ps
T109 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2428324141 Mar 24 12:36:59 PM PDT 24 Mar 24 12:37:02 PM PDT 24 29912569 ps
T1023 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.654751717 Mar 24 12:37:14 PM PDT 24 Mar 24 12:37:15 PM PDT 24 38481018 ps
T1024 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2022176704 Mar 24 12:37:04 PM PDT 24 Mar 24 12:37:09 PM PDT 24 55038455 ps
T1025 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2604317347 Mar 24 12:36:47 PM PDT 24 Mar 24 12:36:49 PM PDT 24 25229309 ps
T1026 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3166849728 Mar 24 12:36:45 PM PDT 24 Mar 24 12:36:47 PM PDT 24 28419600 ps
T1027 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3116351355 Mar 24 12:37:03 PM PDT 24 Mar 24 12:37:08 PM PDT 24 218223092 ps
T1028 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.4281652535 Mar 24 12:37:04 PM PDT 24 Mar 24 12:37:10 PM PDT 24 16331412 ps
T1029 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2556816901 Mar 24 12:37:02 PM PDT 24 Mar 24 12:37:03 PM PDT 24 18281328 ps
T1030 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3489175586 Mar 24 12:37:05 PM PDT 24 Mar 24 12:37:11 PM PDT 24 12607675 ps
T1031 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2318501921 Mar 24 12:36:54 PM PDT 24 Mar 24 12:36:58 PM PDT 24 38240883 ps
T89 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.4194639937 Mar 24 12:36:43 PM PDT 24 Mar 24 12:36:45 PM PDT 24 75778716 ps
T1032 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1754139437 Mar 24 12:36:44 PM PDT 24 Mar 24 12:36:48 PM PDT 24 260844677 ps
T1033 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.91921358 Mar 24 12:37:10 PM PDT 24 Mar 24 12:37:13 PM PDT 24 48185556 ps
T1034 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1900175294 Mar 24 12:37:14 PM PDT 24 Mar 24 12:37:15 PM PDT 24 16046652 ps
T111 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.722763627 Mar 24 12:36:51 PM PDT 24 Mar 24 12:36:55 PM PDT 24 164754260 ps
T1035 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.694333730 Mar 24 12:36:49 PM PDT 24 Mar 24 12:36:50 PM PDT 24 77264555 ps
T1036 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2052534378 Mar 24 12:36:44 PM PDT 24 Mar 24 12:36:46 PM PDT 24 199233892 ps
T1037 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.847649575 Mar 24 12:36:44 PM PDT 24 Mar 24 12:36:59 PM PDT 24 1262017013 ps
T1038 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.4141743367 Mar 24 12:36:45 PM PDT 24 Mar 24 12:36:47 PM PDT 24 174274917 ps
T1039 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2198477721 Mar 24 12:36:52 PM PDT 24 Mar 24 12:36:56 PM PDT 24 23410874 ps
T1040 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2173246316 Mar 24 12:37:13 PM PDT 24 Mar 24 12:37:16 PM PDT 24 161666936 ps
T144 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1391234495 Mar 24 12:37:01 PM PDT 24 Mar 24 12:37:21 PM PDT 24 599223647 ps
T112 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2097640590 Mar 24 12:36:36 PM PDT 24 Mar 24 12:36:39 PM PDT 24 89631727 ps
T113 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1418978042 Mar 24 12:37:09 PM PDT 24 Mar 24 12:37:13 PM PDT 24 19811522 ps
T1041 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3842924042 Mar 24 12:37:22 PM PDT 24 Mar 24 12:37:23 PM PDT 24 19187420 ps
T1042 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1868271774 Mar 24 12:36:55 PM PDT 24 Mar 24 12:36:58 PM PDT 24 857175139 ps
T114 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1101847582 Mar 24 12:36:40 PM PDT 24 Mar 24 12:37:08 PM PDT 24 3778680632 ps
T1043 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1203169810 Mar 24 12:37:22 PM PDT 24 Mar 24 12:37:24 PM PDT 24 16390645 ps
T1044 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3006572036 Mar 24 12:37:01 PM PDT 24 Mar 24 12:37:04 PM PDT 24 530636146 ps
T1045 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1419373117 Mar 24 12:37:04 PM PDT 24 Mar 24 12:37:09 PM PDT 24 13910438 ps
T141 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1087936246 Mar 24 12:37:05 PM PDT 24 Mar 24 12:37:16 PM PDT 24 376898272 ps
T1046 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2739388373 Mar 24 12:37:20 PM PDT 24 Mar 24 12:37:22 PM PDT 24 30067504 ps
T1047 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2549464745 Mar 24 12:36:50 PM PDT 24 Mar 24 12:36:52 PM PDT 24 233029115 ps
T1048 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2496943748 Mar 24 12:36:52 PM PDT 24 Mar 24 12:36:56 PM PDT 24 498302995 ps
T1049 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1866648462 Mar 24 12:37:28 PM PDT 24 Mar 24 12:37:29 PM PDT 24 157999560 ps
T1050 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1050642344 Mar 24 12:37:22 PM PDT 24 Mar 24 12:37:27 PM PDT 24 188323400 ps
T1051 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3020462700 Mar 24 12:37:12 PM PDT 24 Mar 24 12:37:16 PM PDT 24 59189447 ps
T1052 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.279775681 Mar 24 12:37:02 PM PDT 24 Mar 24 12:37:20 PM PDT 24 590673720 ps
T1053 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2091326148 Mar 24 12:36:52 PM PDT 24 Mar 24 12:36:55 PM PDT 24 14191424 ps
T1054 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1319824960 Mar 24 12:37:05 PM PDT 24 Mar 24 12:37:13 PM PDT 24 58933696 ps
T1055 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1794406294 Mar 24 12:37:02 PM PDT 24 Mar 24 12:37:03 PM PDT 24 17591917 ps
T1056 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3115885369 Mar 24 12:36:44 PM PDT 24 Mar 24 12:36:45 PM PDT 24 41179742 ps
T1057 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3581795747 Mar 24 12:37:11 PM PDT 24 Mar 24 12:37:14 PM PDT 24 218274442 ps
T1058 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1560124741 Mar 24 12:37:06 PM PDT 24 Mar 24 12:37:10 PM PDT 24 72692165 ps
T71 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.221312886 Mar 24 12:37:10 PM PDT 24 Mar 24 12:37:13 PM PDT 24 37298760 ps
T72 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1780331867 Mar 24 12:37:08 PM PDT 24 Mar 24 12:37:11 PM PDT 24 99544038 ps
T1059 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.339783356 Mar 24 12:37:02 PM PDT 24 Mar 24 12:37:03 PM PDT 24 14901163 ps
T1060 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3338976135 Mar 24 12:36:37 PM PDT 24 Mar 24 12:36:40 PM PDT 24 265600112 ps
T1061 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2875130451 Mar 24 12:37:02 PM PDT 24 Mar 24 12:37:03 PM PDT 24 14885828 ps
T1062 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3661848189 Mar 24 12:37:07 PM PDT 24 Mar 24 12:37:10 PM PDT 24 16344323 ps
T93 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3360749877 Mar 24 12:37:05 PM PDT 24 Mar 24 12:37:16 PM PDT 24 69947322 ps
T90 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1087367890 Mar 24 12:37:01 PM PDT 24 Mar 24 12:37:06 PM PDT 24 210746322 ps
T1063 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1819414198 Mar 24 12:37:08 PM PDT 24 Mar 24 12:37:11 PM PDT 24 43340278 ps
T91 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1654354201 Mar 24 12:36:56 PM PDT 24 Mar 24 12:37:00 PM PDT 24 46081142 ps
T1064 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.860918872 Mar 24 12:37:09 PM PDT 24 Mar 24 12:37:19 PM PDT 24 300239794 ps
T1065 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1200660466 Mar 24 12:37:18 PM PDT 24 Mar 24 12:37:21 PM PDT 24 44555860 ps
T1066 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3236982807 Mar 24 12:36:44 PM PDT 24 Mar 24 12:36:44 PM PDT 24 37325697 ps
T1067 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.4257293114 Mar 24 12:36:52 PM PDT 24 Mar 24 12:37:05 PM PDT 24 3764715850 ps
T1068 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1691430307 Mar 24 12:37:08 PM PDT 24 Mar 24 12:37:14 PM PDT 24 45912418 ps
T1069 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1301885282 Mar 24 12:37:27 PM PDT 24 Mar 24 12:37:28 PM PDT 24 11447184 ps
T1070 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1208427097 Mar 24 12:37:11 PM PDT 24 Mar 24 12:37:13 PM PDT 24 47112681 ps
T1071 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.625266216 Mar 24 12:36:42 PM PDT 24 Mar 24 12:36:58 PM PDT 24 600425441 ps
T1072 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3830516940 Mar 24 12:37:21 PM PDT 24 Mar 24 12:37:24 PM PDT 24 49400384 ps
T92 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3779011792 Mar 24 12:37:09 PM PDT 24 Mar 24 12:37:15 PM PDT 24 40577273 ps
T73 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2402393551 Mar 24 12:36:49 PM PDT 24 Mar 24 12:36:50 PM PDT 24 19470431 ps
T1073 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3634525951 Mar 24 12:36:55 PM PDT 24 Mar 24 12:37:01 PM PDT 24 718610833 ps
T1074 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3030777633 Mar 24 12:36:56 PM PDT 24 Mar 24 12:37:01 PM PDT 24 812452909 ps
T1075 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1189461697 Mar 24 12:36:54 PM PDT 24 Mar 24 12:36:56 PM PDT 24 48018266 ps
T1076 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3665974996 Mar 24 12:37:07 PM PDT 24 Mar 24 12:37:12 PM PDT 24 50543915 ps
T1077 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1357034900 Mar 24 12:37:13 PM PDT 24 Mar 24 12:37:15 PM PDT 24 26262303 ps
T1078 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1175642257 Mar 24 12:37:14 PM PDT 24 Mar 24 12:37:35 PM PDT 24 1554462443 ps
T1079 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1442980229 Mar 24 12:37:01 PM PDT 24 Mar 24 12:37:03 PM PDT 24 39429679 ps
T1080 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2629837553 Mar 24 12:36:53 PM PDT 24 Mar 24 12:36:59 PM PDT 24 129538608 ps
T1081 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2466286286 Mar 24 12:37:04 PM PDT 24 Mar 24 12:37:13 PM PDT 24 337301712 ps
T1082 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.4288613588 Mar 24 12:37:19 PM PDT 24 Mar 24 12:37:22 PM PDT 24 46552525 ps
T1083 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1004973360 Mar 24 12:36:55 PM PDT 24 Mar 24 12:36:57 PM PDT 24 23589809 ps
T1084 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1224263166 Mar 24 12:36:55 PM PDT 24 Mar 24 12:36:57 PM PDT 24 46794176 ps
T1085 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2328437078 Mar 24 12:37:18 PM PDT 24 Mar 24 12:37:22 PM PDT 24 49274740 ps
T1086 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3169891755 Mar 24 12:36:54 PM PDT 24 Mar 24 12:37:03 PM PDT 24 115117440 ps
T1087 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1779988927 Mar 24 12:36:52 PM PDT 24 Mar 24 12:36:57 PM PDT 24 122664618 ps
T1088 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2548057598 Mar 24 12:37:05 PM PDT 24 Mar 24 12:37:29 PM PDT 24 1598756220 ps
T1089 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3799099326 Mar 24 12:36:47 PM PDT 24 Mar 24 12:36:48 PM PDT 24 19256247 ps
T1090 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1138821261 Mar 24 12:36:57 PM PDT 24 Mar 24 12:36:58 PM PDT 24 15659509 ps
T1091 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2228461173 Mar 24 12:36:59 PM PDT 24 Mar 24 12:37:04 PM PDT 24 59649730 ps
T142 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1100005219 Mar 24 12:37:01 PM PDT 24 Mar 24 12:37:16 PM PDT 24 207289952 ps
T1092 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.719461416 Mar 24 12:37:09 PM PDT 24 Mar 24 12:37:15 PM PDT 24 126762921 ps
T1093 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.174615471 Mar 24 12:37:10 PM PDT 24 Mar 24 12:37:12 PM PDT 24 21055639 ps
T1094 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1592458408 Mar 24 12:36:52 PM PDT 24 Mar 24 12:36:57 PM PDT 24 121641483 ps
T1095 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3396760495 Mar 24 12:37:01 PM PDT 24 Mar 24 12:37:03 PM PDT 24 20068040 ps
T1096 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2346386492 Mar 24 12:36:43 PM PDT 24 Mar 24 12:36:44 PM PDT 24 15547180 ps

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.1641410280
Short name T7
Test name
Test status
Simulation time 34281076644 ps
CPU time 105.15 seconds
Started Mar 24 01:12:56 PM PDT 24
Finished Mar 24 01:14:41 PM PDT 24
Peak memory 237832 kb
Host smart-2489017d-b30e-4dc8-bd5a-b4f272d91e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641410280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.1641410280
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.513246255
Short name T15
Test name
Test status
Simulation time 38494250750 ps
CPU time 238.55 seconds
Started Mar 24 01:12:29 PM PDT 24
Finished Mar 24 01:16:28 PM PDT 24
Peak memory 254180 kb
Host smart-7d7eb916-40ea-444a-b50f-25859b019d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513246255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.513246255
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.3232077617
Short name T19
Test name
Test status
Simulation time 285186798001 ps
CPU time 465.99 seconds
Started Mar 24 01:14:16 PM PDT 24
Finished Mar 24 01:22:02 PM PDT 24
Peak memory 273780 kb
Host smart-92b2e2df-5e6e-4751-a4d7-7e864f19cc23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232077617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.3232077617
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3336952982
Short name T95
Test name
Test status
Simulation time 1029823072 ps
CPU time 23.35 seconds
Started Mar 24 12:37:10 PM PDT 24
Finished Mar 24 12:37:35 PM PDT 24
Peak memory 215336 kb
Host smart-069e3ad9-76aa-4907-a336-71ad917f60ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336952982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.3336952982
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.4271319955
Short name T67
Test name
Test status
Simulation time 39185976840 ps
CPU time 224.02 seconds
Started Mar 24 01:14:49 PM PDT 24
Finished Mar 24 01:18:34 PM PDT 24
Peak memory 290488 kb
Host smart-96487778-a164-43b8-a84d-cf77c9990606
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271319955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.4271319955
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.4180308959
Short name T29
Test name
Test status
Simulation time 398403230396 ps
CPU time 736.68 seconds
Started Mar 24 01:13:17 PM PDT 24
Finished Mar 24 01:25:34 PM PDT 24
Peak memory 257704 kb
Host smart-560039de-09a9-4a42-a54c-7a6c436b43dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180308959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.4180308959
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.3334693886
Short name T332
Test name
Test status
Simulation time 16324623 ps
CPU time 0.75 seconds
Started Mar 24 01:12:31 PM PDT 24
Finished Mar 24 01:12:32 PM PDT 24
Peak memory 216564 kb
Host smart-56621e5a-fc39-4bb2-92c1-6e51c0d8088a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334693886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.3334693886
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.2139289135
Short name T152
Test name
Test status
Simulation time 192747397357 ps
CPU time 396.04 seconds
Started Mar 24 01:13:53 PM PDT 24
Finished Mar 24 01:20:29 PM PDT 24
Peak memory 272312 kb
Host smart-ffca5966-463b-4faf-b5bf-c8d67c340440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139289135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.2139289135
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.2851315633
Short name T69
Test name
Test status
Simulation time 217422180709 ps
CPU time 736.47 seconds
Started Mar 24 01:13:58 PM PDT 24
Finished Mar 24 01:26:15 PM PDT 24
Peak memory 272456 kb
Host smart-cea73597-100b-4134-b927-686c020a44ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851315633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.2851315633
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.2995927521
Short name T52
Test name
Test status
Simulation time 324535926 ps
CPU time 1.16 seconds
Started Mar 24 01:12:41 PM PDT 24
Finished Mar 24 01:12:42 PM PDT 24
Peak memory 235648 kb
Host smart-9d98679f-4b84-4b94-92e4-cfb56812d670
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995927521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.2995927521
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.257634800
Short name T33
Test name
Test status
Simulation time 5245591565 ps
CPU time 17.15 seconds
Started Mar 24 01:12:50 PM PDT 24
Finished Mar 24 01:13:07 PM PDT 24
Peak memory 245720 kb
Host smart-3e8e2326-f1ec-4db5-8350-31979fe8887e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257634800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.257634800
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1025862682
Short name T84
Test name
Test status
Simulation time 664582525 ps
CPU time 4.23 seconds
Started Mar 24 12:37:05 PM PDT 24
Finished Mar 24 12:37:14 PM PDT 24
Peak memory 215096 kb
Host smart-9f1640e0-db5c-4860-9f15-e9964e3315f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025862682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
1025862682
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.2722670793
Short name T27
Test name
Test status
Simulation time 28287431700 ps
CPU time 268.52 seconds
Started Mar 24 01:13:40 PM PDT 24
Finished Mar 24 01:18:09 PM PDT 24
Peak memory 267876 kb
Host smart-9db1848a-797b-42f0-96c3-25e4bcb50ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722670793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.2722670793
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.3826886895
Short name T30
Test name
Test status
Simulation time 68620817783 ps
CPU time 363.01 seconds
Started Mar 24 01:14:23 PM PDT 24
Finished Mar 24 01:20:26 PM PDT 24
Peak memory 273356 kb
Host smart-363c8898-0db1-4c3a-af89-00c23d1147f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826886895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.3826886895
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.1801958498
Short name T170
Test name
Test status
Simulation time 90566957862 ps
CPU time 191.83 seconds
Started Mar 24 01:13:55 PM PDT 24
Finished Mar 24 01:17:07 PM PDT 24
Peak memory 267756 kb
Host smart-ae8b4f7f-9dbc-4741-874d-9237c2f1c815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801958498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.1801958498
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1294198787
Short name T101
Test name
Test status
Simulation time 102788814 ps
CPU time 2.59 seconds
Started Mar 24 12:37:09 PM PDT 24
Finished Mar 24 12:37:14 PM PDT 24
Peak memory 214880 kb
Host smart-48564c78-fc96-497c-9708-22bdf0de7a73
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294198787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
1294198787
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.3024326271
Short name T35
Test name
Test status
Simulation time 8674505717 ps
CPU time 110.25 seconds
Started Mar 24 01:13:34 PM PDT 24
Finished Mar 24 01:15:26 PM PDT 24
Peak memory 249576 kb
Host smart-e87f949d-69e2-428f-9b1a-72a1d6bf21fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024326271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.3024326271
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.4255238689
Short name T196
Test name
Test status
Simulation time 116162129853 ps
CPU time 131.06 seconds
Started Mar 24 01:13:40 PM PDT 24
Finished Mar 24 01:15:52 PM PDT 24
Peak memory 254816 kb
Host smart-e4794b0f-567b-4e22-ae30-688ebec2c9be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255238689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.4255238689
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.2033683788
Short name T20
Test name
Test status
Simulation time 105719937876 ps
CPU time 392.69 seconds
Started Mar 24 01:12:54 PM PDT 24
Finished Mar 24 01:19:27 PM PDT 24
Peak memory 266128 kb
Host smart-14e8b72f-665f-421e-a978-cfb0368aee3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033683788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.2033683788
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.3609637941
Short name T130
Test name
Test status
Simulation time 58187650691 ps
CPU time 349.52 seconds
Started Mar 24 01:12:55 PM PDT 24
Finished Mar 24 01:18:45 PM PDT 24
Peak memory 265920 kb
Host smart-8466bcb8-2609-4116-8b46-0d0a2ab14435
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609637941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.3609637941
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.795667508
Short name T221
Test name
Test status
Simulation time 28490985210 ps
CPU time 63.27 seconds
Started Mar 24 01:13:50 PM PDT 24
Finished Mar 24 01:14:53 PM PDT 24
Peak memory 253144 kb
Host smart-091c976d-1728-4a2c-bd7d-648d975c49f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795667508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stres
s_all.795667508
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.3735146754
Short name T18
Test name
Test status
Simulation time 36178086 ps
CPU time 0.72 seconds
Started Mar 24 01:13:36 PM PDT 24
Finished Mar 24 01:13:38 PM PDT 24
Peak memory 205688 kb
Host smart-c7c6f7fc-48d6-4ba5-87c2-1bd94c7fe082
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735146754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
3735146754
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.4082512519
Short name T82
Test name
Test status
Simulation time 1215603909 ps
CPU time 18.83 seconds
Started Mar 24 12:36:39 PM PDT 24
Finished Mar 24 12:37:02 PM PDT 24
Peak memory 215404 kb
Host smart-ea011dad-6221-4935-a716-b789f6080699
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082512519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.4082512519
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.1581991586
Short name T216
Test name
Test status
Simulation time 107847860670 ps
CPU time 534.65 seconds
Started Mar 24 01:14:01 PM PDT 24
Finished Mar 24 01:22:56 PM PDT 24
Peak memory 271704 kb
Host smart-71b2006d-852f-486d-9b40-7b883cb2ec74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581991586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.1581991586
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.3975912820
Short name T148
Test name
Test status
Simulation time 32516023797 ps
CPU time 266.31 seconds
Started Mar 24 01:13:38 PM PDT 24
Finished Mar 24 01:18:04 PM PDT 24
Peak memory 249620 kb
Host smart-28e671dd-9589-49bf-8a53-1555b31ad2c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975912820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.3975912820
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.929573776
Short name T32
Test name
Test status
Simulation time 26388707761 ps
CPU time 20.14 seconds
Started Mar 24 01:13:56 PM PDT 24
Finished Mar 24 01:14:16 PM PDT 24
Peak memory 234012 kb
Host smart-c3d58c6f-83ac-4243-b159-94335d3b71eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929573776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.929573776
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1654354201
Short name T91
Test name
Test status
Simulation time 46081142 ps
CPU time 3.42 seconds
Started Mar 24 12:36:56 PM PDT 24
Finished Mar 24 12:37:00 PM PDT 24
Peak memory 215184 kb
Host smart-382e8d72-a3ce-47c6-94cc-41de21fca845
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654354201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.1
654354201
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.1833120730
Short name T36
Test name
Test status
Simulation time 28898744087 ps
CPU time 97.64 seconds
Started Mar 24 01:13:06 PM PDT 24
Finished Mar 24 01:14:49 PM PDT 24
Peak memory 257708 kb
Host smart-e4eaf738-9343-4d87-a895-91db2a01bea3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833120730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.1833120730
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.1980485788
Short name T629
Test name
Test status
Simulation time 146227770651 ps
CPU time 244.97 seconds
Started Mar 24 01:12:51 PM PDT 24
Finished Mar 24 01:16:57 PM PDT 24
Peak memory 249524 kb
Host smart-ff80d29b-66e8-4c7e-b1cc-dcb02a604513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980485788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.1980485788
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.4043758444
Short name T116
Test name
Test status
Simulation time 37801699328 ps
CPU time 156.38 seconds
Started Mar 24 01:13:03 PM PDT 24
Finished Mar 24 01:15:44 PM PDT 24
Peak memory 250784 kb
Host smart-5e388a66-6e0f-46af-be19-cb89e5a4e218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043758444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.4043758444
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.3932182789
Short name T244
Test name
Test status
Simulation time 38448847336 ps
CPU time 73.68 seconds
Started Mar 24 01:13:07 PM PDT 24
Finished Mar 24 01:14:21 PM PDT 24
Peak memory 248960 kb
Host smart-68f79148-0a0d-4326-8341-f6696546a36b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932182789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.3932182789
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.1681627462
Short name T257
Test name
Test status
Simulation time 2229668452 ps
CPU time 6.23 seconds
Started Mar 24 01:12:37 PM PDT 24
Finished Mar 24 01:12:43 PM PDT 24
Peak memory 216564 kb
Host smart-8da4628d-b271-4e06-89f9-b377805440b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681627462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.1681627462
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.4077904763
Short name T40
Test name
Test status
Simulation time 187618006327 ps
CPU time 1468.91 seconds
Started Mar 24 01:14:26 PM PDT 24
Finished Mar 24 01:38:55 PM PDT 24
Peak memory 297556 kb
Host smart-25f73b48-0994-46ac-b63e-11efae56cc6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077904763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.4077904763
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.3511023018
Short name T76
Test name
Test status
Simulation time 7798750462 ps
CPU time 90.04 seconds
Started Mar 24 01:13:49 PM PDT 24
Finished Mar 24 01:15:19 PM PDT 24
Peak memory 259360 kb
Host smart-efaad54c-8714-40e1-aa0f-c076445fe06d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511023018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.3511023018
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1100005219
Short name T142
Test name
Test status
Simulation time 207289952 ps
CPU time 13.3 seconds
Started Mar 24 12:37:01 PM PDT 24
Finished Mar 24 12:37:16 PM PDT 24
Peak memory 215376 kb
Host smart-c1c7ba58-3b29-472e-84ed-1078de0a0412
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100005219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.1100005219
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.4290737962
Short name T212
Test name
Test status
Simulation time 57238900931 ps
CPU time 151.89 seconds
Started Mar 24 01:12:40 PM PDT 24
Finished Mar 24 01:15:13 PM PDT 24
Peak memory 264580 kb
Host smart-b1fb791b-eccb-43fc-a2d6-7790112a2f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290737962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.4290737962
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.3140342067
Short name T180
Test name
Test status
Simulation time 37549465816 ps
CPU time 21.64 seconds
Started Mar 24 01:13:00 PM PDT 24
Finished Mar 24 01:13:22 PM PDT 24
Peak memory 224836 kb
Host smart-0fcb1ca2-ff79-400a-ae71-7f933445c50c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140342067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.3140342067
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.2348178258
Short name T238
Test name
Test status
Simulation time 11158231678 ps
CPU time 176.87 seconds
Started Mar 24 01:13:04 PM PDT 24
Finished Mar 24 01:16:02 PM PDT 24
Peak memory 268060 kb
Host smart-209fb3d8-7829-4997-8a63-6fdf2f95d4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348178258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.2348178258
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.4122647303
Short name T231
Test name
Test status
Simulation time 96059697005 ps
CPU time 144.84 seconds
Started Mar 24 01:13:35 PM PDT 24
Finished Mar 24 01:16:00 PM PDT 24
Peak memory 259704 kb
Host smart-c51d3179-36e0-486c-89ed-924608b3f2ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122647303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.4122647303
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.983017797
Short name T239
Test name
Test status
Simulation time 1266408783 ps
CPU time 3.83 seconds
Started Mar 24 01:13:38 PM PDT 24
Finished Mar 24 01:13:42 PM PDT 24
Peak memory 221200 kb
Host smart-5fb25cd5-bd2a-46e8-b203-d8b9b20d8bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983017797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap
.983017797
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.1194774942
Short name T220
Test name
Test status
Simulation time 19946553668 ps
CPU time 189.78 seconds
Started Mar 24 01:14:26 PM PDT 24
Finished Mar 24 01:17:37 PM PDT 24
Peak memory 249532 kb
Host smart-70fee279-0a92-4a94-969c-197cd7e5c648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194774942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.1194774942
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3537518923
Short name T70
Test name
Test status
Simulation time 143395409 ps
CPU time 1.2 seconds
Started Mar 24 12:36:52 PM PDT 24
Finished Mar 24 12:36:55 PM PDT 24
Peak memory 206732 kb
Host smart-5a88830e-150a-40ed-83a5-b09eeb9d3b91
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537518923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.3537518923
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2100193910
Short name T80
Test name
Test status
Simulation time 53140293 ps
CPU time 3.39 seconds
Started Mar 24 12:36:37 PM PDT 24
Finished Mar 24 12:36:45 PM PDT 24
Peak memory 215100 kb
Host smart-cac4e0e8-233f-4807-b62a-05f5d4406d52
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100193910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
2100193910
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3063940805
Short name T987
Test name
Test status
Simulation time 6031683754 ps
CPU time 25.64 seconds
Started Mar 24 12:36:51 PM PDT 24
Finished Mar 24 12:37:16 PM PDT 24
Peak memory 206812 kb
Host smart-30fb1e1c-6000-4d64-b779-6744a70c1435
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063940805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.3063940805
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.4141743367
Short name T1038
Test name
Test status
Simulation time 174274917 ps
CPU time 1.69 seconds
Started Mar 24 12:36:45 PM PDT 24
Finished Mar 24 12:36:47 PM PDT 24
Peak memory 215000 kb
Host smart-ad19797b-d75d-41ed-8528-729bc2818b79
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141743367 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.4141743367
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3494749040
Short name T125
Test name
Test status
Simulation time 479913540 ps
CPU time 1.39 seconds
Started Mar 24 12:37:07 PM PDT 24
Finished Mar 24 12:37:13 PM PDT 24
Peak memory 206760 kb
Host smart-46d8c1fe-9799-4315-a0e1-80029ca0b40a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494749040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.3
494749040
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2022176704
Short name T1024
Test name
Test status
Simulation time 55038455 ps
CPU time 0.76 seconds
Started Mar 24 12:37:04 PM PDT 24
Finished Mar 24 12:37:09 PM PDT 24
Peak memory 203068 kb
Host smart-13bec536-3980-469b-a832-f5309c4bf5d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022176704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2
022176704
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2097640590
Short name T112
Test name
Test status
Simulation time 89631727 ps
CPU time 2.18 seconds
Started Mar 24 12:36:36 PM PDT 24
Finished Mar 24 12:36:39 PM PDT 24
Peak memory 214936 kb
Host smart-925ddeef-49d9-4a31-a442-ec751b2f8454
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097640590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.2097640590
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3796204441
Short name T982
Test name
Test status
Simulation time 38484500 ps
CPU time 0.65 seconds
Started Mar 24 12:37:06 PM PDT 24
Finished Mar 24 12:37:09 PM PDT 24
Peak memory 203048 kb
Host smart-39f55035-49b8-4149-b0c5-f23b659c548e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796204441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.3796204441
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2845131477
Short name T998
Test name
Test status
Simulation time 47949044 ps
CPU time 1.8 seconds
Started Mar 24 12:36:44 PM PDT 24
Finished Mar 24 12:36:46 PM PDT 24
Peak memory 214948 kb
Host smart-5cb0cb83-e123-48c0-b983-6f2f4a2c4c5e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845131477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.2845131477
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.625266216
Short name T1071
Test name
Test status
Simulation time 600425441 ps
CPU time 14.82 seconds
Started Mar 24 12:36:42 PM PDT 24
Finished Mar 24 12:36:58 PM PDT 24
Peak memory 215288 kb
Host smart-45bf9d67-0bc9-4b2e-9a4e-a6b0ce92ff50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625266216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_
tl_intg_err.625266216
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.847649575
Short name T1037
Test name
Test status
Simulation time 1262017013 ps
CPU time 15.05 seconds
Started Mar 24 12:36:44 PM PDT 24
Finished Mar 24 12:36:59 PM PDT 24
Peak memory 214876 kb
Host smart-36f9c3a8-5d38-4797-ae21-0256c52a9306
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847649575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_aliasing.847649575
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2420362209
Short name T996
Test name
Test status
Simulation time 2420855328 ps
CPU time 12.02 seconds
Started Mar 24 12:36:37 PM PDT 24
Finished Mar 24 12:36:54 PM PDT 24
Peak memory 206964 kb
Host smart-acc1ca56-7529-46ea-9a24-7c530274972f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420362209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.2420362209
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1780331867
Short name T72
Test name
Test status
Simulation time 99544038 ps
CPU time 1.22 seconds
Started Mar 24 12:37:08 PM PDT 24
Finished Mar 24 12:37:11 PM PDT 24
Peak memory 206688 kb
Host smart-c0db9d19-b0fa-470f-acf6-45a82b14e1b6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780331867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.1780331867
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2052534378
Short name T1036
Test name
Test status
Simulation time 199233892 ps
CPU time 1.61 seconds
Started Mar 24 12:36:44 PM PDT 24
Finished Mar 24 12:36:46 PM PDT 24
Peak memory 216036 kb
Host smart-da4e53af-3be2-4752-ae85-6729cedb246d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052534378 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.2052534378
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1442980229
Short name T1079
Test name
Test status
Simulation time 39429679 ps
CPU time 1.19 seconds
Started Mar 24 12:37:01 PM PDT 24
Finished Mar 24 12:37:03 PM PDT 24
Peak memory 206732 kb
Host smart-8e7bcbbb-e471-4120-a34c-e41c3b85bbcc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442980229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.1
442980229
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3236982807
Short name T1066
Test name
Test status
Simulation time 37325697 ps
CPU time 0.71 seconds
Started Mar 24 12:36:44 PM PDT 24
Finished Mar 24 12:36:44 PM PDT 24
Peak memory 203056 kb
Host smart-fff13d6b-3ed5-44c6-9c2a-158ca70c14f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236982807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.3
236982807
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3257647648
Short name T100
Test name
Test status
Simulation time 162798960 ps
CPU time 1.79 seconds
Started Mar 24 12:36:48 PM PDT 24
Finished Mar 24 12:36:50 PM PDT 24
Peak memory 214964 kb
Host smart-b4f1ec9c-b5be-4bc2-9e49-05c5317618c2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257647648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.3257647648
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.694333730
Short name T1035
Test name
Test status
Simulation time 77264555 ps
CPU time 0.65 seconds
Started Mar 24 12:36:49 PM PDT 24
Finished Mar 24 12:36:50 PM PDT 24
Peak memory 203044 kb
Host smart-7302c923-378e-4d07-981d-25b06a612290
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694333730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem
_walk.694333730
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1411833379
Short name T991
Test name
Test status
Simulation time 622854185 ps
CPU time 3.98 seconds
Started Mar 24 12:37:00 PM PDT 24
Finished Mar 24 12:37:13 PM PDT 24
Peak memory 214960 kb
Host smart-9fb7c63e-029a-4e88-b60f-4ca56566787b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411833379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.1411833379
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2466286286
Short name T1081
Test name
Test status
Simulation time 337301712 ps
CPU time 4.04 seconds
Started Mar 24 12:37:04 PM PDT 24
Finished Mar 24 12:37:13 PM PDT 24
Peak memory 216020 kb
Host smart-d94a3646-774e-4d3f-ab57-89eda6084699
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466286286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.2
466286286
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3592799822
Short name T1008
Test name
Test status
Simulation time 99275359 ps
CPU time 6.39 seconds
Started Mar 24 12:36:46 PM PDT 24
Finished Mar 24 12:36:54 PM PDT 24
Peak memory 215032 kb
Host smart-5885c4a7-d0a4-44b6-b315-1ba9be29fba8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592799822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.3592799822
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1592458408
Short name T1094
Test name
Test status
Simulation time 121641483 ps
CPU time 3.71 seconds
Started Mar 24 12:36:52 PM PDT 24
Finished Mar 24 12:36:57 PM PDT 24
Peak memory 216836 kb
Host smart-e80786a2-d5dc-4581-98a8-78b15d90b0ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592458408 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.1592458408
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2604317347
Short name T1025
Test name
Test status
Simulation time 25229309 ps
CPU time 0.73 seconds
Started Mar 24 12:36:47 PM PDT 24
Finished Mar 24 12:36:49 PM PDT 24
Peak memory 203040 kb
Host smart-1d270334-d859-47eb-be80-7edafdc0e164
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604317347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
2604317347
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1357034900
Short name T1077
Test name
Test status
Simulation time 26262303 ps
CPU time 1.6 seconds
Started Mar 24 12:37:13 PM PDT 24
Finished Mar 24 12:37:15 PM PDT 24
Peak memory 206688 kb
Host smart-c4a6bf2b-ef5f-4302-86b5-08b4181e7ca2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357034900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.1357034900
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1391234495
Short name T144
Test name
Test status
Simulation time 599223647 ps
CPU time 19.26 seconds
Started Mar 24 12:37:01 PM PDT 24
Finished Mar 24 12:37:21 PM PDT 24
Peak memory 222160 kb
Host smart-22317aa7-faef-41bd-9916-0d33a683be98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391234495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.1391234495
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3069898989
Short name T48
Test name
Test status
Simulation time 623302673 ps
CPU time 4.09 seconds
Started Mar 24 12:36:59 PM PDT 24
Finished Mar 24 12:37:04 PM PDT 24
Peak memory 216700 kb
Host smart-39dd7c42-e353-441c-9c0e-82c03cc08dec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069898989 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.3069898989
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2915818697
Short name T102
Test name
Test status
Simulation time 101725196 ps
CPU time 2.48 seconds
Started Mar 24 12:37:11 PM PDT 24
Finished Mar 24 12:37:14 PM PDT 24
Peak memory 214920 kb
Host smart-c7fa0618-f9e2-41b0-9370-5e5f07718bd6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915818697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
2915818697
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.339783356
Short name T1059
Test name
Test status
Simulation time 14901163 ps
CPU time 0.73 seconds
Started Mar 24 12:37:02 PM PDT 24
Finished Mar 24 12:37:03 PM PDT 24
Peak memory 203128 kb
Host smart-a354cb48-25b9-4d5c-808c-224db927e243
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339783356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.339783356
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3154068540
Short name T1015
Test name
Test status
Simulation time 226135277 ps
CPU time 4.26 seconds
Started Mar 24 12:37:10 PM PDT 24
Finished Mar 24 12:37:16 PM PDT 24
Peak memory 214888 kb
Host smart-6f065f78-118b-48c4-8d00-eaf7586a24c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154068540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.3154068540
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3830516940
Short name T1072
Test name
Test status
Simulation time 49400384 ps
CPU time 3.09 seconds
Started Mar 24 12:37:21 PM PDT 24
Finished Mar 24 12:37:24 PM PDT 24
Peak memory 215124 kb
Host smart-79b09d61-bfb8-4213-99b7-4c543bf7cdca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830516940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3830516940
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3494650248
Short name T1021
Test name
Test status
Simulation time 3234962597 ps
CPU time 17.63 seconds
Started Mar 24 12:37:16 PM PDT 24
Finished Mar 24 12:37:34 PM PDT 24
Peak memory 215060 kb
Host smart-537de61d-e27f-49fd-98d8-380767a2b685
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494650248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.3494650248
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3116351355
Short name T1027
Test name
Test status
Simulation time 218223092 ps
CPU time 4.14 seconds
Started Mar 24 12:37:03 PM PDT 24
Finished Mar 24 12:37:08 PM PDT 24
Peak memory 217056 kb
Host smart-e5812df5-f425-48e3-a447-e991bc0cb97c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116351355 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3116351355
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1636381515
Short name T108
Test name
Test status
Simulation time 101816668 ps
CPU time 1.74 seconds
Started Mar 24 12:36:59 PM PDT 24
Finished Mar 24 12:37:02 PM PDT 24
Peak memory 206720 kb
Host smart-bad24919-5dab-496a-89aa-e422d6a0103b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636381515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
1636381515
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1189461697
Short name T1075
Test name
Test status
Simulation time 48018266 ps
CPU time 0.75 seconds
Started Mar 24 12:36:54 PM PDT 24
Finished Mar 24 12:36:56 PM PDT 24
Peak memory 203428 kb
Host smart-a9688209-886c-48fa-a7df-619ee4e117d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189461697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
1189461697
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1549017628
Short name T1019
Test name
Test status
Simulation time 391453824 ps
CPU time 2.79 seconds
Started Mar 24 12:37:11 PM PDT 24
Finished Mar 24 12:37:15 PM PDT 24
Peak memory 214992 kb
Host smart-ad3eef13-bf6d-41fe-aac4-cb4358cd5760
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549017628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.1549017628
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.701033059
Short name T83
Test name
Test status
Simulation time 1917035200 ps
CPU time 3.94 seconds
Started Mar 24 12:37:02 PM PDT 24
Finished Mar 24 12:37:06 PM PDT 24
Peak memory 214960 kb
Host smart-d13e41a3-b99c-4a45-9378-040403231837
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701033059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.701033059
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.860918872
Short name T1064
Test name
Test status
Simulation time 300239794 ps
CPU time 7.48 seconds
Started Mar 24 12:37:09 PM PDT 24
Finished Mar 24 12:37:19 PM PDT 24
Peak memory 214880 kb
Host smart-ef7570ea-9347-4645-9840-7c0b0439ca98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860918872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device
_tl_intg_err.860918872
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.3468052409
Short name T94
Test name
Test status
Simulation time 121355966 ps
CPU time 1.85 seconds
Started Mar 24 12:37:02 PM PDT 24
Finished Mar 24 12:37:04 PM PDT 24
Peak memory 215000 kb
Host smart-a021fd73-a829-463f-9399-6a2185b60e40
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468052409 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.3468052409
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2318501921
Short name T1031
Test name
Test status
Simulation time 38240883 ps
CPU time 2.46 seconds
Started Mar 24 12:36:54 PM PDT 24
Finished Mar 24 12:36:58 PM PDT 24
Peak memory 206828 kb
Host smart-bd9b181d-05aa-4d70-adb9-1e7a871a60f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318501921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
2318501921
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3957023040
Short name T1017
Test name
Test status
Simulation time 41462743 ps
CPU time 0.73 seconds
Started Mar 24 12:37:10 PM PDT 24
Finished Mar 24 12:37:12 PM PDT 24
Peak memory 203060 kb
Host smart-7e00f856-7640-45e2-9a63-802d99faf4e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957023040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
3957023040
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3634525951
Short name T1073
Test name
Test status
Simulation time 718610833 ps
CPU time 3.86 seconds
Started Mar 24 12:36:55 PM PDT 24
Finished Mar 24 12:37:01 PM PDT 24
Peak memory 214904 kb
Host smart-9ef46394-a6cb-47e5-9855-1ad5217af1d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634525951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.3634525951
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1544862148
Short name T79
Test name
Test status
Simulation time 146535316 ps
CPU time 2.02 seconds
Started Mar 24 12:36:53 PM PDT 24
Finished Mar 24 12:36:58 PM PDT 24
Peak memory 215020 kb
Host smart-d37e8d5b-e7d4-4f2f-95a7-57fb07679abd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544862148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
1544862148
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.795078949
Short name T96
Test name
Test status
Simulation time 3416491223 ps
CPU time 21.2 seconds
Started Mar 24 12:37:06 PM PDT 24
Finished Mar 24 12:37:31 PM PDT 24
Peak memory 214960 kb
Host smart-5def6f2a-5c2c-492b-9f2a-d6732e0d70af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795078949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device
_tl_intg_err.795078949
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2198477721
Short name T1039
Test name
Test status
Simulation time 23410874 ps
CPU time 1.63 seconds
Started Mar 24 12:36:52 PM PDT 24
Finished Mar 24 12:36:56 PM PDT 24
Peak memory 215028 kb
Host smart-caccd1b1-4118-49a0-9424-22fc470daeb4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198477721 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.2198477721
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3987278443
Short name T106
Test name
Test status
Simulation time 338291522 ps
CPU time 2.21 seconds
Started Mar 24 12:37:02 PM PDT 24
Finished Mar 24 12:37:04 PM PDT 24
Peak memory 206760 kb
Host smart-cb3036ef-777f-4d51-945b-c2d577468785
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987278443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
3987278443
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2328437078
Short name T1085
Test name
Test status
Simulation time 49274740 ps
CPU time 0.69 seconds
Started Mar 24 12:37:18 PM PDT 24
Finished Mar 24 12:37:22 PM PDT 24
Peak memory 203048 kb
Host smart-5e4be8fc-3027-43f1-a9e4-fdb3698522e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328437078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
2328437078
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1868271774
Short name T1042
Test name
Test status
Simulation time 857175139 ps
CPU time 1.92 seconds
Started Mar 24 12:36:55 PM PDT 24
Finished Mar 24 12:36:58 PM PDT 24
Peak memory 214924 kb
Host smart-7fbc20f4-fcaa-475b-9244-53e308a265f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868271774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.1868271774
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3779011792
Short name T92
Test name
Test status
Simulation time 40577273 ps
CPU time 2.85 seconds
Started Mar 24 12:37:09 PM PDT 24
Finished Mar 24 12:37:15 PM PDT 24
Peak memory 215192 kb
Host smart-49f237cc-87b0-4c97-a931-cf8a8614559f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779011792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
3779011792
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2548057598
Short name T1088
Test name
Test status
Simulation time 1598756220 ps
CPU time 20.66 seconds
Started Mar 24 12:37:05 PM PDT 24
Finished Mar 24 12:37:29 PM PDT 24
Peak memory 214980 kb
Host smart-ab7b6266-bef5-48c2-9e2c-9217b25c65d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548057598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.2548057598
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3020462700
Short name T1051
Test name
Test status
Simulation time 59189447 ps
CPU time 4.01 seconds
Started Mar 24 12:37:12 PM PDT 24
Finished Mar 24 12:37:16 PM PDT 24
Peak memory 216224 kb
Host smart-b57aaed7-72b9-4402-9015-b58c735969bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020462700 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.3020462700
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1560124741
Short name T1058
Test name
Test status
Simulation time 72692165 ps
CPU time 1.35 seconds
Started Mar 24 12:37:06 PM PDT 24
Finished Mar 24 12:37:10 PM PDT 24
Peak memory 206744 kb
Host smart-dbb2aff5-7da2-4058-8acc-4f8423613008
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560124741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
1560124741
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2875130451
Short name T1061
Test name
Test status
Simulation time 14885828 ps
CPU time 0.79 seconds
Started Mar 24 12:37:02 PM PDT 24
Finished Mar 24 12:37:03 PM PDT 24
Peak memory 203060 kb
Host smart-878665ee-0daa-4c03-ba8a-482be6598387
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875130451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
2875130451
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3581795747
Short name T1057
Test name
Test status
Simulation time 218274442 ps
CPU time 2.71 seconds
Started Mar 24 12:37:11 PM PDT 24
Finished Mar 24 12:37:14 PM PDT 24
Peak memory 214956 kb
Host smart-92f6b8d5-6b74-4e55-9d8f-1b200af0fd71
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581795747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.3581795747
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1911431013
Short name T135
Test name
Test status
Simulation time 248177416 ps
CPU time 1.81 seconds
Started Mar 24 12:36:58 PM PDT 24
Finished Mar 24 12:37:00 PM PDT 24
Peak memory 215244 kb
Host smart-1909dfdc-a3e8-42a3-a754-f9bda62d9251
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911431013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
1911431013
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.279775681
Short name T1052
Test name
Test status
Simulation time 590673720 ps
CPU time 17.54 seconds
Started Mar 24 12:37:02 PM PDT 24
Finished Mar 24 12:37:20 PM PDT 24
Peak memory 214892 kb
Host smart-ddb49f2c-c6b8-4393-a198-113b33d0ccbd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279775681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device
_tl_intg_err.279775681
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2173246316
Short name T1040
Test name
Test status
Simulation time 161666936 ps
CPU time 2.73 seconds
Started Mar 24 12:37:13 PM PDT 24
Finished Mar 24 12:37:16 PM PDT 24
Peak memory 216592 kb
Host smart-79d2a636-b851-488b-bd9c-2a43f3195a78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173246316 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.2173246316
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.247075016
Short name T107
Test name
Test status
Simulation time 311659622 ps
CPU time 2.12 seconds
Started Mar 24 12:37:08 PM PDT 24
Finished Mar 24 12:37:12 PM PDT 24
Peak memory 214984 kb
Host smart-8a1bdeb6-2616-4c54-9843-f36850bb73f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247075016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.247075016
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.185838308
Short name T1001
Test name
Test status
Simulation time 38892587 ps
CPU time 0.69 seconds
Started Mar 24 12:36:59 PM PDT 24
Finished Mar 24 12:37:01 PM PDT 24
Peak memory 202936 kb
Host smart-7909cae5-f376-4ed0-bff7-132ac491e62a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185838308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.185838308
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1171401453
Short name T124
Test name
Test status
Simulation time 132907767 ps
CPU time 2.9 seconds
Started Mar 24 12:37:04 PM PDT 24
Finished Mar 24 12:37:17 PM PDT 24
Peak memory 214924 kb
Host smart-224ec9f5-60ea-4de2-b1e5-5496ad5b1bcf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171401453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.1171401453
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1087367890
Short name T90
Test name
Test status
Simulation time 210746322 ps
CPU time 3.45 seconds
Started Mar 24 12:37:01 PM PDT 24
Finished Mar 24 12:37:06 PM PDT 24
Peak memory 215044 kb
Host smart-fec01622-d214-4158-b3a4-4b8dae1a03fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087367890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
1087367890
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.719461416
Short name T1092
Test name
Test status
Simulation time 126762921 ps
CPU time 3.8 seconds
Started Mar 24 12:37:09 PM PDT 24
Finished Mar 24 12:37:15 PM PDT 24
Peak memory 216580 kb
Host smart-646ac4aa-e538-439e-9787-940601602ae0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719461416 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.719461416
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1418978042
Short name T113
Test name
Test status
Simulation time 19811522 ps
CPU time 1.15 seconds
Started Mar 24 12:37:09 PM PDT 24
Finished Mar 24 12:37:13 PM PDT 24
Peak memory 206756 kb
Host smart-9ffc2020-5f1f-4e0d-bd92-254867c76456
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418978042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
1418978042
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1549870876
Short name T992
Test name
Test status
Simulation time 18774429 ps
CPU time 0.71 seconds
Started Mar 24 12:37:06 PM PDT 24
Finished Mar 24 12:37:12 PM PDT 24
Peak memory 203060 kb
Host smart-0fa4c702-b34f-4bc9-81c5-a3f86687bb5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549870876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
1549870876
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1654067078
Short name T981
Test name
Test status
Simulation time 244221212 ps
CPU time 1.86 seconds
Started Mar 24 12:37:01 PM PDT 24
Finished Mar 24 12:37:04 PM PDT 24
Peak memory 214968 kb
Host smart-eaae85a3-ac37-4672-82f2-fa60abbe6059
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654067078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.1654067078
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.350194865
Short name T86
Test name
Test status
Simulation time 182272095 ps
CPU time 3.04 seconds
Started Mar 24 12:37:07 PM PDT 24
Finished Mar 24 12:37:13 PM PDT 24
Peak memory 214996 kb
Host smart-9b6c66fc-9865-4d06-bc0f-7049f018fb84
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350194865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.350194865
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1114452825
Short name T47
Test name
Test status
Simulation time 340447513 ps
CPU time 12.76 seconds
Started Mar 24 12:37:06 PM PDT 24
Finished Mar 24 12:37:23 PM PDT 24
Peak memory 215432 kb
Host smart-07dfb977-f618-4edc-b573-f60e0845822e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114452825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.1114452825
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3006572036
Short name T1044
Test name
Test status
Simulation time 530636146 ps
CPU time 2.04 seconds
Started Mar 24 12:37:01 PM PDT 24
Finished Mar 24 12:37:04 PM PDT 24
Peak memory 216032 kb
Host smart-e82515a3-dd41-4d4f-82d8-0c537ac21e6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006572036 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.3006572036
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2428324141
Short name T109
Test name
Test status
Simulation time 29912569 ps
CPU time 1.93 seconds
Started Mar 24 12:36:59 PM PDT 24
Finished Mar 24 12:37:02 PM PDT 24
Peak memory 214972 kb
Host smart-0b925110-2418-4faf-97e0-4792cfb45e37
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428324141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
2428324141
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3764567688
Short name T985
Test name
Test status
Simulation time 17011364 ps
CPU time 0.71 seconds
Started Mar 24 12:37:15 PM PDT 24
Finished Mar 24 12:37:16 PM PDT 24
Peak memory 203152 kb
Host smart-042ca274-07de-4b1a-8880-442ab24df2c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764567688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
3764567688
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1319824960
Short name T1054
Test name
Test status
Simulation time 58933696 ps
CPU time 3.59 seconds
Started Mar 24 12:37:05 PM PDT 24
Finished Mar 24 12:37:13 PM PDT 24
Peak memory 214940 kb
Host smart-64cf2b1c-bbb3-4601-baab-0f3396a3fc1b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319824960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.1319824960
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3669023373
Short name T88
Test name
Test status
Simulation time 124712247 ps
CPU time 3.27 seconds
Started Mar 24 12:37:09 PM PDT 24
Finished Mar 24 12:37:15 PM PDT 24
Peak memory 215056 kb
Host smart-12084a9f-f3d0-4c99-bb4d-f4683df36164
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669023373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
3669023373
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2674759074
Short name T126
Test name
Test status
Simulation time 963629367 ps
CPU time 21.79 seconds
Started Mar 24 12:36:57 PM PDT 24
Finished Mar 24 12:37:19 PM PDT 24
Peak memory 215068 kb
Host smart-ee8430a9-24dc-4c01-9763-e704463736e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674759074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.2674759074
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.935262157
Short name T995
Test name
Test status
Simulation time 523052785 ps
CPU time 2.88 seconds
Started Mar 24 12:37:15 PM PDT 24
Finished Mar 24 12:37:18 PM PDT 24
Peak memory 217488 kb
Host smart-3e29eae0-12b4-4998-9235-28df2fad05f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935262157 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.935262157
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1866648462
Short name T1049
Test name
Test status
Simulation time 157999560 ps
CPU time 1.2 seconds
Started Mar 24 12:37:28 PM PDT 24
Finished Mar 24 12:37:29 PM PDT 24
Peak memory 206704 kb
Host smart-3a8f67db-b106-4101-99cf-973c9966e192
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866648462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
1866648462
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.654751717
Short name T1023
Test name
Test status
Simulation time 38481018 ps
CPU time 0.73 seconds
Started Mar 24 12:37:14 PM PDT 24
Finished Mar 24 12:37:15 PM PDT 24
Peak memory 203064 kb
Host smart-e8f2c585-f1b2-4a62-a7ff-5923dcf9710f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654751717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.654751717
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1050642344
Short name T1050
Test name
Test status
Simulation time 188323400 ps
CPU time 3.96 seconds
Started Mar 24 12:37:22 PM PDT 24
Finished Mar 24 12:37:27 PM PDT 24
Peak memory 214908 kb
Host smart-9de0a5e3-ed3c-4f80-b73d-b6d30166d19c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050642344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.1050642344
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3169891755
Short name T1086
Test name
Test status
Simulation time 115117440 ps
CPU time 7.68 seconds
Started Mar 24 12:36:54 PM PDT 24
Finished Mar 24 12:37:03 PM PDT 24
Peak memory 206768 kb
Host smart-42cc3e83-82ea-451c-9663-af5ee7da8a5b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169891755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.3169891755
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.4257293114
Short name T1067
Test name
Test status
Simulation time 3764715850 ps
CPU time 12.57 seconds
Started Mar 24 12:36:52 PM PDT 24
Finished Mar 24 12:37:05 PM PDT 24
Peak memory 214920 kb
Host smart-e212c032-823a-41ff-936b-36deb7718e56
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257293114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.4257293114
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1004973360
Short name T1083
Test name
Test status
Simulation time 23589809 ps
CPU time 0.99 seconds
Started Mar 24 12:36:55 PM PDT 24
Finished Mar 24 12:36:57 PM PDT 24
Peak memory 206500 kb
Host smart-ea6000c7-6374-453e-b86c-77c3ddd64c86
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004973360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.1004973360
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3166849728
Short name T1026
Test name
Test status
Simulation time 28419600 ps
CPU time 1.89 seconds
Started Mar 24 12:36:45 PM PDT 24
Finished Mar 24 12:36:47 PM PDT 24
Peak memory 215040 kb
Host smart-2156ce87-e57f-486f-8e28-82f73ad82f6c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166849728 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.3166849728
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2334819842
Short name T1012
Test name
Test status
Simulation time 42568778 ps
CPU time 2.77 seconds
Started Mar 24 12:36:43 PM PDT 24
Finished Mar 24 12:36:51 PM PDT 24
Peak memory 214908 kb
Host smart-9c6d199d-14bf-4cf1-a485-d557832d8af3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334819842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.2
334819842
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2319012017
Short name T997
Test name
Test status
Simulation time 11152539 ps
CPU time 0.72 seconds
Started Mar 24 12:36:49 PM PDT 24
Finished Mar 24 12:36:55 PM PDT 24
Peak memory 203040 kb
Host smart-f7b8be05-b0f4-46ff-827d-fd125bcaba67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319012017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.2
319012017
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3830286420
Short name T110
Test name
Test status
Simulation time 61320211 ps
CPU time 2.15 seconds
Started Mar 24 12:36:41 PM PDT 24
Finished Mar 24 12:36:45 PM PDT 24
Peak memory 214844 kb
Host smart-9a0fd06f-56ce-443e-b5f7-b06287d9d209
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830286420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.3830286420
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2091326148
Short name T1053
Test name
Test status
Simulation time 14191424 ps
CPU time 0.66 seconds
Started Mar 24 12:36:52 PM PDT 24
Finished Mar 24 12:36:55 PM PDT 24
Peak memory 203040 kb
Host smart-54e1c222-f8d7-4d89-a4fa-9e5397a61c10
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091326148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.2091326148
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.4203452776
Short name T999
Test name
Test status
Simulation time 102407182 ps
CPU time 1.64 seconds
Started Mar 24 12:37:02 PM PDT 24
Finished Mar 24 12:37:04 PM PDT 24
Peak memory 214888 kb
Host smart-1d40ef6e-b2f0-4b87-9325-e1a612a4c84d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203452776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.4203452776
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2402542655
Short name T87
Test name
Test status
Simulation time 57744327 ps
CPU time 3.59 seconds
Started Mar 24 12:36:55 PM PDT 24
Finished Mar 24 12:37:04 PM PDT 24
Peak memory 215068 kb
Host smart-be15c36f-8fde-404e-8390-ee7a98476c29
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402542655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.2
402542655
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1068807593
Short name T140
Test name
Test status
Simulation time 4274917971 ps
CPU time 19.79 seconds
Started Mar 24 12:36:59 PM PDT 24
Finished Mar 24 12:37:20 PM PDT 24
Peak memory 215056 kb
Host smart-b261ff45-9fb7-436b-9b69-1bee296ecf43
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068807593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.1068807593
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.4140504643
Short name T1006
Test name
Test status
Simulation time 12997884 ps
CPU time 0.68 seconds
Started Mar 24 12:37:11 PM PDT 24
Finished Mar 24 12:37:12 PM PDT 24
Peak memory 203040 kb
Host smart-7ad85dfe-a690-4f16-8656-2e1bcd2b4395
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140504643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
4140504643
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.759787231
Short name T980
Test name
Test status
Simulation time 179065335 ps
CPU time 0.73 seconds
Started Mar 24 12:37:03 PM PDT 24
Finished Mar 24 12:37:05 PM PDT 24
Peak memory 203064 kb
Host smart-d4cae21c-a02c-4d9c-823d-16dd2c24bd40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759787231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.759787231
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3842924042
Short name T1041
Test name
Test status
Simulation time 19187420 ps
CPU time 0.71 seconds
Started Mar 24 12:37:22 PM PDT 24
Finished Mar 24 12:37:23 PM PDT 24
Peak memory 203540 kb
Host smart-2ab9552f-c69b-43eb-82bd-f1c21ae278c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842924042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
3842924042
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1200660466
Short name T1065
Test name
Test status
Simulation time 44555860 ps
CPU time 0.73 seconds
Started Mar 24 12:37:18 PM PDT 24
Finished Mar 24 12:37:21 PM PDT 24
Peak memory 203060 kb
Host smart-990ecf7d-3391-4dc1-a2f0-e915ce21f4a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200660466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
1200660466
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2556816901
Short name T1029
Test name
Test status
Simulation time 18281328 ps
CPU time 0.74 seconds
Started Mar 24 12:37:02 PM PDT 24
Finished Mar 24 12:37:03 PM PDT 24
Peak memory 203136 kb
Host smart-dc9ade0e-828f-4127-95b4-33fba650a6de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556816901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
2556816901
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1203169810
Short name T1043
Test name
Test status
Simulation time 16390645 ps
CPU time 0.72 seconds
Started Mar 24 12:37:22 PM PDT 24
Finished Mar 24 12:37:24 PM PDT 24
Peak memory 203104 kb
Host smart-46d07344-5a2b-4748-bc82-8600aaf60bb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203169810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
1203169810
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1888352171
Short name T1000
Test name
Test status
Simulation time 19754934 ps
CPU time 0.77 seconds
Started Mar 24 12:37:01 PM PDT 24
Finished Mar 24 12:37:03 PM PDT 24
Peak memory 203052 kb
Host smart-2aaf6bcd-c57a-46bc-b9f4-cfd6ac50452f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888352171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
1888352171
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1419373117
Short name T1045
Test name
Test status
Simulation time 13910438 ps
CPU time 0.75 seconds
Started Mar 24 12:37:04 PM PDT 24
Finished Mar 24 12:37:09 PM PDT 24
Peak memory 203068 kb
Host smart-40740fd7-ef12-49b9-a1cd-39ca1413aff6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419373117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
1419373117
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2499875850
Short name T1020
Test name
Test status
Simulation time 21407055 ps
CPU time 0.71 seconds
Started Mar 24 12:36:55 PM PDT 24
Finished Mar 24 12:36:56 PM PDT 24
Peak memory 203036 kb
Host smart-85e5559b-143c-45e1-9e83-5a26228a3dfe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499875850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
2499875850
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1794406294
Short name T1055
Test name
Test status
Simulation time 17591917 ps
CPU time 0.71 seconds
Started Mar 24 12:37:02 PM PDT 24
Finished Mar 24 12:37:03 PM PDT 24
Peak memory 203056 kb
Host smart-4a374096-b5d5-4ba1-ade9-23469f71f95f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794406294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
1794406294
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1101847582
Short name T114
Test name
Test status
Simulation time 3778680632 ps
CPU time 24.51 seconds
Started Mar 24 12:36:40 PM PDT 24
Finished Mar 24 12:37:08 PM PDT 24
Peak memory 214968 kb
Host smart-aa311168-40c0-4e42-b5b3-3e0605dce19a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101847582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.1101847582
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.926988512
Short name T1014
Test name
Test status
Simulation time 5762575903 ps
CPU time 37.49 seconds
Started Mar 24 12:36:59 PM PDT 24
Finished Mar 24 12:37:37 PM PDT 24
Peak memory 206684 kb
Host smart-472697e4-bb96-4535-9685-24dfa5a017c9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926988512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_bit_bash.926988512
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2402393551
Short name T73
Test name
Test status
Simulation time 19470431 ps
CPU time 1.15 seconds
Started Mar 24 12:36:49 PM PDT 24
Finished Mar 24 12:36:50 PM PDT 24
Peak memory 206764 kb
Host smart-4bbad3b8-4d05-43dc-afd2-498bd13d0639
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402393551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.2402393551
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.844296235
Short name T49
Test name
Test status
Simulation time 41879117 ps
CPU time 2.65 seconds
Started Mar 24 12:37:04 PM PDT 24
Finished Mar 24 12:37:11 PM PDT 24
Peak memory 215996 kb
Host smart-28ea0fc2-3de5-45be-b384-28b9d9663e98
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844296235 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.844296235
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1691430307
Short name T1068
Test name
Test status
Simulation time 45912418 ps
CPU time 2.27 seconds
Started Mar 24 12:37:08 PM PDT 24
Finished Mar 24 12:37:14 PM PDT 24
Peak memory 214940 kb
Host smart-37976f6a-d797-4ee6-b8f5-38520817a259
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691430307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.1
691430307
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1301885282
Short name T1069
Test name
Test status
Simulation time 11447184 ps
CPU time 0.69 seconds
Started Mar 24 12:37:27 PM PDT 24
Finished Mar 24 12:37:28 PM PDT 24
Peak memory 203072 kb
Host smart-e07cd4e4-ac07-44cb-b723-2214d1acca71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301885282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.1
301885282
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.235833631
Short name T105
Test name
Test status
Simulation time 19793382 ps
CPU time 1.21 seconds
Started Mar 24 12:36:32 PM PDT 24
Finished Mar 24 12:36:33 PM PDT 24
Peak memory 214856 kb
Host smart-a3de0ad3-cbed-4465-bb61-a4d21f673198
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235833631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_
device_mem_partial_access.235833631
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2726611445
Short name T984
Test name
Test status
Simulation time 26373607 ps
CPU time 0.66 seconds
Started Mar 24 12:37:00 PM PDT 24
Finished Mar 24 12:37:01 PM PDT 24
Peak memory 203040 kb
Host smart-df03a8ed-e914-4990-94a4-aac5b046f639
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726611445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.2726611445
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.4222326945
Short name T1007
Test name
Test status
Simulation time 429209487 ps
CPU time 2.73 seconds
Started Mar 24 12:36:58 PM PDT 24
Finished Mar 24 12:37:01 PM PDT 24
Peak memory 214888 kb
Host smart-4ea87f3a-056c-4d25-b20d-7733515382bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222326945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.4222326945
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.4194639937
Short name T89
Test name
Test status
Simulation time 75778716 ps
CPU time 1.56 seconds
Started Mar 24 12:36:43 PM PDT 24
Finished Mar 24 12:36:45 PM PDT 24
Peak memory 216092 kb
Host smart-a97db913-18a6-4de7-9a98-d6b2a42d6a41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194639937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.4
194639937
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3190342436
Short name T98
Test name
Test status
Simulation time 1422595624 ps
CPU time 15.59 seconds
Started Mar 24 12:36:47 PM PDT 24
Finished Mar 24 12:37:04 PM PDT 24
Peak memory 215324 kb
Host smart-e32e86be-b283-4556-836e-78b61e435c5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190342436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.3190342436
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2739388373
Short name T1046
Test name
Test status
Simulation time 30067504 ps
CPU time 0.76 seconds
Started Mar 24 12:37:20 PM PDT 24
Finished Mar 24 12:37:22 PM PDT 24
Peak memory 202992 kb
Host smart-d910b2c1-939d-4ca5-a50d-a6a27eba280f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739388373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
2739388373
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.2407599659
Short name T988
Test name
Test status
Simulation time 12106498 ps
CPU time 0.69 seconds
Started Mar 24 12:37:17 PM PDT 24
Finished Mar 24 12:37:23 PM PDT 24
Peak memory 203036 kb
Host smart-1aaad8e6-14b7-49d5-a2c9-92b97b12eacb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407599659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
2407599659
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3396760495
Short name T1095
Test name
Test status
Simulation time 20068040 ps
CPU time 0.7 seconds
Started Mar 24 12:37:01 PM PDT 24
Finished Mar 24 12:37:03 PM PDT 24
Peak memory 203024 kb
Host smart-83ecd591-f0bc-462a-aa0c-1bd47587e89a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396760495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
3396760495
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.4288613588
Short name T1082
Test name
Test status
Simulation time 46552525 ps
CPU time 0.73 seconds
Started Mar 24 12:37:19 PM PDT 24
Finished Mar 24 12:37:22 PM PDT 24
Peak memory 203140 kb
Host smart-69730569-9a8d-4e18-8930-66a7e3e95e74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288613588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
4288613588
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1657894116
Short name T1005
Test name
Test status
Simulation time 61753420 ps
CPU time 0.78 seconds
Started Mar 24 12:37:24 PM PDT 24
Finished Mar 24 12:37:25 PM PDT 24
Peak memory 203072 kb
Host smart-a57f8833-aa34-4d3e-8dbf-c87d8ad515ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657894116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
1657894116
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2846410668
Short name T1002
Test name
Test status
Simulation time 50735833 ps
CPU time 0.72 seconds
Started Mar 24 12:37:03 PM PDT 24
Finished Mar 24 12:37:05 PM PDT 24
Peak memory 203152 kb
Host smart-6eab1b72-5941-4d4b-a0b7-84f77126ff39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846410668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
2846410668
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.684636806
Short name T989
Test name
Test status
Simulation time 39993286 ps
CPU time 0.68 seconds
Started Mar 24 12:37:05 PM PDT 24
Finished Mar 24 12:37:11 PM PDT 24
Peak memory 203064 kb
Host smart-a1366611-a9a6-456f-8f3b-9ac5fe695692
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684636806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.684636806
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1390883702
Short name T1003
Test name
Test status
Simulation time 13941216 ps
CPU time 0.71 seconds
Started Mar 24 12:37:00 PM PDT 24
Finished Mar 24 12:37:01 PM PDT 24
Peak memory 203040 kb
Host smart-a447011c-9c23-4fb4-b633-a11b1e1663e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390883702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
1390883702
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3489175586
Short name T1030
Test name
Test status
Simulation time 12607675 ps
CPU time 0.74 seconds
Started Mar 24 12:37:05 PM PDT 24
Finished Mar 24 12:37:11 PM PDT 24
Peak memory 203064 kb
Host smart-dfd252fc-879c-4ed4-9b32-0a6362252802
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489175586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
3489175586
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1900175294
Short name T1034
Test name
Test status
Simulation time 16046652 ps
CPU time 0.71 seconds
Started Mar 24 12:37:14 PM PDT 24
Finished Mar 24 12:37:15 PM PDT 24
Peak memory 203072 kb
Host smart-e27fa488-ba60-4c1c-9a57-99b3aff5ae2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900175294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
1900175294
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.210619444
Short name T103
Test name
Test status
Simulation time 212626534 ps
CPU time 14.18 seconds
Started Mar 24 12:36:53 PM PDT 24
Finished Mar 24 12:37:10 PM PDT 24
Peak memory 214912 kb
Host smart-6cc027cb-1115-41ff-b43b-1841ae38ee2a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210619444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_aliasing.210619444
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3616648383
Short name T983
Test name
Test status
Simulation time 1208885086 ps
CPU time 24.61 seconds
Started Mar 24 12:36:41 PM PDT 24
Finished Mar 24 12:37:08 PM PDT 24
Peak memory 206748 kb
Host smart-aea24a2c-63b4-44ec-93bf-fa9930853b05
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616648383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.3616648383
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.221312886
Short name T71
Test name
Test status
Simulation time 37298760 ps
CPU time 1.25 seconds
Started Mar 24 12:37:10 PM PDT 24
Finished Mar 24 12:37:13 PM PDT 24
Peak memory 215944 kb
Host smart-7c38635f-fda0-4cfa-a056-d0b97acc97cb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221312886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_hw_reset.221312886
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.4232255898
Short name T127
Test name
Test status
Simulation time 190749678 ps
CPU time 2.52 seconds
Started Mar 24 12:36:55 PM PDT 24
Finished Mar 24 12:36:58 PM PDT 24
Peak memory 215972 kb
Host smart-372e811c-aaf4-4274-8479-9a13af35c09b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232255898 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.4232255898
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.4241338175
Short name T1016
Test name
Test status
Simulation time 54086323 ps
CPU time 1.36 seconds
Started Mar 24 12:37:00 PM PDT 24
Finished Mar 24 12:37:02 PM PDT 24
Peak memory 206712 kb
Host smart-b5c2345a-ec48-4582-b661-cb299c68cda4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241338175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.4
241338175
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.404493391
Short name T990
Test name
Test status
Simulation time 21567983 ps
CPU time 0.75 seconds
Started Mar 24 12:36:53 PM PDT 24
Finished Mar 24 12:36:56 PM PDT 24
Peak memory 203056 kb
Host smart-df1ce640-d963-4f64-a530-5f6d19a2e071
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404493391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.404493391
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1224263166
Short name T1084
Test name
Test status
Simulation time 46794176 ps
CPU time 1.65 seconds
Started Mar 24 12:36:55 PM PDT 24
Finished Mar 24 12:36:57 PM PDT 24
Peak memory 214972 kb
Host smart-96a1cd61-07d8-4008-858c-4f0b641509cd
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224263166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.1224263166
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2346386492
Short name T1096
Test name
Test status
Simulation time 15547180 ps
CPU time 0.65 seconds
Started Mar 24 12:36:43 PM PDT 24
Finished Mar 24 12:36:44 PM PDT 24
Peak memory 203056 kb
Host smart-88c28f9e-c442-4810-8191-8e203b1f0a0a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346386492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.2346386492
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2406952943
Short name T993
Test name
Test status
Simulation time 621962526 ps
CPU time 3.92 seconds
Started Mar 24 12:36:49 PM PDT 24
Finished Mar 24 12:36:54 PM PDT 24
Peak memory 214732 kb
Host smart-fb3b16d6-c91d-450b-a620-965f7fe38d0f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406952943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.2406952943
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3665974996
Short name T1076
Test name
Test status
Simulation time 50543915 ps
CPU time 3.66 seconds
Started Mar 24 12:37:07 PM PDT 24
Finished Mar 24 12:37:12 PM PDT 24
Peak memory 216032 kb
Host smart-db9ec4d2-c76d-441b-a8ef-86b3f65d12d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665974996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.3
665974996
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2232534397
Short name T81
Test name
Test status
Simulation time 275877505 ps
CPU time 7.54 seconds
Started Mar 24 12:36:50 PM PDT 24
Finished Mar 24 12:36:58 PM PDT 24
Peak memory 215372 kb
Host smart-1446994c-e8be-4427-aa07-e7951e38c0e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232534397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.2232534397
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.4188924300
Short name T979
Test name
Test status
Simulation time 45759330 ps
CPU time 0.75 seconds
Started Mar 24 12:37:30 PM PDT 24
Finished Mar 24 12:37:36 PM PDT 24
Peak memory 203052 kb
Host smart-f39cdeba-4a60-4bfe-8d53-fcd6d2738910
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188924300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
4188924300
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3867192823
Short name T977
Test name
Test status
Simulation time 53718421 ps
CPU time 0.78 seconds
Started Mar 24 12:36:59 PM PDT 24
Finished Mar 24 12:37:01 PM PDT 24
Peak memory 203068 kb
Host smart-8557583a-3877-438b-8713-3bac3174d40b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867192823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
3867192823
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1819414198
Short name T1063
Test name
Test status
Simulation time 43340278 ps
CPU time 0.71 seconds
Started Mar 24 12:37:08 PM PDT 24
Finished Mar 24 12:37:11 PM PDT 24
Peak memory 203052 kb
Host smart-f53b0433-809f-4006-9f11-e55408701103
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819414198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
1819414198
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.440836131
Short name T986
Test name
Test status
Simulation time 53744540 ps
CPU time 0.82 seconds
Started Mar 24 12:37:10 PM PDT 24
Finished Mar 24 12:37:12 PM PDT 24
Peak memory 203148 kb
Host smart-04a31bdd-deb6-41f3-8fc0-e39a5347df9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440836131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.440836131
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1932560925
Short name T1013
Test name
Test status
Simulation time 28222212 ps
CPU time 0.74 seconds
Started Mar 24 12:37:05 PM PDT 24
Finished Mar 24 12:37:10 PM PDT 24
Peak memory 203056 kb
Host smart-58953f73-fadc-4a27-8685-fa6cad1a093a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932560925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
1932560925
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.174615471
Short name T1093
Test name
Test status
Simulation time 21055639 ps
CPU time 0.77 seconds
Started Mar 24 12:37:10 PM PDT 24
Finished Mar 24 12:37:12 PM PDT 24
Peak memory 203080 kb
Host smart-ffcc2f8b-cf0b-4266-b8b9-1fde3cbb6657
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174615471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.174615471
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.4281652535
Short name T1028
Test name
Test status
Simulation time 16331412 ps
CPU time 0.73 seconds
Started Mar 24 12:37:04 PM PDT 24
Finished Mar 24 12:37:10 PM PDT 24
Peak memory 203060 kb
Host smart-0e77d79a-8e4a-42c5-9277-d6548699511a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281652535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
4281652535
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.97506383
Short name T1004
Test name
Test status
Simulation time 13697844 ps
CPU time 0.71 seconds
Started Mar 24 12:37:07 PM PDT 24
Finished Mar 24 12:37:15 PM PDT 24
Peak memory 203088 kb
Host smart-4e80c579-97fc-44d0-9ec8-790f3e8fec50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97506383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.97506383
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3826860044
Short name T978
Test name
Test status
Simulation time 106857103 ps
CPU time 0.72 seconds
Started Mar 24 12:37:18 PM PDT 24
Finished Mar 24 12:37:22 PM PDT 24
Peak memory 203164 kb
Host smart-dc1da039-5d0b-4529-9957-a5e55af0b560
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826860044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
3826860044
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1208427097
Short name T1070
Test name
Test status
Simulation time 47112681 ps
CPU time 0.77 seconds
Started Mar 24 12:37:11 PM PDT 24
Finished Mar 24 12:37:13 PM PDT 24
Peak memory 203452 kb
Host smart-027783c6-8ad6-4463-8a16-ca4b9c86bff7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208427097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
1208427097
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.91921358
Short name T1033
Test name
Test status
Simulation time 48185556 ps
CPU time 1.7 seconds
Started Mar 24 12:37:10 PM PDT 24
Finished Mar 24 12:37:13 PM PDT 24
Peak memory 215040 kb
Host smart-6ab06d5a-21a7-4c19-86e0-1fa09ec68f98
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91921358 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.91921358
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.4151053511
Short name T104
Test name
Test status
Simulation time 374178479 ps
CPU time 2.66 seconds
Started Mar 24 12:36:59 PM PDT 24
Finished Mar 24 12:37:03 PM PDT 24
Peak memory 206792 kb
Host smart-3fc287f0-793f-4249-9d61-641a35e56e17
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151053511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.4
151053511
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3115885369
Short name T1056
Test name
Test status
Simulation time 41179742 ps
CPU time 0.68 seconds
Started Mar 24 12:36:44 PM PDT 24
Finished Mar 24 12:36:45 PM PDT 24
Peak memory 203064 kb
Host smart-c8830e6f-f641-43dd-a72f-fa90f94abed0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115885369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.3
115885369
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.4206965271
Short name T1022
Test name
Test status
Simulation time 133302252 ps
CPU time 3 seconds
Started Mar 24 12:36:49 PM PDT 24
Finished Mar 24 12:36:53 PM PDT 24
Peak memory 215072 kb
Host smart-bebf2c65-52e3-4dd8-9e34-a721dd4e7b35
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206965271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.4206965271
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3030777633
Short name T1074
Test name
Test status
Simulation time 812452909 ps
CPU time 4.49 seconds
Started Mar 24 12:36:56 PM PDT 24
Finished Mar 24 12:37:01 PM PDT 24
Peak memory 215048 kb
Host smart-923ff103-4096-47fd-8325-69329ddcfb00
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030777633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.3
030777633
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2629837553
Short name T1080
Test name
Test status
Simulation time 129538608 ps
CPU time 3.74 seconds
Started Mar 24 12:36:53 PM PDT 24
Finished Mar 24 12:36:59 PM PDT 24
Peak memory 217632 kb
Host smart-90d8721a-971e-422a-b93a-f869fd2eafdb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629837553 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.2629837553
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.724966620
Short name T99
Test name
Test status
Simulation time 85000661 ps
CPU time 2.49 seconds
Started Mar 24 12:36:56 PM PDT 24
Finished Mar 24 12:36:59 PM PDT 24
Peak memory 206652 kb
Host smart-a16987a6-ff42-4421-b9d4-28d5782e8eaa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724966620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.724966620
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.961980901
Short name T1010
Test name
Test status
Simulation time 24053341 ps
CPU time 0.71 seconds
Started Mar 24 12:37:10 PM PDT 24
Finished Mar 24 12:37:12 PM PDT 24
Peak memory 203044 kb
Host smart-5879af3d-ab0a-44ec-8c78-775e2334ea6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961980901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.961980901
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1754139437
Short name T1032
Test name
Test status
Simulation time 260844677 ps
CPU time 3.94 seconds
Started Mar 24 12:36:44 PM PDT 24
Finished Mar 24 12:36:48 PM PDT 24
Peak memory 214972 kb
Host smart-388cad98-97df-4297-adc2-c38ddac8e868
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754139437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.1754139437
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1779988927
Short name T1087
Test name
Test status
Simulation time 122664618 ps
CPU time 3.03 seconds
Started Mar 24 12:36:52 PM PDT 24
Finished Mar 24 12:36:57 PM PDT 24
Peak memory 215220 kb
Host smart-3523fd9f-5843-480f-b006-e62556ceb208
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779988927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.1
779988927
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1175642257
Short name T1078
Test name
Test status
Simulation time 1554462443 ps
CPU time 20.52 seconds
Started Mar 24 12:37:14 PM PDT 24
Finished Mar 24 12:37:35 PM PDT 24
Peak memory 214972 kb
Host smart-f7da7f0a-b340-4f49-af22-fa5728e6faf6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175642257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.1175642257
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2496943748
Short name T1048
Test name
Test status
Simulation time 498302995 ps
CPU time 3.7 seconds
Started Mar 24 12:36:52 PM PDT 24
Finished Mar 24 12:36:56 PM PDT 24
Peak memory 217388 kb
Host smart-8b48d781-d2f1-45d3-b485-09926e98d361
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496943748 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.2496943748
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.722763627
Short name T111
Test name
Test status
Simulation time 164754260 ps
CPU time 2.24 seconds
Started Mar 24 12:36:51 PM PDT 24
Finished Mar 24 12:36:55 PM PDT 24
Peak memory 214852 kb
Host smart-9df311f6-af33-44b8-b423-29d9d3dbc266
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722763627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.722763627
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.4084322571
Short name T1018
Test name
Test status
Simulation time 183105126 ps
CPU time 0.68 seconds
Started Mar 24 12:36:52 PM PDT 24
Finished Mar 24 12:36:53 PM PDT 24
Peak memory 203020 kb
Host smart-5947638a-3711-4543-8ea0-84d556118e79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084322571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.4
084322571
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3338976135
Short name T1060
Test name
Test status
Simulation time 265600112 ps
CPU time 2.83 seconds
Started Mar 24 12:36:37 PM PDT 24
Finished Mar 24 12:36:40 PM PDT 24
Peak memory 214896 kb
Host smart-ab567557-2ec9-4337-ae4d-0a76632202db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338976135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.3338976135
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.4173050905
Short name T1011
Test name
Test status
Simulation time 187611467 ps
CPU time 3.73 seconds
Started Mar 24 12:37:00 PM PDT 24
Finished Mar 24 12:37:04 PM PDT 24
Peak memory 216064 kb
Host smart-eecec376-4749-4aa4-837f-1510f3451768
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173050905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.4
173050905
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1982832723
Short name T145
Test name
Test status
Simulation time 1951104136 ps
CPU time 21.28 seconds
Started Mar 24 12:37:06 PM PDT 24
Finished Mar 24 12:37:31 PM PDT 24
Peak memory 214932 kb
Host smart-8e8949a9-ad79-4b9a-bb13-b64e5e78e38b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982832723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.1982832723
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3243678616
Short name T1009
Test name
Test status
Simulation time 205402582 ps
CPU time 1.69 seconds
Started Mar 24 12:37:06 PM PDT 24
Finished Mar 24 12:37:12 PM PDT 24
Peak memory 215104 kb
Host smart-9bfd7cb7-23d6-45d9-ac97-b0794208b513
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243678616 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.3243678616
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3799099326
Short name T1089
Test name
Test status
Simulation time 19256247 ps
CPU time 1.22 seconds
Started Mar 24 12:36:47 PM PDT 24
Finished Mar 24 12:36:48 PM PDT 24
Peak memory 206688 kb
Host smart-89f8bd17-83d1-4b30-b2e9-4573d6f24314
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799099326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.3
799099326
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1138821261
Short name T1090
Test name
Test status
Simulation time 15659509 ps
CPU time 0.7 seconds
Started Mar 24 12:36:57 PM PDT 24
Finished Mar 24 12:36:58 PM PDT 24
Peak memory 203064 kb
Host smart-4b139b2a-56e5-4112-b78d-ada191e2d49b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138821261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.1
138821261
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2549464745
Short name T1047
Test name
Test status
Simulation time 233029115 ps
CPU time 1.9 seconds
Started Mar 24 12:36:50 PM PDT 24
Finished Mar 24 12:36:52 PM PDT 24
Peak memory 214944 kb
Host smart-c7962976-88f7-42b3-8776-85896c589b35
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549464745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.2549464745
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.4166306874
Short name T85
Test name
Test status
Simulation time 21448581 ps
CPU time 1.53 seconds
Started Mar 24 12:37:00 PM PDT 24
Finished Mar 24 12:37:12 PM PDT 24
Peak memory 215140 kb
Host smart-c1ac3412-cc4e-4b56-97bb-57d13525c0c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166306874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.4
166306874
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1087936246
Short name T141
Test name
Test status
Simulation time 376898272 ps
CPU time 6.43 seconds
Started Mar 24 12:37:05 PM PDT 24
Finished Mar 24 12:37:16 PM PDT 24
Peak memory 214972 kb
Host smart-9b49eff6-7e9f-498e-9b09-5e2c8f09f7f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087936246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.1087936246
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2235945855
Short name T97
Test name
Test status
Simulation time 118837416 ps
CPU time 1.7 seconds
Started Mar 24 12:37:06 PM PDT 24
Finished Mar 24 12:37:12 PM PDT 24
Peak memory 215124 kb
Host smart-8040f3b2-3664-49e4-85ff-8a4a82838ad0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235945855 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.2235945855
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.4059095895
Short name T994
Test name
Test status
Simulation time 38345251 ps
CPU time 1.21 seconds
Started Mar 24 12:37:22 PM PDT 24
Finished Mar 24 12:37:24 PM PDT 24
Peak memory 206764 kb
Host smart-3eda367e-d88a-4bfa-aaa9-66320b7d677c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059095895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.4
059095895
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3661848189
Short name T1062
Test name
Test status
Simulation time 16344323 ps
CPU time 0.73 seconds
Started Mar 24 12:37:07 PM PDT 24
Finished Mar 24 12:37:10 PM PDT 24
Peak memory 203056 kb
Host smart-ec949bc6-5e2d-4189-b9ad-7cd41d767d4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661848189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.3
661848189
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2228461173
Short name T1091
Test name
Test status
Simulation time 59649730 ps
CPU time 3.9 seconds
Started Mar 24 12:36:59 PM PDT 24
Finished Mar 24 12:37:04 PM PDT 24
Peak memory 214952 kb
Host smart-02e879fa-344e-43e3-9346-51cb94946bd6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228461173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.2228461173
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3360749877
Short name T93
Test name
Test status
Simulation time 69947322 ps
CPU time 2.37 seconds
Started Mar 24 12:37:05 PM PDT 24
Finished Mar 24 12:37:16 PM PDT 24
Peak memory 215140 kb
Host smart-5f6d37d7-82c7-47ec-8417-d955dd12fe07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360749877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.3
360749877
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.503530352
Short name T143
Test name
Test status
Simulation time 373850067 ps
CPU time 19.07 seconds
Started Mar 24 12:36:57 PM PDT 24
Finished Mar 24 12:37:17 PM PDT 24
Peak memory 214964 kb
Host smart-b653c000-5938-44da-a4d8-4c2dd15dcf7a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503530352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_
tl_intg_err.503530352
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.838765229
Short name T943
Test name
Test status
Simulation time 24495153 ps
CPU time 0.7 seconds
Started Mar 24 01:12:51 PM PDT 24
Finished Mar 24 01:12:52 PM PDT 24
Peak memory 205752 kb
Host smart-3b971c2d-8527-4000-90f6-721155046b88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838765229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.838765229
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.1928407828
Short name T206
Test name
Test status
Simulation time 516620088 ps
CPU time 2.93 seconds
Started Mar 24 01:12:42 PM PDT 24
Finished Mar 24 01:12:45 PM PDT 24
Peak memory 218884 kb
Host smart-e041a270-82b5-49d6-8ae3-0db1ad0c2ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928407828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.1928407828
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.689625776
Short name T602
Test name
Test status
Simulation time 61693452 ps
CPU time 0.8 seconds
Started Mar 24 01:12:28 PM PDT 24
Finished Mar 24 01:12:28 PM PDT 24
Peak memory 205772 kb
Host smart-498e76cc-a623-442e-b163-037237e0e8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689625776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.689625776
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.2538540941
Short name T391
Test name
Test status
Simulation time 12222870712 ps
CPU time 75.83 seconds
Started Mar 24 01:12:27 PM PDT 24
Finished Mar 24 01:13:43 PM PDT 24
Peak memory 241308 kb
Host smart-60f692d8-9a3c-4b52-a131-d0e519fdab28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538540941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.2538540941
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.3253396566
Short name T153
Test name
Test status
Simulation time 32176810602 ps
CPU time 117.25 seconds
Started Mar 24 01:12:32 PM PDT 24
Finished Mar 24 01:14:29 PM PDT 24
Peak memory 273792 kb
Host smart-d045c143-f11c-494b-8b71-a4c8b811eefc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253396566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.3253396566
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.3890772869
Short name T689
Test name
Test status
Simulation time 3039654235 ps
CPU time 16.79 seconds
Started Mar 24 01:12:27 PM PDT 24
Finished Mar 24 01:12:44 PM PDT 24
Peak memory 239744 kb
Host smart-32f29c2d-1acf-4395-8a84-4aa771a87d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890772869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.3890772869
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.4285938176
Short name T483
Test name
Test status
Simulation time 3251036666 ps
CPU time 12.53 seconds
Started Mar 24 01:12:47 PM PDT 24
Finished Mar 24 01:13:00 PM PDT 24
Peak memory 234880 kb
Host smart-95ccee1a-335f-4827-9ace-2bc8f7d82264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285938176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.4285938176
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.4161252366
Short name T926
Test name
Test status
Simulation time 1111606633 ps
CPU time 6.03 seconds
Started Mar 24 01:12:30 PM PDT 24
Finished Mar 24 01:12:36 PM PDT 24
Peak memory 235000 kb
Host smart-635b8cc0-449e-4d06-aa8c-87d6020e15a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161252366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.4161252366
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.1295881428
Short name T973
Test name
Test status
Simulation time 1274329514 ps
CPU time 3.7 seconds
Started Mar 24 01:12:35 PM PDT 24
Finished Mar 24 01:12:39 PM PDT 24
Peak memory 224852 kb
Host smart-f90d97e1-70dc-4b69-8af5-8c4dd57c7a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295881428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.1295881428
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.3364388712
Short name T193
Test name
Test status
Simulation time 4779010580 ps
CPU time 8.77 seconds
Started Mar 24 01:12:43 PM PDT 24
Finished Mar 24 01:12:52 PM PDT 24
Peak memory 239436 kb
Host smart-0dc2afe7-58c5-4502-96a4-be7203b7be8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364388712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.3364388712
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.1574822369
Short name T605
Test name
Test status
Simulation time 342655588 ps
CPU time 3.98 seconds
Started Mar 24 01:12:42 PM PDT 24
Finished Mar 24 01:12:46 PM PDT 24
Peak memory 219520 kb
Host smart-d2ea0122-f384-4462-acbd-c3f1d7629865
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1574822369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.1574822369
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.4241792778
Short name T55
Test name
Test status
Simulation time 37796065 ps
CPU time 0.95 seconds
Started Mar 24 01:12:32 PM PDT 24
Finished Mar 24 01:12:33 PM PDT 24
Peak memory 235944 kb
Host smart-653edbc9-7770-4b4d-b894-c32064213295
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241792778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.4241792778
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.2995126882
Short name T361
Test name
Test status
Simulation time 104222968929 ps
CPU time 191.12 seconds
Started Mar 24 01:12:50 PM PDT 24
Finished Mar 24 01:16:01 PM PDT 24
Peak memory 267688 kb
Host smart-b325dc6c-c9bc-4a46-83cf-59311f197c1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995126882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.2995126882
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.2062471364
Short name T334
Test name
Test status
Simulation time 2737111633 ps
CPU time 30.18 seconds
Started Mar 24 01:12:27 PM PDT 24
Finished Mar 24 01:12:57 PM PDT 24
Peak memory 216740 kb
Host smart-789f9200-bda3-4f35-b1f5-428f175d3fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062471364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.2062471364
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.3620592249
Short name T767
Test name
Test status
Simulation time 39458055293 ps
CPU time 12.57 seconds
Started Mar 24 01:12:27 PM PDT 24
Finished Mar 24 01:12:40 PM PDT 24
Peak memory 216620 kb
Host smart-1832a3e3-7b4c-4022-90d5-41f347f3b5e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620592249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.3620592249
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.744758501
Short name T614
Test name
Test status
Simulation time 743948014 ps
CPU time 3.59 seconds
Started Mar 24 01:12:42 PM PDT 24
Finished Mar 24 01:12:45 PM PDT 24
Peak memory 216848 kb
Host smart-15cd6823-e836-4ed1-8689-89aac2509eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744758501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.744758501
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.2246116722
Short name T318
Test name
Test status
Simulation time 154756186 ps
CPU time 0.82 seconds
Started Mar 24 01:12:36 PM PDT 24
Finished Mar 24 01:12:37 PM PDT 24
Peak memory 206080 kb
Host smart-f2b4129b-db50-46f1-a2e1-3c8f7d39425d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246116722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.2246116722
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.614573399
Short name T422
Test name
Test status
Simulation time 808652100 ps
CPU time 6.63 seconds
Started Mar 24 01:12:39 PM PDT 24
Finished Mar 24 01:12:46 PM PDT 24
Peak memory 233816 kb
Host smart-aaa34481-3217-4f84-a3d8-a9c1dd5d7959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614573399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.614573399
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.436169630
Short name T621
Test name
Test status
Simulation time 12066142 ps
CPU time 0.74 seconds
Started Mar 24 01:12:38 PM PDT 24
Finished Mar 24 01:12:39 PM PDT 24
Peak memory 205696 kb
Host smart-ee1617de-9963-4c28-943d-03241fee97be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436169630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.436169630
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.3015761251
Short name T345
Test name
Test status
Simulation time 585347122 ps
CPU time 4.05 seconds
Started Mar 24 01:12:37 PM PDT 24
Finished Mar 24 01:12:41 PM PDT 24
Peak memory 234844 kb
Host smart-678174a1-f57f-47cd-9fb2-b571a6be49e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015761251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.3015761251
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.1493216584
Short name T280
Test name
Test status
Simulation time 16878554 ps
CPU time 0.79 seconds
Started Mar 24 01:12:44 PM PDT 24
Finished Mar 24 01:12:45 PM PDT 24
Peak memory 206812 kb
Host smart-04a4e4f4-2a21-48ac-8f80-f45c3fdb60d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493216584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.1493216584
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.104097983
Short name T920
Test name
Test status
Simulation time 46067627383 ps
CPU time 105.35 seconds
Started Mar 24 01:12:43 PM PDT 24
Finished Mar 24 01:14:28 PM PDT 24
Peak memory 265584 kb
Host smart-7fb86402-66ae-41c9-b45d-8d47e3dd59f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104097983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.104097983
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.355941668
Short name T562
Test name
Test status
Simulation time 12908039167 ps
CPU time 28.99 seconds
Started Mar 24 01:12:51 PM PDT 24
Finished Mar 24 01:13:20 PM PDT 24
Peak memory 249320 kb
Host smart-a7d1e06e-ce74-48f0-8d4f-d40334cb3858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355941668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle.
355941668
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.869783372
Short name T363
Test name
Test status
Simulation time 781583026 ps
CPU time 11.1 seconds
Started Mar 24 01:12:45 PM PDT 24
Finished Mar 24 01:12:57 PM PDT 24
Peak memory 239280 kb
Host smart-a9e0d99d-5611-4231-9b92-a5bd94d03f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869783372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.869783372
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.1023957161
Short name T175
Test name
Test status
Simulation time 110336807 ps
CPU time 3.27 seconds
Started Mar 24 01:12:32 PM PDT 24
Finished Mar 24 01:12:35 PM PDT 24
Peak memory 234128 kb
Host smart-64efb06d-9231-4694-a66e-8071d84b43b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023957161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.1023957161
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.315592830
Short name T634
Test name
Test status
Simulation time 246793380 ps
CPU time 3.12 seconds
Started Mar 24 01:12:53 PM PDT 24
Finished Mar 24 01:12:57 PM PDT 24
Peak memory 224868 kb
Host smart-10ea8e9a-a67c-4023-b36b-bfbdedbf9687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315592830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.315592830
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.4009330368
Short name T236
Test name
Test status
Simulation time 2665230379 ps
CPU time 10.93 seconds
Started Mar 24 01:12:47 PM PDT 24
Finished Mar 24 01:12:58 PM PDT 24
Peak memory 238112 kb
Host smart-2de6aa89-6eb5-45ad-b222-461700ab42ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009330368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.4009330368
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.2402582953
Short name T165
Test name
Test status
Simulation time 5579247973 ps
CPU time 11.46 seconds
Started Mar 24 01:12:37 PM PDT 24
Finished Mar 24 01:12:49 PM PDT 24
Peak memory 239768 kb
Host smart-6c9d2719-ea67-411c-ab40-64802776dda1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402582953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.2402582953
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_ram_cfg.2889567972
Short name T452
Test name
Test status
Simulation time 41149339 ps
CPU time 0.77 seconds
Started Mar 24 01:12:50 PM PDT 24
Finished Mar 24 01:12:51 PM PDT 24
Peak memory 216556 kb
Host smart-98cf7fcf-9545-4bcd-883a-f9dbbaf38221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889567972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_ram_cfg.2889567972
Directory /workspace/1.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.1774463731
Short name T262
Test name
Test status
Simulation time 10192065323 ps
CPU time 7.23 seconds
Started Mar 24 01:12:49 PM PDT 24
Finished Mar 24 01:12:56 PM PDT 24
Peak memory 222916 kb
Host smart-813acc9c-33d7-4f8e-a8af-290072373f06
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1774463731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.1774463731
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.3488849780
Short name T56
Test name
Test status
Simulation time 519247080 ps
CPU time 1.09 seconds
Started Mar 24 01:12:48 PM PDT 24
Finished Mar 24 01:12:50 PM PDT 24
Peak memory 235700 kb
Host smart-008d670c-06fb-4c30-b5d2-f0d927fcdc14
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488849780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.3488849780
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.1143687273
Short name T646
Test name
Test status
Simulation time 183752758 ps
CPU time 2.44 seconds
Started Mar 24 01:12:39 PM PDT 24
Finished Mar 24 01:12:41 PM PDT 24
Peak memory 216612 kb
Host smart-598cfc99-8574-4b32-8c30-6ab03de1cebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143687273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.1143687273
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.4172891033
Short name T516
Test name
Test status
Simulation time 1352280991 ps
CPU time 2.15 seconds
Started Mar 24 01:12:36 PM PDT 24
Finished Mar 24 01:12:39 PM PDT 24
Peak memory 208000 kb
Host smart-188f096b-aaad-4439-bfbc-622c61d09045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172891033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.4172891033
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.2699380905
Short name T518
Test name
Test status
Simulation time 144723825 ps
CPU time 2.18 seconds
Started Mar 24 01:12:53 PM PDT 24
Finished Mar 24 01:12:56 PM PDT 24
Peak memory 216800 kb
Host smart-cc9e1b74-7922-4b49-a826-756efc8955dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699380905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2699380905
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.3805183095
Short name T843
Test name
Test status
Simulation time 72620813 ps
CPU time 0.9 seconds
Started Mar 24 01:12:36 PM PDT 24
Finished Mar 24 01:12:37 PM PDT 24
Peak memory 206300 kb
Host smart-08ceaf5f-e5f8-4ee3-8803-5814dd2f34ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805183095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.3805183095
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.221408993
Short name T778
Test name
Test status
Simulation time 23014711092 ps
CPU time 22.44 seconds
Started Mar 24 01:12:28 PM PDT 24
Finished Mar 24 01:12:50 PM PDT 24
Peak memory 237392 kb
Host smart-f2c8f205-e31a-48a9-a727-3826f6eb6180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221408993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.221408993
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.3627798412
Short name T787
Test name
Test status
Simulation time 36605256 ps
CPU time 0.7 seconds
Started Mar 24 01:13:10 PM PDT 24
Finished Mar 24 01:13:11 PM PDT 24
Peak memory 205172 kb
Host smart-7a34a325-7381-4a6c-acbd-66960a5c1b9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627798412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
3627798412
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.668334331
Short name T777
Test name
Test status
Simulation time 1814444416 ps
CPU time 3.36 seconds
Started Mar 24 01:13:02 PM PDT 24
Finished Mar 24 01:13:05 PM PDT 24
Peak memory 218880 kb
Host smart-1f3c7886-cdd0-40c0-bc36-d6f1e8c10c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668334331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.668334331
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.3669095039
Short name T382
Test name
Test status
Simulation time 45920721 ps
CPU time 0.74 seconds
Started Mar 24 01:13:06 PM PDT 24
Finished Mar 24 01:13:07 PM PDT 24
Peak memory 205776 kb
Host smart-cd2e6258-d3ec-4f0a-9565-42d2b1433a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669095039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.3669095039
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.3768491897
Short name T828
Test name
Test status
Simulation time 36272686936 ps
CPU time 10.48 seconds
Started Mar 24 01:13:03 PM PDT 24
Finished Mar 24 01:13:14 PM PDT 24
Peak memory 224896 kb
Host smart-328a635a-4959-44c6-9e59-87d89db154bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768491897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.3768491897
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_intercept.2084702815
Short name T873
Test name
Test status
Simulation time 3302153077 ps
CPU time 4.16 seconds
Started Mar 24 01:13:01 PM PDT 24
Finished Mar 24 01:13:05 PM PDT 24
Peak memory 219416 kb
Host smart-3cfde69c-db58-49a3-9aca-9c3f7df889e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084702815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.2084702815
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.90739230
Short name T651
Test name
Test status
Simulation time 125522793 ps
CPU time 3.6 seconds
Started Mar 24 01:12:54 PM PDT 24
Finished Mar 24 01:12:58 PM PDT 24
Peak memory 218904 kb
Host smart-cca1a3b4-0179-4d13-b2b6-954c2857869d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90739230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.90739230
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.1352772515
Short name T759
Test name
Test status
Simulation time 3287643155 ps
CPU time 11.01 seconds
Started Mar 24 01:12:59 PM PDT 24
Finished Mar 24 01:13:10 PM PDT 24
Peak memory 220176 kb
Host smart-f8a3ac6b-efe3-4c4b-b8b3-fed1ecf31531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352772515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.1352772515
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.1545161865
Short name T707
Test name
Test status
Simulation time 211624512 ps
CPU time 3.68 seconds
Started Mar 24 01:13:00 PM PDT 24
Finished Mar 24 01:13:04 PM PDT 24
Peak memory 234156 kb
Host smart-d06979a0-3694-46b0-a424-a1ce295c8238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545161865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.1545161865
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_ram_cfg.1316793905
Short name T617
Test name
Test status
Simulation time 15630198 ps
CPU time 0.75 seconds
Started Mar 24 01:13:01 PM PDT 24
Finished Mar 24 01:13:02 PM PDT 24
Peak memory 216560 kb
Host smart-aad0cbfd-7e23-466a-9fef-f3a2666d2c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316793905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_ram_cfg.1316793905
Directory /workspace/10.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.1392516729
Short name T616
Test name
Test status
Simulation time 1268905868 ps
CPU time 4.03 seconds
Started Mar 24 01:12:58 PM PDT 24
Finished Mar 24 01:13:02 PM PDT 24
Peak memory 220764 kb
Host smart-381243f0-6b91-42c2-be4c-0e9c728d2af1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1392516729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.1392516729
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.140495196
Short name T775
Test name
Test status
Simulation time 3600953499 ps
CPU time 38.46 seconds
Started Mar 24 01:12:51 PM PDT 24
Finished Mar 24 01:13:30 PM PDT 24
Peak memory 233112 kb
Host smart-32732a04-2e87-49a0-9fbf-64909dfc6cc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140495196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stres
s_all.140495196
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.3895051400
Short name T904
Test name
Test status
Simulation time 9766146809 ps
CPU time 50.68 seconds
Started Mar 24 01:13:06 PM PDT 24
Finished Mar 24 01:13:57 PM PDT 24
Peak memory 216620 kb
Host smart-f1acb308-d9b8-439e-ad58-554249add29f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895051400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.3895051400
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.4239503781
Short name T715
Test name
Test status
Simulation time 85527908184 ps
CPU time 19.66 seconds
Started Mar 24 01:13:06 PM PDT 24
Finished Mar 24 01:13:26 PM PDT 24
Peak memory 216752 kb
Host smart-77aadb47-2c63-406b-b5f3-aa0aa623000e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239503781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.4239503781
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.3148552074
Short name T807
Test name
Test status
Simulation time 688815334 ps
CPU time 4.85 seconds
Started Mar 24 01:13:02 PM PDT 24
Finished Mar 24 01:13:08 PM PDT 24
Peak memory 216600 kb
Host smart-733fbc6a-74a9-4902-b3a4-1dd7fcc7d6f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148552074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.3148552074
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.2248251267
Short name T57
Test name
Test status
Simulation time 81756382 ps
CPU time 0.75 seconds
Started Mar 24 01:13:02 PM PDT 24
Finished Mar 24 01:13:03 PM PDT 24
Peak memory 206064 kb
Host smart-c8da45b8-7a65-44db-8189-a8e3c529bb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248251267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.2248251267
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.1065601193
Short name T809
Test name
Test status
Simulation time 5584937626 ps
CPU time 23.01 seconds
Started Mar 24 01:13:02 PM PDT 24
Finished Mar 24 01:13:25 PM PDT 24
Peak memory 248820 kb
Host smart-ee83e4e9-c23b-4911-bbb5-0226ce84649a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065601193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.1065601193
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.3926674301
Short name T590
Test name
Test status
Simulation time 49257452 ps
CPU time 0.74 seconds
Started Mar 24 01:13:02 PM PDT 24
Finished Mar 24 01:13:04 PM PDT 24
Peak memory 205736 kb
Host smart-4a297327-3bd9-4596-8499-c844d784d117
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926674301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
3926674301
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.958432205
Short name T636
Test name
Test status
Simulation time 13767074050 ps
CPU time 8.17 seconds
Started Mar 24 01:13:07 PM PDT 24
Finished Mar 24 01:13:16 PM PDT 24
Peak memory 234132 kb
Host smart-0da6f2e6-f02f-44f0-9314-af7412fd51da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958432205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.958432205
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.1452841856
Short name T749
Test name
Test status
Simulation time 20422445 ps
CPU time 0.79 seconds
Started Mar 24 01:13:03 PM PDT 24
Finished Mar 24 01:13:05 PM PDT 24
Peak memory 207144 kb
Host smart-7c8f651c-b386-4cf2-a875-5df12a068b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452841856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.1452841856
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.1970370206
Short name T214
Test name
Test status
Simulation time 52948412713 ps
CPU time 134.88 seconds
Started Mar 24 01:12:59 PM PDT 24
Finished Mar 24 01:15:14 PM PDT 24
Peak memory 267200 kb
Host smart-e47da506-5670-4432-a04a-dd2934bc9a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970370206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.1970370206
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.897378892
Short name T613
Test name
Test status
Simulation time 27803422395 ps
CPU time 78.75 seconds
Started Mar 24 01:13:02 PM PDT 24
Finished Mar 24 01:14:21 PM PDT 24
Peak memory 253032 kb
Host smart-b21fbf6f-7723-4cdf-9fb6-a26ca4feb7f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897378892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.897378892
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.2356693425
Short name T756
Test name
Test status
Simulation time 1629780920 ps
CPU time 12.48 seconds
Started Mar 24 01:12:48 PM PDT 24
Finished Mar 24 01:13:00 PM PDT 24
Peak memory 238432 kb
Host smart-6faed62f-fcbf-4b32-bfbd-076cc99a4682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356693425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.2356693425
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.742591534
Short name T704
Test name
Test status
Simulation time 1748979341 ps
CPU time 5.53 seconds
Started Mar 24 01:13:03 PM PDT 24
Finished Mar 24 01:13:09 PM PDT 24
Peak memory 233556 kb
Host smart-c50c64e8-b595-4770-9ecb-c68b8c39e7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742591534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.742591534
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.2346607760
Short name T386
Test name
Test status
Simulation time 10385076005 ps
CPU time 40.59 seconds
Started Mar 24 01:13:03 PM PDT 24
Finished Mar 24 01:13:44 PM PDT 24
Peak memory 249436 kb
Host smart-18daafab-7951-4a68-a3c3-484e3ef426f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346607760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.2346607760
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.647729470
Short name T368
Test name
Test status
Simulation time 2430136561 ps
CPU time 9.37 seconds
Started Mar 24 01:13:03 PM PDT 24
Finished Mar 24 01:13:13 PM PDT 24
Peak memory 218908 kb
Host smart-e38667df-cb1b-47b7-b508-56e76fee984d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647729470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap
.647729470
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.2305790252
Short name T760
Test name
Test status
Simulation time 56104367431 ps
CPU time 36.91 seconds
Started Mar 24 01:13:03 PM PDT 24
Finished Mar 24 01:13:41 PM PDT 24
Peak memory 248024 kb
Host smart-ccdc4a42-c9f6-4824-aa5a-d2715ddc7dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305790252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.2305790252
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_ram_cfg.82413861
Short name T912
Test name
Test status
Simulation time 16829244 ps
CPU time 0.8 seconds
Started Mar 24 01:13:03 PM PDT 24
Finished Mar 24 01:13:05 PM PDT 24
Peak memory 216576 kb
Host smart-5b0027c9-507b-4851-a4f5-8014943fca0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82413861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_ram_cfg.82413861
Directory /workspace/11.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.3867816978
Short name T527
Test name
Test status
Simulation time 806655678 ps
CPU time 5.31 seconds
Started Mar 24 01:13:07 PM PDT 24
Finished Mar 24 01:13:13 PM PDT 24
Peak memory 223496 kb
Host smart-eea87287-dfee-4d9f-953a-051c3332b653
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3867816978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.3867816978
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.289497900
Short name T784
Test name
Test status
Simulation time 30679152631 ps
CPU time 218.61 seconds
Started Mar 24 01:13:01 PM PDT 24
Finished Mar 24 01:16:41 PM PDT 24
Peak memory 249648 kb
Host smart-156bebe6-81d5-4fb7-b084-e46b1869f20c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289497900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stres
s_all.289497900
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.2723962657
Short name T300
Test name
Test status
Simulation time 3822454860 ps
CPU time 23.3 seconds
Started Mar 24 01:13:01 PM PDT 24
Finished Mar 24 01:13:25 PM PDT 24
Peak memory 216840 kb
Host smart-55c5e1ff-6052-4cb7-88ea-c8f043177406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723962657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.2723962657
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.697065050
Short name T792
Test name
Test status
Simulation time 142031187 ps
CPU time 1.26 seconds
Started Mar 24 01:13:06 PM PDT 24
Finished Mar 24 01:13:07 PM PDT 24
Peak memory 207988 kb
Host smart-9f18a1a3-f8ee-4aeb-951f-37b8d0e70e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697065050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.697065050
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.3453475220
Short name T631
Test name
Test status
Simulation time 172773999 ps
CPU time 4.9 seconds
Started Mar 24 01:12:59 PM PDT 24
Finished Mar 24 01:13:04 PM PDT 24
Peak memory 216612 kb
Host smart-85fdfd66-7066-4b45-99a4-873808fb120a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453475220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.3453475220
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.830090082
Short name T270
Test name
Test status
Simulation time 97355611 ps
CPU time 0.94 seconds
Started Mar 24 01:13:03 PM PDT 24
Finished Mar 24 01:13:04 PM PDT 24
Peak memory 207136 kb
Host smart-46d0f59c-beb8-4d50-9fae-f5be04457ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830090082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.830090082
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.1909704705
Short name T582
Test name
Test status
Simulation time 8501704774 ps
CPU time 16.39 seconds
Started Mar 24 01:13:06 PM PDT 24
Finished Mar 24 01:13:23 PM PDT 24
Peak memory 234424 kb
Host smart-62d5bdee-2b2d-4065-8f00-4537f167c4a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909704705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.1909704705
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.385902016
Short name T308
Test name
Test status
Simulation time 48661922 ps
CPU time 0.72 seconds
Started Mar 24 01:13:03 PM PDT 24
Finished Mar 24 01:13:05 PM PDT 24
Peak memory 205532 kb
Host smart-37995b4a-c593-4670-af38-53ab93b32051
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385902016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.385902016
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.3307361029
Short name T596
Test name
Test status
Simulation time 2665026671 ps
CPU time 2.66 seconds
Started Mar 24 01:13:08 PM PDT 24
Finished Mar 24 01:13:11 PM PDT 24
Peak memory 219004 kb
Host smart-46eed224-98a6-4786-a568-93e24f24623e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307361029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.3307361029
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.299490336
Short name T750
Test name
Test status
Simulation time 17377299 ps
CPU time 0.78 seconds
Started Mar 24 01:13:03 PM PDT 24
Finished Mar 24 01:13:04 PM PDT 24
Peak memory 205784 kb
Host smart-ab7a8c3b-6642-492a-b10f-b2eadc7f8531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299490336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.299490336
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.292514423
Short name T799
Test name
Test status
Simulation time 13653410911 ps
CPU time 75.11 seconds
Started Mar 24 01:13:08 PM PDT 24
Finished Mar 24 01:14:23 PM PDT 24
Peak memory 254872 kb
Host smart-d6fa02e4-a410-4322-8b39-1586da64ae00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292514423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.292514423
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.719288359
Short name T149
Test name
Test status
Simulation time 10057552413 ps
CPU time 104.27 seconds
Started Mar 24 01:13:05 PM PDT 24
Finished Mar 24 01:14:50 PM PDT 24
Peak memory 273804 kb
Host smart-2ad5ad39-edd5-4048-a995-9fc6f30cabb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719288359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.719288359
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.3029755887
Short name T353
Test name
Test status
Simulation time 11414366932 ps
CPU time 31.15 seconds
Started Mar 24 01:13:08 PM PDT 24
Finished Mar 24 01:13:40 PM PDT 24
Peak memory 234604 kb
Host smart-a70da2c5-55a8-40c8-ae22-b9cc451a92f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029755887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.3029755887
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.3946961042
Short name T538
Test name
Test status
Simulation time 643193097 ps
CPU time 4.95 seconds
Started Mar 24 01:12:59 PM PDT 24
Finished Mar 24 01:13:04 PM PDT 24
Peak memory 221332 kb
Host smart-53c2a144-e07f-41ab-ada7-111ecc6fd434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946961042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.3946961042
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.916664146
Short name T649
Test name
Test status
Simulation time 5369415139 ps
CPU time 24.57 seconds
Started Mar 24 01:13:09 PM PDT 24
Finished Mar 24 01:13:34 PM PDT 24
Peak memory 239624 kb
Host smart-a01e0b2a-b61f-4263-95e9-bf2334a1493f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916664146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.916664146
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.696884963
Short name T167
Test name
Test status
Simulation time 552932022 ps
CPU time 5.79 seconds
Started Mar 24 01:13:04 PM PDT 24
Finished Mar 24 01:13:11 PM PDT 24
Peak memory 224884 kb
Host smart-2dc86374-d7fd-4c2a-82c8-d862b4637c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696884963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap
.696884963
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.2477936268
Short name T182
Test name
Test status
Simulation time 12329683591 ps
CPU time 9.55 seconds
Started Mar 24 01:13:03 PM PDT 24
Finished Mar 24 01:13:13 PM PDT 24
Peak memory 219096 kb
Host smart-247c8eee-7d44-4981-8c2e-7359b59d693c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477936268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.2477936268
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_ram_cfg.418497555
Short name T898
Test name
Test status
Simulation time 19843830 ps
CPU time 0.73 seconds
Started Mar 24 01:13:00 PM PDT 24
Finished Mar 24 01:13:05 PM PDT 24
Peak memory 216548 kb
Host smart-8a8850dc-c3c7-4196-97fb-0b50bfaf2bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418497555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_ram_cfg.418497555
Directory /workspace/12.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.1449125306
Short name T561
Test name
Test status
Simulation time 301564816 ps
CPU time 4.46 seconds
Started Mar 24 01:13:05 PM PDT 24
Finished Mar 24 01:13:10 PM PDT 24
Peak memory 223128 kb
Host smart-291d292d-e8a4-4527-85e0-832bcca682f2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1449125306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.1449125306
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.1336494301
Short name T115
Test name
Test status
Simulation time 44432325363 ps
CPU time 148.28 seconds
Started Mar 24 01:13:05 PM PDT 24
Finished Mar 24 01:15:34 PM PDT 24
Peak memory 257680 kb
Host smart-6ed63312-f87b-412d-aa2d-8232eedbfe17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336494301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.1336494301
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.1511475396
Short name T938
Test name
Test status
Simulation time 232746321 ps
CPU time 2.61 seconds
Started Mar 24 01:13:02 PM PDT 24
Finished Mar 24 01:13:05 PM PDT 24
Peak memory 216612 kb
Host smart-bd8697e8-80d6-481c-951e-914c6315399c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511475396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.1511475396
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.1314083369
Short name T401
Test name
Test status
Simulation time 5802898261 ps
CPU time 15.16 seconds
Started Mar 24 01:13:03 PM PDT 24
Finished Mar 24 01:13:19 PM PDT 24
Peak memory 216688 kb
Host smart-30754990-fcd6-448b-ae99-ca50a60706d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314083369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.1314083369
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.2412088847
Short name T952
Test name
Test status
Simulation time 29101031 ps
CPU time 1 seconds
Started Mar 24 01:13:07 PM PDT 24
Finished Mar 24 01:13:08 PM PDT 24
Peak memory 207108 kb
Host smart-79c02bfd-51b0-4188-ae93-9ea521221a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412088847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.2412088847
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.4290874300
Short name T63
Test name
Test status
Simulation time 23213876 ps
CPU time 0.78 seconds
Started Mar 24 01:12:59 PM PDT 24
Finished Mar 24 01:13:00 PM PDT 24
Peak memory 206052 kb
Host smart-53cb25e2-f04a-4ba7-a7ef-f7d43cd6e046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290874300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.4290874300
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.800738661
Short name T151
Test name
Test status
Simulation time 37267214343 ps
CPU time 14.1 seconds
Started Mar 24 01:13:11 PM PDT 24
Finished Mar 24 01:13:26 PM PDT 24
Peak memory 230220 kb
Host smart-14ab2fda-a87c-488c-a0f5-380fa8b29fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800738661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.800738661
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.345164812
Short name T662
Test name
Test status
Simulation time 30763785 ps
CPU time 0.73 seconds
Started Mar 24 01:13:03 PM PDT 24
Finished Mar 24 01:13:05 PM PDT 24
Peak memory 205692 kb
Host smart-bc8e6701-93b5-47c2-9b7a-7ef0729f2dad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345164812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.345164812
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.958483749
Short name T783
Test name
Test status
Simulation time 5492897865 ps
CPU time 5.24 seconds
Started Mar 24 01:12:56 PM PDT 24
Finished Mar 24 01:13:02 PM PDT 24
Peak memory 224956 kb
Host smart-91564a04-4031-41f2-b2f8-a2ba808f19fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958483749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.958483749
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.1615006225
Short name T746
Test name
Test status
Simulation time 17700127 ps
CPU time 0.84 seconds
Started Mar 24 01:13:12 PM PDT 24
Finished Mar 24 01:13:13 PM PDT 24
Peak memory 206812 kb
Host smart-021db548-5543-461b-9c20-8fdeed5c31ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615006225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.1615006225
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.4257697718
Short name T819
Test name
Test status
Simulation time 55217970331 ps
CPU time 289.25 seconds
Started Mar 24 01:13:08 PM PDT 24
Finished Mar 24 01:17:57 PM PDT 24
Peak memory 265072 kb
Host smart-d6d38e41-a7f8-48d7-ba9c-ec4a350355c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257697718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.4257697718
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.1435181586
Short name T38
Test name
Test status
Simulation time 55149176357 ps
CPU time 123.52 seconds
Started Mar 24 01:13:03 PM PDT 24
Finished Mar 24 01:15:07 PM PDT 24
Peak memory 273720 kb
Host smart-27cf88bc-fc24-4b3e-b2bc-bf3d828cc0e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435181586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.1435181586
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.3124887949
Short name T60
Test name
Test status
Simulation time 3298396437 ps
CPU time 45.09 seconds
Started Mar 24 01:13:03 PM PDT 24
Finished Mar 24 01:13:49 PM PDT 24
Peak memory 235716 kb
Host smart-4d4b09b0-5671-4edb-8b56-6d8395275d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124887949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.3124887949
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_intercept.663675568
Short name T653
Test name
Test status
Simulation time 247198944 ps
CPU time 4.49 seconds
Started Mar 24 01:13:08 PM PDT 24
Finished Mar 24 01:13:13 PM PDT 24
Peak memory 234244 kb
Host smart-359601de-866e-4d37-9414-e22f82f66ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663675568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.663675568
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.1963893547
Short name T172
Test name
Test status
Simulation time 60598804975 ps
CPU time 43.93 seconds
Started Mar 24 01:13:06 PM PDT 24
Finished Mar 24 01:13:50 PM PDT 24
Peak memory 248620 kb
Host smart-4de42373-8e59-4533-a2d8-a27add716f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963893547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.1963893547
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.2541492711
Short name T570
Test name
Test status
Simulation time 2825958932 ps
CPU time 6.97 seconds
Started Mar 24 01:13:10 PM PDT 24
Finished Mar 24 01:13:17 PM PDT 24
Peak memory 224848 kb
Host smart-9adc4454-0b08-445d-a352-c4d542379754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541492711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.2541492711
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.914324734
Short name T895
Test name
Test status
Simulation time 1608399185 ps
CPU time 7.48 seconds
Started Mar 24 01:13:04 PM PDT 24
Finished Mar 24 01:13:12 PM PDT 24
Peak memory 217300 kb
Host smart-9e01c68c-3032-4b90-b4fb-ab3948f35f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914324734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.914324734
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_ram_cfg.2437373165
Short name T390
Test name
Test status
Simulation time 15988778 ps
CPU time 0.76 seconds
Started Mar 24 01:13:05 PM PDT 24
Finished Mar 24 01:13:06 PM PDT 24
Peak memory 216520 kb
Host smart-7c758534-4582-462a-a75c-c1f0e0a22f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437373165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_ram_cfg.2437373165
Directory /workspace/13.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.3921024696
Short name T327
Test name
Test status
Simulation time 276635094 ps
CPU time 4.12 seconds
Started Mar 24 01:13:07 PM PDT 24
Finished Mar 24 01:13:12 PM PDT 24
Peak memory 222844 kb
Host smart-241da86f-13d1-4040-b8b8-328f5b86bd2f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3921024696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.3921024696
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.276644954
Short name T24
Test name
Test status
Simulation time 53043750421 ps
CPU time 87.45 seconds
Started Mar 24 01:13:01 PM PDT 24
Finished Mar 24 01:14:28 PM PDT 24
Peak memory 237824 kb
Host smart-b7b49cee-f54a-45c9-9900-13dd978578d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276644954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stres
s_all.276644954
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.2056284197
Short name T675
Test name
Test status
Simulation time 106178069 ps
CPU time 2.05 seconds
Started Mar 24 01:13:05 PM PDT 24
Finished Mar 24 01:13:08 PM PDT 24
Peak memory 216936 kb
Host smart-480132bb-fb48-49e0-a4b9-7957295f17cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056284197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.2056284197
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.3175171296
Short name T771
Test name
Test status
Simulation time 2072849668 ps
CPU time 6.47 seconds
Started Mar 24 01:13:03 PM PDT 24
Finished Mar 24 01:13:10 PM PDT 24
Peak memory 216428 kb
Host smart-e585e9cd-2181-485b-8b85-ffbbd1b20888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175171296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.3175171296
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.2234188587
Short name T776
Test name
Test status
Simulation time 468670809 ps
CPU time 3.16 seconds
Started Mar 24 01:12:56 PM PDT 24
Finished Mar 24 01:12:59 PM PDT 24
Peak memory 216672 kb
Host smart-3d95efe8-d778-47d4-93cb-5e2a00b20ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234188587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.2234188587
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.2714140910
Short name T445
Test name
Test status
Simulation time 126647329 ps
CPU time 0.81 seconds
Started Mar 24 01:13:07 PM PDT 24
Finished Mar 24 01:13:08 PM PDT 24
Peak memory 206132 kb
Host smart-ebbfb1d2-2b7e-4aa7-b038-65f559254408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714140910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.2714140910
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.1423906297
Short name T200
Test name
Test status
Simulation time 543007906 ps
CPU time 5.45 seconds
Started Mar 24 01:13:03 PM PDT 24
Finished Mar 24 01:13:09 PM PDT 24
Peak memory 217508 kb
Host smart-a6973c88-f61d-4e5c-a9a9-bf2d0783a34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423906297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.1423906297
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.2525538607
Short name T495
Test name
Test status
Simulation time 25560128 ps
CPU time 0.71 seconds
Started Mar 24 01:13:05 PM PDT 24
Finished Mar 24 01:13:06 PM PDT 24
Peak memory 205000 kb
Host smart-2de6d536-39bb-4510-9f6d-f72e0abb7754
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525538607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
2525538607
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.2394709219
Short name T265
Test name
Test status
Simulation time 1169526937 ps
CPU time 5.27 seconds
Started Mar 24 01:13:07 PM PDT 24
Finished Mar 24 01:13:13 PM PDT 24
Peak memory 220000 kb
Host smart-5e529bcc-7a49-49eb-8975-2a8308902f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394709219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.2394709219
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.507492484
Short name T581
Test name
Test status
Simulation time 83910610 ps
CPU time 0.84 seconds
Started Mar 24 01:13:07 PM PDT 24
Finished Mar 24 01:13:08 PM PDT 24
Peak memory 206872 kb
Host smart-f43b6283-ceb1-4c6d-9f1d-3007df20d35e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507492484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.507492484
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.386416234
Short name T159
Test name
Test status
Simulation time 38980413050 ps
CPU time 178.74 seconds
Started Mar 24 01:13:09 PM PDT 24
Finished Mar 24 01:16:09 PM PDT 24
Peak memory 241244 kb
Host smart-e28b300c-d5bf-4a5b-a5d1-a06a6a444a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386416234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.386416234
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.3135034219
Short name T39
Test name
Test status
Simulation time 6810994283 ps
CPU time 51.52 seconds
Started Mar 24 01:13:15 PM PDT 24
Finished Mar 24 01:14:07 PM PDT 24
Peak memory 235108 kb
Host smart-d812ae8a-ec0f-4e69-9e15-7a0601d6ac4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135034219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.3135034219
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.2050850536
Short name T295
Test name
Test status
Simulation time 10050993403 ps
CPU time 62.36 seconds
Started Mar 24 01:13:08 PM PDT 24
Finished Mar 24 01:14:11 PM PDT 24
Peak memory 241316 kb
Host smart-45d205b5-0e26-4c90-a6ed-e349e73683db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050850536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.2050850536
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.1897290655
Short name T245
Test name
Test status
Simulation time 25669471030 ps
CPU time 35.03 seconds
Started Mar 24 01:13:10 PM PDT 24
Finished Mar 24 01:13:45 PM PDT 24
Peak memory 233220 kb
Host smart-6265f6ec-03f9-4ae3-a5c9-7907cfea5e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897290655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.1897290655
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.3073105957
Short name T900
Test name
Test status
Simulation time 12624500490 ps
CPU time 5.38 seconds
Started Mar 24 01:13:06 PM PDT 24
Finished Mar 24 01:13:12 PM PDT 24
Peak memory 219836 kb
Host smart-1a2c8e7e-2999-4db8-acbc-fe1eab6ecb82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073105957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.3073105957
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.579795863
Short name T860
Test name
Test status
Simulation time 85861340410 ps
CPU time 40.06 seconds
Started Mar 24 01:13:04 PM PDT 24
Finished Mar 24 01:13:44 PM PDT 24
Peak memory 233080 kb
Host smart-8897fdfe-7f32-4cd2-8322-22168469b29e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579795863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.579795863
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.1777354708
Short name T157
Test name
Test status
Simulation time 1532901273 ps
CPU time 9.64 seconds
Started Mar 24 01:13:12 PM PDT 24
Finished Mar 24 01:13:22 PM PDT 24
Peak memory 224156 kb
Host smart-eeaeeb65-2dea-4cc4-8b27-58fe1810cdae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777354708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.1777354708
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.3532587428
Short name T626
Test name
Test status
Simulation time 69555603 ps
CPU time 2.94 seconds
Started Mar 24 01:13:09 PM PDT 24
Finished Mar 24 01:13:13 PM PDT 24
Peak memory 233060 kb
Host smart-7f257c68-972e-4af2-a087-4664d6a164c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532587428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.3532587428
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_ram_cfg.2924304909
Short name T929
Test name
Test status
Simulation time 27731259 ps
CPU time 0.75 seconds
Started Mar 24 01:13:06 PM PDT 24
Finished Mar 24 01:13:07 PM PDT 24
Peak memory 216544 kb
Host smart-6057f470-a092-4b3f-b308-e6123dd9680e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924304909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_ram_cfg.2924304909
Directory /workspace/14.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.2022762039
Short name T448
Test name
Test status
Simulation time 485783444 ps
CPU time 3.59 seconds
Started Mar 24 01:13:16 PM PDT 24
Finished Mar 24 01:13:20 PM PDT 24
Peak memory 223308 kb
Host smart-001ad8dd-73da-41f1-8537-dacf47de9d09
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2022762039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.2022762039
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.1399262508
Short name T134
Test name
Test status
Simulation time 60896786874 ps
CPU time 245.44 seconds
Started Mar 24 01:13:04 PM PDT 24
Finished Mar 24 01:17:09 PM PDT 24
Peak memory 256172 kb
Host smart-c3e8ddfa-69ba-4f1c-878e-a998fc7fa909
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399262508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.1399262508
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.4253542074
Short name T440
Test name
Test status
Simulation time 2309941913 ps
CPU time 9.49 seconds
Started Mar 24 01:13:06 PM PDT 24
Finished Mar 24 01:13:15 PM PDT 24
Peak memory 216696 kb
Host smart-4020f1ba-221f-44fd-b7d8-e85c1fdb6727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253542074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.4253542074
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.2886858619
Short name T648
Test name
Test status
Simulation time 1070168040 ps
CPU time 5.9 seconds
Started Mar 24 01:13:07 PM PDT 24
Finished Mar 24 01:13:13 PM PDT 24
Peak memory 216640 kb
Host smart-3351847c-6184-45ea-97cf-fa0db436e1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886858619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.2886858619
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.219717305
Short name T524
Test name
Test status
Simulation time 21915031 ps
CPU time 0.74 seconds
Started Mar 24 01:13:13 PM PDT 24
Finished Mar 24 01:13:14 PM PDT 24
Peak memory 205968 kb
Host smart-de1da7be-d82b-4458-992b-632544b3ecf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219717305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.219717305
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.2984178662
Short name T301
Test name
Test status
Simulation time 138603437 ps
CPU time 0.98 seconds
Started Mar 24 01:13:03 PM PDT 24
Finished Mar 24 01:13:05 PM PDT 24
Peak memory 206976 kb
Host smart-65bb7e78-5923-43e7-9aaa-6481f9fed286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984178662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.2984178662
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.3407759441
Short name T351
Test name
Test status
Simulation time 3958487515 ps
CPU time 14.54 seconds
Started Mar 24 01:13:22 PM PDT 24
Finished Mar 24 01:13:36 PM PDT 24
Peak memory 220012 kb
Host smart-88550011-de68-4525-9148-a88635e2d392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407759441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.3407759441
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.3200456926
Short name T698
Test name
Test status
Simulation time 28770619 ps
CPU time 0.73 seconds
Started Mar 24 01:13:11 PM PDT 24
Finished Mar 24 01:13:13 PM PDT 24
Peak memory 205396 kb
Host smart-8c0e7cd1-e843-4c5a-b8d4-a7778559d2ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200456926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
3200456926
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.3438128446
Short name T964
Test name
Test status
Simulation time 404126834 ps
CPU time 3.84 seconds
Started Mar 24 01:13:11 PM PDT 24
Finished Mar 24 01:13:15 PM PDT 24
Peak memory 234056 kb
Host smart-dcc4b37c-65b1-4af4-8ae4-29dba16a5740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438128446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.3438128446
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.2443981840
Short name T378
Test name
Test status
Simulation time 13739311 ps
CPU time 0.81 seconds
Started Mar 24 01:13:05 PM PDT 24
Finished Mar 24 01:13:06 PM PDT 24
Peak memory 206812 kb
Host smart-b7653d70-d85d-482f-915c-9f9c35bc8960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443981840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.2443981840
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.800253987
Short name T465
Test name
Test status
Simulation time 42493878090 ps
CPU time 126.35 seconds
Started Mar 24 01:13:10 PM PDT 24
Finished Mar 24 01:15:16 PM PDT 24
Peak memory 254648 kb
Host smart-88a584b4-6e01-4429-bd7d-3bc09b078fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800253987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.800253987
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.3172126294
Short name T692
Test name
Test status
Simulation time 39067977865 ps
CPU time 180.32 seconds
Started Mar 24 01:13:10 PM PDT 24
Finished Mar 24 01:16:10 PM PDT 24
Peak memory 255212 kb
Host smart-ea63fdc1-31f8-4894-ae90-939765c8825e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172126294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.3172126294
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.197692283
Short name T893
Test name
Test status
Simulation time 353819234810 ps
CPU time 243.7 seconds
Started Mar 24 01:13:05 PM PDT 24
Finished Mar 24 01:17:09 PM PDT 24
Peak memory 269232 kb
Host smart-b33c9a75-8457-4b54-a6c5-c632df639dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197692283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idle
.197692283
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.3396173894
Short name T885
Test name
Test status
Simulation time 1310399273 ps
CPU time 15.34 seconds
Started Mar 24 01:13:03 PM PDT 24
Finished Mar 24 01:13:19 PM PDT 24
Peak memory 249000 kb
Host smart-44bb49d3-5e1b-4cee-b386-031fd2f1d896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396173894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.3396173894
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.510898539
Short name T838
Test name
Test status
Simulation time 156037357 ps
CPU time 4.14 seconds
Started Mar 24 01:13:07 PM PDT 24
Finished Mar 24 01:13:12 PM PDT 24
Peak memory 234140 kb
Host smart-a5e3b643-a3fe-4acf-b3b4-38de575e0160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510898539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.510898539
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.1011885519
Short name T349
Test name
Test status
Simulation time 289247214 ps
CPU time 4.65 seconds
Started Mar 24 01:13:27 PM PDT 24
Finished Mar 24 01:13:32 PM PDT 24
Peak memory 229596 kb
Host smart-984053f2-8208-4419-a086-b2fc6060bc4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011885519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.1011885519
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.3789086541
Short name T304
Test name
Test status
Simulation time 17216016612 ps
CPU time 16.02 seconds
Started Mar 24 01:13:04 PM PDT 24
Finished Mar 24 01:13:21 PM PDT 24
Peak memory 234832 kb
Host smart-4f7dc535-08a9-47e5-9ebf-c4f50b7c59f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789086541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.3789086541
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.466790944
Short name T915
Test name
Test status
Simulation time 1061008518 ps
CPU time 3.56 seconds
Started Mar 24 01:13:03 PM PDT 24
Finished Mar 24 01:13:07 PM PDT 24
Peak memory 233996 kb
Host smart-9971aeb4-40b7-4ece-9db2-8cac1b7feac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466790944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.466790944
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_ram_cfg.4013766748
Short name T725
Test name
Test status
Simulation time 32017919 ps
CPU time 0.78 seconds
Started Mar 24 01:13:17 PM PDT 24
Finished Mar 24 01:13:17 PM PDT 24
Peak memory 216516 kb
Host smart-5a9d1e42-7126-49cd-ba29-1cad942d74f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013766748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_ram_cfg.4013766748
Directory /workspace/15.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.2172230505
Short name T65
Test name
Test status
Simulation time 1636849693 ps
CPU time 4.92 seconds
Started Mar 24 01:13:05 PM PDT 24
Finished Mar 24 01:13:10 PM PDT 24
Peak memory 222580 kb
Host smart-364b5f1c-2587-4a8e-8e0c-ff04e8352e4c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2172230505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.2172230505
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.1434883081
Short name T820
Test name
Test status
Simulation time 14123603895 ps
CPU time 19.82 seconds
Started Mar 24 01:13:12 PM PDT 24
Finished Mar 24 01:13:33 PM PDT 24
Peak memory 216756 kb
Host smart-999a2bb3-d084-4e62-a1fd-1bcf961b4a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434883081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.1434883081
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.2436676455
Short name T430
Test name
Test status
Simulation time 1305096067 ps
CPU time 5.69 seconds
Started Mar 24 01:13:09 PM PDT 24
Finished Mar 24 01:13:15 PM PDT 24
Peak memory 216852 kb
Host smart-1b251e8b-bfe8-4063-8fac-57314bd7541a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436676455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.2436676455
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.4263522129
Short name T549
Test name
Test status
Simulation time 293037141 ps
CPU time 1.45 seconds
Started Mar 24 01:13:10 PM PDT 24
Finished Mar 24 01:13:11 PM PDT 24
Peak memory 216656 kb
Host smart-2dcce933-6cc1-4d13-8673-67049836e77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263522129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.4263522129
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.2560657860
Short name T515
Test name
Test status
Simulation time 24478590 ps
CPU time 0.73 seconds
Started Mar 24 01:13:20 PM PDT 24
Finished Mar 24 01:13:21 PM PDT 24
Peak memory 206072 kb
Host smart-319dba7f-dd62-4ef4-8909-ae1c3c3b4245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560657860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.2560657860
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.2178977667
Short name T703
Test name
Test status
Simulation time 1517892396 ps
CPU time 5.13 seconds
Started Mar 24 01:13:18 PM PDT 24
Finished Mar 24 01:13:24 PM PDT 24
Peak memory 233820 kb
Host smart-342ca4a5-cc88-415f-bc6a-b0a64db891fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178977667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.2178977667
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.1933803098
Short name T706
Test name
Test status
Simulation time 44787772 ps
CPU time 0.73 seconds
Started Mar 24 01:13:10 PM PDT 24
Finished Mar 24 01:13:11 PM PDT 24
Peak memory 205124 kb
Host smart-4bab5bfe-ca18-414e-a602-065f953fb3d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933803098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
1933803098
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.1400832806
Short name T523
Test name
Test status
Simulation time 966522102 ps
CPU time 2.94 seconds
Started Mar 24 01:13:13 PM PDT 24
Finished Mar 24 01:13:16 PM PDT 24
Peak memory 233968 kb
Host smart-b8a4b4d0-9ffa-4f4f-bede-10e0b941b1ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400832806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.1400832806
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.3210011072
Short name T902
Test name
Test status
Simulation time 23150712 ps
CPU time 0.78 seconds
Started Mar 24 01:13:14 PM PDT 24
Finished Mar 24 01:13:15 PM PDT 24
Peak memory 206744 kb
Host smart-6517b456-6eb2-4a52-ae90-1b3b702fb9e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210011072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.3210011072
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.2962714242
Short name T955
Test name
Test status
Simulation time 3060508295 ps
CPU time 29.97 seconds
Started Mar 24 01:13:29 PM PDT 24
Finished Mar 24 01:13:59 PM PDT 24
Peak memory 241292 kb
Host smart-bec70c48-361f-407b-9458-5bfb89c34551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962714242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.2962714242
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.2973898637
Short name T847
Test name
Test status
Simulation time 29947536151 ps
CPU time 72.93 seconds
Started Mar 24 01:13:15 PM PDT 24
Finished Mar 24 01:14:33 PM PDT 24
Peak memory 249992 kb
Host smart-edb7c880-8843-46e5-aaba-d6d447708dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973898637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.2973898637
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.2369694166
Short name T118
Test name
Test status
Simulation time 2577066095 ps
CPU time 8.87 seconds
Started Mar 24 01:13:12 PM PDT 24
Finished Mar 24 01:13:22 PM PDT 24
Peak memory 241128 kb
Host smart-cc4e8666-ebcf-436a-a96f-7ebeed503c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369694166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.2369694166
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.3599646372
Short name T935
Test name
Test status
Simulation time 320597490 ps
CPU time 2.17 seconds
Started Mar 24 01:13:41 PM PDT 24
Finished Mar 24 01:13:43 PM PDT 24
Peak memory 217012 kb
Host smart-a409643c-8dcc-4912-bfcd-7e5dd2902f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599646372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.3599646372
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.4030730083
Short name T520
Test name
Test status
Simulation time 1428796661 ps
CPU time 4.36 seconds
Started Mar 24 01:13:27 PM PDT 24
Finished Mar 24 01:13:32 PM PDT 24
Peak memory 222388 kb
Host smart-823a0df6-76f8-4d61-b6ac-3c97a52bfa03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030730083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.4030730083
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.363164546
Short name T563
Test name
Test status
Simulation time 7541451048 ps
CPU time 7.62 seconds
Started Mar 24 01:13:14 PM PDT 24
Finished Mar 24 01:13:22 PM PDT 24
Peak memory 233936 kb
Host smart-cea86233-7680-421c-bc88-aedb8ee61800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363164546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swap
.363164546
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.2372997553
Short name T173
Test name
Test status
Simulation time 1190273866 ps
CPU time 5.06 seconds
Started Mar 24 01:13:28 PM PDT 24
Finished Mar 24 01:13:33 PM PDT 24
Peak memory 224824 kb
Host smart-0869cdb0-76cc-4d73-9ae4-ae3b4c38325c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372997553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.2372997553
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_ram_cfg.1102117784
Short name T50
Test name
Test status
Simulation time 23596113 ps
CPU time 0.76 seconds
Started Mar 24 01:13:13 PM PDT 24
Finished Mar 24 01:13:14 PM PDT 24
Peak memory 216592 kb
Host smart-d6fb057b-0f44-4b63-9b2a-acff7c0ad21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102117784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_ram_cfg.1102117784
Directory /workspace/16.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.3838691850
Short name T753
Test name
Test status
Simulation time 1172572339 ps
CPU time 5.55 seconds
Started Mar 24 01:13:15 PM PDT 24
Finished Mar 24 01:13:20 PM PDT 24
Peak memory 222740 kb
Host smart-83b5ad16-6a11-4655-b24c-f45c0b0f3b97
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3838691850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.3838691850
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.3271324681
Short name T10
Test name
Test status
Simulation time 28426288837 ps
CPU time 50.61 seconds
Started Mar 24 01:13:30 PM PDT 24
Finished Mar 24 01:14:20 PM PDT 24
Peak memory 216720 kb
Host smart-e85ce7c2-ad4c-4b05-bdba-fbc026321d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271324681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.3271324681
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.667430283
Short name T291
Test name
Test status
Simulation time 2260051714 ps
CPU time 9.21 seconds
Started Mar 24 01:13:14 PM PDT 24
Finished Mar 24 01:13:23 PM PDT 24
Peak memory 216684 kb
Host smart-f35a1dac-25a3-4e33-8d41-d74bc9e1d703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667430283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.667430283
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.3824714284
Short name T598
Test name
Test status
Simulation time 84122751 ps
CPU time 2.26 seconds
Started Mar 24 01:13:18 PM PDT 24
Finished Mar 24 01:13:21 PM PDT 24
Peak memory 216696 kb
Host smart-d5ee3160-17b0-45ac-90a3-f9a0701e363d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824714284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.3824714284
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.1908406591
Short name T878
Test name
Test status
Simulation time 295210757 ps
CPU time 0.96 seconds
Started Mar 24 01:13:35 PM PDT 24
Finished Mar 24 01:13:37 PM PDT 24
Peak memory 206056 kb
Host smart-efd35926-fb48-49e6-a52a-eb95e15f3627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908406591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.1908406591
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.3099343125
Short name T850
Test name
Test status
Simulation time 789313486 ps
CPU time 6.58 seconds
Started Mar 24 01:13:33 PM PDT 24
Finished Mar 24 01:13:40 PM PDT 24
Peak memory 236964 kb
Host smart-d42c6468-ddf0-4047-a88a-74cca8ad8d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099343125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.3099343125
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.1045561777
Short name T827
Test name
Test status
Simulation time 22586893 ps
CPU time 0.71 seconds
Started Mar 24 01:13:17 PM PDT 24
Finished Mar 24 01:13:18 PM PDT 24
Peak memory 205208 kb
Host smart-5aa20b31-23c8-48ae-bf0e-089071017d29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045561777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
1045561777
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.780668342
Short name T620
Test name
Test status
Simulation time 1289550764 ps
CPU time 5.46 seconds
Started Mar 24 01:13:26 PM PDT 24
Finished Mar 24 01:13:32 PM PDT 24
Peak memory 233824 kb
Host smart-fea96b36-3ba1-4864-8987-b520f00a1213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780668342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.780668342
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.1889828429
Short name T657
Test name
Test status
Simulation time 31114497 ps
CPU time 0.81 seconds
Started Mar 24 01:13:29 PM PDT 24
Finished Mar 24 01:13:31 PM PDT 24
Peak memory 206064 kb
Host smart-5f7e6647-1b93-4158-8b2c-fccd9d99a796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889828429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.1889828429
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.2675227176
Short name T916
Test name
Test status
Simulation time 1438737919650 ps
CPU time 358.11 seconds
Started Mar 24 01:13:42 PM PDT 24
Finished Mar 24 01:19:40 PM PDT 24
Peak memory 265188 kb
Host smart-a3ba43a0-c572-4332-ad13-d4fed4124a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675227176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.2675227176
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.2560450963
Short name T884
Test name
Test status
Simulation time 14810145318 ps
CPU time 187.44 seconds
Started Mar 24 01:13:43 PM PDT 24
Finished Mar 24 01:16:50 PM PDT 24
Peak memory 255740 kb
Host smart-6707d5ae-5af4-4853-b234-7e3010e0cff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560450963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.2560450963
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.1758762769
Short name T846
Test name
Test status
Simulation time 34275720631 ps
CPU time 141.85 seconds
Started Mar 24 01:13:33 PM PDT 24
Finished Mar 24 01:15:56 PM PDT 24
Peak memory 259736 kb
Host smart-4bb96041-e402-4b22-9efb-925d3f3fe8ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758762769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.1758762769
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.417333234
Short name T441
Test name
Test status
Simulation time 2087871927 ps
CPU time 17.32 seconds
Started Mar 24 01:13:35 PM PDT 24
Finished Mar 24 01:13:54 PM PDT 24
Peak memory 238288 kb
Host smart-d9c380c7-e13e-42ad-99ad-a1d242b13911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417333234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.417333234
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.3723224619
Short name T711
Test name
Test status
Simulation time 6107085020 ps
CPU time 7.82 seconds
Started Mar 24 01:13:19 PM PDT 24
Finished Mar 24 01:13:27 PM PDT 24
Peak memory 221116 kb
Host smart-57a112e3-861f-4334-96be-cdd7bae429e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723224619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.3723224619
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.3860656310
Short name T597
Test name
Test status
Simulation time 4771378897 ps
CPU time 17.18 seconds
Started Mar 24 01:13:35 PM PDT 24
Finished Mar 24 01:13:53 PM PDT 24
Peak memory 249368 kb
Host smart-4d082973-65a0-4eb9-aa60-6e783d7085b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860656310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.3860656310
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.3499558215
Short name T714
Test name
Test status
Simulation time 3948384249 ps
CPU time 11.53 seconds
Started Mar 24 01:13:39 PM PDT 24
Finished Mar 24 01:13:51 PM PDT 24
Peak memory 218792 kb
Host smart-4169b42b-96fb-47ce-835d-9cc9208e4684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499558215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.3499558215
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.1262076721
Short name T496
Test name
Test status
Simulation time 1113908228 ps
CPU time 8.46 seconds
Started Mar 24 01:13:13 PM PDT 24
Finished Mar 24 01:13:22 PM PDT 24
Peak memory 218000 kb
Host smart-a5f864fd-3225-4787-a5cc-dc84fb7a1471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262076721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.1262076721
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_ram_cfg.594787932
Short name T751
Test name
Test status
Simulation time 16197870 ps
CPU time 0.78 seconds
Started Mar 24 01:13:12 PM PDT 24
Finished Mar 24 01:13:13 PM PDT 24
Peak memory 216588 kb
Host smart-060c69f7-1be6-47ae-b272-69550edc028f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594787932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_ram_cfg.594787932
Directory /workspace/17.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.4152595895
Short name T404
Test name
Test status
Simulation time 152605187 ps
CPU time 3.32 seconds
Started Mar 24 01:13:36 PM PDT 24
Finished Mar 24 01:13:40 PM PDT 24
Peak memory 219276 kb
Host smart-49f6367a-d7d2-4b8c-a1ea-69ed70f90bc7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4152595895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.4152595895
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.2619145312
Short name T794
Test name
Test status
Simulation time 76804550470 ps
CPU time 565.57 seconds
Started Mar 24 01:13:40 PM PDT 24
Finished Mar 24 01:23:05 PM PDT 24
Peak memory 265928 kb
Host smart-f7344784-548b-4343-a9bf-b4b77ccfdc94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619145312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.2619145312
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.3073904696
Short name T346
Test name
Test status
Simulation time 19412687905 ps
CPU time 55.12 seconds
Started Mar 24 01:13:12 PM PDT 24
Finished Mar 24 01:14:08 PM PDT 24
Peak memory 216636 kb
Host smart-539e9f10-7424-456c-a591-abfc0918c322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073904696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.3073904696
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.4047410646
Short name T2
Test name
Test status
Simulation time 147890734 ps
CPU time 1.01 seconds
Started Mar 24 01:13:30 PM PDT 24
Finished Mar 24 01:13:32 PM PDT 24
Peak memory 207132 kb
Host smart-c80aab8e-5ac4-464a-8488-08f9b327a0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047410646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.4047410646
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.903200182
Short name T379
Test name
Test status
Simulation time 38720657 ps
CPU time 1.46 seconds
Started Mar 24 01:13:09 PM PDT 24
Finished Mar 24 01:13:11 PM PDT 24
Peak memory 216632 kb
Host smart-6cac29c0-fd88-4a3c-a069-b240db0dc040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903200182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.903200182
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.1367707400
Short name T273
Test name
Test status
Simulation time 285102161 ps
CPU time 0.97 seconds
Started Mar 24 01:13:14 PM PDT 24
Finished Mar 24 01:13:15 PM PDT 24
Peak memory 206076 kb
Host smart-68eeb1d5-4fc1-4efc-841d-21fa6606a80c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367707400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.1367707400
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.2398834623
Short name T281
Test name
Test status
Simulation time 985491536 ps
CPU time 4.58 seconds
Started Mar 24 01:13:40 PM PDT 24
Finished Mar 24 01:13:45 PM PDT 24
Peak memory 234488 kb
Host smart-7ac7114a-7377-4c7d-a76b-b6286f66512d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398834623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.2398834623
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.2934391873
Short name T330
Test name
Test status
Simulation time 17944847 ps
CPU time 0.74 seconds
Started Mar 24 01:13:23 PM PDT 24
Finished Mar 24 01:13:24 PM PDT 24
Peak memory 205740 kb
Host smart-cb3f0dfb-f1e6-45bd-aae3-e4ffb098ce3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934391873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
2934391873
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.3131968843
Short name T545
Test name
Test status
Simulation time 38284586 ps
CPU time 2.75 seconds
Started Mar 24 01:13:22 PM PDT 24
Finished Mar 24 01:13:25 PM PDT 24
Peak memory 234744 kb
Host smart-849a9a94-4c09-4913-9b0d-ccdc19bb6705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131968843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.3131968843
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.3355189201
Short name T510
Test name
Test status
Simulation time 33317184 ps
CPU time 0.8 seconds
Started Mar 24 01:13:37 PM PDT 24
Finished Mar 24 01:13:38 PM PDT 24
Peak memory 206832 kb
Host smart-9f323660-b367-4c15-836f-7657bb91e968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355189201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.3355189201
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.3491422530
Short name T970
Test name
Test status
Simulation time 75094437947 ps
CPU time 192.43 seconds
Started Mar 24 01:13:22 PM PDT 24
Finished Mar 24 01:16:35 PM PDT 24
Peak memory 255748 kb
Host smart-ca525b66-0afd-439a-8ceb-11fb177ec3e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491422530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.3491422530
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.2112747688
Short name T886
Test name
Test status
Simulation time 3873950898 ps
CPU time 13.62 seconds
Started Mar 24 01:13:38 PM PDT 24
Finished Mar 24 01:13:52 PM PDT 24
Peak memory 221548 kb
Host smart-c5c1207d-b34a-4874-bf83-b25c637b0f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112747688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.2112747688
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.4258536042
Short name T242
Test name
Test status
Simulation time 44885551941 ps
CPU time 43.13 seconds
Started Mar 24 01:13:38 PM PDT 24
Finished Mar 24 01:14:22 PM PDT 24
Peak memory 250012 kb
Host smart-551ad75c-2aad-48cf-afb7-aa63f2d8e970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258536042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.4258536042
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.2411217700
Short name T697
Test name
Test status
Simulation time 400471887 ps
CPU time 2.93 seconds
Started Mar 24 01:13:24 PM PDT 24
Finished Mar 24 01:13:27 PM PDT 24
Peak memory 233716 kb
Host smart-924fa344-6303-4b5a-a2b6-b45a6ca275b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411217700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.2411217700
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.47819923
Short name T565
Test name
Test status
Simulation time 2166953065 ps
CPU time 6.72 seconds
Started Mar 24 01:13:41 PM PDT 24
Finished Mar 24 01:13:48 PM PDT 24
Peak memory 236444 kb
Host smart-c5582f2c-f73e-445e-8000-7169a520e201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47819923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.47819923
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.1761964636
Short name T642
Test name
Test status
Simulation time 547308480 ps
CPU time 7.29 seconds
Started Mar 24 01:13:38 PM PDT 24
Finished Mar 24 01:13:45 PM PDT 24
Peak memory 224860 kb
Host smart-e19bd452-3a68-4964-b48a-7df31f20e4ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761964636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.1761964636
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.755502735
Short name T853
Test name
Test status
Simulation time 953896279 ps
CPU time 4.36 seconds
Started Mar 24 01:13:16 PM PDT 24
Finished Mar 24 01:13:20 PM PDT 24
Peak memory 219492 kb
Host smart-3459d607-99a5-4ef0-9253-5a6e0eaeebd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755502735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.755502735
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_ram_cfg.2049682857
Short name T51
Test name
Test status
Simulation time 17889778 ps
CPU time 0.8 seconds
Started Mar 24 01:13:36 PM PDT 24
Finished Mar 24 01:13:37 PM PDT 24
Peak memory 216568 kb
Host smart-73eb0161-eda8-497e-bef5-79382e4cabc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049682857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_ram_cfg.2049682857
Directory /workspace/18.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.799505260
Short name T859
Test name
Test status
Simulation time 217047803 ps
CPU time 3.84 seconds
Started Mar 24 01:13:44 PM PDT 24
Finished Mar 24 01:13:47 PM PDT 24
Peak memory 219460 kb
Host smart-fa25f4a5-b625-4e75-8ceb-1457da5bf5db
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=799505260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dire
ct.799505260
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.2978498189
Short name T263
Test name
Test status
Simulation time 1841519219 ps
CPU time 26.82 seconds
Started Mar 24 01:13:43 PM PDT 24
Finished Mar 24 01:14:10 PM PDT 24
Peak memory 222740 kb
Host smart-d5e4e553-f278-42e6-90a1-1b9839d0e791
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978498189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.2978498189
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.343625339
Short name T412
Test name
Test status
Simulation time 3609552895 ps
CPU time 35.86 seconds
Started Mar 24 01:13:41 PM PDT 24
Finished Mar 24 01:14:17 PM PDT 24
Peak memory 216684 kb
Host smart-7a76c174-585b-4c1f-ae35-1216abb209c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343625339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.343625339
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.2488871468
Short name T637
Test name
Test status
Simulation time 15288065545 ps
CPU time 9.52 seconds
Started Mar 24 01:13:14 PM PDT 24
Finished Mar 24 01:13:24 PM PDT 24
Peak memory 216740 kb
Host smart-d707712a-b959-452a-8c8f-67cb4f20f37b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488871468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.2488871468
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.2905411284
Short name T498
Test name
Test status
Simulation time 121395858 ps
CPU time 1.29 seconds
Started Mar 24 01:13:37 PM PDT 24
Finished Mar 24 01:13:39 PM PDT 24
Peak memory 216704 kb
Host smart-c48b9a24-6f0e-4c15-bc29-f2603b8b906c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905411284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.2905411284
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.2214625726
Short name T302
Test name
Test status
Simulation time 317690074 ps
CPU time 0.99 seconds
Started Mar 24 01:13:13 PM PDT 24
Finished Mar 24 01:13:15 PM PDT 24
Peak memory 206040 kb
Host smart-a5bf617f-ea9e-4f0f-8d6b-5863c49bc2c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214625726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.2214625726
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.1788097314
Short name T536
Test name
Test status
Simulation time 129008793 ps
CPU time 2.94 seconds
Started Mar 24 01:13:22 PM PDT 24
Finished Mar 24 01:13:25 PM PDT 24
Peak memory 224844 kb
Host smart-348fb0ec-0183-4db7-ace1-b1263993125e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788097314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.1788097314
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.1006274554
Short name T306
Test name
Test status
Simulation time 50778174 ps
CPU time 0.77 seconds
Started Mar 24 01:13:44 PM PDT 24
Finished Mar 24 01:13:45 PM PDT 24
Peak memory 206092 kb
Host smart-c2b14070-e8ca-4a38-85c1-1b8ba1923bb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006274554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
1006274554
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.1994831921
Short name T188
Test name
Test status
Simulation time 193419341 ps
CPU time 2.93 seconds
Started Mar 24 01:13:43 PM PDT 24
Finished Mar 24 01:13:46 PM PDT 24
Peak memory 236416 kb
Host smart-c43e906a-d173-407a-aa8a-be08902663a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994831921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.1994831921
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.586957425
Short name T769
Test name
Test status
Simulation time 20079260 ps
CPU time 0.85 seconds
Started Mar 24 01:13:25 PM PDT 24
Finished Mar 24 01:13:26 PM PDT 24
Peak memory 206800 kb
Host smart-4ec3da74-b0b2-4cc3-935c-05fa90791e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586957425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.586957425
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.762280855
Short name T754
Test name
Test status
Simulation time 12385384131 ps
CPU time 92.07 seconds
Started Mar 24 01:13:41 PM PDT 24
Finished Mar 24 01:15:13 PM PDT 24
Peak memory 257640 kb
Host smart-7c010906-ef04-4b65-a366-594c3b529fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762280855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.762280855
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.1185149361
Short name T687
Test name
Test status
Simulation time 28317808354 ps
CPU time 84.83 seconds
Started Mar 24 01:13:39 PM PDT 24
Finished Mar 24 01:15:04 PM PDT 24
Peak memory 257112 kb
Host smart-53863878-0d77-4546-8dac-af1b9bc10887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185149361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.1185149361
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.3584640387
Short name T891
Test name
Test status
Simulation time 43892458215 ps
CPU time 143.36 seconds
Started Mar 24 01:13:28 PM PDT 24
Finished Mar 24 01:15:52 PM PDT 24
Peak memory 224972 kb
Host smart-e442c6ad-e89b-43b7-b153-7e344270c297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584640387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.3584640387
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.466234899
Short name T269
Test name
Test status
Simulation time 7175940916 ps
CPU time 33.22 seconds
Started Mar 24 01:13:28 PM PDT 24
Finished Mar 24 01:14:01 PM PDT 24
Peak memory 250060 kb
Host smart-09d32817-09e6-494d-9f90-05fdf3e8169e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466234899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.466234899
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.1594278612
Short name T12
Test name
Test status
Simulation time 2929629268 ps
CPU time 9.3 seconds
Started Mar 24 01:13:20 PM PDT 24
Finished Mar 24 01:13:30 PM PDT 24
Peak memory 233752 kb
Host smart-c9ce82d4-3262-4f63-bd3c-fd2b5dc04a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594278612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.1594278612
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.562798670
Short name T755
Test name
Test status
Simulation time 13328079912 ps
CPU time 15.87 seconds
Started Mar 24 01:13:23 PM PDT 24
Finished Mar 24 01:13:39 PM PDT 24
Peak memory 248476 kb
Host smart-bb799dd2-40a3-4e4c-bed4-009f80c62a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562798670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.562798670
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.1739480216
Short name T488
Test name
Test status
Simulation time 908420451 ps
CPU time 5.97 seconds
Started Mar 24 01:13:23 PM PDT 24
Finished Mar 24 01:13:29 PM PDT 24
Peak memory 220148 kb
Host smart-157feb52-4dcf-415c-b9e8-85d2d513147b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739480216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.1739480216
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.3183609644
Short name T61
Test name
Test status
Simulation time 4973242472 ps
CPU time 20.74 seconds
Started Mar 24 01:13:21 PM PDT 24
Finished Mar 24 01:13:42 PM PDT 24
Peak memory 240452 kb
Host smart-f7e0fcfb-e3af-4c6e-a0a6-a93f837ce8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183609644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.3183609644
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_ram_cfg.3517798633
Short name T896
Test name
Test status
Simulation time 74984570 ps
CPU time 0.76 seconds
Started Mar 24 01:13:32 PM PDT 24
Finished Mar 24 01:13:33 PM PDT 24
Peak memory 216496 kb
Host smart-0a37d705-00d1-4db7-859f-4d24b08cf012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517798633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_ram_cfg.3517798633
Directory /workspace/19.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.2909338028
Short name T618
Test name
Test status
Simulation time 4038015342 ps
CPU time 5.57 seconds
Started Mar 24 01:13:22 PM PDT 24
Finished Mar 24 01:13:28 PM PDT 24
Peak memory 218996 kb
Host smart-c9ce0e7c-9fe8-40a5-a843-8388ec9b9e8a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2909338028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.2909338028
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.175992362
Short name T969
Test name
Test status
Simulation time 907665588 ps
CPU time 8.36 seconds
Started Mar 24 01:13:22 PM PDT 24
Finished Mar 24 01:13:30 PM PDT 24
Peak memory 216880 kb
Host smart-5fb54b6c-1cdb-4b8b-b981-60246e4b7555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175992362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.175992362
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.1168355412
Short name T897
Test name
Test status
Simulation time 3436585369 ps
CPU time 6.81 seconds
Started Mar 24 01:13:22 PM PDT 24
Finished Mar 24 01:13:29 PM PDT 24
Peak memory 216720 kb
Host smart-934eef3c-5439-43e6-a9e8-df762ec95643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168355412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.1168355412
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.1358198231
Short name T650
Test name
Test status
Simulation time 208665986 ps
CPU time 0.81 seconds
Started Mar 24 01:13:38 PM PDT 24
Finished Mar 24 01:13:39 PM PDT 24
Peak memory 206112 kb
Host smart-e7a41e73-97f9-4465-b646-f1bbea20c380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358198231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.1358198231
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.3162936238
Short name T367
Test name
Test status
Simulation time 138308640 ps
CPU time 0.82 seconds
Started Mar 24 01:13:24 PM PDT 24
Finished Mar 24 01:13:25 PM PDT 24
Peak memory 206040 kb
Host smart-3f5c254a-d279-4838-b708-d338f9b83273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162936238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.3162936238
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.2798308575
Short name T608
Test name
Test status
Simulation time 10876963391 ps
CPU time 11.06 seconds
Started Mar 24 01:13:23 PM PDT 24
Finished Mar 24 01:13:34 PM PDT 24
Peak memory 238548 kb
Host smart-41d1738e-3f01-4475-b85b-2bc73c08ef53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798308575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.2798308575
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.3312163738
Short name T333
Test name
Test status
Simulation time 22516236 ps
CPU time 0.72 seconds
Started Mar 24 01:12:52 PM PDT 24
Finished Mar 24 01:12:53 PM PDT 24
Peak memory 205744 kb
Host smart-9ea24664-888d-4f05-a828-6e7adab51e00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312163738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.3
312163738
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.4067877035
Short name T343
Test name
Test status
Simulation time 259934864 ps
CPU time 4.06 seconds
Started Mar 24 01:12:52 PM PDT 24
Finished Mar 24 01:12:56 PM PDT 24
Peak memory 219864 kb
Host smart-39323263-85e1-4d2c-9db9-e504aa8db36b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067877035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.4067877035
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.101530437
Short name T473
Test name
Test status
Simulation time 19590235 ps
CPU time 0.77 seconds
Started Mar 24 01:12:33 PM PDT 24
Finished Mar 24 01:12:33 PM PDT 24
Peak memory 206812 kb
Host smart-c36f7e8e-de2e-4274-a1c1-ebaf2f1f9e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101530437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.101530437
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.2319163046
Short name T22
Test name
Test status
Simulation time 100695142068 ps
CPU time 366.04 seconds
Started Mar 24 01:12:39 PM PDT 24
Finished Mar 24 01:18:45 PM PDT 24
Peak memory 257772 kb
Host smart-400c6a3f-52c2-40ee-950d-af95b3fbe2ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319163046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.2319163046
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.1368613769
Short name T932
Test name
Test status
Simulation time 57957460218 ps
CPU time 117.99 seconds
Started Mar 24 01:12:46 PM PDT 24
Finished Mar 24 01:14:44 PM PDT 24
Peak memory 251484 kb
Host smart-10a40c53-beae-4ab4-bec6-0727bd3bd4f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368613769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.1368613769
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.2131431654
Short name T939
Test name
Test status
Simulation time 1666074373 ps
CPU time 12.62 seconds
Started Mar 24 01:12:41 PM PDT 24
Finished Mar 24 01:12:54 PM PDT 24
Peak memory 247752 kb
Host smart-582d44c3-028b-44d8-9148-c02730866984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131431654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.2131431654
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.456559592
Short name T832
Test name
Test status
Simulation time 576649642 ps
CPU time 5.98 seconds
Started Mar 24 01:12:45 PM PDT 24
Finished Mar 24 01:12:51 PM PDT 24
Peak memory 234656 kb
Host smart-6b419a14-bc7c-4a01-8951-0a064b5c2a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456559592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.456559592
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.465306644
Short name T46
Test name
Test status
Simulation time 451186790 ps
CPU time 5.43 seconds
Started Mar 24 01:12:41 PM PDT 24
Finished Mar 24 01:12:46 PM PDT 24
Peak memory 228952 kb
Host smart-6182de09-b50c-43ad-94e0-9e411ee20457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465306644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.465306644
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.2077936367
Short name T780
Test name
Test status
Simulation time 59761713597 ps
CPU time 40.41 seconds
Started Mar 24 01:12:48 PM PDT 24
Finished Mar 24 01:13:29 PM PDT 24
Peak memory 234052 kb
Host smart-4bd42de1-c36b-412c-a84a-8b6b902fa421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077936367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.2077936367
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.3173205663
Short name T454
Test name
Test status
Simulation time 39536306346 ps
CPU time 22.17 seconds
Started Mar 24 01:12:42 PM PDT 24
Finished Mar 24 01:13:04 PM PDT 24
Peak memory 227008 kb
Host smart-1940815b-9c56-4791-80fc-c0c5098cd939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173205663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.3173205663
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_ram_cfg.1552481160
Short name T423
Test name
Test status
Simulation time 17920516 ps
CPU time 0.76 seconds
Started Mar 24 01:12:52 PM PDT 24
Finished Mar 24 01:12:53 PM PDT 24
Peak memory 216540 kb
Host smart-b1bbff83-075e-4534-b76f-49d06f714bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552481160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_ram_cfg.1552481160
Directory /workspace/2.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.3727316433
Short name T299
Test name
Test status
Simulation time 121106370 ps
CPU time 3.83 seconds
Started Mar 24 01:12:45 PM PDT 24
Finished Mar 24 01:12:49 PM PDT 24
Peak memory 222880 kb
Host smart-36955ffb-8e8c-40af-b9fe-bcfad46556c8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3727316433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.3727316433
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.1306074371
Short name T854
Test name
Test status
Simulation time 88313679 ps
CPU time 0.94 seconds
Started Mar 24 01:12:41 PM PDT 24
Finished Mar 24 01:12:42 PM PDT 24
Peak memory 206836 kb
Host smart-8da41505-6991-47a8-8a0e-92c1f7c9ff14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306074371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.1306074371
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3445777898
Short name T588
Test name
Test status
Simulation time 5661555696 ps
CPU time 38.64 seconds
Started Mar 24 01:12:52 PM PDT 24
Finished Mar 24 01:13:30 PM PDT 24
Peak memory 216704 kb
Host smart-b1248d0f-400d-42d3-9ade-c5748d290fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445777898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3445777898
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.2521622214
Short name T439
Test name
Test status
Simulation time 46168118 ps
CPU time 2.18 seconds
Started Mar 24 01:12:47 PM PDT 24
Finished Mar 24 01:12:50 PM PDT 24
Peak memory 216620 kb
Host smart-ebcde9ef-07bd-49eb-8257-40606cc8b8a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521622214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.2521622214
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.2848107053
Short name T552
Test name
Test status
Simulation time 90691264 ps
CPU time 1.03 seconds
Started Mar 24 01:12:42 PM PDT 24
Finished Mar 24 01:12:43 PM PDT 24
Peak memory 206052 kb
Host smart-c4ec9920-7010-461d-8ba1-0597d3ae9e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848107053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.2848107053
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.910127807
Short name T400
Test name
Test status
Simulation time 759693843 ps
CPU time 2.51 seconds
Started Mar 24 01:12:49 PM PDT 24
Finished Mar 24 01:12:52 PM PDT 24
Peak memory 216640 kb
Host smart-93a7ec60-14d9-4904-95cb-18eeb2685499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910127807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.910127807
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.2471841463
Short name T491
Test name
Test status
Simulation time 12182165 ps
CPU time 0.74 seconds
Started Mar 24 01:13:27 PM PDT 24
Finished Mar 24 01:13:28 PM PDT 24
Peak memory 206108 kb
Host smart-d529be03-558e-404d-8ded-c25ec7bd7ba8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471841463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
2471841463
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.625084739
Short name T514
Test name
Test status
Simulation time 2121935437 ps
CPU time 6.11 seconds
Started Mar 24 01:13:43 PM PDT 24
Finished Mar 24 01:13:50 PM PDT 24
Peak memory 236088 kb
Host smart-3f0fb590-598c-41b0-b145-f6842cb7b7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625084739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.625084739
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.1064402016
Short name T373
Test name
Test status
Simulation time 36101285 ps
CPU time 0.76 seconds
Started Mar 24 01:13:25 PM PDT 24
Finished Mar 24 01:13:26 PM PDT 24
Peak memory 205768 kb
Host smart-16136187-aafb-42ba-961d-08dbf6aedb9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064402016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.1064402016
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.3933079565
Short name T177
Test name
Test status
Simulation time 1782071466 ps
CPU time 30.95 seconds
Started Mar 24 01:13:31 PM PDT 24
Finished Mar 24 01:14:03 PM PDT 24
Peak memory 253496 kb
Host smart-c2ab6423-3028-4c84-a667-529c665ba6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933079565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.3933079565
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.1905871203
Short name T428
Test name
Test status
Simulation time 5681169464 ps
CPU time 24.5 seconds
Started Mar 24 01:13:44 PM PDT 24
Finished Mar 24 01:14:08 PM PDT 24
Peak memory 241364 kb
Host smart-7214dfd7-3c7e-40bb-99ae-07c4e86dd821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905871203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.1905871203
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.2897486941
Short name T64
Test name
Test status
Simulation time 3215806060 ps
CPU time 25.71 seconds
Started Mar 24 01:13:41 PM PDT 24
Finished Mar 24 01:14:07 PM PDT 24
Peak memory 233096 kb
Host smart-6827aa26-107e-487a-81a4-c1f3988aaad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897486941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.2897486941
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.2780926180
Short name T184
Test name
Test status
Simulation time 8559003547 ps
CPU time 9.12 seconds
Started Mar 24 01:13:27 PM PDT 24
Finished Mar 24 01:13:36 PM PDT 24
Peak memory 234120 kb
Host smart-d29cf1a1-b7ae-462a-88d0-5a7f1a781fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780926180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.2780926180
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.2185269227
Short name T411
Test name
Test status
Simulation time 1993492132 ps
CPU time 8.06 seconds
Started Mar 24 01:13:27 PM PDT 24
Finished Mar 24 01:13:35 PM PDT 24
Peak memory 218936 kb
Host smart-8d96cbc1-7176-4fa2-b199-2d82d2ba37e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185269227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.2185269227
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.1795090918
Short name T311
Test name
Test status
Simulation time 2024577484 ps
CPU time 4.11 seconds
Started Mar 24 01:13:40 PM PDT 24
Finished Mar 24 01:13:44 PM PDT 24
Peak memory 233484 kb
Host smart-7b7a537d-4def-420f-aa24-4611e4909990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795090918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.1795090918
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.2230190933
Short name T6
Test name
Test status
Simulation time 279973806 ps
CPU time 2.72 seconds
Started Mar 24 01:13:44 PM PDT 24
Finished Mar 24 01:13:46 PM PDT 24
Peak memory 217316 kb
Host smart-c0213a7d-4ae1-4558-89f1-9756e5bde355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230190933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.2230190933
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.1311007658
Short name T543
Test name
Test status
Simulation time 693038384 ps
CPU time 3.93 seconds
Started Mar 24 01:13:48 PM PDT 24
Finished Mar 24 01:13:52 PM PDT 24
Peak memory 223148 kb
Host smart-5ffbed83-567b-43eb-8eef-6c5a3aab4abb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1311007658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.1311007658
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.732693979
Short name T399
Test name
Test status
Simulation time 62828954449 ps
CPU time 135.46 seconds
Started Mar 24 01:13:41 PM PDT 24
Finished Mar 24 01:15:57 PM PDT 24
Peak memory 237816 kb
Host smart-54420347-cd18-4f02-9a9d-e18614058830
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732693979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stres
s_all.732693979
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.1896631076
Short name T946
Test name
Test status
Simulation time 6914819753 ps
CPU time 11.53 seconds
Started Mar 24 01:13:28 PM PDT 24
Finished Mar 24 01:13:40 PM PDT 24
Peak memory 216780 kb
Host smart-34a97599-0b89-4373-80ef-74962899eecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896631076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.1896631076
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.1945684356
Short name T822
Test name
Test status
Simulation time 114938548040 ps
CPU time 22.4 seconds
Started Mar 24 01:13:21 PM PDT 24
Finished Mar 24 01:13:44 PM PDT 24
Peak memory 216704 kb
Host smart-f1fe1143-dc29-434d-bdca-539fe5bc9446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945684356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.1945684356
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.2297293568
Short name T414
Test name
Test status
Simulation time 1117800074 ps
CPU time 3.88 seconds
Started Mar 24 01:13:24 PM PDT 24
Finished Mar 24 01:13:28 PM PDT 24
Peak memory 216796 kb
Host smart-11b3933b-9f75-4d9c-984a-62f9d89a2aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297293568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.2297293568
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.2752999483
Short name T705
Test name
Test status
Simulation time 101943783 ps
CPU time 0.95 seconds
Started Mar 24 01:13:33 PM PDT 24
Finished Mar 24 01:13:34 PM PDT 24
Peak memory 206004 kb
Host smart-8da7199d-711a-4c1e-ba36-deb140b2f9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752999483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.2752999483
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.3483898984
Short name T933
Test name
Test status
Simulation time 16466760335 ps
CPU time 16.55 seconds
Started Mar 24 01:13:30 PM PDT 24
Finished Mar 24 01:13:47 PM PDT 24
Peak memory 219192 kb
Host smart-845fc942-536d-4cd5-9fd8-6a994c53e475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483898984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.3483898984
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.3309172178
Short name T743
Test name
Test status
Simulation time 23912280 ps
CPU time 0.74 seconds
Started Mar 24 01:13:40 PM PDT 24
Finished Mar 24 01:13:41 PM PDT 24
Peak memory 206076 kb
Host smart-5b22cd3a-59ed-4383-b348-5ef06bb68daa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309172178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
3309172178
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.1580986742
Short name T525
Test name
Test status
Simulation time 149093982 ps
CPU time 2.57 seconds
Started Mar 24 01:13:29 PM PDT 24
Finished Mar 24 01:13:32 PM PDT 24
Peak memory 225032 kb
Host smart-c6bce996-8755-472a-b61f-54b19c8c905f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580986742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.1580986742
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.392470638
Short name T874
Test name
Test status
Simulation time 12339595 ps
CPU time 0.75 seconds
Started Mar 24 01:13:42 PM PDT 24
Finished Mar 24 01:13:43 PM PDT 24
Peak memory 205760 kb
Host smart-5a48f676-7110-43dd-a1a2-87d27e22b400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392470638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.392470638
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.1888653998
Short name T479
Test name
Test status
Simulation time 41010288094 ps
CPU time 49.35 seconds
Started Mar 24 01:13:31 PM PDT 24
Finished Mar 24 01:14:21 PM PDT 24
Peak memory 237376 kb
Host smart-3e405396-5ee3-4aaa-80f2-b077bb5c115f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888653998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.1888653998
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.950870955
Short name T434
Test name
Test status
Simulation time 2744179758 ps
CPU time 12.75 seconds
Started Mar 24 01:13:30 PM PDT 24
Finished Mar 24 01:13:43 PM PDT 24
Peak memory 222640 kb
Host smart-4b649b57-dfe2-4e81-aabb-30d2d91be84b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950870955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.950870955
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.3004596789
Short name T470
Test name
Test status
Simulation time 14823899592 ps
CPU time 115.56 seconds
Started Mar 24 01:13:52 PM PDT 24
Finished Mar 24 01:15:48 PM PDT 24
Peak memory 250268 kb
Host smart-014afdbe-de89-4e7e-acd8-31e7f363ad52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004596789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.3004596789
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.2005159738
Short name T508
Test name
Test status
Simulation time 20778533227 ps
CPU time 32.45 seconds
Started Mar 24 01:13:27 PM PDT 24
Finished Mar 24 01:13:59 PM PDT 24
Peak memory 234128 kb
Host smart-831565c1-a616-41dc-ab31-f80c0354a772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005159738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.2005159738
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.1284377567
Short name T842
Test name
Test status
Simulation time 4245524978 ps
CPU time 9.67 seconds
Started Mar 24 01:13:38 PM PDT 24
Finished Mar 24 01:13:48 PM PDT 24
Peak memory 219020 kb
Host smart-ec79deb6-da01-4a48-ac81-1bc6ab2151ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284377567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.1284377567
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.2377503742
Short name T712
Test name
Test status
Simulation time 12106306445 ps
CPU time 22.16 seconds
Started Mar 24 01:13:29 PM PDT 24
Finished Mar 24 01:13:52 PM PDT 24
Peak memory 248872 kb
Host smart-1ed225f2-4f82-427f-84f7-42e35f7031f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377503742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.2377503742
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.4242008898
Short name T282
Test name
Test status
Simulation time 184921329 ps
CPU time 2.8 seconds
Started Mar 24 01:13:41 PM PDT 24
Finished Mar 24 01:13:43 PM PDT 24
Peak memory 233024 kb
Host smart-152d0ecd-c904-4b44-a896-d2bbd0159b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242008898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.4242008898
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.1556624765
Short name T482
Test name
Test status
Simulation time 2151120234 ps
CPU time 13.01 seconds
Started Mar 24 01:13:31 PM PDT 24
Finished Mar 24 01:13:44 PM PDT 24
Peak memory 234016 kb
Host smart-5f6d7796-4e34-437a-b60d-28afe023d32c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556624765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.1556624765
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.3731322164
Short name T829
Test name
Test status
Simulation time 2698496585 ps
CPU time 6.46 seconds
Started Mar 24 01:13:26 PM PDT 24
Finished Mar 24 01:13:33 PM PDT 24
Peak memory 219472 kb
Host smart-c9284ca5-6ce6-4db6-9b01-6ee47cf4d6be
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3731322164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.3731322164
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.492686121
Short name T881
Test name
Test status
Simulation time 460143591 ps
CPU time 1.15 seconds
Started Mar 24 01:13:32 PM PDT 24
Finished Mar 24 01:13:34 PM PDT 24
Peak memory 208128 kb
Host smart-029b94d7-2e34-4450-9784-5fcba8009107
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492686121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stres
s_all.492686121
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.2451011747
Short name T437
Test name
Test status
Simulation time 2266195021 ps
CPU time 14.27 seconds
Started Mar 24 01:13:29 PM PDT 24
Finished Mar 24 01:13:43 PM PDT 24
Peak memory 216640 kb
Host smart-70286142-b548-4341-bbe5-19cdd8c11e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451011747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.2451011747
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.73244318
Short name T17
Test name
Test status
Simulation time 6565957971 ps
CPU time 10.09 seconds
Started Mar 24 01:13:29 PM PDT 24
Finished Mar 24 01:13:39 PM PDT 24
Peak memory 216604 kb
Host smart-1b412436-4ee3-4bd3-a776-2feac63b9927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73244318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.73244318
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.2400273818
Short name T693
Test name
Test status
Simulation time 79515207 ps
CPU time 3.63 seconds
Started Mar 24 01:13:45 PM PDT 24
Finished Mar 24 01:13:49 PM PDT 24
Peak memory 216640 kb
Host smart-0278ace3-3ced-418a-9e29-60de33095398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400273818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.2400273818
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.3218261168
Short name T901
Test name
Test status
Simulation time 191399666 ps
CPU time 1 seconds
Started Mar 24 01:13:45 PM PDT 24
Finished Mar 24 01:13:46 PM PDT 24
Peak memory 207108 kb
Host smart-801babb6-8e0b-4f80-9286-322372745cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218261168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.3218261168
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.190927653
Short name T814
Test name
Test status
Simulation time 51448844995 ps
CPU time 36.79 seconds
Started Mar 24 01:13:27 PM PDT 24
Finished Mar 24 01:14:04 PM PDT 24
Peak memory 224068 kb
Host smart-381aea06-83c4-4477-b595-f5d7b3ec2acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190927653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.190927653
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.227232785
Short name T607
Test name
Test status
Simulation time 164135433 ps
CPU time 0.74 seconds
Started Mar 24 01:13:49 PM PDT 24
Finished Mar 24 01:13:49 PM PDT 24
Peak memory 205724 kb
Host smart-b1cb4f81-ec48-493c-b956-c8b57d1f2051
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227232785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.227232785
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.2505289617
Short name T683
Test name
Test status
Simulation time 1310032005 ps
CPU time 5.61 seconds
Started Mar 24 01:13:28 PM PDT 24
Finished Mar 24 01:13:34 PM PDT 24
Peak memory 220184 kb
Host smart-50d34268-f810-408c-b0ab-1b6c9e9853e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505289617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.2505289617
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.3818216562
Short name T974
Test name
Test status
Simulation time 19623557 ps
CPU time 0.81 seconds
Started Mar 24 01:13:28 PM PDT 24
Finished Mar 24 01:13:30 PM PDT 24
Peak memory 207144 kb
Host smart-4d282aff-679c-45c8-b013-2dd6c127f62a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818216562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.3818216562
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.3117637205
Short name T156
Test name
Test status
Simulation time 178939523863 ps
CPU time 253.91 seconds
Started Mar 24 01:13:30 PM PDT 24
Finished Mar 24 01:17:44 PM PDT 24
Peak memory 265816 kb
Host smart-d6487de0-d286-4e12-9e64-9ce9bce8d251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117637205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.3117637205
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.2589972848
Short name T137
Test name
Test status
Simulation time 34898218626 ps
CPU time 113.49 seconds
Started Mar 24 01:13:26 PM PDT 24
Finished Mar 24 01:15:20 PM PDT 24
Peak memory 255800 kb
Host smart-048b202f-db61-4483-a83f-cac94de784b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589972848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.2589972848
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.1031189054
Short name T359
Test name
Test status
Simulation time 35189915917 ps
CPU time 30.41 seconds
Started Mar 24 01:13:30 PM PDT 24
Finished Mar 24 01:14:01 PM PDT 24
Peak memory 239400 kb
Host smart-42121a00-a27c-417b-b2e2-e70605b79211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031189054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.1031189054
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.2850142997
Short name T393
Test name
Test status
Simulation time 207171819 ps
CPU time 7.58 seconds
Started Mar 24 01:13:40 PM PDT 24
Finished Mar 24 01:13:48 PM PDT 24
Peak memory 234640 kb
Host smart-8d3df30c-9b42-4734-a975-e586f2b86404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850142997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.2850142997
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.1044728103
Short name T803
Test name
Test status
Simulation time 1318929343 ps
CPU time 6.48 seconds
Started Mar 24 01:13:44 PM PDT 24
Finished Mar 24 01:13:50 PM PDT 24
Peak memory 233580 kb
Host smart-18ee6b40-1b30-4f4e-ba29-b5a1e67978ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044728103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.1044728103
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.1985264768
Short name T531
Test name
Test status
Simulation time 632938535 ps
CPU time 4.71 seconds
Started Mar 24 01:13:47 PM PDT 24
Finished Mar 24 01:13:52 PM PDT 24
Peak memory 218748 kb
Host smart-d612d97d-7ba3-4355-be21-08e2d0b174b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985264768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.1985264768
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.1324126607
Short name T395
Test name
Test status
Simulation time 14106992190 ps
CPU time 24.88 seconds
Started Mar 24 01:13:30 PM PDT 24
Finished Mar 24 01:13:55 PM PDT 24
Peak memory 248920 kb
Host smart-ef2de790-a864-42cb-8a86-e49e4da644a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324126607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.1324126607
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.1147036711
Short name T11
Test name
Test status
Simulation time 1063874432 ps
CPU time 3.84 seconds
Started Mar 24 01:13:45 PM PDT 24
Finished Mar 24 01:13:49 PM PDT 24
Peak memory 220780 kb
Host smart-1fa82546-52d6-4ccb-b6ba-ee81628a069d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1147036711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.1147036711
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.1520496164
Short name T286
Test name
Test status
Simulation time 35182890 ps
CPU time 0.91 seconds
Started Mar 24 01:13:29 PM PDT 24
Finished Mar 24 01:13:31 PM PDT 24
Peak memory 206824 kb
Host smart-f77dbb55-537b-494a-9b46-d7d6c5efc75a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520496164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.1520496164
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.2294675848
Short name T968
Test name
Test status
Simulation time 2320635479 ps
CPU time 14.47 seconds
Started Mar 24 01:13:27 PM PDT 24
Finished Mar 24 01:13:42 PM PDT 24
Peak memory 216636 kb
Host smart-ec28c419-9db4-461f-b965-0d668b49032e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294675848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.2294675848
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.804488495
Short name T1
Test name
Test status
Simulation time 5850379525 ps
CPU time 20.65 seconds
Started Mar 24 01:13:26 PM PDT 24
Finished Mar 24 01:13:47 PM PDT 24
Peak memory 216728 kb
Host smart-e12a88d5-16be-4031-88aa-1e891f860ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804488495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.804488495
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.3229818938
Short name T380
Test name
Test status
Simulation time 26465869 ps
CPU time 0.97 seconds
Started Mar 24 01:13:30 PM PDT 24
Finished Mar 24 01:13:32 PM PDT 24
Peak memory 207252 kb
Host smart-d215db65-314f-4719-aafc-d9faf470cbff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229818938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.3229818938
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.3184524486
Short name T77
Test name
Test status
Simulation time 56816600 ps
CPU time 0.94 seconds
Started Mar 24 01:13:33 PM PDT 24
Finished Mar 24 01:13:35 PM PDT 24
Peak memory 207084 kb
Host smart-4a795302-e60e-4f9c-947e-4c873852836a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184524486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.3184524486
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.1824220349
Short name T469
Test name
Test status
Simulation time 7192077337 ps
CPU time 13.93 seconds
Started Mar 24 01:13:28 PM PDT 24
Finished Mar 24 01:13:42 PM PDT 24
Peak memory 236176 kb
Host smart-c7a8ebc5-91e0-434e-92a5-2c6fc1ea0119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824220349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.1824220349
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.4104747663
Short name T748
Test name
Test status
Simulation time 639109810 ps
CPU time 4.09 seconds
Started Mar 24 01:13:33 PM PDT 24
Finished Mar 24 01:13:37 PM PDT 24
Peak memory 234424 kb
Host smart-d6b007e6-5abb-48d7-b2b6-cd6bbc960cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104747663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.4104747663
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.868491293
Short name T289
Test name
Test status
Simulation time 18411306 ps
CPU time 0.76 seconds
Started Mar 24 01:13:42 PM PDT 24
Finished Mar 24 01:13:43 PM PDT 24
Peak memory 205776 kb
Host smart-a0cfb90f-1f06-4aaf-b689-dd75440e8d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868491293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.868491293
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.345882752
Short name T624
Test name
Test status
Simulation time 18355013738 ps
CPU time 44.99 seconds
Started Mar 24 01:13:48 PM PDT 24
Finished Mar 24 01:14:33 PM PDT 24
Peak memory 233300 kb
Host smart-d9a56952-42f2-4b70-8d85-cbdb60b0e6aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345882752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.345882752
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.1561306900
Short name T882
Test name
Test status
Simulation time 31378671137 ps
CPU time 194.25 seconds
Started Mar 24 01:13:34 PM PDT 24
Finished Mar 24 01:16:50 PM PDT 24
Peak memory 251620 kb
Host smart-3122266b-2b38-4684-9fb4-16fbb69e7af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561306900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.1561306900
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.1202199238
Short name T119
Test name
Test status
Simulation time 3236169530 ps
CPU time 10.57 seconds
Started Mar 24 01:13:41 PM PDT 24
Finished Mar 24 01:13:52 PM PDT 24
Peak memory 250568 kb
Host smart-6229f269-44ba-4002-841e-0700be8a0974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202199238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.1202199238
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.4156426773
Short name T959
Test name
Test status
Simulation time 1309124871 ps
CPU time 4.56 seconds
Started Mar 24 01:13:30 PM PDT 24
Finished Mar 24 01:13:35 PM PDT 24
Peak memory 233704 kb
Host smart-b4a5754a-d2dc-42de-9102-8b533068d7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156426773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.4156426773
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.2884468202
Short name T166
Test name
Test status
Simulation time 421752418 ps
CPU time 3.41 seconds
Started Mar 24 01:13:28 PM PDT 24
Finished Mar 24 01:13:32 PM PDT 24
Peak memory 216940 kb
Host smart-025a1ca5-afe6-452d-a217-aaa50bca5931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884468202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.2884468202
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.3713295933
Short name T638
Test name
Test status
Simulation time 695315812 ps
CPU time 4.86 seconds
Started Mar 24 01:13:46 PM PDT 24
Finished Mar 24 01:13:51 PM PDT 24
Peak memory 233848 kb
Host smart-fde5b23d-0334-421b-b341-b2bcbb36f3a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713295933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.3713295933
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.2359002390
Short name T504
Test name
Test status
Simulation time 3003107423 ps
CPU time 4.31 seconds
Started Mar 24 01:13:38 PM PDT 24
Finished Mar 24 01:13:42 PM PDT 24
Peak memory 218804 kb
Host smart-9d7d06e3-7443-4ab1-a680-9fde81c5f3ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359002390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.2359002390
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.405919764
Short name T418
Test name
Test status
Simulation time 976974243 ps
CPU time 5.52 seconds
Started Mar 24 01:13:41 PM PDT 24
Finished Mar 24 01:13:47 PM PDT 24
Peak memory 223156 kb
Host smart-b7c38c4c-8a8c-4664-96fa-5ba1d3afcc21
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=405919764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dire
ct.405919764
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.1793396078
Short name T248
Test name
Test status
Simulation time 23697689863 ps
CPU time 39.76 seconds
Started Mar 24 01:13:45 PM PDT 24
Finished Mar 24 01:14:25 PM PDT 24
Peak memory 216688 kb
Host smart-e178d1fc-58d1-4eb0-b63c-18012bd60df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793396078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.1793396078
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.79074164
Short name T575
Test name
Test status
Simulation time 3121489404 ps
CPU time 6.55 seconds
Started Mar 24 01:13:26 PM PDT 24
Finished Mar 24 01:13:33 PM PDT 24
Peak memory 216712 kb
Host smart-5d16bc3f-62f6-4951-be0f-a46caac4711e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79074164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.79074164
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.3662771288
Short name T453
Test name
Test status
Simulation time 406073855 ps
CPU time 3.23 seconds
Started Mar 24 01:13:37 PM PDT 24
Finished Mar 24 01:13:41 PM PDT 24
Peak memory 216656 kb
Host smart-1507ca36-6132-441a-b070-ff271839530c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662771288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.3662771288
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.645979643
Short name T258
Test name
Test status
Simulation time 79507639 ps
CPU time 1.01 seconds
Started Mar 24 01:13:30 PM PDT 24
Finished Mar 24 01:13:31 PM PDT 24
Peak memory 207104 kb
Host smart-184bb6b0-ba29-4c93-a5a3-1574a2fe4188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645979643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.645979643
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.893761406
Short name T374
Test name
Test status
Simulation time 3572669266 ps
CPU time 16.31 seconds
Started Mar 24 01:13:32 PM PDT 24
Finished Mar 24 01:13:49 PM PDT 24
Peak memory 235292 kb
Host smart-762080b0-1c72-49ee-849d-9d0c42b5cd12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893761406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.893761406
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.739239603
Short name T724
Test name
Test status
Simulation time 14364908 ps
CPU time 0.75 seconds
Started Mar 24 01:13:42 PM PDT 24
Finished Mar 24 01:13:43 PM PDT 24
Peak memory 205956 kb
Host smart-64b263a1-cb84-4176-af26-f848a0f22ed9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739239603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.739239603
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.2366573078
Short name T696
Test name
Test status
Simulation time 1099191000 ps
CPU time 3.96 seconds
Started Mar 24 01:13:41 PM PDT 24
Finished Mar 24 01:13:45 PM PDT 24
Peak memory 235684 kb
Host smart-4289f5c5-fdbf-474f-ad3a-c7fe4d4e1296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366573078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.2366573078
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.1686504057
Short name T903
Test name
Test status
Simulation time 127439247 ps
CPU time 0.79 seconds
Started Mar 24 01:13:44 PM PDT 24
Finished Mar 24 01:13:44 PM PDT 24
Peak memory 206864 kb
Host smart-c29b1243-0048-4525-ae50-8ca44c428499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686504057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1686504057
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.3719922745
Short name T868
Test name
Test status
Simulation time 3101083830 ps
CPU time 46.95 seconds
Started Mar 24 01:13:44 PM PDT 24
Finished Mar 24 01:14:31 PM PDT 24
Peak memory 264136 kb
Host smart-de3b602f-20a6-4efc-a3e8-6c8482718e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719922745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.3719922745
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.3236796517
Short name T931
Test name
Test status
Simulation time 1507160406 ps
CPU time 19.6 seconds
Started Mar 24 01:13:38 PM PDT 24
Finished Mar 24 01:13:58 PM PDT 24
Peak memory 238996 kb
Host smart-5cb29877-67ce-4659-a8ed-927cadb21fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236796517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.3236796517
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.2945585149
Short name T224
Test name
Test status
Simulation time 32880673122 ps
CPU time 157.23 seconds
Started Mar 24 01:13:38 PM PDT 24
Finished Mar 24 01:16:15 PM PDT 24
Peak memory 249544 kb
Host smart-e8efda58-498b-4128-9f54-dfb34dd2ee7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945585149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.2945585149
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.1783749773
Short name T419
Test name
Test status
Simulation time 12888662871 ps
CPU time 22.76 seconds
Started Mar 24 01:13:41 PM PDT 24
Finished Mar 24 01:14:04 PM PDT 24
Peak memory 241032 kb
Host smart-d2aa3b7a-222c-48b6-9172-8236339c97dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783749773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.1783749773
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.601796659
Short name T190
Test name
Test status
Simulation time 125927606 ps
CPU time 2.73 seconds
Started Mar 24 01:13:41 PM PDT 24
Finished Mar 24 01:13:44 PM PDT 24
Peak memory 234036 kb
Host smart-504b5a39-d07f-43fa-aeac-9f7154d69859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601796659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.601796659
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.1549716373
Short name T199
Test name
Test status
Simulation time 1180808050 ps
CPU time 12.45 seconds
Started Mar 24 01:13:38 PM PDT 24
Finished Mar 24 01:13:51 PM PDT 24
Peak memory 241128 kb
Host smart-8431027a-c261-4211-a48e-f845ea540287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549716373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.1549716373
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.3205139061
Short name T835
Test name
Test status
Simulation time 1246586173 ps
CPU time 11.9 seconds
Started Mar 24 01:13:32 PM PDT 24
Finished Mar 24 01:13:44 PM PDT 24
Peak memory 239448 kb
Host smart-de6d208e-049c-444b-b701-7bcc639d0f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205139061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.3205139061
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.3366389481
Short name T721
Test name
Test status
Simulation time 131394117920 ps
CPU time 31.85 seconds
Started Mar 24 01:13:33 PM PDT 24
Finished Mar 24 01:14:05 PM PDT 24
Peak memory 227644 kb
Host smart-3ab198aa-08c3-4efb-9884-27725222ab65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366389481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.3366389481
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.469823
Short name T830
Test name
Test status
Simulation time 2982124584 ps
CPU time 6.77 seconds
Started Mar 24 01:13:48 PM PDT 24
Finished Mar 24 01:13:55 PM PDT 24
Peak memory 219680 kb
Host smart-25b40867-76bc-47ae-9f9f-9398f05b3206
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=469823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_direct.469823
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.1148874730
Short name T44
Test name
Test status
Simulation time 70329993 ps
CPU time 1.02 seconds
Started Mar 24 01:13:47 PM PDT 24
Finished Mar 24 01:13:48 PM PDT 24
Peak memory 206748 kb
Host smart-f15e089f-e836-453b-a534-45a635367259
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148874730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.1148874730
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.224268082
Short name T867
Test name
Test status
Simulation time 8430488489 ps
CPU time 12.11 seconds
Started Mar 24 01:13:49 PM PDT 24
Finished Mar 24 01:14:01 PM PDT 24
Peak memory 216736 kb
Host smart-633eac6f-7ad8-4625-8317-03b60b000e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224268082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.224268082
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.2712009202
Short name T546
Test name
Test status
Simulation time 3261854096 ps
CPU time 6.2 seconds
Started Mar 24 01:13:45 PM PDT 24
Finished Mar 24 01:13:51 PM PDT 24
Peak memory 216728 kb
Host smart-838a0d5a-afae-4b0a-b4ce-47bd8a5fed87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712009202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.2712009202
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.3247749287
Short name T475
Test name
Test status
Simulation time 223810053 ps
CPU time 3.25 seconds
Started Mar 24 01:13:48 PM PDT 24
Finished Mar 24 01:13:51 PM PDT 24
Peak memory 216620 kb
Host smart-1dee7b16-5444-4cda-a44e-68c762dcedc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247749287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.3247749287
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.1398000229
Short name T747
Test name
Test status
Simulation time 638049562 ps
CPU time 1.04 seconds
Started Mar 24 01:13:43 PM PDT 24
Finished Mar 24 01:13:44 PM PDT 24
Peak memory 207012 kb
Host smart-843bd467-ebf4-4464-843c-bc8c3acafdfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398000229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.1398000229
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.41858297
Short name T572
Test name
Test status
Simulation time 8766629966 ps
CPU time 11.52 seconds
Started Mar 24 01:13:35 PM PDT 24
Finished Mar 24 01:13:48 PM PDT 24
Peak memory 240096 kb
Host smart-50b9849c-9580-444d-a4cc-b0444cb895aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41858297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.41858297
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.1505121210
Short name T823
Test name
Test status
Simulation time 12370297 ps
CPU time 0.74 seconds
Started Mar 24 01:13:40 PM PDT 24
Finished Mar 24 01:13:41 PM PDT 24
Peak memory 206064 kb
Host smart-b2f1955a-3423-4097-b028-c09273c2e7e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505121210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
1505121210
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.770976596
Short name T672
Test name
Test status
Simulation time 273221244 ps
CPU time 3.94 seconds
Started Mar 24 01:13:48 PM PDT 24
Finished Mar 24 01:13:52 PM PDT 24
Peak memory 219092 kb
Host smart-77d4d886-1073-4be6-9654-af91d1563e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770976596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.770976596
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.769256731
Short name T481
Test name
Test status
Simulation time 14328574 ps
CPU time 0.76 seconds
Started Mar 24 01:13:33 PM PDT 24
Finished Mar 24 01:13:36 PM PDT 24
Peak memory 207172 kb
Host smart-69aeedde-a4f3-4cf0-b8d4-356cc76bf4cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769256731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.769256731
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.1880354990
Short name T936
Test name
Test status
Simulation time 21453789105 ps
CPU time 74.39 seconds
Started Mar 24 01:13:54 PM PDT 24
Finished Mar 24 01:15:09 PM PDT 24
Peak memory 257384 kb
Host smart-4167be6e-4272-4ee3-badd-6db3f92a0fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880354990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.1880354990
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.883180138
Short name T731
Test name
Test status
Simulation time 46036262314 ps
CPU time 313.84 seconds
Started Mar 24 01:13:54 PM PDT 24
Finished Mar 24 01:19:08 PM PDT 24
Peak memory 256652 kb
Host smart-f0bda531-e52e-4bb1-a52f-9114d538f7c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883180138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.883180138
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.3425707334
Short name T467
Test name
Test status
Simulation time 24729607209 ps
CPU time 122.36 seconds
Started Mar 24 01:13:38 PM PDT 24
Finished Mar 24 01:15:41 PM PDT 24
Peak memory 256476 kb
Host smart-cb9b60a2-7599-42b1-beda-da11c8d0ec93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425707334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.3425707334
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.1148886338
Short name T676
Test name
Test status
Simulation time 14556415658 ps
CPU time 21.96 seconds
Started Mar 24 01:13:43 PM PDT 24
Finished Mar 24 01:14:05 PM PDT 24
Peak memory 249972 kb
Host smart-b6cf482d-1d1d-4524-b74b-fba3bf07beb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148886338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.1148886338
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.770020359
Short name T788
Test name
Test status
Simulation time 9220569647 ps
CPU time 8.41 seconds
Started Mar 24 01:13:40 PM PDT 24
Finished Mar 24 01:13:48 PM PDT 24
Peak memory 218848 kb
Host smart-d849b246-b3e9-4569-81f2-e412e2ccefcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770020359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.770020359
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.3936121408
Short name T798
Test name
Test status
Simulation time 4163614435 ps
CPU time 20.82 seconds
Started Mar 24 01:13:38 PM PDT 24
Finished Mar 24 01:13:59 PM PDT 24
Peak memory 248960 kb
Host smart-3e4986c9-0fdb-4364-89ec-9c8c1628443e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936121408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.3936121408
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.898978187
Short name T203
Test name
Test status
Simulation time 159694002 ps
CPU time 3.3 seconds
Started Mar 24 01:13:41 PM PDT 24
Finished Mar 24 01:13:44 PM PDT 24
Peak memory 217092 kb
Host smart-b7d525da-7a6d-41db-9b0a-b269bf7de172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898978187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap
.898978187
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.2248111372
Short name T323
Test name
Test status
Simulation time 914339550 ps
CPU time 3.65 seconds
Started Mar 24 01:13:41 PM PDT 24
Finished Mar 24 01:13:45 PM PDT 24
Peak memory 233888 kb
Host smart-163fdbcd-e48d-45c5-a513-592c6365651f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248111372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.2248111372
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.2961518360
Short name T785
Test name
Test status
Simulation time 870439604 ps
CPU time 4.41 seconds
Started Mar 24 01:13:37 PM PDT 24
Finished Mar 24 01:13:42 PM PDT 24
Peak memory 222088 kb
Host smart-22185632-1d0b-4b5c-b23a-2b266f074210
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2961518360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.2961518360
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.3647737450
Short name T371
Test name
Test status
Simulation time 9678754906 ps
CPU time 84.64 seconds
Started Mar 24 01:13:53 PM PDT 24
Finished Mar 24 01:15:17 PM PDT 24
Peak memory 250608 kb
Host smart-37f20dae-a38c-4410-b77a-c2fc0b017fde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647737450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.3647737450
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.2107099686
Short name T953
Test name
Test status
Simulation time 4469061485 ps
CPU time 23.93 seconds
Started Mar 24 01:13:42 PM PDT 24
Finished Mar 24 01:14:07 PM PDT 24
Peak memory 216748 kb
Host smart-7777475e-2ddd-48e0-9f54-1ec083d25a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107099686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.2107099686
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.3952041551
Short name T722
Test name
Test status
Simulation time 618368577 ps
CPU time 2.02 seconds
Started Mar 24 01:13:34 PM PDT 24
Finished Mar 24 01:13:38 PM PDT 24
Peak memory 208224 kb
Host smart-ba55ecf7-0947-4d80-b59d-3c28aecd335a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952041551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.3952041551
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.508347937
Short name T23
Test name
Test status
Simulation time 88401397 ps
CPU time 0.99 seconds
Started Mar 24 01:13:45 PM PDT 24
Finished Mar 24 01:13:46 PM PDT 24
Peak memory 207496 kb
Host smart-a2a304a1-b9ef-4baa-b90d-49c2133c6432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508347937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.508347937
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.1430589552
Short name T493
Test name
Test status
Simulation time 107306930 ps
CPU time 0.83 seconds
Started Mar 24 01:13:34 PM PDT 24
Finished Mar 24 01:13:36 PM PDT 24
Peak memory 206048 kb
Host smart-3cc34c52-a861-4b8d-a6b3-ded359f6cb9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430589552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.1430589552
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.4156145303
Short name T443
Test name
Test status
Simulation time 10258672203 ps
CPU time 35.01 seconds
Started Mar 24 01:13:33 PM PDT 24
Finished Mar 24 01:14:08 PM PDT 24
Peak memory 228256 kb
Host smart-0016097a-9a73-42ab-b095-6a2ad38c0e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156145303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.4156145303
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.2189805881
Short name T652
Test name
Test status
Simulation time 38026301 ps
CPU time 0.71 seconds
Started Mar 24 01:13:42 PM PDT 24
Finished Mar 24 01:13:43 PM PDT 24
Peak memory 206072 kb
Host smart-144a827f-bd0c-46c2-a08f-798596607b9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189805881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
2189805881
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.3230980242
Short name T195
Test name
Test status
Simulation time 315572598 ps
CPU time 4.8 seconds
Started Mar 24 01:13:52 PM PDT 24
Finished Mar 24 01:13:57 PM PDT 24
Peak memory 234752 kb
Host smart-3758e532-3687-4571-bdc5-9c346680dc51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230980242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.3230980242
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.2646051393
Short name T655
Test name
Test status
Simulation time 16252161 ps
CPU time 0.78 seconds
Started Mar 24 01:13:43 PM PDT 24
Finished Mar 24 01:13:44 PM PDT 24
Peak memory 207140 kb
Host smart-a48048d8-3f27-42f3-a7ed-61cbb708eca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646051393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.2646051393
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.78545809
Short name T647
Test name
Test status
Simulation time 5141464969 ps
CPU time 42.81 seconds
Started Mar 24 01:13:37 PM PDT 24
Finished Mar 24 01:14:20 PM PDT 24
Peak memory 249864 kb
Host smart-59d7a96f-83f6-4295-ab18-3b82f06e4a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78545809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.78545809
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.737628026
Short name T241
Test name
Test status
Simulation time 57025127604 ps
CPU time 341.36 seconds
Started Mar 24 01:13:51 PM PDT 24
Finished Mar 24 01:19:32 PM PDT 24
Peak memory 254212 kb
Host smart-1f6ddfcb-56fd-4820-a73a-0a9b6035eca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737628026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.737628026
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.2051998954
Short name T160
Test name
Test status
Simulation time 281679975903 ps
CPU time 457.58 seconds
Started Mar 24 01:13:56 PM PDT 24
Finished Mar 24 01:21:34 PM PDT 24
Peak memory 266124 kb
Host smart-289ca2b6-656d-4070-bf84-7ca2fc42db75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051998954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.2051998954
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.174129339
Short name T486
Test name
Test status
Simulation time 3441588806 ps
CPU time 26.11 seconds
Started Mar 24 01:13:38 PM PDT 24
Finished Mar 24 01:14:04 PM PDT 24
Peak memory 229288 kb
Host smart-bca97a0d-eadd-4bb5-bd0f-1ad8bdf65c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174129339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.174129339
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.2386743682
Short name T162
Test name
Test status
Simulation time 1576479627 ps
CPU time 7.46 seconds
Started Mar 24 01:13:41 PM PDT 24
Finished Mar 24 01:13:49 PM PDT 24
Peak memory 238144 kb
Host smart-ed1ab6c0-4ead-4537-950d-72c46fb87603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386743682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.2386743682
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.1933947797
Short name T208
Test name
Test status
Simulation time 1103246335 ps
CPU time 4.2 seconds
Started Mar 24 01:13:48 PM PDT 24
Finished Mar 24 01:13:52 PM PDT 24
Peak memory 218800 kb
Host smart-a9208f36-412b-406a-99ed-c7949330aff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933947797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.1933947797
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.3745275305
Short name T228
Test name
Test status
Simulation time 5282248253 ps
CPU time 16.08 seconds
Started Mar 24 01:13:42 PM PDT 24
Finished Mar 24 01:13:58 PM PDT 24
Peak memory 234020 kb
Host smart-7ff4939a-4fc8-4b4e-83fb-9ace19abc0c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745275305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.3745275305
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.624474766
Short name T802
Test name
Test status
Simulation time 6955523792 ps
CPU time 10.48 seconds
Started Mar 24 01:13:50 PM PDT 24
Finished Mar 24 01:14:01 PM PDT 24
Peak memory 219104 kb
Host smart-e66a4a18-314a-4549-aa43-fad6e1bd68b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624474766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.624474766
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.1822356218
Short name T117
Test name
Test status
Simulation time 71826907 ps
CPU time 3.8 seconds
Started Mar 24 01:13:47 PM PDT 24
Finished Mar 24 01:13:51 PM PDT 24
Peak memory 222632 kb
Host smart-9dfa2292-1169-4465-a21c-d29bb0192ac0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1822356218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.1822356218
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.804853348
Short name T171
Test name
Test status
Simulation time 125082911607 ps
CPU time 127.21 seconds
Started Mar 24 01:13:45 PM PDT 24
Finished Mar 24 01:15:52 PM PDT 24
Peak memory 251676 kb
Host smart-fafa3dc1-a770-4d20-9ca5-a05825c7ea51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804853348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stres
s_all.804853348
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.3835354635
Short name T940
Test name
Test status
Simulation time 7808124996 ps
CPU time 12.61 seconds
Started Mar 24 01:13:47 PM PDT 24
Finished Mar 24 01:13:59 PM PDT 24
Peak memory 216776 kb
Host smart-31927194-7d23-4658-b5b3-b19e52c1e245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835354635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.3835354635
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.254814508
Short name T340
Test name
Test status
Simulation time 1426494113 ps
CPU time 7.89 seconds
Started Mar 24 01:13:56 PM PDT 24
Finished Mar 24 01:14:04 PM PDT 24
Peak memory 216616 kb
Host smart-c5b341a5-5d1a-4d56-848c-f7867b1b85cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254814508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.254814508
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.526492427
Short name T528
Test name
Test status
Simulation time 205107619 ps
CPU time 2.5 seconds
Started Mar 24 01:13:56 PM PDT 24
Finished Mar 24 01:13:59 PM PDT 24
Peak memory 216676 kb
Host smart-9ba1f7b5-9c1d-4afa-9b7f-5c0644c6a8c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526492427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.526492427
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.334795554
Short name T385
Test name
Test status
Simulation time 36241965 ps
CPU time 0.92 seconds
Started Mar 24 01:13:43 PM PDT 24
Finished Mar 24 01:13:44 PM PDT 24
Peak memory 207084 kb
Host smart-16b152b6-3674-41c5-9437-63307d1c25de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334795554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.334795554
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.4214897906
Short name T406
Test name
Test status
Simulation time 2627739308 ps
CPU time 6.82 seconds
Started Mar 24 01:13:42 PM PDT 24
Finished Mar 24 01:13:49 PM PDT 24
Peak memory 219260 kb
Host smart-6a357a9c-e2c8-4597-9341-c43c25be74a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214897906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.4214897906
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.647582783
Short name T587
Test name
Test status
Simulation time 32826027 ps
CPU time 0.78 seconds
Started Mar 24 01:13:43 PM PDT 24
Finished Mar 24 01:13:44 PM PDT 24
Peak memory 206020 kb
Host smart-ffde151b-294d-4ff2-b5a9-1f370c83705e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647582783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.647582783
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.1188164821
Short name T267
Test name
Test status
Simulation time 280707311 ps
CPU time 5.32 seconds
Started Mar 24 01:13:42 PM PDT 24
Finished Mar 24 01:13:47 PM PDT 24
Peak memory 234976 kb
Host smart-b53827c4-6b41-4c4f-ad3c-bbd422d7a4ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188164821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.1188164821
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.1582479525
Short name T812
Test name
Test status
Simulation time 51759028 ps
CPU time 0.76 seconds
Started Mar 24 01:13:50 PM PDT 24
Finished Mar 24 01:13:51 PM PDT 24
Peak memory 206108 kb
Host smart-af93f1cd-aacb-41e5-8a7c-20f9b4dd0997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582479525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.1582479525
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.2490458199
Short name T686
Test name
Test status
Simulation time 33814863633 ps
CPU time 175.51 seconds
Started Mar 24 01:13:51 PM PDT 24
Finished Mar 24 01:16:46 PM PDT 24
Peak memory 257124 kb
Host smart-ab1e1995-2f00-4419-bed3-f08015d86710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490458199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.2490458199
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.2642553961
Short name T701
Test name
Test status
Simulation time 8615872785 ps
CPU time 66.31 seconds
Started Mar 24 01:13:56 PM PDT 24
Finished Mar 24 01:15:03 PM PDT 24
Peak memory 254904 kb
Host smart-ae2d849c-28c3-47d7-af3d-cdd8c657c921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642553961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.2642553961
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.202189250
Short name T155
Test name
Test status
Simulation time 15384935226 ps
CPU time 114.98 seconds
Started Mar 24 01:13:38 PM PDT 24
Finished Mar 24 01:15:34 PM PDT 24
Peak memory 237960 kb
Host smart-c06644e9-a031-4e2f-8e81-1c9216d9df1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202189250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idle
.202189250
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.2863457002
Short name T592
Test name
Test status
Simulation time 6846203240 ps
CPU time 33.99 seconds
Started Mar 24 01:13:38 PM PDT 24
Finished Mar 24 01:14:12 PM PDT 24
Peak memory 237136 kb
Host smart-936c3003-5523-47bd-b786-6d7a992bacdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863457002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.2863457002
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.2461787240
Short name T384
Test name
Test status
Simulation time 4903296774 ps
CPU time 5.84 seconds
Started Mar 24 01:13:56 PM PDT 24
Finished Mar 24 01:14:02 PM PDT 24
Peak memory 234944 kb
Host smart-70930b99-47f2-4c96-b071-f782c8a5b4e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461787240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.2461787240
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2200312631
Short name T339
Test name
Test status
Simulation time 1383470856 ps
CPU time 7.53 seconds
Started Mar 24 01:13:44 PM PDT 24
Finished Mar 24 01:13:51 PM PDT 24
Peak memory 220196 kb
Host smart-4060895b-0590-4a58-8a4d-413211276679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200312631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2200312631
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.479135618
Short name T436
Test name
Test status
Simulation time 6886654023 ps
CPU time 19.52 seconds
Started Mar 24 01:13:40 PM PDT 24
Finished Mar 24 01:14:00 PM PDT 24
Peak memory 219164 kb
Host smart-a3b276a7-ddaa-4c2f-bed2-b43f3a17c97d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479135618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap
.479135618
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.87893010
Short name T679
Test name
Test status
Simulation time 17402756069 ps
CPU time 46.03 seconds
Started Mar 24 01:13:50 PM PDT 24
Finished Mar 24 01:14:36 PM PDT 24
Peak memory 217440 kb
Host smart-c0a10cb9-fc96-42bd-8aad-bfd392bb59c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87893010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.87893010
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.1259482363
Short name T34
Test name
Test status
Simulation time 1011162540 ps
CPU time 4.71 seconds
Started Mar 24 01:13:56 PM PDT 24
Finished Mar 24 01:14:01 PM PDT 24
Peak memory 222900 kb
Host smart-cd22cea1-f20c-4e28-9692-ba78c7c7ce18
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1259482363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.1259482363
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.3610220857
Short name T303
Test name
Test status
Simulation time 198890633 ps
CPU time 0.99 seconds
Started Mar 24 01:13:44 PM PDT 24
Finished Mar 24 01:13:45 PM PDT 24
Peak memory 207148 kb
Host smart-8834432e-8557-4d89-8d97-06889d148737
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610220857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.3610220857
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.1112156496
Short name T328
Test name
Test status
Simulation time 1369586700 ps
CPU time 11.89 seconds
Started Mar 24 01:13:42 PM PDT 24
Finished Mar 24 01:13:54 PM PDT 24
Peak memory 216660 kb
Host smart-21a2b493-2953-4b3b-a76d-fd9bf5a0283f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112156496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.1112156496
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.1350514847
Short name T643
Test name
Test status
Simulation time 7589142632 ps
CPU time 20.06 seconds
Started Mar 24 01:13:56 PM PDT 24
Finished Mar 24 01:14:17 PM PDT 24
Peak memory 216760 kb
Host smart-f0a39a50-430d-4a69-93e3-5f50e9a15f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350514847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.1350514847
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.743197133
Short name T658
Test name
Test status
Simulation time 39604529 ps
CPU time 1.03 seconds
Started Mar 24 01:13:45 PM PDT 24
Finished Mar 24 01:13:46 PM PDT 24
Peak memory 208452 kb
Host smart-02fa8836-f42f-40f5-9be6-14babc0024a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743197133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.743197133
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.963114151
Short name T834
Test name
Test status
Simulation time 126141176 ps
CPU time 1.04 seconds
Started Mar 24 01:13:56 PM PDT 24
Finished Mar 24 01:13:57 PM PDT 24
Peak memory 207100 kb
Host smart-39abd67a-55c5-4d25-a819-b0940a6ec02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963114151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.963114151
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.364111995
Short name T355
Test name
Test status
Simulation time 868687958 ps
CPU time 6.02 seconds
Started Mar 24 01:13:45 PM PDT 24
Finished Mar 24 01:13:51 PM PDT 24
Peak memory 228216 kb
Host smart-3d684095-de91-4ee6-a00e-01a0a6bde6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364111995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.364111995
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.2602277552
Short name T42
Test name
Test status
Simulation time 56920174 ps
CPU time 0.73 seconds
Started Mar 24 01:13:48 PM PDT 24
Finished Mar 24 01:13:49 PM PDT 24
Peak memory 205660 kb
Host smart-bdbe7186-e34c-41ea-991e-fd2ed4b92da9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602277552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
2602277552
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.982779298
Short name T211
Test name
Test status
Simulation time 26450864983 ps
CPU time 9.19 seconds
Started Mar 24 01:13:44 PM PDT 24
Finished Mar 24 01:13:54 PM PDT 24
Peak memory 221000 kb
Host smart-b13a0f99-4c8b-44a9-a78a-591eeef3c5ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982779298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.982779298
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.2767034183
Short name T557
Test name
Test status
Simulation time 36124642 ps
CPU time 0.78 seconds
Started Mar 24 01:13:50 PM PDT 24
Finished Mar 24 01:13:51 PM PDT 24
Peak memory 207140 kb
Host smart-3bfee2e4-4402-4505-9739-0801ba038fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767034183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.2767034183
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.1448990670
Short name T219
Test name
Test status
Simulation time 4379064504 ps
CPU time 22.47 seconds
Started Mar 24 01:13:46 PM PDT 24
Finished Mar 24 01:14:08 PM PDT 24
Peak memory 233776 kb
Host smart-0f8c3aca-dd4a-4aad-9ae0-c2f1f57c5154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448990670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.1448990670
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.3459792682
Short name T25
Test name
Test status
Simulation time 136592297910 ps
CPU time 207.96 seconds
Started Mar 24 01:13:49 PM PDT 24
Finished Mar 24 01:17:17 PM PDT 24
Peak memory 250888 kb
Host smart-ac23852e-80b4-438c-a0a0-7648c033c274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459792682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.3459792682
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.43486276
Short name T68
Test name
Test status
Simulation time 20053726505 ps
CPU time 175.07 seconds
Started Mar 24 01:13:49 PM PDT 24
Finished Mar 24 01:16:44 PM PDT 24
Peak memory 261220 kb
Host smart-375c8eac-f047-4761-9b93-6585b1cf80c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43486276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idle.43486276
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.2569905352
Short name T967
Test name
Test status
Simulation time 1945401337 ps
CPU time 9.94 seconds
Started Mar 24 01:13:46 PM PDT 24
Finished Mar 24 01:13:56 PM PDT 24
Peak memory 236228 kb
Host smart-b5e01fe2-c380-465b-8cb2-6841b938afc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569905352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.2569905352
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.2874949582
Short name T732
Test name
Test status
Simulation time 2685562110 ps
CPU time 5.7 seconds
Started Mar 24 01:13:45 PM PDT 24
Finished Mar 24 01:13:51 PM PDT 24
Peak memory 218772 kb
Host smart-fcd9faa2-a3f3-4420-ba7c-2339dd0d3720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874949582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.2874949582
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.401066219
Short name T186
Test name
Test status
Simulation time 24484873848 ps
CPU time 14.53 seconds
Started Mar 24 01:13:48 PM PDT 24
Finished Mar 24 01:14:02 PM PDT 24
Peak memory 239188 kb
Host smart-9131b4ca-84df-4424-8fd0-1439e617dd79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401066219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.401066219
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.2318095393
Short name T942
Test name
Test status
Simulation time 1144897770 ps
CPU time 5.86 seconds
Started Mar 24 01:13:53 PM PDT 24
Finished Mar 24 01:13:59 PM PDT 24
Peak memory 237772 kb
Host smart-46a68f4b-8e5b-4a76-8d64-8763c2479309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318095393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.2318095393
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.2402475260
Short name T951
Test name
Test status
Simulation time 6191663807 ps
CPU time 9.2 seconds
Started Mar 24 01:13:52 PM PDT 24
Finished Mar 24 01:14:01 PM PDT 24
Peak memory 233928 kb
Host smart-c993525e-1e24-426e-9aea-9ec4ea497b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402475260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.2402475260
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.2954686992
Short name T370
Test name
Test status
Simulation time 1030135899 ps
CPU time 4 seconds
Started Mar 24 01:13:51 PM PDT 24
Finished Mar 24 01:13:55 PM PDT 24
Peak memory 220860 kb
Host smart-9034e77f-acc7-4ffc-9113-f9cf6870d010
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2954686992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.2954686992
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.1956590851
Short name T861
Test name
Test status
Simulation time 51735119 ps
CPU time 1.07 seconds
Started Mar 24 01:13:45 PM PDT 24
Finished Mar 24 01:13:46 PM PDT 24
Peak memory 207004 kb
Host smart-2f1e5ca2-1dcc-4424-b5c0-8edaaaa005ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956590851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.1956590851
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.2586889792
Short name T627
Test name
Test status
Simulation time 9576415766 ps
CPU time 36.23 seconds
Started Mar 24 01:13:45 PM PDT 24
Finished Mar 24 01:14:22 PM PDT 24
Peak memory 216676 kb
Host smart-a3eb1aca-9ebd-4b0c-b197-ddb8de97c020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586889792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2586889792
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.1207574159
Short name T4
Test name
Test status
Simulation time 7443591487 ps
CPU time 24.11 seconds
Started Mar 24 01:13:45 PM PDT 24
Finished Mar 24 01:14:09 PM PDT 24
Peak memory 216632 kb
Host smart-93510c9c-ab0d-4376-b901-eda72c127348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207574159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.1207574159
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.190544229
Short name T671
Test name
Test status
Simulation time 21671181 ps
CPU time 1.17 seconds
Started Mar 24 01:13:43 PM PDT 24
Finished Mar 24 01:13:44 PM PDT 24
Peak memory 216636 kb
Host smart-19dbd457-033e-4907-a412-0ca45c433f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190544229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.190544229
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.2973442093
Short name T274
Test name
Test status
Simulation time 219506396 ps
CPU time 0.97 seconds
Started Mar 24 01:13:54 PM PDT 24
Finished Mar 24 01:13:55 PM PDT 24
Peak memory 207096 kb
Host smart-7c1546f9-c1a4-47d7-b2ec-0b6637482dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973442093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.2973442093
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.949707943
Short name T556
Test name
Test status
Simulation time 1973929032 ps
CPU time 7.52 seconds
Started Mar 24 01:13:50 PM PDT 24
Finished Mar 24 01:13:58 PM PDT 24
Peak memory 219300 kb
Host smart-51cba58c-4400-4d5b-b42d-d9ee878bd408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949707943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.949707943
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.2350304515
Short name T278
Test name
Test status
Simulation time 43068879 ps
CPU time 0.76 seconds
Started Mar 24 01:13:56 PM PDT 24
Finished Mar 24 01:13:57 PM PDT 24
Peak memory 206064 kb
Host smart-bcd1c274-7ef8-4d1c-aea5-e07166f08c1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350304515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
2350304515
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.496383882
Short name T201
Test name
Test status
Simulation time 1033600900 ps
CPU time 3.06 seconds
Started Mar 24 01:13:47 PM PDT 24
Finished Mar 24 01:13:50 PM PDT 24
Peak memory 218636 kb
Host smart-c3e0a806-8b96-4a9f-916e-faf27f132fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496383882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.496383882
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.2348981899
Short name T949
Test name
Test status
Simulation time 53550437 ps
CPU time 0.74 seconds
Started Mar 24 01:13:49 PM PDT 24
Finished Mar 24 01:13:50 PM PDT 24
Peak memory 206168 kb
Host smart-25556c06-9a25-44d8-968a-d30eb7f11f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348981899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.2348981899
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.422606258
Short name T883
Test name
Test status
Simulation time 56131245919 ps
CPU time 206.22 seconds
Started Mar 24 01:13:43 PM PDT 24
Finished Mar 24 01:17:10 PM PDT 24
Peak memory 249480 kb
Host smart-a046c32c-d518-49d0-acd0-bf0b9629166f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422606258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.422606258
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.1959851542
Short name T161
Test name
Test status
Simulation time 6762494480 ps
CPU time 100.64 seconds
Started Mar 24 01:13:44 PM PDT 24
Finished Mar 24 01:15:25 PM PDT 24
Peak memory 257744 kb
Host smart-a0f1d084-d3db-4388-b931-acf4b9ac4ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959851542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.1959851542
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.4183947487
Short name T917
Test name
Test status
Simulation time 789323270 ps
CPU time 7.05 seconds
Started Mar 24 01:13:47 PM PDT 24
Finished Mar 24 01:13:54 PM PDT 24
Peak memory 234184 kb
Host smart-be499fb9-c06f-4003-8b51-b0d1194ac876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183947487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.4183947487
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.3982497966
Short name T764
Test name
Test status
Simulation time 1710373351 ps
CPU time 6.96 seconds
Started Mar 24 01:13:44 PM PDT 24
Finished Mar 24 01:13:51 PM PDT 24
Peak memory 218864 kb
Host smart-422f9456-eac9-4703-acbc-bfbf64fe5e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982497966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.3982497966
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.976926293
Short name T28
Test name
Test status
Simulation time 795610883 ps
CPU time 4.34 seconds
Started Mar 24 01:13:56 PM PDT 24
Finished Mar 24 01:14:01 PM PDT 24
Peak memory 233792 kb
Host smart-32f0fa67-15b7-4170-9a02-82984039b47e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976926293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap
.976926293
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.3755911222
Short name T610
Test name
Test status
Simulation time 6789197618 ps
CPU time 10.19 seconds
Started Mar 24 01:13:46 PM PDT 24
Finished Mar 24 01:13:56 PM PDT 24
Peak memory 230544 kb
Host smart-1ab57c3d-7151-449e-9f18-4d2435604884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755911222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3755911222
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.2407491790
Short name T593
Test name
Test status
Simulation time 747268656 ps
CPU time 5.05 seconds
Started Mar 24 01:13:52 PM PDT 24
Finished Mar 24 01:13:57 PM PDT 24
Peak memory 219180 kb
Host smart-ee8d554b-cc0d-4689-bbaf-2d34c2b22f62
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2407491790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.2407491790
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.3702293258
Short name T74
Test name
Test status
Simulation time 16246225843 ps
CPU time 115.47 seconds
Started Mar 24 01:13:45 PM PDT 24
Finished Mar 24 01:15:40 PM PDT 24
Peak memory 264156 kb
Host smart-fe39a1cb-0741-4a42-8abc-196c6dc088e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702293258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.3702293258
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.4266352249
Short name T947
Test name
Test status
Simulation time 10509274383 ps
CPU time 57.21 seconds
Started Mar 24 01:13:45 PM PDT 24
Finished Mar 24 01:14:43 PM PDT 24
Peak memory 216976 kb
Host smart-f4b2d3d1-88d0-4d1f-baa6-06ec8d242b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266352249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.4266352249
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.272675098
Short name T699
Test name
Test status
Simulation time 12893306114 ps
CPU time 23.89 seconds
Started Mar 24 01:13:44 PM PDT 24
Finished Mar 24 01:14:08 PM PDT 24
Peak memory 217448 kb
Host smart-cb1fb5f9-5943-40c4-9abd-91a748f0282d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272675098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.272675098
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.3960339889
Short name T256
Test name
Test status
Simulation time 342994709 ps
CPU time 9.59 seconds
Started Mar 24 01:13:43 PM PDT 24
Finished Mar 24 01:13:53 PM PDT 24
Peak memory 216596 kb
Host smart-340aff78-208a-4d97-827a-1c609599cbc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960339889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.3960339889
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.1973839386
Short name T407
Test name
Test status
Simulation time 176127542 ps
CPU time 0.92 seconds
Started Mar 24 01:13:45 PM PDT 24
Finished Mar 24 01:13:46 PM PDT 24
Peak memory 207060 kb
Host smart-fab2b7e6-d7bf-478c-b161-6ec3622ac2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973839386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.1973839386
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.546231385
Short name T717
Test name
Test status
Simulation time 1759587702 ps
CPU time 6.22 seconds
Started Mar 24 01:13:49 PM PDT 24
Finished Mar 24 01:13:55 PM PDT 24
Peak memory 229588 kb
Host smart-d659fd2d-99b2-4175-bea3-861529d942ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546231385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.546231385
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.2421199009
Short name T555
Test name
Test status
Simulation time 13036189 ps
CPU time 0.76 seconds
Started Mar 24 01:12:47 PM PDT 24
Finished Mar 24 01:12:48 PM PDT 24
Peak memory 205748 kb
Host smart-8b2ccc01-aa18-45b8-a5ea-913ea2a4ef67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421199009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.2
421199009
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.3419308894
Short name T892
Test name
Test status
Simulation time 40132957 ps
CPU time 2.64 seconds
Started Mar 24 01:12:40 PM PDT 24
Finished Mar 24 01:12:43 PM PDT 24
Peak memory 234048 kb
Host smart-f5629748-a826-473c-b73f-757aa0e4ef6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419308894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.3419308894
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.1560950974
Short name T550
Test name
Test status
Simulation time 81504599 ps
CPU time 0.77 seconds
Started Mar 24 01:12:41 PM PDT 24
Finished Mar 24 01:12:42 PM PDT 24
Peak memory 206800 kb
Host smart-dc8fd871-2844-497f-8157-b6c75872ee13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560950974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.1560950974
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.500112454
Short name T654
Test name
Test status
Simulation time 4703002478 ps
CPU time 23.4 seconds
Started Mar 24 01:12:51 PM PDT 24
Finished Mar 24 01:13:15 PM PDT 24
Peak memory 241340 kb
Host smart-e46b47ba-a407-4591-b8dc-7b0a826bae40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500112454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.500112454
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.1866573092
Short name T26
Test name
Test status
Simulation time 88068127706 ps
CPU time 607.57 seconds
Started Mar 24 01:12:36 PM PDT 24
Finished Mar 24 01:22:44 PM PDT 24
Peak memory 265312 kb
Host smart-abffd0a5-5a16-4429-bedb-ede9750db3c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866573092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.1866573092
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.3538930220
Short name T229
Test name
Test status
Simulation time 249852906576 ps
CPU time 341.68 seconds
Started Mar 24 01:12:42 PM PDT 24
Finished Mar 24 01:18:24 PM PDT 24
Peak memory 264472 kb
Host smart-1d5a5b92-ebb9-467f-8dd1-d59e3845fc53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538930220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.3538930220
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.2636768635
Short name T797
Test name
Test status
Simulation time 3762918747 ps
CPU time 21.07 seconds
Started Mar 24 01:12:51 PM PDT 24
Finished Mar 24 01:13:12 PM PDT 24
Peak memory 229756 kb
Host smart-eece12ff-62b1-4ef4-8657-3b715c40a554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636768635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.2636768635
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.2209806617
Short name T366
Test name
Test status
Simulation time 30767063921 ps
CPU time 13.43 seconds
Started Mar 24 01:12:39 PM PDT 24
Finished Mar 24 01:12:52 PM PDT 24
Peak memory 233808 kb
Host smart-da377317-825c-4e4b-b62d-af7ecbdf71ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209806617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.2209806617
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.3856193995
Short name T950
Test name
Test status
Simulation time 42917717268 ps
CPU time 32.39 seconds
Started Mar 24 01:12:37 PM PDT 24
Finished Mar 24 01:13:10 PM PDT 24
Peak memory 230092 kb
Host smart-52dd02c6-b7db-4c5e-b160-ee2ab2c9a7ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856193995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.3856193995
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.1548221142
Short name T501
Test name
Test status
Simulation time 16701112803 ps
CPU time 12.32 seconds
Started Mar 24 01:12:47 PM PDT 24
Finished Mar 24 01:13:00 PM PDT 24
Peak memory 216948 kb
Host smart-6a70d283-2344-4761-9f50-42fb75f59ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548221142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.1548221142
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.4088034787
Short name T958
Test name
Test status
Simulation time 1994876126 ps
CPU time 4.94 seconds
Started Mar 24 01:12:33 PM PDT 24
Finished Mar 24 01:12:38 PM PDT 24
Peak memory 233624 kb
Host smart-5b1d345c-5957-497d-b1b2-bba64592cb69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088034787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.4088034787
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_ram_cfg.790957428
Short name T890
Test name
Test status
Simulation time 32484155 ps
CPU time 0.78 seconds
Started Mar 24 01:12:35 PM PDT 24
Finished Mar 24 01:12:36 PM PDT 24
Peak memory 216516 kb
Host smart-f6eb0a9c-edb0-4e8a-92b0-b513aaecf8a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790957428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_ram_cfg.790957428
Directory /workspace/3.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.1601525699
Short name T690
Test name
Test status
Simulation time 757612395 ps
CPU time 4.19 seconds
Started Mar 24 01:12:46 PM PDT 24
Finished Mar 24 01:12:50 PM PDT 24
Peak memory 221004 kb
Host smart-9be0447a-45dd-4cb7-9b88-70830e7bde46
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1601525699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.1601525699
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.649140214
Short name T53
Test name
Test status
Simulation time 81427359 ps
CPU time 1.32 seconds
Started Mar 24 01:12:51 PM PDT 24
Finished Mar 24 01:12:53 PM PDT 24
Peak memory 235712 kb
Host smart-37391dbc-476e-40b4-912a-99e14ff5da25
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649140214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.649140214
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.3037999041
Short name T609
Test name
Test status
Simulation time 7387862177 ps
CPU time 125.15 seconds
Started Mar 24 01:12:50 PM PDT 24
Finished Mar 24 01:14:55 PM PDT 24
Peak memory 271880 kb
Host smart-360670d1-b827-47db-956b-aa03e399fdfb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037999041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.3037999041
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.3787872590
Short name T695
Test name
Test status
Simulation time 12361549695 ps
CPU time 32.55 seconds
Started Mar 24 01:12:40 PM PDT 24
Finished Mar 24 01:13:13 PM PDT 24
Peak memory 216948 kb
Host smart-5fed09c1-5ace-4df2-aab4-c6889486e2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787872590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.3787872590
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.1662344113
Short name T911
Test name
Test status
Simulation time 1575170546 ps
CPU time 9.42 seconds
Started Mar 24 01:12:46 PM PDT 24
Finished Mar 24 01:12:56 PM PDT 24
Peak memory 216544 kb
Host smart-cfa9cb49-0627-4c78-85c4-1529351dfffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662344113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.1662344113
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.3519089540
Short name T252
Test name
Test status
Simulation time 15618398 ps
CPU time 0.82 seconds
Started Mar 24 01:12:51 PM PDT 24
Finished Mar 24 01:12:52 PM PDT 24
Peak memory 206080 kb
Host smart-31ac30e3-be10-45bf-9b04-7d88eabea73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519089540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3519089540
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.3255838346
Short name T296
Test name
Test status
Simulation time 101345458 ps
CPU time 0.83 seconds
Started Mar 24 01:12:50 PM PDT 24
Finished Mar 24 01:12:51 PM PDT 24
Peak memory 206320 kb
Host smart-a90e48ac-61d6-44ef-8689-08ee34346c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255838346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.3255838346
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.2129040756
Short name T734
Test name
Test status
Simulation time 27438769029 ps
CPU time 21.79 seconds
Started Mar 24 01:12:52 PM PDT 24
Finished Mar 24 01:13:14 PM PDT 24
Peak memory 233168 kb
Host smart-367a4f7d-1f88-4ebf-b9b2-431d950e4a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129040756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.2129040756
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.2273091122
Short name T250
Test name
Test status
Simulation time 19787392 ps
CPU time 0.73 seconds
Started Mar 24 01:13:49 PM PDT 24
Finished Mar 24 01:13:50 PM PDT 24
Peak memory 205756 kb
Host smart-80d553c4-397e-4ebc-a983-4bb69a226349
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273091122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
2273091122
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.2515667770
Short name T324
Test name
Test status
Simulation time 108421760 ps
CPU time 2.58 seconds
Started Mar 24 01:13:48 PM PDT 24
Finished Mar 24 01:13:51 PM PDT 24
Peak memory 234012 kb
Host smart-cb862a82-4a01-4229-b361-c55914cc8795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515667770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.2515667770
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.1158024427
Short name T735
Test name
Test status
Simulation time 41044206 ps
CPU time 0.85 seconds
Started Mar 24 01:13:51 PM PDT 24
Finished Mar 24 01:13:52 PM PDT 24
Peak memory 206816 kb
Host smart-4385a3cf-84f5-424b-8f8e-2bd21cdb2f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158024427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.1158024427
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.1712054344
Short name T719
Test name
Test status
Simulation time 1013931120 ps
CPU time 6.27 seconds
Started Mar 24 01:13:44 PM PDT 24
Finished Mar 24 01:13:50 PM PDT 24
Peak memory 219304 kb
Host smart-72357d81-f3aa-44b9-9db0-54a04fc27b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712054344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.1712054344
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.3722821834
Short name T660
Test name
Test status
Simulation time 90733902838 ps
CPU time 125.37 seconds
Started Mar 24 01:13:48 PM PDT 24
Finished Mar 24 01:15:53 PM PDT 24
Peak memory 250936 kb
Host smart-433b0a03-08e4-4fd3-b867-b0f32e272711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722821834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.3722821834
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.2478288014
Short name T544
Test name
Test status
Simulation time 19238778137 ps
CPU time 30.38 seconds
Started Mar 24 01:13:55 PM PDT 24
Finished Mar 24 01:14:26 PM PDT 24
Peak memory 240716 kb
Host smart-59ec7d08-dcc9-4c46-a019-8ae41b445c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478288014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.2478288014
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.3124349715
Short name T578
Test name
Test status
Simulation time 751090130 ps
CPU time 3.54 seconds
Started Mar 24 01:13:51 PM PDT 24
Finished Mar 24 01:13:54 PM PDT 24
Peak memory 224820 kb
Host smart-07cc25d3-2e39-4467-bf7d-ccb7c656ea95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124349715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.3124349715
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.3110711609
Short name T553
Test name
Test status
Simulation time 5905096220 ps
CPU time 19.64 seconds
Started Mar 24 01:13:47 PM PDT 24
Finished Mar 24 01:14:07 PM PDT 24
Peak memory 218872 kb
Host smart-46c7c998-7f4a-487a-8497-8a846c12ca44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110711609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.3110711609
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.64993777
Short name T532
Test name
Test status
Simulation time 1968639832 ps
CPU time 4.11 seconds
Started Mar 24 01:13:49 PM PDT 24
Finished Mar 24 01:13:54 PM PDT 24
Peak memory 234080 kb
Host smart-74a89568-b11c-4c94-8e74-a61c37de1167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64993777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap.64993777
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.3371643642
Short name T584
Test name
Test status
Simulation time 5614992940 ps
CPU time 16.45 seconds
Started Mar 24 01:13:44 PM PDT 24
Finished Mar 24 01:14:00 PM PDT 24
Peak memory 235580 kb
Host smart-07122d0e-dc1d-47f6-9b27-03ecbfb2df16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371643642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.3371643642
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.1750505211
Short name T862
Test name
Test status
Simulation time 2317891231 ps
CPU time 4.06 seconds
Started Mar 24 01:13:56 PM PDT 24
Finished Mar 24 01:14:00 PM PDT 24
Peak memory 219860 kb
Host smart-8b59c01c-3931-43a7-8e5b-4abd3080594b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1750505211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.1750505211
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.849394632
Short name T396
Test name
Test status
Simulation time 452291155 ps
CPU time 1.07 seconds
Started Mar 24 01:13:51 PM PDT 24
Finished Mar 24 01:13:52 PM PDT 24
Peak memory 207172 kb
Host smart-7a7fca35-c2bd-4f94-b553-dd3416223c0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849394632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stres
s_all.849394632
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.690837666
Short name T858
Test name
Test status
Simulation time 4199848264 ps
CPU time 34.37 seconds
Started Mar 24 01:13:56 PM PDT 24
Finished Mar 24 01:14:31 PM PDT 24
Peak memory 220528 kb
Host smart-93a21cc7-867d-4ac7-a327-94c4dded50d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690837666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.690837666
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.683785286
Short name T645
Test name
Test status
Simulation time 1434328551 ps
CPU time 3.68 seconds
Started Mar 24 01:13:52 PM PDT 24
Finished Mar 24 01:13:55 PM PDT 24
Peak memory 216620 kb
Host smart-71c0689a-642c-4fdb-9d7d-bfd0639565f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683785286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.683785286
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.4068415701
Short name T666
Test name
Test status
Simulation time 276841796 ps
CPU time 4.17 seconds
Started Mar 24 01:13:47 PM PDT 24
Finished Mar 24 01:13:51 PM PDT 24
Peak memory 216660 kb
Host smart-6be6a753-ab8a-4c44-8e23-5468ce4bd5b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068415701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.4068415701
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.2121721674
Short name T961
Test name
Test status
Simulation time 27751518 ps
CPU time 0.72 seconds
Started Mar 24 01:13:56 PM PDT 24
Finished Mar 24 01:13:57 PM PDT 24
Peak memory 206056 kb
Host smart-67b9e998-bb64-4d9c-8c86-f0b380e7f027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121721674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.2121721674
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.1611028520
Short name T925
Test name
Test status
Simulation time 74385748 ps
CPU time 2.76 seconds
Started Mar 24 01:13:54 PM PDT 24
Finished Mar 24 01:13:57 PM PDT 24
Peak memory 224868 kb
Host smart-fdcd8e39-22d9-4b79-8ac0-3011ed1c8d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611028520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.1611028520
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.1164622159
Short name T603
Test name
Test status
Simulation time 17576801 ps
CPU time 0.76 seconds
Started Mar 24 01:13:54 PM PDT 24
Finished Mar 24 01:13:55 PM PDT 24
Peak memory 205740 kb
Host smart-ec422329-febe-493d-83bb-1c05f1403c1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164622159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
1164622159
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.2324196580
Short name T894
Test name
Test status
Simulation time 36238187 ps
CPU time 2.53 seconds
Started Mar 24 01:13:53 PM PDT 24
Finished Mar 24 01:13:56 PM PDT 24
Peak memory 234100 kb
Host smart-1e87879c-ecbe-426b-9e6e-ae0f09bff67d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324196580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.2324196580
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.1286459802
Short name T635
Test name
Test status
Simulation time 91094558 ps
CPU time 0.76 seconds
Started Mar 24 01:13:55 PM PDT 24
Finished Mar 24 01:13:56 PM PDT 24
Peak memory 206096 kb
Host smart-23999c14-170e-410a-be17-46edb78c163c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286459802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.1286459802
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.1978622562
Short name T474
Test name
Test status
Simulation time 4115051518 ps
CPU time 29.26 seconds
Started Mar 24 01:13:49 PM PDT 24
Finished Mar 24 01:14:19 PM PDT 24
Peak memory 241296 kb
Host smart-7770d2dd-c8fd-418f-b849-887a58ee5cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978622562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.1978622562
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.3439728335
Short name T227
Test name
Test status
Simulation time 5825644340 ps
CPU time 66.92 seconds
Started Mar 24 01:13:52 PM PDT 24
Finished Mar 24 01:14:59 PM PDT 24
Peak memory 238360 kb
Host smart-6d6d72fa-5f74-45b4-b154-308a61d502b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439728335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.3439728335
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.191605551
Short name T468
Test name
Test status
Simulation time 765646138 ps
CPU time 11.28 seconds
Started Mar 24 01:13:53 PM PDT 24
Finished Mar 24 01:14:05 PM PDT 24
Peak memory 233052 kb
Host smart-96e4befd-ec2b-4e2c-9edc-332f6424c8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191605551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.191605551
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.2450114739
Short name T336
Test name
Test status
Simulation time 3605454092 ps
CPU time 7.03 seconds
Started Mar 24 01:13:53 PM PDT 24
Finished Mar 24 01:14:00 PM PDT 24
Peak memory 220104 kb
Host smart-e5875435-16bf-4749-b9fa-28a3d1a46320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450114739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.2450114739
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.4117904410
Short name T601
Test name
Test status
Simulation time 25364520112 ps
CPU time 20.96 seconds
Started Mar 24 01:13:51 PM PDT 24
Finished Mar 24 01:14:12 PM PDT 24
Peak memory 232844 kb
Host smart-7c78671f-d83f-48c2-8f92-b6865629498a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117904410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.4117904410
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.153959830
Short name T880
Test name
Test status
Simulation time 710134789 ps
CPU time 4.1 seconds
Started Mar 24 01:13:50 PM PDT 24
Finished Mar 24 01:13:54 PM PDT 24
Peak memory 233320 kb
Host smart-bdf57c9f-0dcd-47cd-a406-056602ce4546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153959830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap
.153959830
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.77385421
Short name T312
Test name
Test status
Simulation time 6370128416 ps
CPU time 7.22 seconds
Started Mar 24 01:13:53 PM PDT 24
Finished Mar 24 01:14:01 PM PDT 24
Peak memory 233956 kb
Host smart-5f6ad348-74ee-4ecc-9d3d-fa4bff3c8622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77385421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.77385421
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.3439981674
Short name T713
Test name
Test status
Simulation time 391132129 ps
CPU time 3.63 seconds
Started Mar 24 01:13:51 PM PDT 24
Finished Mar 24 01:13:55 PM PDT 24
Peak memory 222728 kb
Host smart-19a209d3-dd6d-485a-9b08-fa80c632a815
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3439981674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.3439981674
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.184275198
Short name T852
Test name
Test status
Simulation time 876431254 ps
CPU time 14.24 seconds
Started Mar 24 01:13:55 PM PDT 24
Finished Mar 24 01:14:10 PM PDT 24
Peak memory 219672 kb
Host smart-1b871b90-d377-4f1e-8af6-a8213e19b250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184275198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.184275198
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.2825415786
Short name T287
Test name
Test status
Simulation time 13707055004 ps
CPU time 12.83 seconds
Started Mar 24 01:13:57 PM PDT 24
Finished Mar 24 01:14:10 PM PDT 24
Peak memory 216768 kb
Host smart-0a06dc03-cf0e-4f5d-a2d9-ac75c48f59fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825415786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.2825415786
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.2323858290
Short name T729
Test name
Test status
Simulation time 136810811 ps
CPU time 0.75 seconds
Started Mar 24 01:13:56 PM PDT 24
Finished Mar 24 01:13:57 PM PDT 24
Peak memory 206272 kb
Host smart-490728e8-cf89-4798-8ffa-463410ba4f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323858290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.2323858290
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.4012096663
Short name T290
Test name
Test status
Simulation time 17572963 ps
CPU time 0.72 seconds
Started Mar 24 01:13:55 PM PDT 24
Finished Mar 24 01:13:56 PM PDT 24
Peak memory 206004 kb
Host smart-af79f3e5-f427-46fb-ad44-eae8286d555a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012096663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.4012096663
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.3640696489
Short name T526
Test name
Test status
Simulation time 1277050457 ps
CPU time 6.15 seconds
Started Mar 24 01:13:53 PM PDT 24
Finished Mar 24 01:13:59 PM PDT 24
Peak memory 227380 kb
Host smart-fb13edfb-b0a2-4406-900e-2383f8a7571f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640696489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.3640696489
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.3336054938
Short name T41
Test name
Test status
Simulation time 27752139 ps
CPU time 0.79 seconds
Started Mar 24 01:13:56 PM PDT 24
Finished Mar 24 01:13:57 PM PDT 24
Peak memory 205744 kb
Host smart-913c0f39-b0db-4a1e-acee-819a1f75d402
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336054938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
3336054938
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.350393160
Short name T869
Test name
Test status
Simulation time 928365571 ps
CPU time 5.18 seconds
Started Mar 24 01:13:53 PM PDT 24
Finished Mar 24 01:13:58 PM PDT 24
Peak memory 220180 kb
Host smart-f8b2e867-fb67-431a-9330-5d50be07b154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350393160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.350393160
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.3649880863
Short name T331
Test name
Test status
Simulation time 26653374 ps
CPU time 0.76 seconds
Started Mar 24 01:13:52 PM PDT 24
Finished Mar 24 01:13:53 PM PDT 24
Peak memory 205752 kb
Host smart-0438473e-0ddb-4804-8ef3-b13687fed04a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649880863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.3649880863
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.3274055985
Short name T856
Test name
Test status
Simulation time 18976994341 ps
CPU time 37.32 seconds
Started Mar 24 01:13:54 PM PDT 24
Finished Mar 24 01:14:31 PM PDT 24
Peak memory 249888 kb
Host smart-a8ced7bb-fca0-490f-a057-e1ff2d8b3dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274055985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.3274055985
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.825706002
Short name T158
Test name
Test status
Simulation time 338134588634 ps
CPU time 464.8 seconds
Started Mar 24 01:13:49 PM PDT 24
Finished Mar 24 01:21:34 PM PDT 24
Peak memory 268784 kb
Host smart-8d2942fb-469a-4980-a5db-a46438820fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825706002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.825706002
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.1455725062
Short name T21
Test name
Test status
Simulation time 20472468970 ps
CPU time 53.91 seconds
Started Mar 24 01:13:50 PM PDT 24
Finished Mar 24 01:14:44 PM PDT 24
Peak memory 249260 kb
Host smart-b3f22039-096e-4271-94ec-fb13ff66b255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455725062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.1455725062
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.2544659343
Short name T392
Test name
Test status
Simulation time 4683869675 ps
CPU time 14.79 seconds
Started Mar 24 01:13:54 PM PDT 24
Finished Mar 24 01:14:09 PM PDT 24
Peak memory 241036 kb
Host smart-1ffb21e3-0fc4-4022-b9d1-aa05e44b4fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544659343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.2544659343
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.3830286871
Short name T426
Test name
Test status
Simulation time 7026607900 ps
CPU time 6.59 seconds
Started Mar 24 01:13:49 PM PDT 24
Finished Mar 24 01:13:56 PM PDT 24
Peak memory 234012 kb
Host smart-7072fdad-d4f0-44b2-b130-044b07f4fc82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830286871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.3830286871
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.29673736
Short name T487
Test name
Test status
Simulation time 633113816 ps
CPU time 7.62 seconds
Started Mar 24 01:13:52 PM PDT 24
Finished Mar 24 01:13:59 PM PDT 24
Peak memory 231284 kb
Host smart-e36f796a-13b6-4a55-b2c5-cddd74807350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29673736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.29673736
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.4288221353
Short name T928
Test name
Test status
Simulation time 58459365040 ps
CPU time 41.82 seconds
Started Mar 24 01:13:58 PM PDT 24
Finished Mar 24 01:14:40 PM PDT 24
Peak memory 237668 kb
Host smart-0fb8b7da-b902-4d94-81ca-a9c30632ca9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288221353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.4288221353
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.1593615263
Short name T210
Test name
Test status
Simulation time 4567522393 ps
CPU time 4.1 seconds
Started Mar 24 01:13:53 PM PDT 24
Finished Mar 24 01:13:57 PM PDT 24
Peak memory 218292 kb
Host smart-fbc39ec0-de4d-4307-b58f-eb4b86497d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593615263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.1593615263
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.1209817198
Short name T292
Test name
Test status
Simulation time 1479867931 ps
CPU time 4.29 seconds
Started Mar 24 01:13:51 PM PDT 24
Finished Mar 24 01:13:56 PM PDT 24
Peak memory 219648 kb
Host smart-6d381d7f-877e-4770-b469-d89979c3a9e6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1209817198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.1209817198
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.4001739122
Short name T132
Test name
Test status
Simulation time 69805133 ps
CPU time 1.21 seconds
Started Mar 24 01:13:52 PM PDT 24
Finished Mar 24 01:13:54 PM PDT 24
Peak memory 207560 kb
Host smart-e91bd83f-e6f8-425b-80a5-b697dce193a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001739122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.4001739122
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.3298060506
Short name T744
Test name
Test status
Simulation time 1172627495 ps
CPU time 17.08 seconds
Started Mar 24 01:13:50 PM PDT 24
Finished Mar 24 01:14:07 PM PDT 24
Peak memory 216696 kb
Host smart-2022f6b2-e1c8-4b29-829f-d4443c54b858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298060506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.3298060506
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.2811946615
Short name T774
Test name
Test status
Simulation time 11041963017 ps
CPU time 5.73 seconds
Started Mar 24 01:13:57 PM PDT 24
Finished Mar 24 01:14:04 PM PDT 24
Peak memory 216644 kb
Host smart-b7e8db12-89b3-41a1-8767-b3ee71afe7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811946615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.2811946615
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.942756109
Short name T791
Test name
Test status
Simulation time 36121438 ps
CPU time 0.76 seconds
Started Mar 24 01:13:56 PM PDT 24
Finished Mar 24 01:13:57 PM PDT 24
Peak memory 206076 kb
Host smart-6cf6a7ae-6277-4fd8-a38d-b4635795fd04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942756109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.942756109
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.260113858
Short name T688
Test name
Test status
Simulation time 122360299 ps
CPU time 0.85 seconds
Started Mar 24 01:13:50 PM PDT 24
Finished Mar 24 01:13:51 PM PDT 24
Peak memory 206412 kb
Host smart-34be8184-2371-461a-8a4f-9fd71958fb63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260113858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.260113858
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.1811967750
Short name T511
Test name
Test status
Simulation time 697746003 ps
CPU time 6.7 seconds
Started Mar 24 01:13:57 PM PDT 24
Finished Mar 24 01:14:05 PM PDT 24
Peak memory 237684 kb
Host smart-a78e01e1-faab-4231-8067-763d2e2a492c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811967750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.1811967750
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.2265011134
Short name T615
Test name
Test status
Simulation time 16438341 ps
CPU time 0.7 seconds
Started Mar 24 01:13:59 PM PDT 24
Finished Mar 24 01:14:00 PM PDT 24
Peak memory 205124 kb
Host smart-7df39b14-f284-4ce2-a85c-07f0a6371ecb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265011134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
2265011134
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.2298439960
Short name T606
Test name
Test status
Simulation time 262578126 ps
CPU time 2.64 seconds
Started Mar 24 01:13:56 PM PDT 24
Finished Mar 24 01:13:59 PM PDT 24
Peak memory 218620 kb
Host smart-37c18826-d522-4842-8b30-0b0f4c8e8f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298439960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.2298439960
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.1811674186
Short name T435
Test name
Test status
Simulation time 63919239 ps
CPU time 0.81 seconds
Started Mar 24 01:13:59 PM PDT 24
Finished Mar 24 01:14:00 PM PDT 24
Peak memory 206796 kb
Host smart-403c860f-1512-4b74-927b-69682ff9a80b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811674186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.1811674186
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.2978256164
Short name T320
Test name
Test status
Simulation time 18837247421 ps
CPU time 44.65 seconds
Started Mar 24 01:13:55 PM PDT 24
Finished Mar 24 01:14:39 PM PDT 24
Peak memory 237568 kb
Host smart-922c3107-d3c9-431d-a728-44b012e8679b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978256164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.2978256164
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.3357538000
Short name T240
Test name
Test status
Simulation time 17062745266 ps
CPU time 144.45 seconds
Started Mar 24 01:13:57 PM PDT 24
Finished Mar 24 01:16:22 PM PDT 24
Peak memory 233168 kb
Host smart-95b0913c-63db-4b32-9ca7-ef10cc13268e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357538000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.3357538000
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.3125761865
Short name T226
Test name
Test status
Simulation time 6133568846 ps
CPU time 60.48 seconds
Started Mar 24 01:13:57 PM PDT 24
Finished Mar 24 01:14:58 PM PDT 24
Peak memory 255592 kb
Host smart-08378eba-e66a-4862-a72e-f162fe21abe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125761865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.3125761865
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.436332954
Short name T573
Test name
Test status
Simulation time 2246284515 ps
CPU time 14.1 seconds
Started Mar 24 01:13:59 PM PDT 24
Finished Mar 24 01:14:13 PM PDT 24
Peak memory 236784 kb
Host smart-9000e3b0-ec60-4476-a0d0-39a1203424d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436332954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.436332954
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.3643165384
Short name T530
Test name
Test status
Simulation time 6222745210 ps
CPU time 6.53 seconds
Started Mar 24 01:13:58 PM PDT 24
Finished Mar 24 01:14:05 PM PDT 24
Peak memory 233888 kb
Host smart-d900eacf-8e3c-4863-9b18-c6bae7652425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643165384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.3643165384
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.1562921176
Short name T325
Test name
Test status
Simulation time 427987899 ps
CPU time 3.58 seconds
Started Mar 24 01:13:57 PM PDT 24
Finished Mar 24 01:14:01 PM PDT 24
Peak memory 234104 kb
Host smart-d56dcb97-ecf9-4683-9767-4541c2f77115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562921176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.1562921176
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.3773635555
Short name T674
Test name
Test status
Simulation time 2726195270 ps
CPU time 8.89 seconds
Started Mar 24 01:13:57 PM PDT 24
Finished Mar 24 01:14:06 PM PDT 24
Peak memory 235556 kb
Host smart-bda08a0a-d448-4bfa-ada6-2c9111f5c862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773635555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.3773635555
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.3959246700
Short name T663
Test name
Test status
Simulation time 10860581394 ps
CPU time 9.69 seconds
Started Mar 24 01:13:54 PM PDT 24
Finished Mar 24 01:14:04 PM PDT 24
Peak memory 220872 kb
Host smart-f5437a95-f637-40f7-acea-092691581966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959246700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.3959246700
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.2235427086
Short name T121
Test name
Test status
Simulation time 753729965 ps
CPU time 4.69 seconds
Started Mar 24 01:13:57 PM PDT 24
Finished Mar 24 01:14:02 PM PDT 24
Peak memory 219128 kb
Host smart-cf1fec3e-8c2f-4497-9f38-41583b251662
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2235427086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.2235427086
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.9885644
Short name T740
Test name
Test status
Simulation time 5924907518 ps
CPU time 10.29 seconds
Started Mar 24 01:13:57 PM PDT 24
Finished Mar 24 01:14:08 PM PDT 24
Peak memory 216716 kb
Host smart-b881774d-86b3-427c-b83a-6d816df37a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9885644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.9885644
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.602429758
Short name T907
Test name
Test status
Simulation time 1162601713 ps
CPU time 4.17 seconds
Started Mar 24 01:14:04 PM PDT 24
Finished Mar 24 01:14:09 PM PDT 24
Peak memory 216620 kb
Host smart-d60381ba-9ae2-41bf-93f3-00117678c988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602429758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.602429758
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.318508437
Short name T271
Test name
Test status
Simulation time 87865950 ps
CPU time 0.99 seconds
Started Mar 24 01:13:56 PM PDT 24
Finished Mar 24 01:13:57 PM PDT 24
Peak memory 207912 kb
Host smart-e55127e0-f8ca-41d9-9194-e91d7b647263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318508437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.318508437
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.1751904289
Short name T558
Test name
Test status
Simulation time 87804545 ps
CPU time 0.82 seconds
Started Mar 24 01:13:58 PM PDT 24
Finished Mar 24 01:13:59 PM PDT 24
Peak memory 206076 kb
Host smart-46a62e9f-96f7-4679-82a7-65605c3a838b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751904289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.1751904289
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.2263412297
Short name T319
Test name
Test status
Simulation time 3924708817 ps
CPU time 13.22 seconds
Started Mar 24 01:13:54 PM PDT 24
Finished Mar 24 01:14:08 PM PDT 24
Peak memory 219096 kb
Host smart-9f1be349-2d00-4704-99d5-890a03f5f52d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263412297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.2263412297
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.3640311956
Short name T971
Test name
Test status
Simulation time 14608212 ps
CPU time 0.72 seconds
Started Mar 24 01:14:02 PM PDT 24
Finished Mar 24 01:14:03 PM PDT 24
Peak memory 205732 kb
Host smart-53ac27a0-d1c6-4244-b34c-a34d079041c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640311956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
3640311956
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.54328916
Short name T357
Test name
Test status
Simulation time 5160745876 ps
CPU time 4.22 seconds
Started Mar 24 01:14:02 PM PDT 24
Finished Mar 24 01:14:06 PM PDT 24
Peak memory 219288 kb
Host smart-28479319-a514-45f4-8899-fc369429fe6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54328916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.54328916
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.417959257
Short name T547
Test name
Test status
Simulation time 101092650 ps
CPU time 0.72 seconds
Started Mar 24 01:14:00 PM PDT 24
Finished Mar 24 01:14:01 PM PDT 24
Peak memory 205780 kb
Host smart-c6a5ce61-bf9c-4948-a6cb-dbd62d8212d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417959257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.417959257
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.3314049447
Short name T205
Test name
Test status
Simulation time 44490459063 ps
CPU time 159.5 seconds
Started Mar 24 01:14:02 PM PDT 24
Finished Mar 24 01:16:42 PM PDT 24
Peak memory 249568 kb
Host smart-6d80efa8-bd7a-4a8f-91fa-9b626fe8f355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314049447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.3314049447
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.1061711129
Short name T348
Test name
Test status
Simulation time 12862455137 ps
CPU time 122.94 seconds
Started Mar 24 01:14:01 PM PDT 24
Finished Mar 24 01:16:04 PM PDT 24
Peak memory 249520 kb
Host smart-39ac81b7-7034-4a78-a8db-c9c1a86ac914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061711129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.1061711129
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.3159111668
Short name T957
Test name
Test status
Simulation time 4756390823 ps
CPU time 18.83 seconds
Started Mar 24 01:14:01 PM PDT 24
Finished Mar 24 01:14:20 PM PDT 24
Peak memory 241272 kb
Host smart-65029ba7-5113-4d9f-aa3e-de57030d656a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159111668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.3159111668
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.2725977718
Short name T405
Test name
Test status
Simulation time 5866137061 ps
CPU time 6.53 seconds
Started Mar 24 01:14:01 PM PDT 24
Finished Mar 24 01:14:08 PM PDT 24
Peak memory 234052 kb
Host smart-dfe28234-2621-43e8-bc85-7573ec5604e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725977718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.2725977718
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.4243488502
Short name T877
Test name
Test status
Simulation time 28726277195 ps
CPU time 39.41 seconds
Started Mar 24 01:14:01 PM PDT 24
Finished Mar 24 01:14:41 PM PDT 24
Peak memory 235548 kb
Host smart-af78bae5-dd5e-4e1f-ba10-6baf880b10ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243488502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.4243488502
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.4211181783
Short name T728
Test name
Test status
Simulation time 29547266155 ps
CPU time 12.18 seconds
Started Mar 24 01:13:59 PM PDT 24
Finished Mar 24 01:14:12 PM PDT 24
Peak memory 251240 kb
Host smart-6a89825c-97cd-43d7-a82c-08faed345321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211181783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.4211181783
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.422396429
Short name T975
Test name
Test status
Simulation time 2626701982 ps
CPU time 6.37 seconds
Started Mar 24 01:13:58 PM PDT 24
Finished Mar 24 01:14:09 PM PDT 24
Peak memory 218100 kb
Host smart-4081a2e4-34e4-416e-9e98-f22b21fd2d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422396429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.422396429
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.4038891403
Short name T264
Test name
Test status
Simulation time 563624872 ps
CPU time 3.86 seconds
Started Mar 24 01:14:20 PM PDT 24
Finished Mar 24 01:14:25 PM PDT 24
Peak memory 223168 kb
Host smart-7e9fe112-7071-4e2e-a88e-ef55af2ef702
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4038891403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.4038891403
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.1621822496
Short name T133
Test name
Test status
Simulation time 128300538 ps
CPU time 1.16 seconds
Started Mar 24 01:14:01 PM PDT 24
Finished Mar 24 01:14:03 PM PDT 24
Peak memory 207504 kb
Host smart-a7dd929f-9de4-4569-b4bb-df04680e245b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621822496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.1621822496
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.3544004899
Short name T277
Test name
Test status
Simulation time 8860775244 ps
CPU time 24.19 seconds
Started Mar 24 01:13:55 PM PDT 24
Finished Mar 24 01:14:19 PM PDT 24
Peak memory 216660 kb
Host smart-ae18357a-cff4-4565-8eaf-6f274ce3e294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544004899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.3544004899
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.2711065613
Short name T259
Test name
Test status
Simulation time 10403193530 ps
CPU time 16.18 seconds
Started Mar 24 01:13:57 PM PDT 24
Finished Mar 24 01:14:14 PM PDT 24
Peak memory 216668 kb
Host smart-a5690ee9-3578-4910-af25-011ea7aa5f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711065613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.2711065613
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.2697035061
Short name T962
Test name
Test status
Simulation time 203299384 ps
CPU time 1.89 seconds
Started Mar 24 01:13:56 PM PDT 24
Finished Mar 24 01:13:59 PM PDT 24
Peak memory 216556 kb
Host smart-447fac6a-b439-4c49-bebc-b9af1fb0f433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697035061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.2697035061
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.761446266
Short name T16
Test name
Test status
Simulation time 120746716 ps
CPU time 0.8 seconds
Started Mar 24 01:13:54 PM PDT 24
Finished Mar 24 01:13:56 PM PDT 24
Peak memory 206012 kb
Host smart-7215dc01-cd0e-418e-87c2-e3fbaf4740cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761446266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.761446266
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.1350529261
Short name T781
Test name
Test status
Simulation time 13047878862 ps
CPU time 7.08 seconds
Started Mar 24 01:14:02 PM PDT 24
Finished Mar 24 01:14:09 PM PDT 24
Peak memory 234004 kb
Host smart-276e7d2f-c583-455b-917e-3ee13bac603c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350529261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.1350529261
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.2748745010
Short name T591
Test name
Test status
Simulation time 13506359 ps
CPU time 0.75 seconds
Started Mar 24 01:14:08 PM PDT 24
Finished Mar 24 01:14:09 PM PDT 24
Peak memory 206044 kb
Host smart-475e3cdc-1b26-4f7b-b880-be1aa2ef6239
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748745010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
2748745010
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.3278240797
Short name T736
Test name
Test status
Simulation time 87199546 ps
CPU time 2.94 seconds
Started Mar 24 01:14:04 PM PDT 24
Finished Mar 24 01:14:07 PM PDT 24
Peak memory 234080 kb
Host smart-2cb933d6-ff98-4ee8-b8d8-bad0fab2382a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278240797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.3278240797
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.4034302945
Short name T872
Test name
Test status
Simulation time 80977576 ps
CPU time 0.8 seconds
Started Mar 24 01:14:02 PM PDT 24
Finished Mar 24 01:14:03 PM PDT 24
Peak memory 206772 kb
Host smart-7fefe863-2646-46c5-b835-cb0e777113d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034302945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.4034302945
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.137233382
Short name T376
Test name
Test status
Simulation time 8134449590 ps
CPU time 23.46 seconds
Started Mar 24 01:14:03 PM PDT 24
Finished Mar 24 01:14:32 PM PDT 24
Peak memory 241292 kb
Host smart-235d7a01-973d-4e3b-b1d8-9750ecc3960a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137233382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.137233382
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.3448674850
Short name T381
Test name
Test status
Simulation time 94087965343 ps
CPU time 306.54 seconds
Started Mar 24 01:14:03 PM PDT 24
Finished Mar 24 01:19:10 PM PDT 24
Peak memory 257400 kb
Host smart-04b15867-64e4-4093-845d-f816e30f1da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448674850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.3448674850
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.964092982
Short name T234
Test name
Test status
Simulation time 8741522572 ps
CPU time 133.54 seconds
Started Mar 24 01:14:07 PM PDT 24
Finished Mar 24 01:16:20 PM PDT 24
Peak memory 265708 kb
Host smart-34346785-aafc-4ed7-8dc3-a79270429a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964092982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idle
.964092982
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.1104086553
Short name T569
Test name
Test status
Simulation time 8488366458 ps
CPU time 40.11 seconds
Started Mar 24 01:14:01 PM PDT 24
Finished Mar 24 01:14:42 PM PDT 24
Peak memory 247840 kb
Host smart-1b58aa3c-da8d-47da-9978-a9398d065f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104086553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.1104086553
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.557923177
Short name T879
Test name
Test status
Simulation time 942585620 ps
CPU time 4.91 seconds
Started Mar 24 01:14:01 PM PDT 24
Finished Mar 24 01:14:06 PM PDT 24
Peak memory 218000 kb
Host smart-abe7af5e-619c-41d8-b334-56f8266a97d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557923177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.557923177
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.778401119
Short name T913
Test name
Test status
Simulation time 31249814683 ps
CPU time 35.41 seconds
Started Mar 24 01:14:01 PM PDT 24
Finished Mar 24 01:14:36 PM PDT 24
Peak memory 251332 kb
Host smart-0276786f-8fbb-47bb-9975-65123c90116c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778401119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.778401119
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.2624008265
Short name T752
Test name
Test status
Simulation time 11358555545 ps
CPU time 10.34 seconds
Started Mar 24 01:14:01 PM PDT 24
Finished Mar 24 01:14:11 PM PDT 24
Peak memory 235048 kb
Host smart-ee6aa515-1f08-4e1e-a77f-d58739fa7b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624008265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.2624008265
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.3207743904
Short name T623
Test name
Test status
Simulation time 2859055676 ps
CPU time 9.78 seconds
Started Mar 24 01:13:59 PM PDT 24
Finished Mar 24 01:14:10 PM PDT 24
Peak memory 224920 kb
Host smart-580995b5-26b6-4544-a333-a43611a5a933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207743904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.3207743904
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.30383942
Short name T314
Test name
Test status
Simulation time 151143544 ps
CPU time 3.79 seconds
Started Mar 24 01:14:05 PM PDT 24
Finished Mar 24 01:14:09 PM PDT 24
Peak memory 223272 kb
Host smart-b1782835-ff5c-447d-8048-c3d5700cc062
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=30383942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_direc
t.30383942
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.189017353
Short name T350
Test name
Test status
Simulation time 11884328445 ps
CPU time 33.17 seconds
Started Mar 24 01:14:02 PM PDT 24
Finished Mar 24 01:14:35 PM PDT 24
Peak memory 222128 kb
Host smart-db6dcdb9-5bf3-4edb-8ea2-13da85d78919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189017353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.189017353
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.3699638727
Short name T260
Test name
Test status
Simulation time 51389996873 ps
CPU time 33.92 seconds
Started Mar 24 01:14:03 PM PDT 24
Finished Mar 24 01:14:37 PM PDT 24
Peak memory 216700 kb
Host smart-66510147-8c19-4ad9-92f9-d230e2e44bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699638727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.3699638727
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.1364634082
Short name T976
Test name
Test status
Simulation time 18309605 ps
CPU time 0.95 seconds
Started Mar 24 01:14:02 PM PDT 24
Finished Mar 24 01:14:03 PM PDT 24
Peak memory 207280 kb
Host smart-fd0a1692-69d0-4267-9389-e4b6ddcdeacb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364634082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.1364634082
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.333276881
Short name T507
Test name
Test status
Simulation time 44077803 ps
CPU time 0.81 seconds
Started Mar 24 01:13:59 PM PDT 24
Finished Mar 24 01:14:01 PM PDT 24
Peak memory 205988 kb
Host smart-86709cb7-3163-4b66-8a48-1d39fe9fa7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333276881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.333276881
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.943550075
Short name T930
Test name
Test status
Simulation time 4696849201 ps
CPU time 6.42 seconds
Started Mar 24 01:14:00 PM PDT 24
Finished Mar 24 01:14:07 PM PDT 24
Peak memory 224872 kb
Host smart-16784845-6340-481d-8bf4-89bffbdc193d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943550075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.943550075
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.3361671283
Short name T254
Test name
Test status
Simulation time 89163375 ps
CPU time 0.73 seconds
Started Mar 24 01:14:13 PM PDT 24
Finished Mar 24 01:14:14 PM PDT 24
Peak memory 205164 kb
Host smart-977f39c6-3698-4c98-ad30-8d5dcf71e555
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361671283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
3361671283
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.1835019725
Short name T534
Test name
Test status
Simulation time 740987590 ps
CPU time 3.43 seconds
Started Mar 24 01:14:09 PM PDT 24
Finished Mar 24 01:14:13 PM PDT 24
Peak memory 218268 kb
Host smart-61bcf50a-6f7c-4d77-9087-a6591bd63618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835019725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.1835019725
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.3773273127
Short name T506
Test name
Test status
Simulation time 60052923 ps
CPU time 0.84 seconds
Started Mar 24 01:14:08 PM PDT 24
Finished Mar 24 01:14:09 PM PDT 24
Peak memory 205776 kb
Host smart-503578ea-b6a6-4c49-9a21-8d4a60b421f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773273127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.3773273127
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.1696198832
Short name T833
Test name
Test status
Simulation time 48159289912 ps
CPU time 67.71 seconds
Started Mar 24 01:14:20 PM PDT 24
Finished Mar 24 01:15:29 PM PDT 24
Peak memory 241300 kb
Host smart-563578e4-5d1f-4499-8101-a3b058fa23c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696198832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.1696198832
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.1082701308
Short name T500
Test name
Test status
Simulation time 15249637919 ps
CPU time 87.79 seconds
Started Mar 24 01:14:06 PM PDT 24
Finished Mar 24 01:15:34 PM PDT 24
Peak memory 250776 kb
Host smart-11d9e2c0-a029-4f17-9a74-bc0356585a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082701308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.1082701308
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.676907272
Short name T31
Test name
Test status
Simulation time 13007130679 ps
CPU time 147.47 seconds
Started Mar 24 01:14:25 PM PDT 24
Finished Mar 24 01:16:53 PM PDT 24
Peak memory 265296 kb
Host smart-debba335-78d5-4934-b369-b76e3d71b00f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676907272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idle
.676907272
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.2757634452
Short name T571
Test name
Test status
Simulation time 2469738740 ps
CPU time 11.46 seconds
Started Mar 24 01:14:19 PM PDT 24
Finished Mar 24 01:14:30 PM PDT 24
Peak memory 241044 kb
Host smart-6c557431-0ad0-42bb-9b09-268d1feac445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757634452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.2757634452
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.3632255398
Short name T179
Test name
Test status
Simulation time 1821038017 ps
CPU time 3.24 seconds
Started Mar 24 01:14:10 PM PDT 24
Finished Mar 24 01:14:14 PM PDT 24
Peak memory 216964 kb
Host smart-c07fe79c-595d-490a-9e6a-96f8382e17ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632255398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.3632255398
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.437729174
Short name T559
Test name
Test status
Simulation time 10826608895 ps
CPU time 17.39 seconds
Started Mar 24 01:14:19 PM PDT 24
Finished Mar 24 01:14:36 PM PDT 24
Peak memory 235420 kb
Host smart-d40526ba-8b6a-450f-9bde-dc7ddafda64a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437729174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.437729174
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.2314591075
Short name T934
Test name
Test status
Simulation time 294826724 ps
CPU time 4.34 seconds
Started Mar 24 01:14:28 PM PDT 24
Finished Mar 24 01:14:32 PM PDT 24
Peak memory 224760 kb
Host smart-a9552c2a-7d02-478e-823e-ffd25bee2cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314591075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.2314591075
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.166112505
Short name T770
Test name
Test status
Simulation time 29615214371 ps
CPU time 22.44 seconds
Started Mar 24 01:14:17 PM PDT 24
Finished Mar 24 01:14:40 PM PDT 24
Peak memory 233632 kb
Host smart-1728ede2-2f12-4b1e-b9f5-fa679c534bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166112505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.166112505
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.1400860616
Short name T585
Test name
Test status
Simulation time 152497743 ps
CPU time 3.16 seconds
Started Mar 24 01:14:19 PM PDT 24
Finished Mar 24 01:14:23 PM PDT 24
Peak memory 219564 kb
Host smart-a0de1622-60a4-456a-9768-39a25925a642
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1400860616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.1400860616
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.2646671553
Short name T128
Test name
Test status
Simulation time 356209287452 ps
CPU time 363.18 seconds
Started Mar 24 01:14:21 PM PDT 24
Finished Mar 24 01:20:25 PM PDT 24
Peak memory 269564 kb
Host smart-9d26c698-0f46-4a77-8be1-54f303370347
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646671553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.2646671553
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.678246346
Short name T806
Test name
Test status
Simulation time 1910646542 ps
CPU time 10.59 seconds
Started Mar 24 01:14:07 PM PDT 24
Finished Mar 24 01:14:18 PM PDT 24
Peak memory 216496 kb
Host smart-30615722-338d-45c6-9172-de844496ff60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678246346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.678246346
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.249191436
Short name T335
Test name
Test status
Simulation time 7295466148 ps
CPU time 3.95 seconds
Started Mar 24 01:14:09 PM PDT 24
Finished Mar 24 01:14:13 PM PDT 24
Peak memory 216452 kb
Host smart-6b7f956f-6107-4b09-bcce-03182c350045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249191436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.249191436
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.4276726889
Short name T477
Test name
Test status
Simulation time 67320737 ps
CPU time 1.61 seconds
Started Mar 24 01:14:09 PM PDT 24
Finished Mar 24 01:14:11 PM PDT 24
Peak memory 216628 kb
Host smart-ba7397bc-b49f-45b9-8c5d-389157bc6251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276726889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.4276726889
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.1674047770
Short name T497
Test name
Test status
Simulation time 151284387 ps
CPU time 1.16 seconds
Started Mar 24 01:14:21 PM PDT 24
Finished Mar 24 01:14:23 PM PDT 24
Peak memory 207072 kb
Host smart-2d31c08f-312b-40e7-9a1e-cb50bb82be89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674047770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.1674047770
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.2756788567
Short name T665
Test name
Test status
Simulation time 16891815154 ps
CPU time 15.51 seconds
Started Mar 24 01:14:09 PM PDT 24
Finished Mar 24 01:14:25 PM PDT 24
Peak memory 240428 kb
Host smart-0857e1b9-14f0-4b3a-9b09-9f540ba7c406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756788567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.2756788567
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.276384746
Short name T548
Test name
Test status
Simulation time 15314662 ps
CPU time 0.75 seconds
Started Mar 24 01:14:21 PM PDT 24
Finished Mar 24 01:14:22 PM PDT 24
Peak memory 205176 kb
Host smart-c6ab9766-3c6b-4f0a-a5f4-a2f5dcd16368
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276384746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.276384746
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.2663891219
Short name T517
Test name
Test status
Simulation time 719448675 ps
CPU time 2.65 seconds
Started Mar 24 01:14:21 PM PDT 24
Finished Mar 24 01:14:24 PM PDT 24
Peak memory 219116 kb
Host smart-7c456186-011c-4cb6-9d20-ab4b9a55fa99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663891219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.2663891219
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.3399038058
Short name T682
Test name
Test status
Simulation time 15576920 ps
CPU time 0.79 seconds
Started Mar 24 01:14:27 PM PDT 24
Finished Mar 24 01:14:28 PM PDT 24
Peak memory 207392 kb
Host smart-bb5a0ce5-a8a5-4ff4-8bc8-e45de732b645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399038058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.3399038058
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.414068279
Short name T580
Test name
Test status
Simulation time 16322799110 ps
CPU time 56.5 seconds
Started Mar 24 01:14:33 PM PDT 24
Finished Mar 24 01:15:30 PM PDT 24
Peak memory 249484 kb
Host smart-c92c9567-2c8b-4c7a-93bf-f71e83943bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414068279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.414068279
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.3420004913
Short name T824
Test name
Test status
Simulation time 79508126538 ps
CPU time 281.61 seconds
Started Mar 24 01:14:27 PM PDT 24
Finished Mar 24 01:19:10 PM PDT 24
Peak memory 256228 kb
Host smart-0c1ece8b-ecc4-4135-8e2a-035dc4dbab60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420004913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.3420004913
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.2959301558
Short name T410
Test name
Test status
Simulation time 7183671033 ps
CPU time 35.01 seconds
Started Mar 24 01:14:30 PM PDT 24
Finished Mar 24 01:15:06 PM PDT 24
Peak memory 249484 kb
Host smart-f9a4ece9-2482-4727-a6bd-bb48ca2b6a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959301558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.2959301558
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.2593286927
Short name T632
Test name
Test status
Simulation time 2231932626 ps
CPU time 6.12 seconds
Started Mar 24 01:14:10 PM PDT 24
Finished Mar 24 01:14:16 PM PDT 24
Peak memory 219180 kb
Host smart-f34ee92f-0555-4083-9302-ffa1036e1516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593286927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.2593286927
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.1012588105
Short name T630
Test name
Test status
Simulation time 369365968 ps
CPU time 5.29 seconds
Started Mar 24 01:14:20 PM PDT 24
Finished Mar 24 01:14:26 PM PDT 24
Peak memory 224712 kb
Host smart-6794f94e-fba3-47f6-8f6d-b1cc99a7c843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012588105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.1012588105
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.2132063720
Short name T793
Test name
Test status
Simulation time 3469082394 ps
CPU time 7.34 seconds
Started Mar 24 01:14:07 PM PDT 24
Finished Mar 24 01:14:14 PM PDT 24
Peak memory 233120 kb
Host smart-1ef19ce6-87ca-45a1-a8e2-99d906f0478d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132063720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.2132063720
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.2851403140
Short name T466
Test name
Test status
Simulation time 2739548240 ps
CPU time 11.33 seconds
Started Mar 24 01:14:10 PM PDT 24
Finished Mar 24 01:14:21 PM PDT 24
Peak memory 218388 kb
Host smart-3381e657-22dc-43ed-bbef-832506b9ed3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851403140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.2851403140
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.2784271182
Short name T840
Test name
Test status
Simulation time 104995626 ps
CPU time 3.12 seconds
Started Mar 24 01:14:14 PM PDT 24
Finished Mar 24 01:14:17 PM PDT 24
Peak memory 219444 kb
Host smart-690bc69e-274a-4818-973e-4ee7035c4666
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2784271182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.2784271182
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.2439865904
Short name T362
Test name
Test status
Simulation time 25141487145 ps
CPU time 113.34 seconds
Started Mar 24 01:14:13 PM PDT 24
Finished Mar 24 01:16:06 PM PDT 24
Peak memory 266320 kb
Host smart-db0fd579-f26e-4376-ba23-530833b257fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439865904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.2439865904
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.2198911403
Short name T826
Test name
Test status
Simulation time 4975146750 ps
CPU time 31.72 seconds
Started Mar 24 01:14:10 PM PDT 24
Finished Mar 24 01:14:42 PM PDT 24
Peak memory 220068 kb
Host smart-406243cd-e868-4fb3-a1c3-e80528efe406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198911403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.2198911403
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.2204533585
Short name T611
Test name
Test status
Simulation time 6173547426 ps
CPU time 6.46 seconds
Started Mar 24 01:14:07 PM PDT 24
Finished Mar 24 01:14:13 PM PDT 24
Peak memory 216672 kb
Host smart-56c7f881-562a-4526-8cb7-6bb48e6bc4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204533585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.2204533585
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.1421986372
Short name T533
Test name
Test status
Simulation time 24884791 ps
CPU time 1.47 seconds
Started Mar 24 01:14:09 PM PDT 24
Finished Mar 24 01:14:11 PM PDT 24
Peak memory 216380 kb
Host smart-b7c2aac3-f507-44a4-abb8-58e11a59fdc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421986372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.1421986372
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.1480546481
Short name T416
Test name
Test status
Simulation time 68412575 ps
CPU time 0.77 seconds
Started Mar 24 01:14:18 PM PDT 24
Finished Mar 24 01:14:19 PM PDT 24
Peak memory 206048 kb
Host smart-3a447357-d6a6-466c-bed8-4afcccf3cc28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480546481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.1480546481
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.3359625522
Short name T677
Test name
Test status
Simulation time 1182881525 ps
CPU time 7.7 seconds
Started Mar 24 01:14:27 PM PDT 24
Finished Mar 24 01:14:36 PM PDT 24
Peak memory 241236 kb
Host smart-a98b3f61-715e-4296-a46a-22655d902f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359625522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.3359625522
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.124421482
Short name T876
Test name
Test status
Simulation time 158729121 ps
CPU time 0.7 seconds
Started Mar 24 01:14:12 PM PDT 24
Finished Mar 24 01:14:13 PM PDT 24
Peak memory 205744 kb
Host smart-8bfb2438-b86e-4320-ac2a-788b0a568cfa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124421482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.124421482
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.146839877
Short name T13
Test name
Test status
Simulation time 377690108 ps
CPU time 3.86 seconds
Started Mar 24 01:14:14 PM PDT 24
Finished Mar 24 01:14:18 PM PDT 24
Peak memory 234112 kb
Host smart-a7ba199f-4a76-4ecc-8156-4ce3577615a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146839877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.146839877
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.2209729194
Short name T447
Test name
Test status
Simulation time 36642098 ps
CPU time 0.75 seconds
Started Mar 24 01:14:22 PM PDT 24
Finished Mar 24 01:14:23 PM PDT 24
Peak memory 207096 kb
Host smart-eecd2a0c-d80d-43b1-9816-75ce09bc6b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209729194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.2209729194
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.906361451
Short name T875
Test name
Test status
Simulation time 17818227218 ps
CPU time 69.26 seconds
Started Mar 24 01:14:13 PM PDT 24
Finished Mar 24 01:15:23 PM PDT 24
Peak memory 268808 kb
Host smart-c1f93c5a-6812-4e17-887c-9f543e50a4ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906361451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.906361451
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.2426882284
Short name T960
Test name
Test status
Simulation time 3427234458 ps
CPU time 60.4 seconds
Started Mar 24 01:14:33 PM PDT 24
Finished Mar 24 01:15:34 PM PDT 24
Peak memory 240920 kb
Host smart-299ae90c-bee3-49d6-a08f-6bc5d9dca1f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426882284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.2426882284
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.84821791
Short name T708
Test name
Test status
Simulation time 85527688532 ps
CPU time 364.44 seconds
Started Mar 24 01:14:12 PM PDT 24
Finished Mar 24 01:20:17 PM PDT 24
Peak memory 274096 kb
Host smart-c451742c-5cf2-44b9-95cb-c624653fa5cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84821791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idle.84821791
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.2922109660
Short name T554
Test name
Test status
Simulation time 1721839617 ps
CPU time 13.77 seconds
Started Mar 24 01:14:14 PM PDT 24
Finished Mar 24 01:14:28 PM PDT 24
Peak memory 240044 kb
Host smart-7ee595e0-bec8-4003-8332-8dc626541840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922109660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.2922109660
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.1309799009
Short name T460
Test name
Test status
Simulation time 403501952 ps
CPU time 4.13 seconds
Started Mar 24 01:14:12 PM PDT 24
Finished Mar 24 01:14:16 PM PDT 24
Peak memory 219004 kb
Host smart-5ea5d7b7-e0ea-4d10-b7e0-7b2b6e9bdb4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309799009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.1309799009
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.1361928131
Short name T78
Test name
Test status
Simulation time 4456827188 ps
CPU time 15.39 seconds
Started Mar 24 01:14:12 PM PDT 24
Finished Mar 24 01:14:28 PM PDT 24
Peak memory 234680 kb
Host smart-dc58521d-2c7f-4307-8bf5-69a2d52c54f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361928131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.1361928131
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.1177111481
Short name T681
Test name
Test status
Simulation time 34067661141 ps
CPU time 23.28 seconds
Started Mar 24 01:14:15 PM PDT 24
Finished Mar 24 01:14:38 PM PDT 24
Peak memory 219364 kb
Host smart-0e7c8f64-3798-4a69-980e-38a4e0029072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177111481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.1177111481
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.1843871406
Short name T954
Test name
Test status
Simulation time 28158065371 ps
CPU time 18.74 seconds
Started Mar 24 01:14:11 PM PDT 24
Finished Mar 24 01:14:30 PM PDT 24
Peak memory 229708 kb
Host smart-fcfe3c8d-56f6-4ba2-b306-bae9cb47f412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843871406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.1843871406
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.1607815180
Short name T123
Test name
Test status
Simulation time 739724280 ps
CPU time 4.25 seconds
Started Mar 24 01:14:13 PM PDT 24
Finished Mar 24 01:14:17 PM PDT 24
Peak memory 219492 kb
Host smart-df53c238-36aa-4a06-a809-bb61344954c5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1607815180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.1607815180
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.788919811
Short name T129
Test name
Test status
Simulation time 8253053916 ps
CPU time 55.7 seconds
Started Mar 24 01:14:12 PM PDT 24
Finished Mar 24 01:15:08 PM PDT 24
Peak memory 249588 kb
Host smart-739a28d6-0ea4-4a7d-95e1-761f4dd72bab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788919811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stres
s_all.788919811
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.4160376059
Short name T537
Test name
Test status
Simulation time 10045858921 ps
CPU time 55.45 seconds
Started Mar 24 01:14:15 PM PDT 24
Finished Mar 24 01:15:10 PM PDT 24
Peak memory 216660 kb
Host smart-1f849246-2d04-4ad6-96d0-94cccef908e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160376059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.4160376059
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.1777539322
Short name T909
Test name
Test status
Simulation time 2687751677 ps
CPU time 13.78 seconds
Started Mar 24 01:14:12 PM PDT 24
Finished Mar 24 01:14:26 PM PDT 24
Peak memory 216648 kb
Host smart-023a3b26-b23a-459c-9fe8-0fc310c25773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777539322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.1777539322
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.4220218801
Short name T851
Test name
Test status
Simulation time 61543604 ps
CPU time 1.25 seconds
Started Mar 24 01:14:15 PM PDT 24
Finished Mar 24 01:14:16 PM PDT 24
Peak memory 208436 kb
Host smart-0acdbafe-e24e-409d-ac85-f200bcac370f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220218801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.4220218801
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.323580181
Short name T476
Test name
Test status
Simulation time 154575504 ps
CPU time 1.14 seconds
Started Mar 24 01:14:30 PM PDT 24
Finished Mar 24 01:14:32 PM PDT 24
Peak memory 206480 kb
Host smart-d7e12c28-6626-494f-9343-98b400d4ed28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323580181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.323580181
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.475969619
Short name T800
Test name
Test status
Simulation time 1653646605 ps
CPU time 6.04 seconds
Started Mar 24 01:14:11 PM PDT 24
Finished Mar 24 01:14:17 PM PDT 24
Peak memory 217876 kb
Host smart-dbed5233-bb97-4ddd-a4b4-e61befb6886b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475969619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.475969619
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.2607623784
Short name T670
Test name
Test status
Simulation time 33278581 ps
CPU time 0.72 seconds
Started Mar 24 01:14:28 PM PDT 24
Finished Mar 24 01:14:29 PM PDT 24
Peak memory 205076 kb
Host smart-b5740efc-57d8-4ac4-bffc-7365032c0568
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607623784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
2607623784
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.3728382807
Short name T923
Test name
Test status
Simulation time 70978320 ps
CPU time 2.44 seconds
Started Mar 24 01:14:32 PM PDT 24
Finished Mar 24 01:14:35 PM PDT 24
Peak memory 233592 kb
Host smart-e595312d-f195-4306-a561-6b6309b11152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728382807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.3728382807
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.2163591208
Short name T59
Test name
Test status
Simulation time 35072233 ps
CPU time 0.78 seconds
Started Mar 24 01:14:12 PM PDT 24
Finished Mar 24 01:14:13 PM PDT 24
Peak memory 205764 kb
Host smart-302edd82-e349-411c-a1af-f9128f8f4a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163591208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.2163591208
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.4045067618
Short name T425
Test name
Test status
Simulation time 4319110919 ps
CPU time 70.09 seconds
Started Mar 24 01:14:24 PM PDT 24
Finished Mar 24 01:15:34 PM PDT 24
Peak memory 257672 kb
Host smart-421dbf9f-059b-4c03-9fe7-59e083a04b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045067618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.4045067618
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.1272021037
Short name T5
Test name
Test status
Simulation time 11777973574 ps
CPU time 114.42 seconds
Started Mar 24 01:14:26 PM PDT 24
Finished Mar 24 01:16:20 PM PDT 24
Peak memory 259984 kb
Host smart-64da6a6b-1dbe-4422-9133-5be419cf986b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272021037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.1272021037
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.1473642471
Short name T9
Test name
Test status
Simulation time 1672345675 ps
CPU time 23.83 seconds
Started Mar 24 01:14:28 PM PDT 24
Finished Mar 24 01:14:52 PM PDT 24
Peak memory 250240 kb
Host smart-dd1e070c-7591-4550-afbf-d149b3159a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473642471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.1473642471
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.1234906032
Short name T583
Test name
Test status
Simulation time 33145438159 ps
CPU time 32.11 seconds
Started Mar 24 01:14:23 PM PDT 24
Finished Mar 24 01:14:55 PM PDT 24
Peak memory 244416 kb
Host smart-35991284-1e9b-44d6-9df7-809f86252942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234906032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.1234906032
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.3002429662
Short name T462
Test name
Test status
Simulation time 486244394 ps
CPU time 4.68 seconds
Started Mar 24 01:14:23 PM PDT 24
Finished Mar 24 01:14:28 PM PDT 24
Peak memory 238196 kb
Host smart-cdd69c72-078e-4cda-8145-d53fb0a5a401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002429662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.3002429662
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.523898754
Short name T288
Test name
Test status
Simulation time 11171241600 ps
CPU time 8.03 seconds
Started Mar 24 01:14:29 PM PDT 24
Finished Mar 24 01:14:37 PM PDT 24
Peak memory 233124 kb
Host smart-feaff9e2-5177-457d-815a-08f08586f98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523898754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.523898754
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.1883083241
Short name T358
Test name
Test status
Simulation time 2994390513 ps
CPU time 4.1 seconds
Started Mar 24 01:14:25 PM PDT 24
Finished Mar 24 01:14:29 PM PDT 24
Peak memory 217280 kb
Host smart-ac39dee6-aba9-48ef-97a0-a9fbd5b365aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883083241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.1883083241
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.181419358
Short name T490
Test name
Test status
Simulation time 71067518146 ps
CPU time 15.19 seconds
Started Mar 24 01:14:25 PM PDT 24
Finished Mar 24 01:14:41 PM PDT 24
Peak memory 230732 kb
Host smart-e83b1cc2-d870-485a-a358-e753c5b9bf0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181419358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.181419358
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.2205340881
Short name T586
Test name
Test status
Simulation time 735701749 ps
CPU time 4.06 seconds
Started Mar 24 01:14:32 PM PDT 24
Finished Mar 24 01:14:37 PM PDT 24
Peak memory 222600 kb
Host smart-992f4318-384d-4cde-8f25-7d7cbbe4bb30
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2205340881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.2205340881
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.122396216
Short name T217
Test name
Test status
Simulation time 11456808068 ps
CPU time 144.09 seconds
Started Mar 24 01:14:26 PM PDT 24
Finished Mar 24 01:16:51 PM PDT 24
Peak memory 252352 kb
Host smart-2dc34182-35b3-41c7-949d-428e0c58153f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122396216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stres
s_all.122396216
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.1344639596
Short name T566
Test name
Test status
Simulation time 5996101893 ps
CPU time 15.95 seconds
Started Mar 24 01:14:14 PM PDT 24
Finished Mar 24 01:14:30 PM PDT 24
Peak memory 216708 kb
Host smart-a8351a17-ab55-43ee-8c42-8f8ade04e9cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344639596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1344639596
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.2783164248
Short name T458
Test name
Test status
Simulation time 2818339852 ps
CPU time 8.66 seconds
Started Mar 24 01:14:14 PM PDT 24
Finished Mar 24 01:14:23 PM PDT 24
Peak memory 216728 kb
Host smart-e6289002-d1d8-4aa9-bad0-cd288fb2ce8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783164248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.2783164248
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.645152246
Short name T509
Test name
Test status
Simulation time 21147187 ps
CPU time 0.92 seconds
Started Mar 24 01:14:31 PM PDT 24
Finished Mar 24 01:14:33 PM PDT 24
Peak memory 206656 kb
Host smart-cee9af71-fae8-4f94-9cc7-cda3c1043df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645152246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.645152246
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.292182904
Short name T268
Test name
Test status
Simulation time 31927824 ps
CPU time 0.68 seconds
Started Mar 24 01:14:30 PM PDT 24
Finished Mar 24 01:14:31 PM PDT 24
Peak memory 206032 kb
Host smart-982cd2ad-5d87-43dc-9d08-6b775f4801f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292182904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.292182904
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.1211533093
Short name T668
Test name
Test status
Simulation time 18795404049 ps
CPU time 16.15 seconds
Started Mar 24 01:14:33 PM PDT 24
Finished Mar 24 01:14:50 PM PDT 24
Peak memory 219236 kb
Host smart-7b2d6602-a9a6-403f-ad97-6f2fc01485d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211533093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.1211533093
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.3580583077
Short name T388
Test name
Test status
Simulation time 13723741 ps
CPU time 0.74 seconds
Started Mar 24 01:12:37 PM PDT 24
Finished Mar 24 01:12:38 PM PDT 24
Peak memory 205740 kb
Host smart-b2dafa40-0ee5-4654-88db-5f5f702db47a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580583077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.3
580583077
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.2777571981
Short name T815
Test name
Test status
Simulation time 6250873045 ps
CPU time 7.4 seconds
Started Mar 24 01:12:56 PM PDT 24
Finished Mar 24 01:13:04 PM PDT 24
Peak memory 220184 kb
Host smart-cff6e248-6a02-4b0e-b0bf-bed5a8796ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777571981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.2777571981
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.3113072008
Short name T285
Test name
Test status
Simulation time 14191139 ps
CPU time 0.82 seconds
Started Mar 24 01:12:36 PM PDT 24
Finished Mar 24 01:12:37 PM PDT 24
Peak memory 206780 kb
Host smart-1400475e-4e05-457a-8f6e-46907803dd18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113072008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.3113072008
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.1024015595
Short name T139
Test name
Test status
Simulation time 101311899074 ps
CPU time 121.76 seconds
Started Mar 24 01:12:47 PM PDT 24
Finished Mar 24 01:14:50 PM PDT 24
Peak memory 250548 kb
Host smart-e899d171-4e12-44b3-ad27-3b737eed04b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024015595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.1024015595
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.3318916161
Short name T169
Test name
Test status
Simulation time 18805594609 ps
CPU time 209.89 seconds
Started Mar 24 01:12:50 PM PDT 24
Finished Mar 24 01:16:20 PM PDT 24
Peak memory 273948 kb
Host smart-f27109e1-b42b-4516-b297-5da3f78f8f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318916161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.3318916161
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.49541133
Short name T484
Test name
Test status
Simulation time 6595349925 ps
CPU time 38.63 seconds
Started Mar 24 01:12:50 PM PDT 24
Finished Mar 24 01:13:29 PM PDT 24
Peak memory 222760 kb
Host smart-e7cff87a-a7cf-48cb-9c67-9fed599b9dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49541133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.49541133
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.3616348295
Short name T279
Test name
Test status
Simulation time 1328241953 ps
CPU time 8.14 seconds
Started Mar 24 01:12:47 PM PDT 24
Finished Mar 24 01:12:55 PM PDT 24
Peak memory 244384 kb
Host smart-5fb9b40d-8590-4eda-8afa-21c2e87192fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616348295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.3616348295
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.3922834408
Short name T413
Test name
Test status
Simulation time 1525645258 ps
CPU time 3.21 seconds
Started Mar 24 01:12:56 PM PDT 24
Finished Mar 24 01:12:59 PM PDT 24
Peak memory 217228 kb
Host smart-1b7e237f-c9d1-4db4-bed0-f0deaf269e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922834408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.3922834408
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.1754556145
Short name T599
Test name
Test status
Simulation time 4557679005 ps
CPU time 20.25 seconds
Started Mar 24 01:12:47 PM PDT 24
Finished Mar 24 01:13:07 PM PDT 24
Peak memory 237204 kb
Host smart-29585ba8-ce63-47c6-9141-31526df18963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754556145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.1754556145
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.3807594106
Short name T232
Test name
Test status
Simulation time 7315310094 ps
CPU time 10.15 seconds
Started Mar 24 01:12:51 PM PDT 24
Finished Mar 24 01:13:02 PM PDT 24
Peak memory 234136 kb
Host smart-38d73ae3-5bab-4593-aea8-4d6113343c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807594106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.3807594106
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.829352178
Short name T185
Test name
Test status
Simulation time 14346862227 ps
CPU time 21.95 seconds
Started Mar 24 01:12:49 PM PDT 24
Finished Mar 24 01:13:11 PM PDT 24
Peak memory 235896 kb
Host smart-6268ed12-dca3-463a-b16d-dc0069180a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829352178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.829352178
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_ram_cfg.1432882639
Short name T342
Test name
Test status
Simulation time 18987573 ps
CPU time 0.76 seconds
Started Mar 24 01:12:51 PM PDT 24
Finished Mar 24 01:12:51 PM PDT 24
Peak memory 216508 kb
Host smart-dbe02e3d-01ff-483b-88e8-b88f132f05e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432882639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_ram_cfg.1432882639
Directory /workspace/4.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.370929541
Short name T122
Test name
Test status
Simulation time 3661053771 ps
CPU time 5.22 seconds
Started Mar 24 01:12:47 PM PDT 24
Finished Mar 24 01:12:52 PM PDT 24
Peak memory 221500 kb
Host smart-5047b51e-2222-44ea-88ae-5d1de3d6f00b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=370929541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_direc
t.370929541
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.4079560890
Short name T54
Test name
Test status
Simulation time 91311730 ps
CPU time 1.01 seconds
Started Mar 24 01:12:51 PM PDT 24
Finished Mar 24 01:12:53 PM PDT 24
Peak memory 235620 kb
Host smart-c377adfc-51ac-4d50-a710-e0c211180427
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079560890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.4079560890
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.3208658669
Short name T176
Test name
Test status
Simulation time 135543443386 ps
CPU time 365.8 seconds
Started Mar 24 01:12:52 PM PDT 24
Finished Mar 24 01:18:58 PM PDT 24
Peak memory 286360 kb
Host smart-27cd68ef-4db8-4adf-893b-1d4c8598a0fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208658669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.3208658669
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.129501568
Short name T795
Test name
Test status
Simulation time 3180553674 ps
CPU time 17.16 seconds
Started Mar 24 01:12:50 PM PDT 24
Finished Mar 24 01:13:07 PM PDT 24
Peak memory 216752 kb
Host smart-ba361ebd-d0b7-47b2-94f0-afdf9bda5ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129501568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.129501568
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.1776889892
Short name T480
Test name
Test status
Simulation time 2687655374 ps
CPU time 7.91 seconds
Started Mar 24 01:12:42 PM PDT 24
Finished Mar 24 01:12:50 PM PDT 24
Peak memory 216636 kb
Host smart-e818e6da-b95d-42ff-acfb-e67c1ef03695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776889892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.1776889892
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.3577090346
Short name T272
Test name
Test status
Simulation time 364124478 ps
CPU time 7.59 seconds
Started Mar 24 01:12:47 PM PDT 24
Finished Mar 24 01:12:55 PM PDT 24
Peak memory 216560 kb
Host smart-0ab6907f-1931-4503-b509-dbda2bb9f7bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577090346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.3577090346
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.2719993706
Short name T948
Test name
Test status
Simulation time 38417398 ps
CPU time 0.83 seconds
Started Mar 24 01:12:43 PM PDT 24
Finished Mar 24 01:12:44 PM PDT 24
Peak memory 206060 kb
Host smart-e8f7dd3e-8894-47b2-a50e-2f8f1433bdad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719993706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.2719993706
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.4197314053
Short name T540
Test name
Test status
Simulation time 14850083238 ps
CPU time 14.41 seconds
Started Mar 24 01:12:55 PM PDT 24
Finished Mar 24 01:13:10 PM PDT 24
Peak memory 241260 kb
Host smart-aef40c73-73af-49e9-b7db-32addd38215e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197314053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.4197314053
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.302524304
Short name T963
Test name
Test status
Simulation time 98498123 ps
CPU time 0.7 seconds
Started Mar 24 01:14:25 PM PDT 24
Finished Mar 24 01:14:26 PM PDT 24
Peak memory 205748 kb
Host smart-f93f4872-c4fd-4b5e-a088-c3196f9ac0cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302524304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.302524304
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.1608679453
Short name T811
Test name
Test status
Simulation time 1189666943 ps
CPU time 3.25 seconds
Started Mar 24 01:14:34 PM PDT 24
Finished Mar 24 01:14:38 PM PDT 24
Peak memory 220192 kb
Host smart-b1e10c9b-5c2e-411f-bde7-80367db24dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608679453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.1608679453
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.3121980914
Short name T294
Test name
Test status
Simulation time 35885811 ps
CPU time 0.82 seconds
Started Mar 24 01:14:21 PM PDT 24
Finished Mar 24 01:14:22 PM PDT 24
Peak memory 206828 kb
Host smart-54dd0952-74da-4b12-8780-415ee356e349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121980914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.3121980914
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.1474306711
Short name T233
Test name
Test status
Simulation time 288061280471 ps
CPU time 341.84 seconds
Started Mar 24 01:14:31 PM PDT 24
Finished Mar 24 01:20:13 PM PDT 24
Peak memory 265872 kb
Host smart-079a55d8-94bd-49a8-883e-3f70aaac082c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474306711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.1474306711
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.4243249519
Short name T673
Test name
Test status
Simulation time 52270922533 ps
CPU time 74.64 seconds
Started Mar 24 01:14:18 PM PDT 24
Finished Mar 24 01:15:32 PM PDT 24
Peak memory 236288 kb
Host smart-33e02fa4-1390-463c-ba07-9b4a09b681f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243249519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.4243249519
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.2677073474
Short name T431
Test name
Test status
Simulation time 1079208865 ps
CPU time 15.5 seconds
Started Mar 24 01:14:21 PM PDT 24
Finished Mar 24 01:14:37 PM PDT 24
Peak memory 249768 kb
Host smart-a5f08816-b86b-416a-9b04-17a6bac4d215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677073474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2677073474
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.3825423149
Short name T541
Test name
Test status
Simulation time 2467676590 ps
CPU time 5.54 seconds
Started Mar 24 01:14:25 PM PDT 24
Finished Mar 24 01:14:31 PM PDT 24
Peak memory 217980 kb
Host smart-b2de66c0-a02e-4894-9ec7-dda83a173d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825423149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.3825423149
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.4193845468
Short name T150
Test name
Test status
Simulation time 2982894387 ps
CPU time 14.15 seconds
Started Mar 24 01:14:32 PM PDT 24
Finished Mar 24 01:14:47 PM PDT 24
Peak memory 220220 kb
Host smart-2cccceb7-8dac-466e-8562-a6046f9f9e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193845468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.4193845468
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.2684470640
Short name T421
Test name
Test status
Simulation time 13396463873 ps
CPU time 43.26 seconds
Started Mar 24 01:14:29 PM PDT 24
Finished Mar 24 01:15:13 PM PDT 24
Peak memory 251292 kb
Host smart-17b7c05a-10af-4362-9134-2c8c34b90d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684470640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.2684470640
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.3995640852
Short name T539
Test name
Test status
Simulation time 11252399072 ps
CPU time 9.9 seconds
Started Mar 24 01:14:22 PM PDT 24
Finished Mar 24 01:14:32 PM PDT 24
Peak memory 224828 kb
Host smart-08db6904-6a1c-40c2-be3d-e9062e335a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995640852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.3995640852
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.2892578663
Short name T742
Test name
Test status
Simulation time 9808593156 ps
CPU time 5.26 seconds
Started Mar 24 01:14:25 PM PDT 24
Finished Mar 24 01:14:31 PM PDT 24
Peak memory 220460 kb
Host smart-a9037451-0f07-456d-a19c-419ae7381c4f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2892578663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.2892578663
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.1100933310
Short name T821
Test name
Test status
Simulation time 12013819627 ps
CPU time 54.19 seconds
Started Mar 24 01:14:29 PM PDT 24
Finished Mar 24 01:15:23 PM PDT 24
Peak memory 216692 kb
Host smart-5910cb64-05e8-4c46-80bd-d3a7c049fdbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100933310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.1100933310
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.1619745608
Short name T444
Test name
Test status
Simulation time 2741087183 ps
CPU time 7.47 seconds
Started Mar 24 01:14:22 PM PDT 24
Finished Mar 24 01:14:29 PM PDT 24
Peak memory 216676 kb
Host smart-565d6cde-7450-4445-a17e-ae1d83f6f85f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619745608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.1619745608
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.3026937441
Short name T352
Test name
Test status
Simulation time 450634837 ps
CPU time 4.69 seconds
Started Mar 24 01:14:18 PM PDT 24
Finished Mar 24 01:14:23 PM PDT 24
Peak memory 216492 kb
Host smart-cf57fcf2-1494-4458-9a46-6a721e2b2128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026937441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.3026937441
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.3785426639
Short name T604
Test name
Test status
Simulation time 85219610 ps
CPU time 0.77 seconds
Started Mar 24 01:14:29 PM PDT 24
Finished Mar 24 01:14:30 PM PDT 24
Peak memory 206068 kb
Host smart-707c12b4-fbc5-47c1-a9d1-72b7b3e1c932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785426639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.3785426639
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.1428339636
Short name T600
Test name
Test status
Simulation time 3551993179 ps
CPU time 7.35 seconds
Started Mar 24 01:14:26 PM PDT 24
Finished Mar 24 01:14:33 PM PDT 24
Peak memory 234196 kb
Host smart-eb08232a-2ff3-4c39-b430-62ababe05374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428339636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.1428339636
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.928794878
Short name T612
Test name
Test status
Simulation time 31595942 ps
CPU time 0.71 seconds
Started Mar 24 01:14:29 PM PDT 24
Finished Mar 24 01:14:30 PM PDT 24
Peak memory 205748 kb
Host smart-4183f9d3-8d92-4c39-ac33-3d92b3032a13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928794878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.928794878
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.970002496
Short name T535
Test name
Test status
Simulation time 108537796 ps
CPU time 2.86 seconds
Started Mar 24 01:14:30 PM PDT 24
Finished Mar 24 01:14:34 PM PDT 24
Peak memory 234660 kb
Host smart-b2fba479-46ed-4cb5-8420-73beec5e8c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970002496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.970002496
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.3271561171
Short name T360
Test name
Test status
Simulation time 30835630 ps
CPU time 0.78 seconds
Started Mar 24 01:14:31 PM PDT 24
Finished Mar 24 01:14:32 PM PDT 24
Peak memory 205784 kb
Host smart-0be57fc0-8aef-469e-a3fa-f4b476372c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271561171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.3271561171
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.37329633
Short name T383
Test name
Test status
Simulation time 6443463917 ps
CPU time 47.81 seconds
Started Mar 24 01:14:38 PM PDT 24
Finished Mar 24 01:15:26 PM PDT 24
Peak memory 249468 kb
Host smart-ed775af7-54d2-444a-8bb0-00447b32f945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37329633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.37329633
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.1225234790
Short name T356
Test name
Test status
Simulation time 15940562860 ps
CPU time 73.06 seconds
Started Mar 24 01:14:34 PM PDT 24
Finished Mar 24 01:15:48 PM PDT 24
Peak memory 241304 kb
Host smart-856b978f-56f4-4dcb-90ea-8fcf0de0a6fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225234790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.1225234790
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.2896444033
Short name T499
Test name
Test status
Simulation time 97494408678 ps
CPU time 196.11 seconds
Started Mar 24 01:14:37 PM PDT 24
Finished Mar 24 01:17:54 PM PDT 24
Peak memory 260344 kb
Host smart-ffabd55d-97a4-4f30-90d9-834f86ccd282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896444033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.2896444033
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.840128110
Short name T844
Test name
Test status
Simulation time 762129146 ps
CPU time 19.31 seconds
Started Mar 24 01:14:37 PM PDT 24
Finished Mar 24 01:14:57 PM PDT 24
Peak memory 241144 kb
Host smart-e3cb273e-5464-497c-b1d7-feab39f322f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840128110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.840128110
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.4124720500
Short name T779
Test name
Test status
Simulation time 1194439314 ps
CPU time 3.42 seconds
Started Mar 24 01:14:26 PM PDT 24
Finished Mar 24 01:14:30 PM PDT 24
Peak memory 233512 kb
Host smart-6eacd974-30e8-4248-a685-7c2c63251c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124720500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.4124720500
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.2265105234
Short name T694
Test name
Test status
Simulation time 2823113955 ps
CPU time 10.53 seconds
Started Mar 24 01:14:32 PM PDT 24
Finished Mar 24 01:14:43 PM PDT 24
Peak memory 234368 kb
Host smart-c9db2361-b964-4ea5-a0ed-5b87091dd628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265105234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.2265105234
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.3938771278
Short name T222
Test name
Test status
Simulation time 14850910975 ps
CPU time 8.08 seconds
Started Mar 24 01:14:24 PM PDT 24
Finished Mar 24 01:14:32 PM PDT 24
Peak memory 219044 kb
Host smart-3a597216-61c8-4f81-ab40-5363b325ab8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938771278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.3938771278
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.2272117164
Short name T337
Test name
Test status
Simulation time 232723413 ps
CPU time 4.4 seconds
Started Mar 24 01:14:27 PM PDT 24
Finished Mar 24 01:14:32 PM PDT 24
Peak memory 233340 kb
Host smart-4516be79-1cc9-4feb-a1d6-cba7154eae63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272117164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.2272117164
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.4057441842
Short name T398
Test name
Test status
Simulation time 2192753719 ps
CPU time 5.93 seconds
Started Mar 24 01:14:34 PM PDT 24
Finished Mar 24 01:14:40 PM PDT 24
Peak memory 222152 kb
Host smart-e5d1d00e-99dc-4e1b-8561-4d2180e574f0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4057441842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.4057441842
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.3302954245
Short name T131
Test name
Test status
Simulation time 131706126101 ps
CPU time 199.89 seconds
Started Mar 24 01:14:31 PM PDT 24
Finished Mar 24 01:17:51 PM PDT 24
Peak memory 249464 kb
Host smart-787061f0-0b0d-4ac1-aa85-ad5a78a0be25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302954245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.3302954245
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.1387503350
Short name T247
Test name
Test status
Simulation time 7638136314 ps
CPU time 37.49 seconds
Started Mar 24 01:14:25 PM PDT 24
Finished Mar 24 01:15:03 PM PDT 24
Peak memory 216752 kb
Host smart-e360790c-54d0-40d0-84a6-794d800936a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387503350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.1387503350
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.3698505867
Short name T513
Test name
Test status
Simulation time 914538368 ps
CPU time 5.24 seconds
Started Mar 24 01:14:19 PM PDT 24
Finished Mar 24 01:14:24 PM PDT 24
Peak memory 216620 kb
Host smart-a624f72d-bdb2-406e-ad6e-090bb19ebc72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698505867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.3698505867
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.929950922
Short name T424
Test name
Test status
Simulation time 225903399 ps
CPU time 1.84 seconds
Started Mar 24 01:14:19 PM PDT 24
Finished Mar 24 01:14:21 PM PDT 24
Peak memory 216720 kb
Host smart-9542ff39-b50c-4a85-8884-262bc3100d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929950922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.929950922
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.1697382482
Short name T329
Test name
Test status
Simulation time 111148857 ps
CPU time 1.11 seconds
Started Mar 24 01:14:26 PM PDT 24
Finished Mar 24 01:14:27 PM PDT 24
Peak memory 207072 kb
Host smart-e1938689-c6c0-44e2-bb5d-67267271b103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697382482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.1697382482
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.3602566788
Short name T449
Test name
Test status
Simulation time 377897107 ps
CPU time 3.96 seconds
Started Mar 24 01:14:34 PM PDT 24
Finished Mar 24 01:14:38 PM PDT 24
Peak memory 219308 kb
Host smart-fb59d132-1114-4d4e-811a-7a5f8e9e9e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602566788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.3602566788
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.3378278506
Short name T446
Test name
Test status
Simulation time 15335007 ps
CPU time 0.74 seconds
Started Mar 24 01:14:25 PM PDT 24
Finished Mar 24 01:14:26 PM PDT 24
Peak memory 205756 kb
Host smart-b6c2c483-3831-4658-9806-5803240639f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378278506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
3378278506
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.790720737
Short name T45
Test name
Test status
Simulation time 1608251082 ps
CPU time 3.99 seconds
Started Mar 24 01:14:34 PM PDT 24
Finished Mar 24 01:14:38 PM PDT 24
Peak memory 238016 kb
Host smart-d87afdfb-002c-4d4f-b2bd-7c3ed9256334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790720737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.790720737
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.3190379462
Short name T574
Test name
Test status
Simulation time 17027292 ps
CPU time 0.76 seconds
Started Mar 24 01:14:34 PM PDT 24
Finished Mar 24 01:14:35 PM PDT 24
Peak memory 205804 kb
Host smart-11bf0f3b-ee54-43ec-b686-6997b7cc2bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190379462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.3190379462
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.2906791503
Short name T138
Test name
Test status
Simulation time 18084651488 ps
CPU time 120.12 seconds
Started Mar 24 01:14:32 PM PDT 24
Finished Mar 24 01:16:33 PM PDT 24
Peak memory 269392 kb
Host smart-8a5c7e2e-c482-40e2-a574-c797943fb797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906791503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.2906791503
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.1702742007
Short name T502
Test name
Test status
Simulation time 33582092590 ps
CPU time 91.77 seconds
Started Mar 24 01:14:25 PM PDT 24
Finished Mar 24 01:15:57 PM PDT 24
Peak memory 257764 kb
Host smart-c9fb931b-86bb-41cd-98e0-32b5a5f4347f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702742007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.1702742007
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.1093375744
Short name T661
Test name
Test status
Simulation time 454289762003 ps
CPU time 327.55 seconds
Started Mar 24 01:14:34 PM PDT 24
Finished Mar 24 01:20:02 PM PDT 24
Peak memory 253312 kb
Host smart-8923a655-37dd-4fd7-a443-f4d07e2fdb02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093375744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.1093375744
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.2745668200
Short name T922
Test name
Test status
Simulation time 629361442 ps
CPU time 9.86 seconds
Started Mar 24 01:14:37 PM PDT 24
Finished Mar 24 01:14:47 PM PDT 24
Peak memory 241212 kb
Host smart-3c5dae7e-a5c9-492c-86cc-a159375c38e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745668200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.2745668200
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.2188267575
Short name T818
Test name
Test status
Simulation time 687960213 ps
CPU time 4.39 seconds
Started Mar 24 01:14:25 PM PDT 24
Finished Mar 24 01:14:30 PM PDT 24
Peak memory 233796 kb
Host smart-913f7bf4-ab51-4029-af41-671f46a52801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188267575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.2188267575
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.666742636
Short name T451
Test name
Test status
Simulation time 14604178264 ps
CPU time 26.96 seconds
Started Mar 24 01:14:25 PM PDT 24
Finished Mar 24 01:14:52 PM PDT 24
Peak memory 241076 kb
Host smart-984885e2-3719-4c83-9d29-185bad91b5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666742636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.666742636
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.1688136660
Short name T154
Test name
Test status
Simulation time 674341610 ps
CPU time 6.63 seconds
Started Mar 24 01:14:28 PM PDT 24
Finished Mar 24 01:14:35 PM PDT 24
Peak memory 233824 kb
Host smart-d4e0e41b-0fcc-47d5-b6f5-e3f4922a4191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688136660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.1688136660
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.1569635471
Short name T14
Test name
Test status
Simulation time 757642908 ps
CPU time 4.63 seconds
Started Mar 24 01:14:33 PM PDT 24
Finished Mar 24 01:14:38 PM PDT 24
Peak memory 233908 kb
Host smart-a237f8a0-eea7-4c3d-85e2-d74849591454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569635471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1569635471
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.1749723209
Short name T765
Test name
Test status
Simulation time 4110304487 ps
CPU time 6.04 seconds
Started Mar 24 01:14:35 PM PDT 24
Finished Mar 24 01:14:42 PM PDT 24
Peak memory 222768 kb
Host smart-b941d91c-2c94-4ded-980d-30c63cb89d89
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1749723209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.1749723209
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.1900928128
Short name T372
Test name
Test status
Simulation time 94686236 ps
CPU time 1.04 seconds
Started Mar 24 01:14:35 PM PDT 24
Finished Mar 24 01:14:37 PM PDT 24
Peak memory 207256 kb
Host smart-dcd72edd-034a-451d-958b-4942c454aa1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900928128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.1900928128
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.4010970723
Short name T249
Test name
Test status
Simulation time 21025646405 ps
CPU time 59.47 seconds
Started Mar 24 01:14:24 PM PDT 24
Finished Mar 24 01:15:23 PM PDT 24
Peak memory 216704 kb
Host smart-f329dc35-a33f-42bd-9a39-d80ecfcb8a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010970723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.4010970723
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.3819877951
Short name T804
Test name
Test status
Simulation time 9285521975 ps
CPU time 18.01 seconds
Started Mar 24 01:14:28 PM PDT 24
Finished Mar 24 01:14:46 PM PDT 24
Peak memory 216728 kb
Host smart-e7ac0a64-8c29-4857-8cba-4847b2dbd714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819877951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3819877951
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.1286048124
Short name T866
Test name
Test status
Simulation time 315582717 ps
CPU time 1.69 seconds
Started Mar 24 01:14:37 PM PDT 24
Finished Mar 24 01:14:39 PM PDT 24
Peak memory 216628 kb
Host smart-e9eb3d9a-5096-4071-aa57-108f75411909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286048124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.1286048124
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.3867835685
Short name T315
Test name
Test status
Simulation time 117418390 ps
CPU time 0.84 seconds
Started Mar 24 01:14:37 PM PDT 24
Finished Mar 24 01:14:38 PM PDT 24
Peak memory 206044 kb
Host smart-86b2c292-3053-46e3-8967-54081c7af8e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867835685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.3867835685
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.925047797
Short name T702
Test name
Test status
Simulation time 6559208488 ps
CPU time 12.32 seconds
Started Mar 24 01:14:24 PM PDT 24
Finished Mar 24 01:14:36 PM PDT 24
Peak memory 249144 kb
Host smart-b0a6ecc7-1f0b-47ee-8e7a-f6af19d3b446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925047797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.925047797
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.2537493524
Short name T941
Test name
Test status
Simulation time 37110608 ps
CPU time 0.7 seconds
Started Mar 24 01:14:30 PM PDT 24
Finished Mar 24 01:14:32 PM PDT 24
Peak memory 205660 kb
Host smart-c5b8ae2a-8456-4feb-a9c7-99ca419b5b10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537493524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
2537493524
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.3087017193
Short name T595
Test name
Test status
Simulation time 2631683787 ps
CPU time 6.21 seconds
Started Mar 24 01:14:27 PM PDT 24
Finished Mar 24 01:14:34 PM PDT 24
Peak memory 219764 kb
Host smart-61b213c0-9626-4615-b10e-b3c181c0f55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087017193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.3087017193
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.3293730612
Short name T307
Test name
Test status
Simulation time 13186995 ps
CPU time 0.76 seconds
Started Mar 24 01:14:23 PM PDT 24
Finished Mar 24 01:14:24 PM PDT 24
Peak memory 205764 kb
Host smart-0d9d4455-9bc9-486a-8346-40b6b110eb89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293730612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.3293730612
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.396423317
Short name T223
Test name
Test status
Simulation time 42769402431 ps
CPU time 192.58 seconds
Started Mar 24 01:14:35 PM PDT 24
Finished Mar 24 01:17:48 PM PDT 24
Peak memory 255732 kb
Host smart-4d7689b8-7c44-4031-9613-f7811b57da25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396423317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.396423317
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.1383525026
Short name T377
Test name
Test status
Simulation time 26950332825 ps
CPU time 56.5 seconds
Started Mar 24 01:14:25 PM PDT 24
Finished Mar 24 01:15:22 PM PDT 24
Peak memory 252432 kb
Host smart-16d62840-04b3-482d-9ef7-f8a7c809c0af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383525026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.1383525026
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.1788911555
Short name T810
Test name
Test status
Simulation time 37633686749 ps
CPU time 58.77 seconds
Started Mar 24 01:14:27 PM PDT 24
Finished Mar 24 01:15:27 PM PDT 24
Peak memory 241332 kb
Host smart-e477ebd4-0106-412c-bf18-52239ae11834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788911555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.1788911555
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.2333137021
Short name T966
Test name
Test status
Simulation time 2362055270 ps
CPU time 12.06 seconds
Started Mar 24 01:14:38 PM PDT 24
Finished Mar 24 01:14:50 PM PDT 24
Peak memory 234328 kb
Host smart-e0c18273-b0ca-4c99-8906-d9378cc33f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333137021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.2333137021
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.3624979845
Short name T757
Test name
Test status
Simulation time 3206173756 ps
CPU time 4.2 seconds
Started Mar 24 01:14:25 PM PDT 24
Finished Mar 24 01:14:30 PM PDT 24
Peak memory 218788 kb
Host smart-bc4d2bdd-f66b-40d3-9ca3-09cc53ad3c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624979845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.3624979845
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.3033537994
Short name T918
Test name
Test status
Simulation time 928536277 ps
CPU time 7.19 seconds
Started Mar 24 01:14:26 PM PDT 24
Finished Mar 24 01:14:33 PM PDT 24
Peak memory 232996 kb
Host smart-642ff3e0-7b8b-47ca-b56c-50b7f782f423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033537994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.3033537994
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.2859795002
Short name T62
Test name
Test status
Simulation time 9392064274 ps
CPU time 23.17 seconds
Started Mar 24 01:14:37 PM PDT 24
Finished Mar 24 01:15:00 PM PDT 24
Peak memory 236992 kb
Host smart-1e272ece-fb75-4b49-a790-a59f971d7b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859795002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.2859795002
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.2287675097
Short name T718
Test name
Test status
Simulation time 717643632 ps
CPU time 7.16 seconds
Started Mar 24 01:14:30 PM PDT 24
Finished Mar 24 01:14:37 PM PDT 24
Peak memory 234644 kb
Host smart-c57a3ae0-4384-4917-85c8-5ab7eac27e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287675097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.2287675097
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.1914481032
Short name T120
Test name
Test status
Simulation time 96261443 ps
CPU time 3.8 seconds
Started Mar 24 01:14:43 PM PDT 24
Finished Mar 24 01:14:47 PM PDT 24
Peak memory 222520 kb
Host smart-dc83c14b-1828-4ad3-830b-d6f3b77cd84e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1914481032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.1914481032
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.1033511390
Short name T204
Test name
Test status
Simulation time 275702696363 ps
CPU time 349.3 seconds
Started Mar 24 01:14:39 PM PDT 24
Finished Mar 24 01:20:28 PM PDT 24
Peak memory 255612 kb
Host smart-83f7ed86-dd49-4069-afc2-df1a80894025
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033511390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.1033511390
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.2418251700
Short name T387
Test name
Test status
Simulation time 4756076610 ps
CPU time 28.74 seconds
Started Mar 24 01:14:34 PM PDT 24
Finished Mar 24 01:15:03 PM PDT 24
Peak memory 220436 kb
Host smart-0ac2ac86-540f-4546-8480-6e419d88d4ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418251700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.2418251700
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.2207922228
Short name T956
Test name
Test status
Simulation time 21349049061 ps
CPU time 14.42 seconds
Started Mar 24 01:14:30 PM PDT 24
Finished Mar 24 01:14:45 PM PDT 24
Peak memory 216632 kb
Host smart-e5fde8fd-569f-4f89-98e6-cb7da88a5e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207922228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.2207922228
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.3267800512
Short name T505
Test name
Test status
Simulation time 19617706 ps
CPU time 0.8 seconds
Started Mar 24 01:14:37 PM PDT 24
Finished Mar 24 01:14:38 PM PDT 24
Peak memory 206068 kb
Host smart-cd8876f9-723c-4948-b983-eb382eacdb43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267800512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.3267800512
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.2336433360
Short name T275
Test name
Test status
Simulation time 86539665 ps
CPU time 0.84 seconds
Started Mar 24 01:14:33 PM PDT 24
Finished Mar 24 01:14:35 PM PDT 24
Peak memory 206048 kb
Host smart-e9a79466-e0b1-4bbc-b1dc-8fef7c594683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336433360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.2336433360
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.730386994
Short name T207
Test name
Test status
Simulation time 234094358 ps
CPU time 5.03 seconds
Started Mar 24 01:14:33 PM PDT 24
Finished Mar 24 01:14:39 PM PDT 24
Peak memory 236176 kb
Host smart-7bb4f238-5fa4-4b6e-bbff-56bcd3168824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730386994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.730386994
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.1978973337
Short name T456
Test name
Test status
Simulation time 78242092 ps
CPU time 0.73 seconds
Started Mar 24 01:14:35 PM PDT 24
Finished Mar 24 01:14:36 PM PDT 24
Peak memory 206084 kb
Host smart-5cad76a7-7a15-427f-a804-55ec23c48009
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978973337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
1978973337
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.3805017670
Short name T521
Test name
Test status
Simulation time 618962812 ps
CPU time 3.04 seconds
Started Mar 24 01:14:30 PM PDT 24
Finished Mar 24 01:14:34 PM PDT 24
Peak memory 232972 kb
Host smart-c2170a05-d5dd-432c-a1a6-79e172b1518e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805017670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.3805017670
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.1395055305
Short name T836
Test name
Test status
Simulation time 33701833 ps
CPU time 0.78 seconds
Started Mar 24 01:14:30 PM PDT 24
Finished Mar 24 01:14:31 PM PDT 24
Peak memory 205820 kb
Host smart-0ef0593b-5ef7-4059-bac1-7b222fe26329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395055305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.1395055305
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.3508467163
Short name T919
Test name
Test status
Simulation time 27022520714 ps
CPU time 93.22 seconds
Started Mar 24 01:14:30 PM PDT 24
Finished Mar 24 01:16:04 PM PDT 24
Peak memory 257568 kb
Host smart-e2478dcf-eaf2-4924-bafe-e35c6d6633dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508467163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.3508467163
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.3992531729
Short name T965
Test name
Test status
Simulation time 8184261156 ps
CPU time 98.27 seconds
Started Mar 24 01:14:36 PM PDT 24
Finished Mar 24 01:16:14 PM PDT 24
Peak memory 262220 kb
Host smart-cf1e1ead-5984-49a8-9ef5-e1d6fa675b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992531729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.3992531729
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.114372663
Short name T664
Test name
Test status
Simulation time 200858637947 ps
CPU time 380.32 seconds
Started Mar 24 01:14:29 PM PDT 24
Finished Mar 24 01:20:49 PM PDT 24
Peak memory 253896 kb
Host smart-4efd1010-3c7a-4b08-9e8d-c0f7d9a7a3ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114372663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle
.114372663
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.372360401
Short name T625
Test name
Test status
Simulation time 1244955263 ps
CPU time 8.96 seconds
Started Mar 24 01:14:45 PM PDT 24
Finished Mar 24 01:14:54 PM PDT 24
Peak memory 234492 kb
Host smart-d3cb9b68-5768-434b-bcf5-8c3ec29606fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372360401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.372360401
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.1097791172
Short name T194
Test name
Test status
Simulation time 343553345 ps
CPU time 3 seconds
Started Mar 24 01:14:33 PM PDT 24
Finished Mar 24 01:14:37 PM PDT 24
Peak memory 233068 kb
Host smart-dab0f385-eed1-4515-b911-168398ff589f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097791172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.1097791172
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.3811531056
Short name T310
Test name
Test status
Simulation time 970340364 ps
CPU time 6.79 seconds
Started Mar 24 01:14:28 PM PDT 24
Finished Mar 24 01:14:35 PM PDT 24
Peak memory 233812 kb
Host smart-d15bf19d-10b7-43f6-9224-6a384a817b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811531056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.3811531056
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.68592273
Short name T864
Test name
Test status
Simulation time 390174856 ps
CPU time 4.12 seconds
Started Mar 24 01:14:36 PM PDT 24
Finished Mar 24 01:14:40 PM PDT 24
Peak memory 233524 kb
Host smart-baaa9b0a-2da4-49ba-b041-91342008d754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68592273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap.68592273
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.878376669
Short name T43
Test name
Test status
Simulation time 413518289 ps
CPU time 2.2 seconds
Started Mar 24 01:14:34 PM PDT 24
Finished Mar 24 01:14:37 PM PDT 24
Peak memory 217144 kb
Host smart-12e92d62-ec39-4838-acf3-672f36f3a880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878376669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.878376669
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.3832433228
Short name T761
Test name
Test status
Simulation time 69396116 ps
CPU time 3.14 seconds
Started Mar 24 01:14:38 PM PDT 24
Finished Mar 24 01:14:41 PM PDT 24
Peak memory 220448 kb
Host smart-2dc5d5d3-dd40-42c4-ad36-4bd3c0cde66e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3832433228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.3832433228
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.1508736741
Short name T168
Test name
Test status
Simulation time 124570731130 ps
CPU time 415.77 seconds
Started Mar 24 01:14:37 PM PDT 24
Finished Mar 24 01:21:33 PM PDT 24
Peak memory 265992 kb
Host smart-dfb66a6d-fee2-4dad-a77b-0c60b8ebf415
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508736741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.1508736741
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.1182637308
Short name T579
Test name
Test status
Simulation time 1507549686 ps
CPU time 11.15 seconds
Started Mar 24 01:14:40 PM PDT 24
Finished Mar 24 01:14:51 PM PDT 24
Peak memory 216620 kb
Host smart-f062cc55-4e0f-4598-bb2f-c81ada9d0b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182637308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.1182637308
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.1938913292
Short name T455
Test name
Test status
Simulation time 10296865216 ps
CPU time 17.41 seconds
Started Mar 24 01:14:44 PM PDT 24
Finished Mar 24 01:15:02 PM PDT 24
Peak memory 216644 kb
Host smart-1844eb21-2ac6-4ff1-986a-e9d8f1815e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938913292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.1938913292
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.3230809118
Short name T739
Test name
Test status
Simulation time 45582976 ps
CPU time 1.21 seconds
Started Mar 24 01:14:37 PM PDT 24
Finished Mar 24 01:14:38 PM PDT 24
Peak memory 208540 kb
Host smart-65b219c1-0554-478a-83e1-77772283af37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230809118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.3230809118
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.3121461931
Short name T937
Test name
Test status
Simulation time 147319929 ps
CPU time 0.86 seconds
Started Mar 24 01:14:36 PM PDT 24
Finished Mar 24 01:14:37 PM PDT 24
Peak memory 206544 kb
Host smart-762d5b99-d5bf-47f3-b472-4d803ce456a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121461931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.3121461931
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.4273871969
Short name T888
Test name
Test status
Simulation time 2558764559 ps
CPU time 6.61 seconds
Started Mar 24 01:14:29 PM PDT 24
Finished Mar 24 01:14:36 PM PDT 24
Peak memory 234440 kb
Host smart-0cdbf293-c20f-4454-8b31-f9add6d8dac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273871969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.4273871969
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.31318822
Short name T805
Test name
Test status
Simulation time 14206330 ps
CPU time 0.71 seconds
Started Mar 24 01:14:30 PM PDT 24
Finished Mar 24 01:14:31 PM PDT 24
Peak memory 205684 kb
Host smart-b5a903ad-c662-4d7f-9220-4ecffa80e875
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31318822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.31318822
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.2970947394
Short name T341
Test name
Test status
Simulation time 169764664 ps
CPU time 2.47 seconds
Started Mar 24 01:14:38 PM PDT 24
Finished Mar 24 01:14:40 PM PDT 24
Peak memory 224804 kb
Host smart-54519ee4-cfeb-4c80-a9f6-c4193acb77b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970947394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.2970947394
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.261311123
Short name T253
Test name
Test status
Simulation time 104515952 ps
CPU time 0.79 seconds
Started Mar 24 01:14:33 PM PDT 24
Finished Mar 24 01:14:34 PM PDT 24
Peak memory 206828 kb
Host smart-d1d6058a-ce37-4d95-ba9d-9ba577b5b507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261311123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.261311123
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.48712729
Short name T865
Test name
Test status
Simulation time 21098552645 ps
CPU time 92.35 seconds
Started Mar 24 01:14:33 PM PDT 24
Finished Mar 24 01:16:06 PM PDT 24
Peak memory 240996 kb
Host smart-0af3482c-a2f1-4474-92dd-a96f99a55f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48712729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.48712729
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.1513656021
Short name T230
Test name
Test status
Simulation time 23597827395 ps
CPU time 111.36 seconds
Started Mar 24 01:14:31 PM PDT 24
Finished Mar 24 01:16:23 PM PDT 24
Peak memory 255244 kb
Host smart-fad50b6c-8227-4fbd-afb8-c32ff03947ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513656021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.1513656021
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.3251687636
Short name T202
Test name
Test status
Simulation time 12179994306 ps
CPU time 79.89 seconds
Started Mar 24 01:14:38 PM PDT 24
Finished Mar 24 01:15:58 PM PDT 24
Peak memory 255948 kb
Host smart-1922bdca-bb47-446d-b62e-d0e95298cebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251687636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.3251687636
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.1726818753
Short name T816
Test name
Test status
Simulation time 1780786609 ps
CPU time 19.35 seconds
Started Mar 24 01:14:35 PM PDT 24
Finished Mar 24 01:14:55 PM PDT 24
Peak memory 239376 kb
Host smart-b4e129c7-099a-4f1b-83d6-3c967a8be89b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726818753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.1726818753
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.3956919733
Short name T457
Test name
Test status
Simulation time 6390706787 ps
CPU time 7.88 seconds
Started Mar 24 01:14:37 PM PDT 24
Finished Mar 24 01:14:46 PM PDT 24
Peak memory 220072 kb
Host smart-1249aab2-5d5b-404c-a916-d70674d92685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956919733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.3956919733
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.3664277156
Short name T146
Test name
Test status
Simulation time 619245645 ps
CPU time 8.96 seconds
Started Mar 24 01:14:38 PM PDT 24
Finished Mar 24 01:14:47 PM PDT 24
Peak memory 235952 kb
Host smart-b457bf08-b0f2-4007-827b-b2f94669d10a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664277156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.3664277156
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.488655809
Short name T174
Test name
Test status
Simulation time 16331655997 ps
CPU time 12.02 seconds
Started Mar 24 01:14:35 PM PDT 24
Finished Mar 24 01:14:48 PM PDT 24
Peak memory 219628 kb
Host smart-a67c54cc-b9a0-4f5f-afcd-ae7ff4a5aa77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488655809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap
.488655809
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.1599752614
Short name T594
Test name
Test status
Simulation time 662059306 ps
CPU time 2.68 seconds
Started Mar 24 01:14:46 PM PDT 24
Finished Mar 24 01:14:48 PM PDT 24
Peak memory 218688 kb
Host smart-53226363-16b4-466c-b1a8-4f30a32792c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599752614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.1599752614
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.3750619428
Short name T415
Test name
Test status
Simulation time 1919573064 ps
CPU time 4.22 seconds
Started Mar 24 01:14:31 PM PDT 24
Finished Mar 24 01:14:36 PM PDT 24
Peak memory 219648 kb
Host smart-3579cd39-1a2e-4bbc-86a6-23e961b1d03a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3750619428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.3750619428
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.2723193046
Short name T628
Test name
Test status
Simulation time 3216011076 ps
CPU time 30.46 seconds
Started Mar 24 01:14:49 PM PDT 24
Finished Mar 24 01:15:20 PM PDT 24
Peak memory 233176 kb
Host smart-496e20c9-10a7-49f6-8707-78bae0f51787
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723193046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.2723193046
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.1072066427
Short name T478
Test name
Test status
Simulation time 2086421322 ps
CPU time 29.47 seconds
Started Mar 24 01:14:36 PM PDT 24
Finished Mar 24 01:15:06 PM PDT 24
Peak memory 219528 kb
Host smart-97052dde-3ebb-4107-ae69-26f38b43e3f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072066427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.1072066427
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.52826743
Short name T887
Test name
Test status
Simulation time 1842826197 ps
CPU time 4.95 seconds
Started Mar 24 01:14:32 PM PDT 24
Finished Mar 24 01:14:37 PM PDT 24
Peak memory 216600 kb
Host smart-38da8849-ebb1-483e-b63e-3d8152a79355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52826743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.52826743
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.761072275
Short name T640
Test name
Test status
Simulation time 5750889558 ps
CPU time 3.56 seconds
Started Mar 24 01:14:30 PM PDT 24
Finished Mar 24 01:14:34 PM PDT 24
Peak memory 216900 kb
Host smart-16721a50-7043-4a4e-b2f8-c10f23aba684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761072275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.761072275
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.162603317
Short name T567
Test name
Test status
Simulation time 116315382 ps
CPU time 0.87 seconds
Started Mar 24 01:14:28 PM PDT 24
Finished Mar 24 01:14:29 PM PDT 24
Peak memory 206024 kb
Host smart-b3eb6165-7e6c-478e-af7e-565d79c72d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162603317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.162603317
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.774862823
Short name T522
Test name
Test status
Simulation time 14791270175 ps
CPU time 26.8 seconds
Started Mar 24 01:14:29 PM PDT 24
Finished Mar 24 01:14:56 PM PDT 24
Peak memory 238124 kb
Host smart-a5f8b29d-f085-49cf-bdc0-761a0953e295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774862823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.774862823
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.606811008
Short name T633
Test name
Test status
Simulation time 15850378 ps
CPU time 0.73 seconds
Started Mar 24 01:14:49 PM PDT 24
Finished Mar 24 01:14:50 PM PDT 24
Peak memory 205676 kb
Host smart-8012f048-a5ca-4a18-a05a-3b27b14b8765
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606811008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.606811008
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.525153693
Short name T720
Test name
Test status
Simulation time 335971584 ps
CPU time 2.49 seconds
Started Mar 24 01:14:51 PM PDT 24
Finished Mar 24 01:14:54 PM PDT 24
Peak memory 224868 kb
Host smart-a411230e-7f8c-414c-8f28-5787a3343335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525153693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.525153693
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.3570089124
Short name T542
Test name
Test status
Simulation time 71696990 ps
CPU time 0.79 seconds
Started Mar 24 01:14:30 PM PDT 24
Finished Mar 24 01:14:31 PM PDT 24
Peak memory 206816 kb
Host smart-de50e609-a0a5-4eee-b790-65202ac53564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570089124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.3570089124
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.248187584
Short name T225
Test name
Test status
Simulation time 31999569864 ps
CPU time 82.4 seconds
Started Mar 24 01:14:48 PM PDT 24
Finished Mar 24 01:16:10 PM PDT 24
Peak memory 237248 kb
Host smart-4c49fd50-a5ba-4f7e-ab03-be6c893b8916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248187584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.248187584
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.2360122911
Short name T37
Test name
Test status
Simulation time 53991255537 ps
CPU time 183.99 seconds
Started Mar 24 01:14:51 PM PDT 24
Finished Mar 24 01:17:56 PM PDT 24
Peak memory 273684 kb
Host smart-d7a649d4-2aa9-4322-9994-fa339cd3a99e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360122911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.2360122911
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.2579781662
Short name T215
Test name
Test status
Simulation time 81550406320 ps
CPU time 379.78 seconds
Started Mar 24 01:14:48 PM PDT 24
Finished Mar 24 01:21:08 PM PDT 24
Peak memory 265672 kb
Host smart-17245474-3f22-43a6-acab-2278e2dfbee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579781662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.2579781662
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.1125672687
Short name T276
Test name
Test status
Simulation time 524856458 ps
CPU time 9.39 seconds
Started Mar 24 01:14:49 PM PDT 24
Finished Mar 24 01:15:00 PM PDT 24
Peak memory 240272 kb
Host smart-501393ee-db76-4f14-92f4-1a8985b8ba74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125672687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.1125672687
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.4199954758
Short name T914
Test name
Test status
Simulation time 99113317 ps
CPU time 2.88 seconds
Started Mar 24 01:14:38 PM PDT 24
Finished Mar 24 01:14:41 PM PDT 24
Peak memory 233904 kb
Host smart-e9a19d61-b247-44f6-9167-1d344fb7af81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199954758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.4199954758
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.1294498487
Short name T198
Test name
Test status
Simulation time 1280926653 ps
CPU time 10.41 seconds
Started Mar 24 01:14:44 PM PDT 24
Finished Mar 24 01:14:55 PM PDT 24
Peak memory 235260 kb
Host smart-b36162c0-4fdb-4c31-b8bf-1460831fd995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294498487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.1294498487
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.3914759202
Short name T354
Test name
Test status
Simulation time 115940092042 ps
CPU time 40.36 seconds
Started Mar 24 01:14:35 PM PDT 24
Finished Mar 24 01:15:16 PM PDT 24
Peak memory 249872 kb
Host smart-413ac84c-d56a-470e-9697-6ed9c74128f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914759202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.3914759202
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.3848825453
Short name T3
Test name
Test status
Simulation time 124162630 ps
CPU time 2.67 seconds
Started Mar 24 01:14:33 PM PDT 24
Finished Mar 24 01:14:37 PM PDT 24
Peak memory 233012 kb
Host smart-42885419-a663-4263-9f84-66cca5f14fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848825453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.3848825453
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.1759664682
Short name T669
Test name
Test status
Simulation time 4864297236 ps
CPU time 6.83 seconds
Started Mar 24 01:14:44 PM PDT 24
Finished Mar 24 01:14:51 PM PDT 24
Peak memory 223400 kb
Host smart-ef96c5fe-ac7b-4d8a-a7d8-77c82e2ed6a7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1759664682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.1759664682
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.2353009922
Short name T589
Test name
Test status
Simulation time 37715090 ps
CPU time 0.98 seconds
Started Mar 24 01:14:46 PM PDT 24
Finished Mar 24 01:14:47 PM PDT 24
Peak memory 207164 kb
Host smart-f8e5aff6-77dc-44ac-9f5f-e41b022d9f61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353009922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.2353009922
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.3757030982
Short name T758
Test name
Test status
Simulation time 293681364 ps
CPU time 2.78 seconds
Started Mar 24 01:14:40 PM PDT 24
Finished Mar 24 01:14:42 PM PDT 24
Peak memory 216620 kb
Host smart-a6ceb508-c9ac-43a4-83c7-935172eb7348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757030982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.3757030982
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.3098562714
Short name T298
Test name
Test status
Simulation time 2532112018 ps
CPU time 2.53 seconds
Started Mar 24 01:14:34 PM PDT 24
Finished Mar 24 01:14:37 PM PDT 24
Peak memory 216672 kb
Host smart-b63971a5-d5be-4b88-a88e-2f9438307ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098562714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.3098562714
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.3063546766
Short name T369
Test name
Test status
Simulation time 204451079 ps
CPU time 1.77 seconds
Started Mar 24 01:14:43 PM PDT 24
Finished Mar 24 01:14:45 PM PDT 24
Peak memory 216632 kb
Host smart-e9792d79-4d90-4ebf-bc38-2da6f74dc8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063546766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.3063546766
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.85640816
Short name T529
Test name
Test status
Simulation time 241027662 ps
CPU time 1.02 seconds
Started Mar 24 01:14:30 PM PDT 24
Finished Mar 24 01:14:32 PM PDT 24
Peak memory 207084 kb
Host smart-9fcfb042-788e-43a7-ae6a-6e6ebf6bb22d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85640816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.85640816
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.1909899017
Short name T284
Test name
Test status
Simulation time 652905221 ps
CPU time 4.3 seconds
Started Mar 24 01:14:49 PM PDT 24
Finished Mar 24 01:14:55 PM PDT 24
Peak memory 234008 kb
Host smart-1a492dd4-39de-4fb5-97d7-a408e220839b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909899017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.1909899017
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.2542676249
Short name T839
Test name
Test status
Simulation time 52616210 ps
CPU time 0.71 seconds
Started Mar 24 01:14:43 PM PDT 24
Finished Mar 24 01:14:44 PM PDT 24
Peak memory 205956 kb
Host smart-e36b2b14-f9ca-4423-8b2c-12c741f8ec44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542676249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
2542676249
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.3492525537
Short name T738
Test name
Test status
Simulation time 51212714018 ps
CPU time 11.3 seconds
Started Mar 24 01:14:49 PM PDT 24
Finished Mar 24 01:15:01 PM PDT 24
Peak memory 219668 kb
Host smart-81db444a-6368-4441-8c38-ec371f14d6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492525537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.3492525537
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.1692821343
Short name T730
Test name
Test status
Simulation time 16867858 ps
CPU time 0.73 seconds
Started Mar 24 01:14:46 PM PDT 24
Finished Mar 24 01:14:47 PM PDT 24
Peak memory 206048 kb
Host smart-15fcbdb5-2ee2-4506-a9b5-63ce721b9129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692821343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.1692821343
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.4151658067
Short name T841
Test name
Test status
Simulation time 48602668290 ps
CPU time 47.94 seconds
Started Mar 24 01:14:43 PM PDT 24
Finished Mar 24 01:15:31 PM PDT 24
Peak memory 237888 kb
Host smart-07df6644-d471-4a6f-8180-1fd2f858c7b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151658067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.4151658067
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.3823781864
Short name T183
Test name
Test status
Simulation time 980336081096 ps
CPU time 644.39 seconds
Started Mar 24 01:14:36 PM PDT 24
Finished Mar 24 01:25:21 PM PDT 24
Peak memory 267576 kb
Host smart-38b02f16-f59b-429d-a6d8-c33af48d20a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823781864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.3823781864
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.3560766393
Short name T181
Test name
Test status
Simulation time 645811778 ps
CPU time 10.33 seconds
Started Mar 24 01:14:34 PM PDT 24
Finished Mar 24 01:14:45 PM PDT 24
Peak memory 233024 kb
Host smart-bd196113-9f59-4e39-9b71-659f9ef8bead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560766393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.3560766393
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.4111913027
Short name T837
Test name
Test status
Simulation time 777450486 ps
CPU time 6.44 seconds
Started Mar 24 01:14:49 PM PDT 24
Finished Mar 24 01:14:56 PM PDT 24
Peak memory 219844 kb
Host smart-8bfbb979-dee3-4741-b701-6d61ef8479e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111913027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.4111913027
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.296063191
Short name T293
Test name
Test status
Simulation time 1128712934 ps
CPU time 7.88 seconds
Started Mar 24 01:14:49 PM PDT 24
Finished Mar 24 01:14:58 PM PDT 24
Peak memory 234656 kb
Host smart-1779dc38-fbfc-447a-a750-818a15f4ff29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296063191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.296063191
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.161491427
Short name T857
Test name
Test status
Simulation time 1597115978 ps
CPU time 12.03 seconds
Started Mar 24 01:14:41 PM PDT 24
Finished Mar 24 01:14:53 PM PDT 24
Peak memory 240036 kb
Host smart-4a55cabe-f83a-4ed8-9bf5-3ec4a7804d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161491427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap
.161491427
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.1820382322
Short name T622
Test name
Test status
Simulation time 348889598 ps
CPU time 5.33 seconds
Started Mar 24 01:14:47 PM PDT 24
Finished Mar 24 01:14:53 PM PDT 24
Peak memory 236628 kb
Host smart-7f578342-6cb6-48b8-adba-5a976bb68442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820382322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.1820382322
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.914807244
Short name T726
Test name
Test status
Simulation time 450224816 ps
CPU time 3.47 seconds
Started Mar 24 01:14:44 PM PDT 24
Finished Mar 24 01:14:48 PM PDT 24
Peak memory 219552 kb
Host smart-5bc22105-4dcf-44ce-bb05-484b4a029a4c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=914807244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dire
ct.914807244
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.1654963114
Short name T442
Test name
Test status
Simulation time 26465722356 ps
CPU time 92.54 seconds
Started Mar 24 01:14:43 PM PDT 24
Finished Mar 24 01:16:16 PM PDT 24
Peak memory 241312 kb
Host smart-9dfc4b4d-7101-420f-a56b-571d57a56aa5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654963114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.1654963114
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.4193399396
Short name T733
Test name
Test status
Simulation time 9639720438 ps
CPU time 15.33 seconds
Started Mar 24 01:14:48 PM PDT 24
Finished Mar 24 01:15:03 PM PDT 24
Peak memory 216680 kb
Host smart-5471541e-ad6a-4f10-8667-1dad3ea47eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193399396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.4193399396
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.476470474
Short name T316
Test name
Test status
Simulation time 1821558766 ps
CPU time 7.83 seconds
Started Mar 24 01:14:45 PM PDT 24
Finished Mar 24 01:14:53 PM PDT 24
Peak memory 216552 kb
Host smart-f75ad2b7-ce38-4620-8d7e-2056211c6d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476470474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.476470474
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.1924940840
Short name T910
Test name
Test status
Simulation time 133436128 ps
CPU time 1.03 seconds
Started Mar 24 01:14:40 PM PDT 24
Finished Mar 24 01:14:41 PM PDT 24
Peak memory 208236 kb
Host smart-40569426-ac82-4b70-9844-724ee9c3227a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924940840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.1924940840
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.4018846920
Short name T450
Test name
Test status
Simulation time 45263076 ps
CPU time 0.98 seconds
Started Mar 24 01:14:44 PM PDT 24
Finished Mar 24 01:14:45 PM PDT 24
Peak memory 206156 kb
Host smart-7e641835-8442-45f2-8d7e-74d8b422dee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018846920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.4018846920
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.3582440861
Short name T187
Test name
Test status
Simulation time 4679557745 ps
CPU time 17.33 seconds
Started Mar 24 01:14:43 PM PDT 24
Finished Mar 24 01:15:01 PM PDT 24
Peak memory 238460 kb
Host smart-907b5d02-8931-4391-8ea6-b60fbf497b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582440861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.3582440861
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.4005237223
Short name T519
Test name
Test status
Simulation time 18318535 ps
CPU time 0.8 seconds
Started Mar 24 01:14:45 PM PDT 24
Finished Mar 24 01:14:45 PM PDT 24
Peak memory 205744 kb
Host smart-050a7085-0432-430c-a9c1-9fbbf67ef7d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005237223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
4005237223
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.2332240531
Short name T927
Test name
Test status
Simulation time 2794852237 ps
CPU time 6.18 seconds
Started Mar 24 01:14:47 PM PDT 24
Finished Mar 24 01:14:53 PM PDT 24
Peak memory 220176 kb
Host smart-5485b089-2dcb-42f4-a6be-425a4eefa97f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332240531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.2332240531
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.3517727731
Short name T408
Test name
Test status
Simulation time 21138099 ps
CPU time 0.8 seconds
Started Mar 24 01:14:45 PM PDT 24
Finished Mar 24 01:14:46 PM PDT 24
Peak memory 206760 kb
Host smart-744f9c69-c809-4f35-8038-41f492b0f74b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517727731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.3517727731
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.392495998
Short name T338
Test name
Test status
Simulation time 8212114106 ps
CPU time 43.46 seconds
Started Mar 24 01:14:43 PM PDT 24
Finished Mar 24 01:15:27 PM PDT 24
Peak memory 236960 kb
Host smart-35cb24b7-9f0b-4114-b0fc-b770771cb82a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392495998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.392495998
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.3172671976
Short name T235
Test name
Test status
Simulation time 4696903795 ps
CPU time 50.66 seconds
Started Mar 24 01:14:49 PM PDT 24
Finished Mar 24 01:15:40 PM PDT 24
Peak memory 234956 kb
Host smart-57120947-670c-4c5f-ab51-97b01c1bf096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172671976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.3172671976
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.2579357427
Short name T848
Test name
Test status
Simulation time 4736042729 ps
CPU time 27.12 seconds
Started Mar 24 01:14:49 PM PDT 24
Finished Mar 24 01:15:17 PM PDT 24
Peak memory 236236 kb
Host smart-63cd7b52-1fe4-44f7-8b73-b1fa3768a78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579357427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.2579357427
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.1896439713
Short name T243
Test name
Test status
Simulation time 3808374796 ps
CPU time 27.93 seconds
Started Mar 24 01:14:36 PM PDT 24
Finished Mar 24 01:15:04 PM PDT 24
Peak memory 234712 kb
Host smart-335a17cf-1dd6-4c51-ba2b-03f30cb09487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896439713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.1896439713
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.895106876
Short name T808
Test name
Test status
Simulation time 176733398 ps
CPU time 2.78 seconds
Started Mar 24 01:14:45 PM PDT 24
Finished Mar 24 01:14:48 PM PDT 24
Peak memory 224780 kb
Host smart-cbdbdebd-f1fd-4f36-b675-940fd3d4efef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895106876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.895106876
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.980442851
Short name T680
Test name
Test status
Simulation time 671849692 ps
CPU time 9.98 seconds
Started Mar 24 01:14:38 PM PDT 24
Finished Mar 24 01:14:48 PM PDT 24
Peak memory 234160 kb
Host smart-47ec6e87-46fa-4f72-976e-b210ac8d35a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980442851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.980442851
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.1692917314
Short name T237
Test name
Test status
Simulation time 2768925180 ps
CPU time 6.56 seconds
Started Mar 24 01:14:46 PM PDT 24
Finished Mar 24 01:14:52 PM PDT 24
Peak memory 241580 kb
Host smart-af6faba3-85f4-4bd9-83be-386ee915ee0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692917314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.1692917314
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.1620347345
Short name T485
Test name
Test status
Simulation time 6922976774 ps
CPU time 21.66 seconds
Started Mar 24 01:14:48 PM PDT 24
Finished Mar 24 01:15:10 PM PDT 24
Peak memory 233652 kb
Host smart-a50973b4-a80d-4b98-91a1-8c7205aaa2ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620347345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.1620347345
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.477158331
Short name T375
Test name
Test status
Simulation time 230309430 ps
CPU time 3.58 seconds
Started Mar 24 01:14:50 PM PDT 24
Finished Mar 24 01:14:54 PM PDT 24
Peak memory 222700 kb
Host smart-688dd88b-5e93-4505-8d35-665b7bbd8e97
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=477158331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dire
ct.477158331
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.1352172253
Short name T737
Test name
Test status
Simulation time 2321370677 ps
CPU time 10.69 seconds
Started Mar 24 01:14:45 PM PDT 24
Finished Mar 24 01:14:56 PM PDT 24
Peak memory 216680 kb
Host smart-4cb01d09-08b6-4716-b4da-2e1a31853597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352172253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.1352172253
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.965316613
Short name T745
Test name
Test status
Simulation time 650716499 ps
CPU time 2.86 seconds
Started Mar 24 01:14:41 PM PDT 24
Finished Mar 24 01:14:44 PM PDT 24
Peak memory 216568 kb
Host smart-1411b615-cd10-4924-bed0-9e5d19d7e163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965316613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.965316613
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.546788765
Short name T322
Test name
Test status
Simulation time 760661947 ps
CPU time 1.33 seconds
Started Mar 24 01:14:49 PM PDT 24
Finished Mar 24 01:14:51 PM PDT 24
Peak memory 208172 kb
Host smart-8ef5dcdc-d640-423d-990c-82d4866388e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546788765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.546788765
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.3053479194
Short name T471
Test name
Test status
Simulation time 52612232 ps
CPU time 0.92 seconds
Started Mar 24 01:14:48 PM PDT 24
Finished Mar 24 01:14:49 PM PDT 24
Peak memory 207072 kb
Host smart-ed3597bf-256d-4c18-b431-9c925b2fd060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053479194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.3053479194
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.2810435332
Short name T459
Test name
Test status
Simulation time 5510111665 ps
CPU time 6.3 seconds
Started Mar 24 01:14:44 PM PDT 24
Finished Mar 24 01:14:51 PM PDT 24
Peak memory 234300 kb
Host smart-3e5677d4-596e-4245-bbbe-a363dbe03cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810435332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.2810435332
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.1267031439
Short name T684
Test name
Test status
Simulation time 21594632 ps
CPU time 0.69 seconds
Started Mar 24 01:14:50 PM PDT 24
Finished Mar 24 01:14:51 PM PDT 24
Peak memory 205164 kb
Host smart-a17958f0-ab0f-4c60-91fe-5874e87322d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267031439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
1267031439
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.1938033808
Short name T209
Test name
Test status
Simulation time 111117441 ps
CPU time 2.39 seconds
Started Mar 24 01:14:43 PM PDT 24
Finished Mar 24 01:14:46 PM PDT 24
Peak memory 234092 kb
Host smart-702d03ec-209f-4b3b-88ff-5f7970bff72d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938033808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.1938033808
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.2095306224
Short name T58
Test name
Test status
Simulation time 41988156 ps
CPU time 0.82 seconds
Started Mar 24 01:14:44 PM PDT 24
Finished Mar 24 01:14:45 PM PDT 24
Peak memory 205848 kb
Host smart-e4aa7598-4c37-4d55-afc8-d9bb992b1c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095306224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.2095306224
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.2118618394
Short name T813
Test name
Test status
Simulation time 29121070578 ps
CPU time 36.01 seconds
Started Mar 24 01:14:46 PM PDT 24
Finished Mar 24 01:15:23 PM PDT 24
Peak memory 236232 kb
Host smart-76889734-b8d4-4975-8f75-a5448976bbc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118618394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.2118618394
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.3645382580
Short name T75
Test name
Test status
Simulation time 8075569777 ps
CPU time 107.47 seconds
Started Mar 24 01:14:50 PM PDT 24
Finished Mar 24 01:16:38 PM PDT 24
Peak memory 265936 kb
Host smart-d9d78959-38eb-4f57-a140-fc87657b3ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645382580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.3645382580
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.1256657707
Short name T66
Test name
Test status
Simulation time 7582239507 ps
CPU time 74.77 seconds
Started Mar 24 01:14:50 PM PDT 24
Finished Mar 24 01:16:05 PM PDT 24
Peak memory 250568 kb
Host smart-67152b33-da26-4554-9de8-707ddc0e1216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256657707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.1256657707
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.2950339845
Short name T723
Test name
Test status
Simulation time 21078912788 ps
CPU time 37.6 seconds
Started Mar 24 01:14:39 PM PDT 24
Finished Mar 24 01:15:16 PM PDT 24
Peak memory 233052 kb
Host smart-31f10b81-39e4-4465-8373-7ce3d87dd7e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950339845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.2950339845
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.1212232160
Short name T908
Test name
Test status
Simulation time 5457499357 ps
CPU time 7.74 seconds
Started Mar 24 01:14:47 PM PDT 24
Finished Mar 24 01:14:55 PM PDT 24
Peak memory 234064 kb
Host smart-694156eb-cba8-453d-aeb8-049b7b0aedd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212232160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.1212232160
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.3581680710
Short name T766
Test name
Test status
Simulation time 14301728143 ps
CPU time 12.33 seconds
Started Mar 24 01:14:49 PM PDT 24
Finished Mar 24 01:15:02 PM PDT 24
Peak memory 241164 kb
Host smart-9139d161-d3d2-424c-ace4-256b36a7e5cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581680710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.3581680710
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.2480944847
Short name T924
Test name
Test status
Simulation time 346122230 ps
CPU time 5.51 seconds
Started Mar 24 01:14:43 PM PDT 24
Finished Mar 24 01:14:48 PM PDT 24
Peak memory 233884 kb
Host smart-d9a0f655-ef83-482b-83a2-868e3bb42a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480944847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.2480944847
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.649573031
Short name T191
Test name
Test status
Simulation time 1759089463 ps
CPU time 3.96 seconds
Started Mar 24 01:14:48 PM PDT 24
Finished Mar 24 01:14:52 PM PDT 24
Peak memory 233904 kb
Host smart-83dc38a7-f1e7-47bb-b9be-cc48fd77fad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649573031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.649573031
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.952294302
Short name T972
Test name
Test status
Simulation time 513975200 ps
CPU time 3.42 seconds
Started Mar 24 01:14:49 PM PDT 24
Finished Mar 24 01:14:53 PM PDT 24
Peak memory 220588 kb
Host smart-7f2849ac-6242-4b66-bcbc-e4aed1d43bc1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=952294302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dire
ct.952294302
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.2894316114
Short name T503
Test name
Test status
Simulation time 36665543 ps
CPU time 0.92 seconds
Started Mar 24 01:14:49 PM PDT 24
Finished Mar 24 01:14:50 PM PDT 24
Peak memory 206680 kb
Host smart-fcd632fb-ab0c-4487-a505-b23a1d5a37d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894316114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.2894316114
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.4242424748
Short name T709
Test name
Test status
Simulation time 13262329413 ps
CPU time 17.08 seconds
Started Mar 24 01:14:39 PM PDT 24
Finished Mar 24 01:14:56 PM PDT 24
Peak memory 216684 kb
Host smart-244ed6fa-42a8-40a3-9bc8-1934497937bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242424748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.4242424748
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.2715330936
Short name T463
Test name
Test status
Simulation time 1740621336 ps
CPU time 5.74 seconds
Started Mar 24 01:14:45 PM PDT 24
Finished Mar 24 01:14:50 PM PDT 24
Peak memory 216588 kb
Host smart-fb75a66c-2792-4bc2-bac5-c32e53217364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715330936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.2715330936
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.371420943
Short name T472
Test name
Test status
Simulation time 50125454 ps
CPU time 1 seconds
Started Mar 24 01:14:44 PM PDT 24
Finished Mar 24 01:14:45 PM PDT 24
Peak memory 208248 kb
Host smart-6482355e-3646-43e6-ac46-67cf66e0fe8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371420943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.371420943
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.546187148
Short name T763
Test name
Test status
Simulation time 106717277 ps
CPU time 1.12 seconds
Started Mar 24 01:14:44 PM PDT 24
Finished Mar 24 01:14:45 PM PDT 24
Peak memory 207084 kb
Host smart-1c0ae06b-b442-4205-b8f3-f83d4f0c912e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546187148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.546187148
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.1183660411
Short name T192
Test name
Test status
Simulation time 124164575 ps
CPU time 2.81 seconds
Started Mar 24 01:14:47 PM PDT 24
Finished Mar 24 01:14:50 PM PDT 24
Peak memory 233056 kb
Host smart-2f1f73a2-0081-4237-a300-287e5b269eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183660411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.1183660411
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.2737542907
Short name T871
Test name
Test status
Simulation time 41241083 ps
CPU time 0.73 seconds
Started Mar 24 01:12:48 PM PDT 24
Finished Mar 24 01:12:49 PM PDT 24
Peak memory 205740 kb
Host smart-59974f27-f423-41dc-beb7-b9de020dca98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737542907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.2
737542907
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.3595507449
Short name T790
Test name
Test status
Simulation time 156146701 ps
CPU time 2.96 seconds
Started Mar 24 01:12:51 PM PDT 24
Finished Mar 24 01:12:54 PM PDT 24
Peak memory 220192 kb
Host smart-6c8f9d16-321b-4344-a61d-e55b67bc6cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595507449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.3595507449
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.4188614082
Short name T313
Test name
Test status
Simulation time 64972582 ps
CPU time 0.77 seconds
Started Mar 24 01:12:41 PM PDT 24
Finished Mar 24 01:12:42 PM PDT 24
Peak memory 206816 kb
Host smart-dfbce9b1-3d12-44d1-91f5-c087a5ae2398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188614082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.4188614082
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.2070879365
Short name T136
Test name
Test status
Simulation time 22781441099 ps
CPU time 87.89 seconds
Started Mar 24 01:12:48 PM PDT 24
Finished Mar 24 01:14:16 PM PDT 24
Peak memory 264684 kb
Host smart-6101b829-1f2e-43fe-8420-89944598a3c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070879365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.2070879365
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.646713294
Short name T786
Test name
Test status
Simulation time 12915922166 ps
CPU time 77.07 seconds
Started Mar 24 01:12:47 PM PDT 24
Finished Mar 24 01:14:05 PM PDT 24
Peak memory 239784 kb
Host smart-c160a95a-756d-42f7-8f40-fc63726e339e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646713294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.646713294
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.1022764421
Short name T899
Test name
Test status
Simulation time 161371598755 ps
CPU time 315.43 seconds
Started Mar 24 01:12:51 PM PDT 24
Finished Mar 24 01:18:07 PM PDT 24
Peak memory 274164 kb
Host smart-170b90e3-2d31-4315-bd94-f07d385d7b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022764421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.1022764421
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.4171655699
Short name T344
Test name
Test status
Simulation time 6599035458 ps
CPU time 42.25 seconds
Started Mar 24 01:12:53 PM PDT 24
Finished Mar 24 01:13:35 PM PDT 24
Peak memory 237988 kb
Host smart-30b79185-1f7d-4814-8a4c-ec9d782c21c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171655699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.4171655699
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.3216279671
Short name T644
Test name
Test status
Simulation time 2129350520 ps
CPU time 7.66 seconds
Started Mar 24 01:12:51 PM PDT 24
Finished Mar 24 01:12:59 PM PDT 24
Peak memory 218728 kb
Host smart-c60a5de0-8bdc-4cdb-b124-97a9c92b6d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216279671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.3216279671
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.2459035620
Short name T944
Test name
Test status
Simulation time 2859106103 ps
CPU time 11.68 seconds
Started Mar 24 01:12:40 PM PDT 24
Finished Mar 24 01:12:52 PM PDT 24
Peak memory 241276 kb
Host smart-100d8c3b-525d-4428-acf2-ea5ce556c02f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459035620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.2459035620
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.1546199743
Short name T762
Test name
Test status
Simulation time 8548031564 ps
CPU time 12.21 seconds
Started Mar 24 01:12:54 PM PDT 24
Finished Mar 24 01:13:06 PM PDT 24
Peak memory 233160 kb
Host smart-27249e32-b9e1-431e-abc9-3691abb87627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546199743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.1546199743
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.806719049
Short name T831
Test name
Test status
Simulation time 45122758545 ps
CPU time 21.59 seconds
Started Mar 24 01:12:52 PM PDT 24
Finished Mar 24 01:13:14 PM PDT 24
Peak memory 228252 kb
Host smart-d566746a-0e1d-46b4-b250-e3952f2c5811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806719049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.806719049
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_ram_cfg.613713042
Short name T768
Test name
Test status
Simulation time 17752348 ps
CPU time 0.77 seconds
Started Mar 24 01:12:39 PM PDT 24
Finished Mar 24 01:12:40 PM PDT 24
Peak memory 216544 kb
Host smart-f2802317-39ed-4edf-8e1b-8281a792385d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613713042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_ram_cfg.613713042
Directory /workspace/5.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.325945987
Short name T741
Test name
Test status
Simulation time 236048867 ps
CPU time 3.44 seconds
Started Mar 24 01:12:46 PM PDT 24
Finished Mar 24 01:12:50 PM PDT 24
Peak memory 220268 kb
Host smart-378dde3c-4a44-490b-b264-84f8875626c4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=325945987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direc
t.325945987
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.1756503599
Short name T576
Test name
Test status
Simulation time 148010941766 ps
CPU time 516.87 seconds
Started Mar 24 01:12:45 PM PDT 24
Finished Mar 24 01:21:22 PM PDT 24
Peak memory 274156 kb
Host smart-379868af-0018-49ad-bea7-ca161c6a8ea6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756503599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.1756503599
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.257328601
Short name T849
Test name
Test status
Simulation time 2453683162 ps
CPU time 9.44 seconds
Started Mar 24 01:12:49 PM PDT 24
Finished Mar 24 01:12:58 PM PDT 24
Peak memory 216724 kb
Host smart-7daf8c5c-fc58-4ddb-b0c5-4e0bf4b28e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257328601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.257328601
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.2317085951
Short name T710
Test name
Test status
Simulation time 27976506124 ps
CPU time 18.09 seconds
Started Mar 24 01:12:50 PM PDT 24
Finished Mar 24 01:13:08 PM PDT 24
Peak memory 216604 kb
Host smart-31adf726-07d8-4fa9-8c2f-1b7e807f9afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317085951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.2317085951
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.1416435344
Short name T347
Test name
Test status
Simulation time 34701943 ps
CPU time 1.14 seconds
Started Mar 24 01:12:51 PM PDT 24
Finished Mar 24 01:12:52 PM PDT 24
Peak memory 207800 kb
Host smart-9dc13ce9-3ea4-4d57-ba11-acd824258b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416435344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.1416435344
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.3201722947
Short name T409
Test name
Test status
Simulation time 151590337 ps
CPU time 0.87 seconds
Started Mar 24 01:12:52 PM PDT 24
Finished Mar 24 01:12:53 PM PDT 24
Peak memory 206544 kb
Host smart-ec55d57d-c6ae-41b9-85f3-e20ebd635526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201722947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.3201722947
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.3143000880
Short name T197
Test name
Test status
Simulation time 21778647636 ps
CPU time 20.85 seconds
Started Mar 24 01:12:44 PM PDT 24
Finished Mar 24 01:13:05 PM PDT 24
Peak memory 228500 kb
Host smart-0a101699-d9da-40fc-8124-ffb48704eee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143000880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.3143000880
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.2310680230
Short name T305
Test name
Test status
Simulation time 13844434 ps
CPU time 0.72 seconds
Started Mar 24 01:12:49 PM PDT 24
Finished Mar 24 01:12:49 PM PDT 24
Peak memory 205760 kb
Host smart-1b14eaf9-495c-49b1-a2da-6429d0ee85df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310680230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.2
310680230
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.2255281772
Short name T641
Test name
Test status
Simulation time 660816231 ps
CPU time 4.65 seconds
Started Mar 24 01:12:58 PM PDT 24
Finished Mar 24 01:13:02 PM PDT 24
Peak memory 234040 kb
Host smart-e2af0dfb-7e7e-4bdb-85cd-831cbb8f7f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255281772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.2255281772
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.3346905583
Short name T317
Test name
Test status
Simulation time 37587556 ps
CPU time 0.78 seconds
Started Mar 24 01:12:51 PM PDT 24
Finished Mar 24 01:12:52 PM PDT 24
Peak memory 206776 kb
Host smart-ce6c3cc0-57c5-4217-b441-7648ba16f815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346905583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.3346905583
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.1495808161
Short name T147
Test name
Test status
Simulation time 290768445570 ps
CPU time 66.9 seconds
Started Mar 24 01:12:49 PM PDT 24
Finished Mar 24 01:13:56 PM PDT 24
Peak memory 233088 kb
Host smart-a47cbdd6-dd4a-43b2-9697-474ebc61e182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495808161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.1495808161
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.1206449238
Short name T801
Test name
Test status
Simulation time 9232221835 ps
CPU time 19.48 seconds
Started Mar 24 01:12:47 PM PDT 24
Finished Mar 24 01:13:07 PM PDT 24
Peak memory 221296 kb
Host smart-c80ded14-a6a0-4fcf-a52e-cbc875aeb215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206449238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.1206449238
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.2547890247
Short name T178
Test name
Test status
Simulation time 10672577172 ps
CPU time 68.92 seconds
Started Mar 24 01:12:48 PM PDT 24
Finished Mar 24 01:13:57 PM PDT 24
Peak memory 253928 kb
Host smart-eb1b6774-3981-453f-87b8-4b9f84c9311c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547890247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.2547890247
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_intercept.1826940430
Short name T433
Test name
Test status
Simulation time 1964684408 ps
CPU time 8.94 seconds
Started Mar 24 01:12:52 PM PDT 24
Finished Mar 24 01:13:01 PM PDT 24
Peak memory 233996 kb
Host smart-23ad6314-5662-4212-94f8-403a7968c8c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826940430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.1826940430
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.4005656412
Short name T921
Test name
Test status
Simulation time 3773366832 ps
CPU time 12.59 seconds
Started Mar 24 01:12:55 PM PDT 24
Finished Mar 24 01:13:08 PM PDT 24
Peak memory 236376 kb
Host smart-e6f03baa-8c06-423b-8710-1fffe0016a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005656412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.4005656412
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.4098895963
Short name T855
Test name
Test status
Simulation time 3478006886 ps
CPU time 11.11 seconds
Started Mar 24 01:12:52 PM PDT 24
Finished Mar 24 01:13:03 PM PDT 24
Peak memory 233108 kb
Host smart-a3c194b3-85f8-473b-adc4-3ccbe8c2a7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098895963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.4098895963
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.483153140
Short name T309
Test name
Test status
Simulation time 262175155 ps
CPU time 3.72 seconds
Started Mar 24 01:12:41 PM PDT 24
Finished Mar 24 01:12:45 PM PDT 24
Peak memory 219112 kb
Host smart-313268e5-a5f3-4cd2-bdc5-c5dcaaa95335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483153140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.483153140
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_ram_cfg.75361278
Short name T297
Test name
Test status
Simulation time 16149364 ps
CPU time 0.74 seconds
Started Mar 24 01:12:43 PM PDT 24
Finished Mar 24 01:12:44 PM PDT 24
Peak memory 216588 kb
Host smart-357836e8-1984-45ca-9b7e-ca7d94b29a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75361278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_ram_cfg.75361278
Directory /workspace/6.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.1675959082
Short name T438
Test name
Test status
Simulation time 357708738 ps
CPU time 3.93 seconds
Started Mar 24 01:12:39 PM PDT 24
Finished Mar 24 01:12:43 PM PDT 24
Peak memory 222592 kb
Host smart-c595c7d6-c0bb-4f62-9d9d-c4771794d95b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1675959082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.1675959082
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.3545330510
Short name T464
Test name
Test status
Simulation time 534562851157 ps
CPU time 495.78 seconds
Started Mar 24 01:12:43 PM PDT 24
Finished Mar 24 01:20:59 PM PDT 24
Peak memory 265980 kb
Host smart-d32da584-3fcc-4835-8633-ebc33dffb54b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545330510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.3545330510
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.71540808
Short name T246
Test name
Test status
Simulation time 1270329200 ps
CPU time 13.59 seconds
Started Mar 24 01:12:52 PM PDT 24
Finished Mar 24 01:13:06 PM PDT 24
Peak memory 216588 kb
Host smart-976e8588-ff54-4a86-8dfa-c20fa5f4a265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71540808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.71540808
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.1226105499
Short name T773
Test name
Test status
Simulation time 5170718238 ps
CPU time 8.57 seconds
Started Mar 24 01:12:42 PM PDT 24
Finished Mar 24 01:12:50 PM PDT 24
Peak memory 216576 kb
Host smart-b36c6301-4e01-46fd-badd-b935cae662ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226105499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.1226105499
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.1654718565
Short name T365
Test name
Test status
Simulation time 32148760 ps
CPU time 0.75 seconds
Started Mar 24 01:12:56 PM PDT 24
Finished Mar 24 01:12:57 PM PDT 24
Peak memory 206088 kb
Host smart-75ea913d-b7f7-41c2-ae93-a4a1af13ddbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654718565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.1654718565
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.2966039895
Short name T817
Test name
Test status
Simulation time 132224538 ps
CPU time 0.92 seconds
Started Mar 24 01:12:54 PM PDT 24
Finished Mar 24 01:12:55 PM PDT 24
Peak memory 206032 kb
Host smart-e683f950-f87c-4603-9d16-92fb741a3f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966039895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.2966039895
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.1784891473
Short name T564
Test name
Test status
Simulation time 7199718629 ps
CPU time 11.22 seconds
Started Mar 24 01:12:50 PM PDT 24
Finished Mar 24 01:13:01 PM PDT 24
Peak memory 241212 kb
Host smart-be3891f8-38c2-4027-a448-de5baa919648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784891473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.1784891473
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.2359550019
Short name T863
Test name
Test status
Simulation time 21032588 ps
CPU time 0.72 seconds
Started Mar 24 01:12:54 PM PDT 24
Finished Mar 24 01:12:54 PM PDT 24
Peak memory 205700 kb
Host smart-0c6e3d05-b424-4c28-9a53-278d7f2c4408
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359550019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.2
359550019
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.2115973852
Short name T326
Test name
Test status
Simulation time 551139639 ps
CPU time 4.3 seconds
Started Mar 24 01:12:38 PM PDT 24
Finished Mar 24 01:12:43 PM PDT 24
Peak memory 234008 kb
Host smart-ffb9ffcd-4412-44c0-8571-efec9023f731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115973852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.2115973852
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.4230012131
Short name T560
Test name
Test status
Simulation time 51883236 ps
CPU time 0.74 seconds
Started Mar 24 01:12:43 PM PDT 24
Finished Mar 24 01:12:44 PM PDT 24
Peak memory 205692 kb
Host smart-55e4182e-94d3-4022-a0ec-8b4cb2e7d4c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230012131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.4230012131
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.3303500907
Short name T512
Test name
Test status
Simulation time 98630256788 ps
CPU time 40.24 seconds
Started Mar 24 01:12:41 PM PDT 24
Finished Mar 24 01:13:21 PM PDT 24
Peak memory 233088 kb
Host smart-97fce547-1edb-45cc-8374-ac327bbb2287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303500907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.3303500907
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.4187790068
Short name T659
Test name
Test status
Simulation time 19843919661 ps
CPU time 77.03 seconds
Started Mar 24 01:12:51 PM PDT 24
Finished Mar 24 01:14:09 PM PDT 24
Peak memory 251844 kb
Host smart-f98a86ef-192f-4a74-bcbe-75df3eae7c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187790068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.4187790068
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.1210579446
Short name T461
Test name
Test status
Simulation time 7078490069 ps
CPU time 82.4 seconds
Started Mar 24 01:13:05 PM PDT 24
Finished Mar 24 01:14:28 PM PDT 24
Peak memory 241340 kb
Host smart-b55f72e3-635c-4bf6-baf0-290c55886057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210579446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.1210579446
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.4036626711
Short name T691
Test name
Test status
Simulation time 20971206587 ps
CPU time 73.59 seconds
Started Mar 24 01:12:48 PM PDT 24
Finished Mar 24 01:14:01 PM PDT 24
Peak memory 250664 kb
Host smart-db81ab21-d7ee-4b51-a4d2-f4572936a079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036626711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.4036626711
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.2750988023
Short name T494
Test name
Test status
Simulation time 4748201416 ps
CPU time 5.41 seconds
Started Mar 24 01:12:43 PM PDT 24
Finished Mar 24 01:12:48 PM PDT 24
Peak memory 224832 kb
Host smart-28f0e31e-6947-4f7d-9555-17460101795d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750988023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.2750988023
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.2701918249
Short name T189
Test name
Test status
Simulation time 369801020 ps
CPU time 4.52 seconds
Started Mar 24 01:12:46 PM PDT 24
Finished Mar 24 01:12:51 PM PDT 24
Peak memory 218848 kb
Host smart-a8d1324f-beb2-4499-b745-92a6535114ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701918249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.2701918249
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.159699051
Short name T420
Test name
Test status
Simulation time 174338939 ps
CPU time 3 seconds
Started Mar 24 01:12:43 PM PDT 24
Finished Mar 24 01:12:46 PM PDT 24
Peak memory 219964 kb
Host smart-13aa34fd-2510-4284-ba6e-982d70a78130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159699051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.
159699051
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.1339508165
Short name T432
Test name
Test status
Simulation time 2876349520 ps
CPU time 7.79 seconds
Started Mar 24 01:12:56 PM PDT 24
Finished Mar 24 01:13:04 PM PDT 24
Peak memory 227552 kb
Host smart-5e1e6b47-1fe0-4a41-b05e-acbc49336249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339508165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.1339508165
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_ram_cfg.2412811870
Short name T8
Test name
Test status
Simulation time 27932629 ps
CPU time 0.73 seconds
Started Mar 24 01:12:46 PM PDT 24
Finished Mar 24 01:12:47 PM PDT 24
Peak memory 216492 kb
Host smart-443adb6e-ff10-4340-acbd-c1fc33554600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412811870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_ram_cfg.2412811870
Directory /workspace/7.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.543404201
Short name T727
Test name
Test status
Simulation time 4679497979 ps
CPU time 6.81 seconds
Started Mar 24 01:12:51 PM PDT 24
Finished Mar 24 01:12:58 PM PDT 24
Peak memory 223660 kb
Host smart-be4349e8-f70b-4e35-b8a0-899642740888
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=543404201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direc
t.543404201
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.2448767442
Short name T218
Test name
Test status
Simulation time 102628731785 ps
CPU time 406.65 seconds
Started Mar 24 01:13:07 PM PDT 24
Finished Mar 24 01:19:53 PM PDT 24
Peak memory 261184 kb
Host smart-b203a220-0d7e-4434-af8a-3b39e636380e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448767442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.2448767442
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.3342658241
Short name T321
Test name
Test status
Simulation time 6932039744 ps
CPU time 14.18 seconds
Started Mar 24 01:12:49 PM PDT 24
Finished Mar 24 01:13:03 PM PDT 24
Peak memory 220008 kb
Host smart-41860eb4-daa6-4787-b87a-03f22ce09136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342658241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.3342658241
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.1289633469
Short name T782
Test name
Test status
Simulation time 1416773046 ps
CPU time 2.82 seconds
Started Mar 24 01:12:47 PM PDT 24
Finished Mar 24 01:12:50 PM PDT 24
Peak memory 216572 kb
Host smart-9de05c76-1573-49d5-a304-958ba15e75ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289633469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.1289633469
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.1024134444
Short name T261
Test name
Test status
Simulation time 165632364 ps
CPU time 2.13 seconds
Started Mar 24 01:12:46 PM PDT 24
Finished Mar 24 01:12:49 PM PDT 24
Peak memory 216656 kb
Host smart-bab58a42-cd0b-43e4-8972-51cc8b901c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024134444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.1024134444
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.735255031
Short name T266
Test name
Test status
Simulation time 164471616 ps
CPU time 0.98 seconds
Started Mar 24 01:12:41 PM PDT 24
Finished Mar 24 01:12:42 PM PDT 24
Peak memory 207072 kb
Host smart-3775e076-f12a-4eda-9de2-28c0e326daee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735255031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.735255031
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.2722872687
Short name T678
Test name
Test status
Simulation time 3155160728 ps
CPU time 4.37 seconds
Started Mar 24 01:12:45 PM PDT 24
Finished Mar 24 01:12:50 PM PDT 24
Peak memory 235832 kb
Host smart-36f27fc3-ae82-49e6-91c4-ab304eb3cfa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722872687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.2722872687
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.517186985
Short name T255
Test name
Test status
Simulation time 14539542 ps
CPU time 0.71 seconds
Started Mar 24 01:12:46 PM PDT 24
Finished Mar 24 01:12:47 PM PDT 24
Peak memory 205728 kb
Host smart-0a1379ee-81d0-4aa0-8212-a4315d856f1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517186985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.517186985
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.3996636031
Short name T716
Test name
Test status
Simulation time 9280160087 ps
CPU time 7.38 seconds
Started Mar 24 01:12:49 PM PDT 24
Finished Mar 24 01:12:56 PM PDT 24
Peak memory 224896 kb
Host smart-5ad9f13d-93f9-4acd-a6c7-04aa9467292c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996636031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.3996636031
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.3106091770
Short name T905
Test name
Test status
Simulation time 21836403 ps
CPU time 0.77 seconds
Started Mar 24 01:12:51 PM PDT 24
Finished Mar 24 01:12:52 PM PDT 24
Peak memory 206744 kb
Host smart-ef60ca49-a4a1-4891-b267-eb14db789c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106091770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.3106091770
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.1522023421
Short name T402
Test name
Test status
Simulation time 21807178383 ps
CPU time 15.03 seconds
Started Mar 24 01:12:53 PM PDT 24
Finished Mar 24 01:13:08 PM PDT 24
Peak memory 234852 kb
Host smart-76b98079-f293-408f-b03d-e0be4b214a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522023421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.1522023421
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.1543149486
Short name T489
Test name
Test status
Simulation time 149474407066 ps
CPU time 124.68 seconds
Started Mar 24 01:12:49 PM PDT 24
Finished Mar 24 01:14:53 PM PDT 24
Peak memory 251036 kb
Host smart-e6712b31-f45e-474d-866b-eac6a9a2bc02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543149486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.1543149486
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.2973956985
Short name T163
Test name
Test status
Simulation time 54530093577 ps
CPU time 80.24 seconds
Started Mar 24 01:12:56 PM PDT 24
Finished Mar 24 01:14:18 PM PDT 24
Peak memory 234756 kb
Host smart-adcd3428-cdb1-4741-86ec-916e48b4b8d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973956985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.2973956985
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.2728040106
Short name T619
Test name
Test status
Simulation time 5850800425 ps
CPU time 27.69 seconds
Started Mar 24 01:12:49 PM PDT 24
Finished Mar 24 01:13:17 PM PDT 24
Peak memory 233084 kb
Host smart-8baa4fb9-6f43-4ffc-ad41-f96c8e3f5ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728040106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.2728040106
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.4038932441
Short name T845
Test name
Test status
Simulation time 3339418537 ps
CPU time 6.01 seconds
Started Mar 24 01:12:50 PM PDT 24
Finished Mar 24 01:12:56 PM PDT 24
Peak memory 233864 kb
Host smart-3f3345f3-f378-42d3-8826-e1dbeb07112e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038932441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.4038932441
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.1410589060
Short name T397
Test name
Test status
Simulation time 2925294890 ps
CPU time 11.27 seconds
Started Mar 24 01:12:54 PM PDT 24
Finished Mar 24 01:13:05 PM PDT 24
Peak memory 233012 kb
Host smart-73df8e6a-b9d3-43c4-a4af-21ee6b186d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410589060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.1410589060
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.3173528505
Short name T789
Test name
Test status
Simulation time 2801218818 ps
CPU time 3.62 seconds
Started Mar 24 01:12:47 PM PDT 24
Finished Mar 24 01:12:51 PM PDT 24
Peak memory 218744 kb
Host smart-a55a52c2-9fb5-4b39-9714-17055ebfc61f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173528505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.3173528505
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.2302587259
Short name T394
Test name
Test status
Simulation time 2596897058 ps
CPU time 13.96 seconds
Started Mar 24 01:12:46 PM PDT 24
Finished Mar 24 01:13:00 PM PDT 24
Peak memory 233772 kb
Host smart-9f32e247-71e7-45c5-a1bb-786e093d9616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302587259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.2302587259
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_ram_cfg.1553878112
Short name T796
Test name
Test status
Simulation time 36085075 ps
CPU time 0.73 seconds
Started Mar 24 01:12:53 PM PDT 24
Finished Mar 24 01:12:54 PM PDT 24
Peak memory 216524 kb
Host smart-083d6f96-8339-461a-8bce-b3cec21d094f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553878112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_ram_cfg.1553878112
Directory /workspace/8.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.212966719
Short name T700
Test name
Test status
Simulation time 113053239 ps
CPU time 3.83 seconds
Started Mar 24 01:12:48 PM PDT 24
Finished Mar 24 01:12:52 PM PDT 24
Peak memory 223512 kb
Host smart-dc8bf567-1a75-4cf6-8c67-974922437299
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=212966719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direc
t.212966719
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.3515485390
Short name T656
Test name
Test status
Simulation time 52279842 ps
CPU time 1.07 seconds
Started Mar 24 01:12:52 PM PDT 24
Finished Mar 24 01:12:53 PM PDT 24
Peak memory 207448 kb
Host smart-61ed2260-385e-4629-9784-a339605397ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515485390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.3515485390
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.3040198216
Short name T427
Test name
Test status
Simulation time 10787648709 ps
CPU time 56.57 seconds
Started Mar 24 01:12:47 PM PDT 24
Finished Mar 24 01:13:44 PM PDT 24
Peak memory 216748 kb
Host smart-8842abec-6dbb-490b-b1a0-7bc22b087ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040198216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.3040198216
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.3236242512
Short name T639
Test name
Test status
Simulation time 4782439925 ps
CPU time 13.62 seconds
Started Mar 24 01:12:50 PM PDT 24
Finished Mar 24 01:13:03 PM PDT 24
Peak memory 216696 kb
Host smart-ca4b456a-f7ac-47d9-994b-0c97a762f04e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236242512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.3236242512
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.386766279
Short name T251
Test name
Test status
Simulation time 80634176 ps
CPU time 1.06 seconds
Started Mar 24 01:12:57 PM PDT 24
Finished Mar 24 01:12:59 PM PDT 24
Peak memory 207280 kb
Host smart-966d2037-bed3-43f2-8195-0d0f8135a558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386766279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.386766279
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.714980086
Short name T870
Test name
Test status
Simulation time 46764608 ps
CPU time 0.94 seconds
Started Mar 24 01:12:49 PM PDT 24
Finished Mar 24 01:12:50 PM PDT 24
Peak memory 207052 kb
Host smart-bd368a60-7667-496a-b6c0-7e00e0e1d36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714980086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.714980086
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.3365772492
Short name T283
Test name
Test status
Simulation time 500781550 ps
CPU time 4.29 seconds
Started Mar 24 01:12:54 PM PDT 24
Finished Mar 24 01:12:59 PM PDT 24
Peak memory 234672 kb
Host smart-e37c075d-0302-4bd1-95f4-b6c540c93706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365772492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.3365772492
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.3877056789
Short name T389
Test name
Test status
Simulation time 34929885 ps
CPU time 0.69 seconds
Started Mar 24 01:13:07 PM PDT 24
Finished Mar 24 01:13:07 PM PDT 24
Peak memory 205140 kb
Host smart-dc18e654-2e87-4f20-b165-ece2b12b1487
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877056789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.3
877056789
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.781410804
Short name T685
Test name
Test status
Simulation time 35904844 ps
CPU time 2.53 seconds
Started Mar 24 01:12:56 PM PDT 24
Finished Mar 24 01:13:00 PM PDT 24
Peak memory 233928 kb
Host smart-388c97b4-1005-4868-a995-63686cea0ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781410804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.781410804
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.953028820
Short name T403
Test name
Test status
Simulation time 27373637 ps
CPU time 0.77 seconds
Started Mar 24 01:12:48 PM PDT 24
Finished Mar 24 01:12:49 PM PDT 24
Peak memory 206824 kb
Host smart-10c95248-f1c9-4d7b-9a96-3140888d97c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953028820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.953028820
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.1581844237
Short name T213
Test name
Test status
Simulation time 8566366025 ps
CPU time 75.97 seconds
Started Mar 24 01:12:52 PM PDT 24
Finished Mar 24 01:14:08 PM PDT 24
Peak memory 265676 kb
Host smart-6f27cc28-46bc-4513-aa14-b028dfd2774b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581844237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.1581844237
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.467900669
Short name T825
Test name
Test status
Simulation time 7995794151 ps
CPU time 48.47 seconds
Started Mar 24 01:12:46 PM PDT 24
Finished Mar 24 01:13:34 PM PDT 24
Peak memory 250524 kb
Host smart-1b5de82a-28ed-4beb-bde1-37107b5c8d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467900669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.467900669
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.507584949
Short name T945
Test name
Test status
Simulation time 129963814459 ps
CPU time 227.5 seconds
Started Mar 24 01:12:46 PM PDT 24
Finished Mar 24 01:16:34 PM PDT 24
Peak memory 240464 kb
Host smart-f534f8fd-d0de-4afb-a154-88fa6ead0c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507584949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.
507584949
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.3080688299
Short name T577
Test name
Test status
Simulation time 1084040137 ps
CPU time 12.82 seconds
Started Mar 24 01:12:51 PM PDT 24
Finished Mar 24 01:13:04 PM PDT 24
Peak memory 233044 kb
Host smart-86bb9749-1188-4982-9966-c226a78f85df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080688299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.3080688299
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.1187763266
Short name T164
Test name
Test status
Simulation time 192591980 ps
CPU time 2.4 seconds
Started Mar 24 01:12:52 PM PDT 24
Finished Mar 24 01:12:54 PM PDT 24
Peak memory 233992 kb
Host smart-1c2c5694-1b93-403c-b701-f026a51a0f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187763266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.1187763266
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.1746663850
Short name T492
Test name
Test status
Simulation time 3783728264 ps
CPU time 6.29 seconds
Started Mar 24 01:12:46 PM PDT 24
Finished Mar 24 01:12:52 PM PDT 24
Peak memory 237752 kb
Host smart-69a06216-b5ab-4a12-9de9-9479b1ebc4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746663850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.1746663850
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.523693148
Short name T772
Test name
Test status
Simulation time 10853389603 ps
CPU time 16.47 seconds
Started Mar 24 01:12:55 PM PDT 24
Finished Mar 24 01:13:11 PM PDT 24
Peak memory 234048 kb
Host smart-e1dc375f-ad26-4ecc-a529-84173b800f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523693148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.
523693148
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.260028374
Short name T551
Test name
Test status
Simulation time 3914453775 ps
CPU time 14.65 seconds
Started Mar 24 01:12:47 PM PDT 24
Finished Mar 24 01:13:02 PM PDT 24
Peak memory 235636 kb
Host smart-f298a0f7-9f34-4a77-8a45-45056131e1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260028374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.260028374
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_ram_cfg.2625644798
Short name T429
Test name
Test status
Simulation time 31959975 ps
CPU time 0.74 seconds
Started Mar 24 01:12:52 PM PDT 24
Finished Mar 24 01:12:53 PM PDT 24
Peak memory 216452 kb
Host smart-54ede45e-f181-427d-b037-c1c3f0d43de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625644798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_ram_cfg.2625644798
Directory /workspace/9.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.3557313894
Short name T906
Test name
Test status
Simulation time 378276725 ps
CPU time 3.19 seconds
Started Mar 24 01:12:51 PM PDT 24
Finished Mar 24 01:12:55 PM PDT 24
Peak memory 220340 kb
Host smart-321edb66-0e3a-4105-b004-a4417f4515f9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3557313894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.3557313894
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.3976585761
Short name T667
Test name
Test status
Simulation time 6586232581 ps
CPU time 49.18 seconds
Started Mar 24 01:12:55 PM PDT 24
Finished Mar 24 01:13:44 PM PDT 24
Peak memory 216756 kb
Host smart-5fb0a625-a22f-4797-b6e9-a3061bb94636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976585761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.3976585761
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.4033621556
Short name T568
Test name
Test status
Simulation time 48873733170 ps
CPU time 16.53 seconds
Started Mar 24 01:12:46 PM PDT 24
Finished Mar 24 01:13:03 PM PDT 24
Peak memory 216660 kb
Host smart-76b1812d-414a-413d-9159-214fd0b467ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033621556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.4033621556
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.1882047045
Short name T364
Test name
Test status
Simulation time 263551469 ps
CPU time 6.84 seconds
Started Mar 24 01:12:50 PM PDT 24
Finished Mar 24 01:12:57 PM PDT 24
Peak memory 216628 kb
Host smart-295cee7f-a23a-4df2-8af6-5480879c1f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882047045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.1882047045
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.4271627321
Short name T417
Test name
Test status
Simulation time 142051667 ps
CPU time 0.85 seconds
Started Mar 24 01:12:52 PM PDT 24
Finished Mar 24 01:12:53 PM PDT 24
Peak memory 206052 kb
Host smart-235b1193-f289-4938-98ab-f9ef2bbd2ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271627321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.4271627321
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.78996553
Short name T889
Test name
Test status
Simulation time 4788111444 ps
CPU time 13.75 seconds
Started Mar 24 01:12:55 PM PDT 24
Finished Mar 24 01:13:09 PM PDT 24
Peak memory 228588 kb
Host smart-b793bfbc-6358-4029-b2ad-f2729e6a390b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78996553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.78996553
Directory /workspace/9.spi_device_upload/latest
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