Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6213406	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

6626490

1

T1

46

T2

509

T3

33098

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	8307827	1			T1	1		T2	1		T3	42252
values[0x0]	2264146	1			T1	25		T2	310		T3	12985
values[0x1]	2267923	1			T1	33		T2	304		T3	12692

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4510271	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

8329625

1

T1

48

T2

544

T3

42813

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	51853	1			T3	284		T4	3		T5	6
valid_sources[0x01]	48113	1			T3	211		T4	5		T5	9
valid_sources[0x02]	50774	1			T2	3		T3	373		T4	3
valid_sources[0x03]	48129	1			T2	5		T3	220		T4	3
valid_sources[0x04]	47406	1			T3	363		T4	10		T5	2
valid_sources[0x05]	45548	1			T3	328		T4	7		T5	7
valid_sources[0x06]	50751	1			T3	186		T4	3		T5	7
valid_sources[0x07]	49173	1			T2	1		T3	311		T4	1
valid_sources[0x08]	47288	1			T2	3		T3	291		T4	2
valid_sources[0x09]	47643	1			T2	8		T3	228		T4	5
valid_sources[0x0a]	50062	1			T3	283		T5	6		T6	1
valid_sources[0x0b]	52741	1			T3	246		T4	13		T6	2
valid_sources[0x0c]	60591	1			T2	10		T3	271		T4	3
valid_sources[0x0d]	53519	1			T3	303		T4	5		T5	1
valid_sources[0x0e]	49517	1			T3	295		T4	4		T5	19
valid_sources[0x0f]	49382	1			T3	310		T4	3		T5	1
valid_sources[0x10]	49304	1			T3	254		T4	5		T5	4
valid_sources[0x11]	50378	1			T1	4		T2	17		T3	210
valid_sources[0x12]	57862	1			T3	276		T4	1		T6	1
valid_sources[0x13]	47693	1			T3	329		T4	8		T10	5
valid_sources[0x14]	47181	1			T3	271		T4	11		T5	4
valid_sources[0x15]	47901	1			T3	301		T4	4		T5	2
valid_sources[0x16]	47175	1			T2	10		T3	318		T4	12
valid_sources[0x17]	53035	1			T2	1		T3	277		T4	5
valid_sources[0x18]	48514	1			T3	281		T4	1		T5	2
valid_sources[0x19]	45217	1			T3	244		T4	4		T5	2
valid_sources[0x1a]	51068	1			T3	288		T4	2		T5	2
valid_sources[0x1b]	48781	1			T3	287		T4	8		T5	7
valid_sources[0x1c]	48534	1			T3	325		T4	7		T5	2
valid_sources[0x1d]	52557	1			T3	259		T4	8		T5	4
valid_sources[0x1e]	48273	1			T2	4		T3	265		T4	5
valid_sources[0x1f]	49363	1			T1	2		T2	1		T3	281
valid_sources[0x20]	46058	1			T3	188		T4	10		T5	2
valid_sources[0x21]	50778	1			T3	150		T4	3		T5	1
valid_sources[0x22]	48539	1			T3	271		T4	5		T5	5
valid_sources[0x23]	48142	1			T3	336		T4	5		T6	6
valid_sources[0x24]	50523	1			T3	278		T4	1		T5	1
valid_sources[0x25]	48807	1			T3	256		T4	9		T5	6
valid_sources[0x26]	51685	1			T3	281		T4	5		T5	2
valid_sources[0x27]	51070	1			T2	1		T3	266		T4	9
valid_sources[0x28]	51150	1			T2	1		T3	204		T4	3
valid_sources[0x29]	50465	1			T2	5		T3	203		T4	4
valid_sources[0x2a]	49488	1			T3	280		T4	6		T5	8
valid_sources[0x2b]	49315	1			T2	9		T3	201		T4	2
valid_sources[0x2c]	54388	1			T3	308		T4	3		T5	3
valid_sources[0x2d]	47582	1			T3	261		T4	4		T6	3
valid_sources[0x2e]	46132	1			T3	190		T4	9		T5	9
valid_sources[0x2f]	51599	1			T3	318		T4	5		T5	5
valid_sources[0x30]	49452	1			T2	8		T3	331		T4	8
valid_sources[0x31]	49317	1			T2	3		T3	225		T4	2
valid_sources[0x32]	49308	1			T3	267		T4	3		T6	4
valid_sources[0x33]	52112	1			T3	221		T4	2		T5	6
valid_sources[0x34]	51177	1			T3	301		T4	3		T10	7
valid_sources[0x35]	55041	1			T3	252		T4	2		T6	4
valid_sources[0x36]	52734	1			T2	1		T3	230		T4	3
valid_sources[0x37]	52107	1			T3	347		T4	5		T5	15
valid_sources[0x38]	50911	1			T2	1		T3	402		T4	4
valid_sources[0x39]	50282	1			T3	197		T4	1		T6	3
valid_sources[0x3a]	45690	1			T2	27		T3	284		T4	9
valid_sources[0x3b]	49274	1			T2	11		T3	212		T4	7
valid_sources[0x3c]	47440	1			T1	3		T3	244		T4	4
valid_sources[0x3d]	50079	1			T2	18		T3	194		T4	7
valid_sources[0x3e]	46536	1			T3	171		T4	1		T5	9
valid_sources[0x3f]	47390	1			T1	6		T2	2		T3	309
valid_sources[0x40]	49605	1			T3	363		T4	6		T6	10
valid_sources[0x41]	55270	1			T3	225		T4	4		T5	2
valid_sources[0x42]	46863	1			T3	216		T4	5		T5	13
valid_sources[0x43]	53607	1			T3	270		T4	7		T5	6
valid_sources[0x44]	48325	1			T3	227		T4	1		T5	5
valid_sources[0x45]	52376	1			T3	331		T4	2		T5	10
valid_sources[0x46]	51612	1			T2	3		T3	278		T4	4
valid_sources[0x47]	53025	1			T3	337		T4	1		T5	4
valid_sources[0x48]	47506	1			T2	14		T3	285		T4	2
valid_sources[0x49]	53147	1			T3	322		T4	6		T5	1
valid_sources[0x4a]	52965	1			T3	210		T4	4		T6	2
valid_sources[0x4b]	49874	1			T3	252		T4	6		T5	2
valid_sources[0x4c]	52985	1			T3	198		T4	3		T5	5
valid_sources[0x4d]	46478	1			T2	10		T3	230		T4	4
valid_sources[0x4e]	50165	1			T2	5		T3	358		T4	3
valid_sources[0x4f]	52420	1			T2	8		T3	280		T4	5
valid_sources[0x50]	48298	1			T2	3		T3	162		T4	5
valid_sources[0x51]	47308	1			T3	376		T4	11		T5	5
valid_sources[0x52]	48861	1			T3	199		T4	4		T5	12
valid_sources[0x53]	49228	1			T1	2		T3	298		T4	7
valid_sources[0x54]	47246	1			T3	227		T4	3		T5	8
valid_sources[0x55]	53331	1			T2	11		T3	331		T4	8
valid_sources[0x56]	48656	1			T3	442		T4	5		T5	9
valid_sources[0x57]	49532	1			T3	178		T4	3		T5	8
valid_sources[0x58]	58835	1			T2	2		T3	236		T4	8
valid_sources[0x59]	49843	1			T2	22		T3	205		T4	8
valid_sources[0x5a]	53188	1			T3	221		T4	5		T5	2
valid_sources[0x5b]	51627	1			T3	295		T4	4		T6	3
valid_sources[0x5c]	49875	1			T3	223		T4	1		T5	3
valid_sources[0x5d]	49692	1			T1	6		T3	201		T4	4
valid_sources[0x5e]	51189	1			T1	2		T2	16		T3	210
valid_sources[0x5f]	47245	1			T3	422		T4	1		T5	4
valid_sources[0x60]	46200	1			T2	8		T3	188		T4	1
valid_sources[0x61]	49598	1			T3	186		T4	6		T6	2
valid_sources[0x62]	50114	1			T3	310		T4	6		T5	5
valid_sources[0x63]	52715	1			T3	208		T4	3		T5	1
valid_sources[0x64]	47580	1			T1	5		T3	289		T4	1
valid_sources[0x65]	45432	1			T3	233		T4	3		T5	4
valid_sources[0x66]	51469	1			T2	7		T3	295		T4	5
valid_sources[0x67]	51070	1			T2	3		T3	285		T4	3
valid_sources[0x68]	48052	1			T3	305		T4	3		T5	4
valid_sources[0x69]	49132	1			T3	283		T4	5		T8	1
valid_sources[0x6a]	51683	1			T2	7		T3	311		T4	1
valid_sources[0x6b]	50746	1			T3	260		T4	2		T5	6
valid_sources[0x6c]	48567	1			T3	478		T4	5		T10	1
valid_sources[0x6d]	46996	1			T3	455		T4	3		T5	2
valid_sources[0x6e]	49347	1			T1	1		T3	265		T4	8
valid_sources[0x6f]	49248	1			T3	168		T4	3		T5	4
valid_sources[0x70]	48561	1			T1	4		T3	297		T4	4
valid_sources[0x71]	49418	1			T3	251		T4	3		T5	7
valid_sources[0x72]	49482	1			T1	1		T3	215		T4	4
valid_sources[0x73]	46331	1			T3	145		T4	7		T6	6
valid_sources[0x74]	49710	1			T3	207		T4	1		T5	2
valid_sources[0x75]	51259	1			T3	250		T4	4		T5	3
valid_sources[0x76]	47994	1			T2	3		T3	204		T4	4
valid_sources[0x77]	51131	1			T3	244		T4	5		T5	21
valid_sources[0x78]	55815	1			T2	5		T3	185		T4	4
valid_sources[0x79]	51912	1			T2	12		T3	272		T4	5
valid_sources[0x7a]	51195	1			T1	4		T3	244		T4	4
valid_sources[0x7b]	52415	1			T3	359		T4	3		T5	11
valid_sources[0x7c]	51443	1			T2	6		T3	184		T4	9
valid_sources[0x7d]	48196	1			T3	218		T4	4		T5	1
valid_sources[0x7e]	51978	1			T2	1		T3	278		T4	9
valid_sources[0x7f]	56416	1			T2	15		T3	186		T4	5
valid_sources[0x80]	50769	1			T3	157		T4	4		T5	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

2573102

1

T3

10913

T5

15

T6

20

values[0x0]

all_enables

biggest_size

2042460

1

T1

18

T2

266

T3

11327

values[0x1]

all_enables

biggest_size

2010928

1

T1

28

T2

243

T3

10858