Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

6236391

1

T1

13

T2

106

T3

34831

full_word

6627888

1

T1

46

T2

509

T3

33098

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	12863859	1			T1	59		T2	615		T3	67929
auto[TlIntgErrCmd]	135	1			T59	3		T61	2		T88	6
auto[TlIntgErrData]	143	1			T59	5		T61	3		T88	6
auto[TlIntgErrBoth]	142	1			T59	2		T61	5		T88	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8311725

1

T1

1

T2

1

T3

42252

auto[1]

4552554

1

T1

58

T2

614

T3

25677

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	5738144	1			T1	1		T2	1		T3	31339
auto[TlIntgErrNone]	partial	auto[1]	497859	1			T1	12		T2	105		T3	3492
auto[TlIntgErrNone]	full_word	auto[0]	2573396	1			T3	10913		T5	15		T6	20
auto[TlIntgErrNone]	full_word	auto[1]	4054460	1			T1	46		T2	509		T3	22185
auto[TlIntgErrCmd]	partial	auto[0]	55	1			T59	1		T61	1		T88	1
auto[TlIntgErrCmd]	partial	auto[1]	70	1			T59	2		T61	1		T88	5
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T106	1		T133	1		T166	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T165	1		T106	2		T167	1
auto[TlIntgErrData]	partial	auto[0]	61	1			T59	3		T61	2		T88	1
auto[TlIntgErrData]	partial	auto[1]	71	1			T59	1		T61	1		T88	5
auto[TlIntgErrData]	full_word	auto[0]	4	1			T130	1		T131	1		T164	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T59	1		T130	1		T131	1
auto[TlIntgErrBoth]	partial	auto[0]	52	1			T59	1		T61	3		T88	2
auto[TlIntgErrBoth]	partial	auto[1]	79	1			T59	1		T61	1		T88	4
auto[TlIntgErrBoth]	full_word	auto[0]	8	1			T61	1		T88	1		T106	2
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T88	1		T163	1		T167	1