Unified Coverage Report :: Module :: prim_pulse_sync

Module : prim_pulse_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_flash_readbuf_watermark_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_flash_readbuf_flip_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_upload.u_payloadptr_clr_psync	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.69	94.25	84.31	96.94		87.50	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.69	94.25	84.31	96.94		87.50	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_upload.u_payloadptr_clr_psync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.37	100.00	86.11		100.00	95.74	100.00	u_upload

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T14
1	0	Covered	T3,T6,T14
1	1	Covered	T3,T6,T14

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T14
1	0	Covered	T3,T6,T14
1	1	Covered	T3,T6,T14

---

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1722257031	3461	0	0
SrcPulseCheck_M	580639563	3461	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1722257031	3461	0	0
T3	198537	25	0	0
T4	740851	0	0	0
T5	257092	0	0	0
T6	52149	7	0	0
T7	3165	0	0	0
T8	3831	0	0	0
T9	227319	0	0	0
T10	1011363	0	0	0
T11	43346	0	0	0
T12	279480	0	0	0
T13	104830	0	0	0
T14	0	30	0	0
T16	371766	0	0	0
T17	3680	0	0	0
T22	0	5	0	0
T23	0	28	0	0
T24	0	18	0	0
T25	0	22	0	0
T26	0	7	0	0
T27	0	4	0	0
T36	0	19	0	0
T38	0	7	0	0
T40	0	2	0	0
T43	0	14	0	0
T121	0	3	0	0
T122	0	7	0	0
T123	0	14	0	0
T124	0	7	0	0
T125	0	7	0	0
T126	0	7	0	0
T127	0	7	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	580639563	3461	0	0
T3	629757	25	0	0
T4	118850	0	0	0
T5	31504	0	0	0
T6	53715	7	0	0
T9	69636	0	0	0
T10	142998	0	0	0
T11	161244	0	0	0
T12	248481	0	0	0
T13	582816	0	0	0
T14	216178	30	0	0
T15	352848	0	0	0
T16	534120	0	0	0
T18	1296	0	0	0
T22	0	5	0	0
T23	0	28	0	0
T24	0	18	0	0
T25	0	22	0	0
T26	0	7	0	0
T27	0	4	0	0
T36	0	19	0	0
T38	0	7	0	0
T40	0	2	0	0
T43	0	14	0	0
T121	0	3	0	0
T122	0	7	0	0
T123	0	14	0	0
T124	0	7	0	0
T125	0	7	0	0
T126	0	7	0	0
T127	0	7	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T36,T38
1	0	Covered	T6,T36,T38
1	1	Covered	T6,T36,T38

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T36,T38
1	0	Covered	T6,T36,T38
1	1	Covered	T6,T36,T38

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	574085677	411	0	0
SrcPulseCheck_M	193546521	411	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574085677	411	0	0
T6	17383	2	0	0
T7	1055	0	0	0
T8	1277	0	0	0
T9	75773	0	0	0
T10	337121	0	0	0
T11	21673	0	0	0
T12	93160	0	0	0
T13	52415	0	0	0
T16	123922	0	0	0
T17	1840	0	0	0
T36	0	10	0	0
T38	0	2	0	0
T121	0	2	0	0
T122	0	2	0	0
T123	0	7	0	0
T124	0	2	0	0
T125	0	2	0	0
T126	0	2	0	0
T127	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	193546521	411	0	0
T6	17905	2	0	0
T9	23212	0	0	0
T10	47666	0	0	0
T11	53748	0	0	0
T12	82827	0	0	0
T13	194272	0	0	0
T14	108089	0	0	0
T15	176424	0	0	0
T16	178040	0	0	0
T18	648	0	0	0
T36	0	10	0	0
T38	0	2	0	0
T121	0	2	0	0
T122	0	2	0	0
T123	0	7	0	0
T124	0	2	0	0
T125	0	2	0	0
T126	0	2	0	0
T127	0	2	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T36,T38
1	0	Covered	T6,T36,T38
1	1	Covered	T6,T36,T38

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T36,T38
1	0	Covered	T6,T36,T38
1	1	Covered	T6,T36,T38

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	574085677	583	0	0
SrcPulseCheck_M	193546521	583	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574085677	583	0	0
T6	17383	5	0	0
T7	1055	0	0	0
T8	1277	0	0	0
T9	75773	0	0	0
T10	337121	0	0	0
T11	21673	0	0	0
T12	93160	0	0	0
T13	52415	0	0	0
T16	123922	0	0	0
T17	1840	0	0	0
T36	0	9	0	0
T38	0	5	0	0
T121	0	1	0	0
T122	0	5	0	0
T123	0	7	0	0
T124	0	5	0	0
T125	0	5	0	0
T126	0	5	0	0
T127	0	5	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	193546521	583	0	0
T6	17905	5	0	0
T9	23212	0	0	0
T10	47666	0	0	0
T11	53748	0	0	0
T12	82827	0	0	0
T13	194272	0	0	0
T14	108089	0	0	0
T15	176424	0	0	0
T16	178040	0	0	0
T18	648	0	0	0
T36	0	9	0	0
T38	0	5	0	0
T121	0	1	0	0
T122	0	5	0	0
T123	0	7	0	0
T124	0	5	0	0
T125	0	5	0	0
T126	0	5	0	0
T127	0	5	0	0

Line Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T14,T22
1	0	Covered	T3,T14,T22
1	1	Covered	T3,T14,T22

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T14,T22
1	0	Covered	T3,T14,T22
1	1	Covered	T3,T14,T22

---

Branch Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	574085677	2467	0	0
SrcPulseCheck_M	193546521	2467	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574085677	2467	0	0
T3	198537	25	0	0
T4	740851	0	0	0
T5	257092	0	0	0
T6	17383	0	0	0
T7	1055	0	0	0
T8	1277	0	0	0
T9	75773	0	0	0
T10	337121	0	0	0
T12	93160	0	0	0
T14	0	30	0	0
T16	123922	0	0	0
T22	0	5	0	0
T23	0	28	0	0
T24	0	18	0	0
T25	0	22	0	0
T26	0	7	0	0
T27	0	4	0	0
T40	0	2	0	0
T43	0	14	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	193546521	2467	0	0
T3	629757	25	0	0
T4	118850	0	0	0
T5	31504	0	0	0
T6	17905	0	0	0
T9	23212	0	0	0
T10	47666	0	0	0
T11	53748	0	0	0
T12	82827	0	0	0
T13	194272	0	0	0
T14	0	30	0	0
T16	178040	0	0	0
T22	0	5	0	0
T23	0	28	0	0
T24	0	18	0	0
T25	0	22	0	0
T26	0	7	0	0
T27	0	4	0	0
T40	0	2	0	0
T43	0	14	0	0