Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	576637868	11036327	0	0
DepthKnown_A	576637868	576506704	0	0
RvalidKnown_A	576637868	576506704	0	0
WreadyKnown_A	576637868	576506704	0	0
gen_passthru_fifo.paramCheckPass	1097	1097	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576637868	11036327	0	0
T1	4846	59	0	0
T2	283166	615	0	0
T3	198537	55826	0	0
T4	740851	1153	0	0
T5	257092	160	0	0
T6	17383	84	0	0
T7	1055	1	0	0
T8	1277	41	0	0
T9	75773	144	0	0
T10	337121	544	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576637868	576506704	0	0
T1	4846	4771	0	0
T2	283166	283112	0	0
T3	198537	198531	0	0
T4	740851	740799	0	0
T5	257092	257031	0	0
T6	17383	17322	0	0
T7	1055	993	0	0
T8	1277	1206	0	0
T9	75773	75723	0	0
T10	337121	337067	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576637868	576506704	0	0
T1	4846	4771	0	0
T2	283166	283112	0	0
T3	198537	198531	0	0
T4	740851	740799	0	0
T5	257092	257031	0	0
T6	17383	17322	0	0
T7	1055	993	0	0
T8	1277	1206	0	0
T9	75773	75723	0	0
T10	337121	337067	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576637868	576506704	0	0
T1	4846	4771	0	0
T2	283166	283112	0	0
T3	198537	198531	0	0
T4	740851	740799	0	0
T5	257092	257031	0	0
T6	17383	17322	0	0
T7	1055	993	0	0
T8	1277	1206	0	0
T9	75773	75723	0	0
T10	337121	337067	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1097	1097	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	576637868	23798808	0	0
DepthKnown_A	576637868	576506704	0	0
RvalidKnown_A	576637868	576506704	0	0
WreadyKnown_A	576637868	576506704	0	0
gen_passthru_fifo.paramCheckPass	1097	1097	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576637868	23798808	0	0
T1	4846	59	0	0
T2	283166	615	0	0
T3	198537	55195	0	0
T4	740851	5177	0	0
T5	257092	548	0	0
T6	17383	378	0	0
T7	1055	1	0	0
T8	1277	41	0	0
T9	75773	357	0	0
T10	337121	544	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576637868	576506704	0	0
T1	4846	4771	0	0
T2	283166	283112	0	0
T3	198537	198531	0	0
T4	740851	740799	0	0
T5	257092	257031	0	0
T6	17383	17322	0	0
T7	1055	993	0	0
T8	1277	1206	0	0
T9	75773	75723	0	0
T10	337121	337067	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576637868	576506704	0	0
T1	4846	4771	0	0
T2	283166	283112	0	0
T3	198537	198531	0	0
T4	740851	740799	0	0
T5	257092	257031	0	0
T6	17383	17322	0	0
T7	1055	993	0	0
T8	1277	1206	0	0
T9	75773	75723	0	0
T10	337121	337067	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576637868	576506704	0	0
T1	4846	4771	0	0
T2	283166	283112	0	0
T3	198537	198531	0	0
T4	740851	740799	0	0
T5	257092	257031	0	0
T6	17383	17322	0	0
T7	1055	993	0	0
T8	1277	1206	0	0
T9	75773	75723	0	0
T10	337121	337067	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1097	1097	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0