Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T16,T14
1	0	Covered	T3,T16,T14

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T3,T16,T14

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T14,T22

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T14,T22
1	0	Covered	T3,T14,T22

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T6
1	0	Unreachable
1	1	Covered	T3,T14,T22

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T16,T14

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T16,T14
1	0	Covered	T3,T5,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T3,T5,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T16,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T5,T6
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	961178719	765617054	0	0
CheckNGreaterZero_A	2766	2766	0	0
GntImpliesReady_A	961178719	4394449	0	0
GntImpliesValid_A	961178719	4394449	0	0
GrantKnown_A	961178719	765617054	0	0
IdxKnown_A	961178719	765617054	0	0
IndexIsCorrect_A	961178719	4394449	0	0
LockArbDecision_A	961178719	0	0	0
NoReadyValidNoGrant_A	961178719	0	0	0
ReadyAndValidImplyGrant_A	961178719	4394449	0	0
ReqAndReadyImplyGrant_A	961178719	4394449	0	0
ReqImpliesValid_A	961178719	4394449	0	0
ReqStaysHighUntilGranted0_M	961178719	0	0	0
RoundRobin_A	961178719	10	0	922
ValidKnown_A	961178719	765617054	0	0
gen_data_port_assertion.DataFlow_A	961178719	4394449	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	961178719	765617054	0	0
T1	6214	6139	0	0
T2	347638	344360	0	0
T3	1458051	816819	0	0
T4	978551	855391	0	0
T5	320100	288535	0	0
T6	53193	34824	0	0
T7	1055	993	0	0
T8	1277	1206	0	0
T9	122197	98935	0	0
T10	432453	384255	0	0
T11	53748	53748	0	0
T12	165654	82530	0	0
T13	194272	193786	0	0
T14	0	1059201	0	0
T15	0	171706	0	0
T16	356080	172088	0	0
T18	0	648	0	0
T22	0	30576	0	0
T39	0	67624	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2766	2766	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	961178719	4394449	0	0
T3	1458051	26586	0	0
T4	978551	0	0	0
T5	320100	832	0	0
T6	53193	832	0	0
T7	1055	0	0	0
T8	1277	0	0	0
T9	122197	832	0	0
T10	432453	832	0	0
T11	107496	832	0	0
T12	258814	832	0	0
T13	388544	832	0	0
T14	0	38654	0	0
T15	0	3598	0	0
T16	480002	10958	0	0
T22	0	3066	0	0
T23	0	19538	0	0
T24	0	801	0	0
T25	0	1639	0	0
T26	0	5256	0	0
T27	0	8272	0	0
T40	0	4	0	0
T41	0	4695	0	0
T42	0	4050	0	0
T43	0	409	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	961178719	4394449	0	0
T3	1458051	26586	0	0
T4	978551	0	0	0
T5	320100	832	0	0
T6	53193	832	0	0
T7	1055	0	0	0
T8	1277	0	0	0
T9	122197	832	0	0
T10	432453	832	0	0
T11	107496	832	0	0
T12	258814	832	0	0
T13	388544	832	0	0
T14	0	38654	0	0
T15	0	3598	0	0
T16	480002	10958	0	0
T22	0	3066	0	0
T23	0	19538	0	0
T24	0	801	0	0
T25	0	1639	0	0
T26	0	5256	0	0
T27	0	8272	0	0
T40	0	4	0	0
T41	0	4695	0	0
T42	0	4050	0	0
T43	0	409	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	961178719	765617054	0	0
T1	6214	6139	0	0
T2	347638	344360	0	0
T3	1458051	816819	0	0
T4	978551	855391	0	0
T5	320100	288535	0	0
T6	53193	34824	0	0
T7	1055	993	0	0
T8	1277	1206	0	0
T9	122197	98935	0	0
T10	432453	384255	0	0
T11	53748	53748	0	0
T12	165654	82530	0	0
T13	194272	193786	0	0
T14	0	1059201	0	0
T15	0	171706	0	0
T16	356080	172088	0	0
T18	0	648	0	0
T22	0	30576	0	0
T39	0	67624	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	961178719	765617054	0	0
T1	6214	6139	0	0
T2	347638	344360	0	0
T3	1458051	816819	0	0
T4	978551	855391	0	0
T5	320100	288535	0	0
T6	53193	34824	0	0
T7	1055	993	0	0
T8	1277	1206	0	0
T9	122197	98935	0	0
T10	432453	384255	0	0
T11	53748	53748	0	0
T12	165654	82530	0	0
T13	194272	193786	0	0
T14	0	1059201	0	0
T15	0	171706	0	0
T16	356080	172088	0	0
T18	0	648	0	0
T22	0	30576	0	0
T39	0	67624	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	961178719	4394449	0	0
T3	1458051	26586	0	0
T4	978551	0	0	0
T5	320100	832	0	0
T6	53193	832	0	0
T7	1055	0	0	0
T8	1277	0	0	0
T9	122197	832	0	0
T10	432453	832	0	0
T11	107496	832	0	0
T12	258814	832	0	0
T13	388544	832	0	0
T14	0	38654	0	0
T15	0	3598	0	0
T16	480002	10958	0	0
T22	0	3066	0	0
T23	0	19538	0	0
T24	0	801	0	0
T25	0	1639	0	0
T26	0	5256	0	0
T27	0	8272	0	0
T40	0	4	0	0
T41	0	4695	0	0
T42	0	4050	0	0
T43	0	409	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	961178719	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	961178719	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	961178719	4394449	0	0
T3	1458051	26586	0	0
T4	978551	0	0	0
T5	320100	832	0	0
T6	53193	832	0	0
T7	1055	0	0	0
T8	1277	0	0	0
T9	122197	832	0	0
T10	432453	832	0	0
T11	107496	832	0	0
T12	258814	832	0	0
T13	388544	832	0	0
T14	0	38654	0	0
T15	0	3598	0	0
T16	480002	10958	0	0
T22	0	3066	0	0
T23	0	19538	0	0
T24	0	801	0	0
T25	0	1639	0	0
T26	0	5256	0	0
T27	0	8272	0	0
T40	0	4	0	0
T41	0	4695	0	0
T42	0	4050	0	0
T43	0	409	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	961178719	4394449	0	0
T3	1458051	26586	0	0
T4	978551	0	0	0
T5	320100	832	0	0
T6	53193	832	0	0
T7	1055	0	0	0
T8	1277	0	0	0
T9	122197	832	0	0
T10	432453	832	0	0
T11	107496	832	0	0
T12	258814	832	0	0
T13	388544	832	0	0
T14	0	38654	0	0
T15	0	3598	0	0
T16	480002	10958	0	0
T22	0	3066	0	0
T23	0	19538	0	0
T24	0	801	0	0
T25	0	1639	0	0
T26	0	5256	0	0
T27	0	8272	0	0
T40	0	4	0	0
T41	0	4695	0	0
T42	0	4050	0	0
T43	0	409	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	961178719	4394449	0	0
T3	1458051	26586	0	0
T4	978551	0	0	0
T5	320100	832	0	0
T6	53193	832	0	0
T7	1055	0	0	0
T8	1277	0	0	0
T9	122197	832	0	0
T10	432453	832	0	0
T11	107496	832	0	0
T12	258814	832	0	0
T13	388544	832	0	0
T14	0	38654	0	0
T15	0	3598	0	0
T16	480002	10958	0	0
T22	0	3066	0	0
T23	0	19538	0	0
T24	0	801	0	0
T25	0	1639	0	0
T26	0	5256	0	0
T27	0	8272	0	0
T40	0	4	0	0
T41	0	4695	0	0
T42	0	4050	0	0
T43	0	409	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	961178719	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	961178719	10	0	922
T3	198537	1	0	1
T4	740851	0	0	1
T5	257092	0	0	1
T6	17383	0	0	1
T7	1055	0	0	1
T8	1277	0	0	1
T9	75773	0	0	1
T10	337121	0	0	1
T12	93160	0	0	1
T16	123922	0	0	1
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	961178719	765617054	0	0
T1	6214	6139	0	0
T2	347638	344360	0	0
T3	1458051	816819	0	0
T4	978551	855391	0	0
T5	320100	288535	0	0
T6	53193	34824	0	0
T7	1055	993	0	0
T8	1277	1206	0	0
T9	122197	98935	0	0
T10	432453	384255	0	0
T11	53748	53748	0	0
T12	165654	82530	0	0
T13	194272	193786	0	0
T14	0	1059201	0	0
T15	0	171706	0	0
T16	356080	172088	0	0
T18	0	648	0	0
T22	0	30576	0	0
T39	0	67624	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	961178719	4394449	0	0
T3	1458051	26586	0	0
T4	978551	0	0	0
T5	320100	832	0	0
T6	53193	832	0	0
T7	1055	0	0	0
T8	1277	0	0	0
T9	122197	832	0	0
T10	432453	832	0	0
T11	107496	832	0	0
T12	258814	832	0	0
T13	388544	832	0	0
T14	0	38654	0	0
T15	0	3598	0	0
T16	480002	10958	0	0
T22	0	3066	0	0
T23	0	19538	0	0
T24	0	801	0	0
T25	0	1639	0	0
T26	0	5256	0	0
T27	0	8272	0	0
T40	0	4	0	0
T41	0	4695	0	0
T42	0	4050	0	0
T43	0	409	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T16,T14
1	0	Covered	T3,T16,T14

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T3,T16,T14

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T16,T14
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T16,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T16,T14
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	193546521	43124157	0	0
CheckNGreaterZero_A	922	922	0	0
GntImpliesReady_A	193546521	986900	0	0
GntImpliesValid_A	193546521	986900	0	0
GrantKnown_A	193546521	43124157	0	0
IdxKnown_A	193546521	43124157	0	0
IndexIsCorrect_A	193546521	986900	0	0
LockArbDecision_A	193546521	0	0	0
NoReadyValidNoGrant_A	193546521	0	0	0
ReadyAndValidImplyGrant_A	193546521	986900	0	0
ReqAndReadyImplyGrant_A	193546521	986900	0	0
ReqImpliesValid_A	193546521	986900	0	0
ReqStaysHighUntilGranted0_M	193546521	0	0	0
RoundRobin_A	193546521	0	0	0
ValidKnown_A	193546521	43124157	0	0
gen_data_port_assertion.DataFlow_A	193546521	986900	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193546521	43124157	0	0
T1	1368	1368	0	0
T2	64472	61248	0	0
T3	629757	212768	0	0
T4	118850	114592	0	0
T5	31504	0	0	0
T6	17905	0	0	0
T9	23212	0	0	0
T10	47666	0	0	0
T12	82827	0	0	0
T14	0	554493	0	0
T15	0	78952	0	0
T16	178040	172088	0	0
T18	0	648	0	0
T22	0	30576	0	0
T39	0	67624	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	922	922	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193546521	986900	0	0
T3	629757	8605	0	0
T4	118850	0	0	0
T5	31504	0	0	0
T6	17905	0	0	0
T9	23212	0	0	0
T10	47666	0	0	0
T11	53748	0	0	0
T12	82827	0	0	0
T13	194272	0	0	0
T14	0	13066	0	0
T15	0	3598	0	0
T16	178040	7429	0	0
T22	0	1149	0	0
T23	0	9515	0	0
T26	0	5240	0	0
T27	0	8265	0	0
T41	0	4695	0	0
T42	0	4050	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193546521	986900	0	0
T3	629757	8605	0	0
T4	118850	0	0	0
T5	31504	0	0	0
T6	17905	0	0	0
T9	23212	0	0	0
T10	47666	0	0	0
T11	53748	0	0	0
T12	82827	0	0	0
T13	194272	0	0	0
T14	0	13066	0	0
T15	0	3598	0	0
T16	178040	7429	0	0
T22	0	1149	0	0
T23	0	9515	0	0
T26	0	5240	0	0
T27	0	8265	0	0
T41	0	4695	0	0
T42	0	4050	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193546521	43124157	0	0
T1	1368	1368	0	0
T2	64472	61248	0	0
T3	629757	212768	0	0
T4	118850	114592	0	0
T5	31504	0	0	0
T6	17905	0	0	0
T9	23212	0	0	0
T10	47666	0	0	0
T12	82827	0	0	0
T14	0	554493	0	0
T15	0	78952	0	0
T16	178040	172088	0	0
T18	0	648	0	0
T22	0	30576	0	0
T39	0	67624	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193546521	43124157	0	0
T1	1368	1368	0	0
T2	64472	61248	0	0
T3	629757	212768	0	0
T4	118850	114592	0	0
T5	31504	0	0	0
T6	17905	0	0	0
T9	23212	0	0	0
T10	47666	0	0	0
T12	82827	0	0	0
T14	0	554493	0	0
T15	0	78952	0	0
T16	178040	172088	0	0
T18	0	648	0	0
T22	0	30576	0	0
T39	0	67624	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193546521	986900	0	0
T3	629757	8605	0	0
T4	118850	0	0	0
T5	31504	0	0	0
T6	17905	0	0	0
T9	23212	0	0	0
T10	47666	0	0	0
T11	53748	0	0	0
T12	82827	0	0	0
T13	194272	0	0	0
T14	0	13066	0	0
T15	0	3598	0	0
T16	178040	7429	0	0
T22	0	1149	0	0
T23	0	9515	0	0
T26	0	5240	0	0
T27	0	8265	0	0
T41	0	4695	0	0
T42	0	4050	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193546521	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193546521	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193546521	986900	0	0
T3	629757	8605	0	0
T4	118850	0	0	0
T5	31504	0	0	0
T6	17905	0	0	0
T9	23212	0	0	0
T10	47666	0	0	0
T11	53748	0	0	0
T12	82827	0	0	0
T13	194272	0	0	0
T14	0	13066	0	0
T15	0	3598	0	0
T16	178040	7429	0	0
T22	0	1149	0	0
T23	0	9515	0	0
T26	0	5240	0	0
T27	0	8265	0	0
T41	0	4695	0	0
T42	0	4050	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193546521	986900	0	0
T3	629757	8605	0	0
T4	118850	0	0	0
T5	31504	0	0	0
T6	17905	0	0	0
T9	23212	0	0	0
T10	47666	0	0	0
T11	53748	0	0	0
T12	82827	0	0	0
T13	194272	0	0	0
T14	0	13066	0	0
T15	0	3598	0	0
T16	178040	7429	0	0
T22	0	1149	0	0
T23	0	9515	0	0
T26	0	5240	0	0
T27	0	8265	0	0
T41	0	4695	0	0
T42	0	4050	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193546521	986900	0	0
T3	629757	8605	0	0
T4	118850	0	0	0
T5	31504	0	0	0
T6	17905	0	0	0
T9	23212	0	0	0
T10	47666	0	0	0
T11	53748	0	0	0
T12	82827	0	0	0
T13	194272	0	0	0
T14	0	13066	0	0
T15	0	3598	0	0
T16	178040	7429	0	0
T22	0	1149	0	0
T23	0	9515	0	0
T26	0	5240	0	0
T27	0	8265	0	0
T41	0	4695	0	0
T42	0	4050	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	193546521	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193546521	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193546521	43124157	0	0
T1	1368	1368	0	0
T2	64472	61248	0	0
T3	629757	212768	0	0
T4	118850	114592	0	0
T5	31504	0	0	0
T6	17905	0	0	0
T9	23212	0	0	0
T10	47666	0	0	0
T12	82827	0	0	0
T14	0	554493	0	0
T15	0	78952	0	0
T16	178040	172088	0	0
T18	0	648	0	0
T22	0	30576	0	0
T39	0	67624	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193546521	986900	0	0
T3	629757	8605	0	0
T4	118850	0	0	0
T5	31504	0	0	0
T6	17905	0	0	0
T9	23212	0	0	0
T10	47666	0	0	0
T11	53748	0	0	0
T12	82827	0	0	0
T13	194272	0	0	0
T14	0	13066	0	0
T15	0	3598	0	0
T16	178040	7429	0	0
T22	0	1149	0	0
T23	0	9515	0	0
T26	0	5240	0	0
T27	0	8265	0	0
T41	0	4695	0	0
T42	0	4050	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T14,T22

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T14,T22
1	0	Covered	T3,T14,T22

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T6
1	0	Unreachable
1	1	Covered	T3,T14,T22

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T14,T22
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T14,T22
0	0	1	Unreachable
0	0	0	Covered	T3,T5,T6

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T14,T22
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T14,T22
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	193546521	148491681	0	0
CheckNGreaterZero_A	922	922	0	0
GntImpliesReady_A	193546521	646038	0	0
GntImpliesValid_A	193546521	646038	0	0
GrantKnown_A	193546521	148491681	0	0
IdxKnown_A	193546521	148491681	0	0
IndexIsCorrect_A	193546521	646038	0	0
LockArbDecision_A	193546521	0	0	0
NoReadyValidNoGrant_A	193546521	0	0	0
ReadyAndValidImplyGrant_A	193546521	646038	0	0
ReqAndReadyImplyGrant_A	193546521	646038	0	0
ReqImpliesValid_A	193546521	646038	0	0
ReqStaysHighUntilGranted0_M	193546521	0	0	0
RoundRobin_A	193546521	0	0	0
ValidKnown_A	193546521	148491681	0	0
gen_data_port_assertion.DataFlow_A	193546521	646038	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193546521	148491681	0	0
T3	629757	405520	0	0
T4	118850	0	0	0
T5	31504	31504	0	0
T6	17905	17502	0	0
T9	23212	23212	0	0
T10	47666	47188	0	0
T11	53748	53748	0	0
T12	82827	82530	0	0
T13	194272	193786	0	0
T14	0	504708	0	0
T15	0	92754	0	0
T16	178040	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	922	922	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193546521	646038	0	0
T3	629757	2520	0	0
T4	118850	0	0	0
T5	31504	0	0	0
T6	17905	0	0	0
T9	23212	0	0	0
T10	47666	0	0	0
T11	53748	0	0	0
T12	82827	0	0	0
T13	194272	0	0	0
T14	0	7078	0	0
T16	178040	0	0	0
T22	0	1917	0	0
T23	0	10023	0	0
T24	0	801	0	0
T25	0	1639	0	0
T26	0	16	0	0
T27	0	7	0	0
T40	0	4	0	0
T43	0	409	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193546521	646038	0	0
T3	629757	2520	0	0
T4	118850	0	0	0
T5	31504	0	0	0
T6	17905	0	0	0
T9	23212	0	0	0
T10	47666	0	0	0
T11	53748	0	0	0
T12	82827	0	0	0
T13	194272	0	0	0
T14	0	7078	0	0
T16	178040	0	0	0
T22	0	1917	0	0
T23	0	10023	0	0
T24	0	801	0	0
T25	0	1639	0	0
T26	0	16	0	0
T27	0	7	0	0
T40	0	4	0	0
T43	0	409	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193546521	148491681	0	0
T3	629757	405520	0	0
T4	118850	0	0	0
T5	31504	31504	0	0
T6	17905	17502	0	0
T9	23212	23212	0	0
T10	47666	47188	0	0
T11	53748	53748	0	0
T12	82827	82530	0	0
T13	194272	193786	0	0
T14	0	504708	0	0
T15	0	92754	0	0
T16	178040	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193546521	148491681	0	0
T3	629757	405520	0	0
T4	118850	0	0	0
T5	31504	31504	0	0
T6	17905	17502	0	0
T9	23212	23212	0	0
T10	47666	47188	0	0
T11	53748	53748	0	0
T12	82827	82530	0	0
T13	194272	193786	0	0
T14	0	504708	0	0
T15	0	92754	0	0
T16	178040	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193546521	646038	0	0
T3	629757	2520	0	0
T4	118850	0	0	0
T5	31504	0	0	0
T6	17905	0	0	0
T9	23212	0	0	0
T10	47666	0	0	0
T11	53748	0	0	0
T12	82827	0	0	0
T13	194272	0	0	0
T14	0	7078	0	0
T16	178040	0	0	0
T22	0	1917	0	0
T23	0	10023	0	0
T24	0	801	0	0
T25	0	1639	0	0
T26	0	16	0	0
T27	0	7	0	0
T40	0	4	0	0
T43	0	409	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193546521	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193546521	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193546521	646038	0	0
T3	629757	2520	0	0
T4	118850	0	0	0
T5	31504	0	0	0
T6	17905	0	0	0
T9	23212	0	0	0
T10	47666	0	0	0
T11	53748	0	0	0
T12	82827	0	0	0
T13	194272	0	0	0
T14	0	7078	0	0
T16	178040	0	0	0
T22	0	1917	0	0
T23	0	10023	0	0
T24	0	801	0	0
T25	0	1639	0	0
T26	0	16	0	0
T27	0	7	0	0
T40	0	4	0	0
T43	0	409	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193546521	646038	0	0
T3	629757	2520	0	0
T4	118850	0	0	0
T5	31504	0	0	0
T6	17905	0	0	0
T9	23212	0	0	0
T10	47666	0	0	0
T11	53748	0	0	0
T12	82827	0	0	0
T13	194272	0	0	0
T14	0	7078	0	0
T16	178040	0	0	0
T22	0	1917	0	0
T23	0	10023	0	0
T24	0	801	0	0
T25	0	1639	0	0
T26	0	16	0	0
T27	0	7	0	0
T40	0	4	0	0
T43	0	409	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193546521	646038	0	0
T3	629757	2520	0	0
T4	118850	0	0	0
T5	31504	0	0	0
T6	17905	0	0	0
T9	23212	0	0	0
T10	47666	0	0	0
T11	53748	0	0	0
T12	82827	0	0	0
T13	194272	0	0	0
T14	0	7078	0	0
T16	178040	0	0	0
T22	0	1917	0	0
T23	0	10023	0	0
T24	0	801	0	0
T25	0	1639	0	0
T26	0	16	0	0
T27	0	7	0	0
T40	0	4	0	0
T43	0	409	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	193546521	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193546521	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193546521	148491681	0	0
T3	629757	405520	0	0
T4	118850	0	0	0
T5	31504	31504	0	0
T6	17905	17502	0	0
T9	23212	23212	0	0
T10	47666	47188	0	0
T11	53748	53748	0	0
T12	82827	82530	0	0
T13	194272	193786	0	0
T14	0	504708	0	0
T15	0	92754	0	0
T16	178040	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193546521	646038	0	0
T3	629757	2520	0	0
T4	118850	0	0	0
T5	31504	0	0	0
T6	17905	0	0	0
T9	23212	0	0	0
T10	47666	0	0	0
T11	53748	0	0	0
T12	82827	0	0	0
T13	194272	0	0	0
T14	0	7078	0	0
T16	178040	0	0	0
T22	0	1917	0	0
T23	0	10023	0	0
T24	0	801	0	0
T25	0	1639	0	0
T26	0	16	0	0
T27	0	7	0	0
T40	0	4	0	0
T43	0	409	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T16,T14

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T16,T14
1	0	Covered	T3,T5,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T3,T5,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T16,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T5,T6
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	574085677	574001216	0	0
CheckNGreaterZero_A	922	922	0	0
GntImpliesReady_A	574085677	2761511	0	0
GntImpliesValid_A	574085677	2761511	0	0
GrantKnown_A	574085677	574001216	0	0
IdxKnown_A	574085677	574001216	0	0
IndexIsCorrect_A	574085677	2761511	0	0
LockArbDecision_A	574085677	0	0	0
NoReadyValidNoGrant_A	574085677	0	0	0
ReadyAndValidImplyGrant_A	574085677	2761511	0	0
ReqAndReadyImplyGrant_A	574085677	2761511	0	0
ReqImpliesValid_A	574085677	2761511	0	0
ReqStaysHighUntilGranted0_M	574085677	0	0	0
RoundRobin_A	574085677	10	0	922
ValidKnown_A	574085677	574001216	0	0
gen_data_port_assertion.DataFlow_A	574085677	2761511	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574085677	574001216	0	0
T1	4846	4771	0	0
T2	283166	283112	0	0
T3	198537	198531	0	0
T4	740851	740799	0	0
T5	257092	257031	0	0
T6	17383	17322	0	0
T7	1055	993	0	0
T8	1277	1206	0	0
T9	75773	75723	0	0
T10	337121	337067	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	922	922	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574085677	2761511	0	0
T3	198537	15461	0	0
T4	740851	0	0	0
T5	257092	832	0	0
T6	17383	832	0	0
T7	1055	0	0	0
T8	1277	0	0	0
T9	75773	832	0	0
T10	337121	832	0	0
T11	0	832	0	0
T12	93160	832	0	0
T13	0	832	0	0
T14	0	18510	0	0
T16	123922	3529	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574085677	2761511	0	0
T3	198537	15461	0	0
T4	740851	0	0	0
T5	257092	832	0	0
T6	17383	832	0	0
T7	1055	0	0	0
T8	1277	0	0	0
T9	75773	832	0	0
T10	337121	832	0	0
T11	0	832	0	0
T12	93160	832	0	0
T13	0	832	0	0
T14	0	18510	0	0
T16	123922	3529	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574085677	574001216	0	0
T1	4846	4771	0	0
T2	283166	283112	0	0
T3	198537	198531	0	0
T4	740851	740799	0	0
T5	257092	257031	0	0
T6	17383	17322	0	0
T7	1055	993	0	0
T8	1277	1206	0	0
T9	75773	75723	0	0
T10	337121	337067	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574085677	574001216	0	0
T1	4846	4771	0	0
T2	283166	283112	0	0
T3	198537	198531	0	0
T4	740851	740799	0	0
T5	257092	257031	0	0
T6	17383	17322	0	0
T7	1055	993	0	0
T8	1277	1206	0	0
T9	75773	75723	0	0
T10	337121	337067	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574085677	2761511	0	0
T3	198537	15461	0	0
T4	740851	0	0	0
T5	257092	832	0	0
T6	17383	832	0	0
T7	1055	0	0	0
T8	1277	0	0	0
T9	75773	832	0	0
T10	337121	832	0	0
T11	0	832	0	0
T12	93160	832	0	0
T13	0	832	0	0
T14	0	18510	0	0
T16	123922	3529	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574085677	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574085677	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574085677	2761511	0	0
T3	198537	15461	0	0
T4	740851	0	0	0
T5	257092	832	0	0
T6	17383	832	0	0
T7	1055	0	0	0
T8	1277	0	0	0
T9	75773	832	0	0
T10	337121	832	0	0
T11	0	832	0	0
T12	93160	832	0	0
T13	0	832	0	0
T14	0	18510	0	0
T16	123922	3529	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574085677	2761511	0	0
T3	198537	15461	0	0
T4	740851	0	0	0
T5	257092	832	0	0
T6	17383	832	0	0
T7	1055	0	0	0
T8	1277	0	0	0
T9	75773	832	0	0
T10	337121	832	0	0
T11	0	832	0	0
T12	93160	832	0	0
T13	0	832	0	0
T14	0	18510	0	0
T16	123922	3529	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574085677	2761511	0	0
T3	198537	15461	0	0
T4	740851	0	0	0
T5	257092	832	0	0
T6	17383	832	0	0
T7	1055	0	0	0
T8	1277	0	0	0
T9	75773	832	0	0
T10	337121	832	0	0
T11	0	832	0	0
T12	93160	832	0	0
T13	0	832	0	0
T14	0	18510	0	0
T16	123922	3529	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	574085677	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574085677	10	0	922
T3	198537	1	0	1
T4	740851	0	0	1
T5	257092	0	0	1
T6	17383	0	0	1
T7	1055	0	0	1
T8	1277	0	0	1
T9	75773	0	0	1
T10	337121	0	0	1
T12	93160	0	0	1
T16	123922	0	0	1
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574085677	574001216	0	0
T1	4846	4771	0	0
T2	283166	283112	0	0
T3	198537	198531	0	0
T4	740851	740799	0	0
T5	257092	257031	0	0
T6	17383	17322	0	0
T7	1055	993	0	0
T8	1277	1206	0	0
T9	75773	75723	0	0
T10	337121	337067	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574085677	2761511	0	0
T3	198537	15461	0	0
T4	740851	0	0	0
T5	257092	832	0	0
T6	17383	832	0	0
T7	1055	0	0	0
T8	1277	0	0	0
T9	75773	832	0	0
T10	337121	832	0	0
T11	0	832	0	0
T12	93160	832	0	0
T13	0	832	0	0
T14	0	18510	0	0
T16	123922	3529	0	0