Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
576637868 |
3943 |
0 |
0 |
T59 |
26412 |
1 |
0 |
0 |
T60 |
13357 |
11 |
0 |
0 |
T61 |
10258 |
2 |
0 |
0 |
T85 |
5374 |
2 |
0 |
0 |
T86 |
2442 |
89 |
0 |
0 |
T87 |
1782 |
71 |
0 |
0 |
T89 |
5799 |
289 |
0 |
0 |
T95 |
14126 |
249 |
0 |
0 |
T96 |
4184 |
166 |
0 |
0 |
T103 |
4995 |
5 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
576637868 |
3108 |
0 |
0 |
T74 |
1746 |
1 |
0 |
0 |
T88 |
76331 |
85 |
0 |
0 |
T104 |
11102 |
14 |
0 |
0 |
T108 |
6742 |
6 |
0 |
0 |
T111 |
3697 |
5 |
0 |
0 |
T128 |
7617 |
28 |
0 |
0 |
T129 |
9133 |
1 |
0 |
0 |
T130 |
107654 |
132 |
0 |
0 |
T131 |
92178 |
108 |
0 |
0 |
T132 |
37569 |
95 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
576637868 |
3213 |
0 |
0 |
T74 |
1746 |
2 |
0 |
0 |
T88 |
76331 |
71 |
0 |
0 |
T104 |
11102 |
20 |
0 |
0 |
T108 |
6742 |
9 |
0 |
0 |
T111 |
3697 |
6 |
0 |
0 |
T128 |
7617 |
37 |
0 |
0 |
T129 |
9133 |
5 |
0 |
0 |
T130 |
107654 |
131 |
0 |
0 |
T131 |
92178 |
136 |
0 |
0 |
T132 |
37569 |
151 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
576637868 |
3798 |
0 |
0 |
T74 |
1746 |
1 |
0 |
0 |
T88 |
76331 |
159 |
0 |
0 |
T104 |
11102 |
27 |
0 |
0 |
T108 |
6742 |
6 |
0 |
0 |
T111 |
3697 |
1 |
0 |
0 |
T128 |
7617 |
1 |
0 |
0 |
T129 |
9133 |
9 |
0 |
0 |
T130 |
107654 |
186 |
0 |
0 |
T131 |
92178 |
249 |
0 |
0 |
T132 |
37569 |
111 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
576637868 |
14317 |
0 |
0 |
T88 |
76331 |
1788 |
0 |
0 |
T104 |
11102 |
145 |
0 |
0 |
T108 |
6742 |
188 |
0 |
0 |
T111 |
3697 |
79 |
0 |
0 |
T113 |
108976 |
682 |
0 |
0 |
T128 |
7617 |
31 |
0 |
0 |
T129 |
9133 |
133 |
0 |
0 |
T130 |
107654 |
1960 |
0 |
0 |
T131 |
92178 |
1480 |
0 |
0 |
T132 |
37569 |
145 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
576637868 |
14928 |
0 |
0 |
T88 |
76331 |
1462 |
0 |
0 |
T104 |
11102 |
277 |
0 |
0 |
T108 |
6742 |
66 |
0 |
0 |
T111 |
3697 |
61 |
0 |
0 |
T113 |
108976 |
753 |
0 |
0 |
T128 |
7617 |
6 |
0 |
0 |
T129 |
9133 |
38 |
0 |
0 |
T130 |
107654 |
2158 |
0 |
0 |
T131 |
92178 |
1852 |
0 |
0 |
T132 |
37569 |
143 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
576637868 |
13119 |
0 |
0 |
T88 |
76331 |
1119 |
0 |
0 |
T104 |
11102 |
8 |
0 |
0 |
T108 |
6742 |
8 |
0 |
0 |
T111 |
3697 |
51 |
0 |
0 |
T113 |
108976 |
650 |
0 |
0 |
T128 |
7617 |
38 |
0 |
0 |
T129 |
9133 |
81 |
0 |
0 |
T130 |
107654 |
1946 |
0 |
0 |
T131 |
92178 |
2046 |
0 |
0 |
T132 |
37569 |
142 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
576637868 |
12878 |
0 |
0 |
T88 |
76331 |
761 |
0 |
0 |
T104 |
11102 |
21 |
0 |
0 |
T108 |
6742 |
49 |
0 |
0 |
T113 |
108976 |
626 |
0 |
0 |
T128 |
7617 |
24 |
0 |
0 |
T129 |
9133 |
10 |
0 |
0 |
T130 |
107654 |
1487 |
0 |
0 |
T131 |
92178 |
2030 |
0 |
0 |
T132 |
37569 |
163 |
0 |
0 |
T133 |
100165 |
2525 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
576637868 |
12681 |
0 |
0 |
T74 |
1746 |
4 |
0 |
0 |
T88 |
76331 |
1134 |
0 |
0 |
T104 |
11102 |
123 |
0 |
0 |
T108 |
6742 |
64 |
0 |
0 |
T111 |
3697 |
3 |
0 |
0 |
T128 |
7617 |
3 |
0 |
0 |
T129 |
9133 |
7 |
0 |
0 |
T130 |
107654 |
1962 |
0 |
0 |
T131 |
92178 |
1681 |
0 |
0 |
T132 |
37569 |
147 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
576637868 |
12974 |
0 |
0 |
T88 |
76331 |
1030 |
0 |
0 |
T104 |
11102 |
277 |
0 |
0 |
T108 |
6742 |
65 |
0 |
0 |
T111 |
3697 |
71 |
0 |
0 |
T113 |
108976 |
715 |
0 |
0 |
T128 |
7617 |
15 |
0 |
0 |
T129 |
9133 |
126 |
0 |
0 |
T130 |
107654 |
1967 |
0 |
0 |
T131 |
92178 |
1329 |
0 |
0 |
T132 |
37569 |
120 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
576637868 |
12372 |
0 |
0 |
T74 |
1746 |
1 |
0 |
0 |
T88 |
76331 |
1177 |
0 |
0 |
T104 |
11102 |
267 |
0 |
0 |
T108 |
6742 |
49 |
0 |
0 |
T111 |
3697 |
4 |
0 |
0 |
T128 |
7617 |
7 |
0 |
0 |
T129 |
9133 |
10 |
0 |
0 |
T130 |
107654 |
2150 |
0 |
0 |
T131 |
92178 |
1274 |
0 |
0 |
T132 |
37569 |
123 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
576637868 |
12702 |
0 |
0 |
T88 |
76331 |
1494 |
0 |
0 |
T104 |
11102 |
23 |
0 |
0 |
T108 |
6742 |
68 |
0 |
0 |
T111 |
3697 |
53 |
0 |
0 |
T113 |
108976 |
734 |
0 |
0 |
T128 |
7617 |
20 |
0 |
0 |
T129 |
9133 |
82 |
0 |
0 |
T130 |
107654 |
1762 |
0 |
0 |
T131 |
92178 |
1544 |
0 |
0 |
T132 |
37569 |
123 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
576637868 |
7308 |
0 |
0 |
T74 |
1746 |
4 |
0 |
0 |
T88 |
76331 |
476 |
0 |
0 |
T104 |
11102 |
51 |
0 |
0 |
T108 |
6742 |
30 |
0 |
0 |
T113 |
108976 |
714 |
0 |
0 |
T128 |
7617 |
46 |
0 |
0 |
T129 |
9133 |
17 |
0 |
0 |
T130 |
107654 |
818 |
0 |
0 |
T131 |
92178 |
744 |
0 |
0 |
T132 |
37569 |
145 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
576637868 |
7077 |
0 |
0 |
T88 |
76331 |
666 |
0 |
0 |
T104 |
11102 |
106 |
0 |
0 |
T108 |
6742 |
7 |
0 |
0 |
T113 |
108976 |
663 |
0 |
0 |
T128 |
7617 |
31 |
0 |
0 |
T129 |
9133 |
81 |
0 |
0 |
T130 |
107654 |
563 |
0 |
0 |
T131 |
92178 |
734 |
0 |
0 |
T132 |
37569 |
157 |
0 |
0 |
T133 |
100165 |
753 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
576637868 |
7569 |
0 |
0 |
T74 |
1746 |
3 |
0 |
0 |
T88 |
76331 |
697 |
0 |
0 |
T104 |
11102 |
134 |
0 |
0 |
T108 |
6742 |
18 |
0 |
0 |
T111 |
3697 |
6 |
0 |
0 |
T128 |
7617 |
36 |
0 |
0 |
T129 |
9133 |
4 |
0 |
0 |
T130 |
107654 |
1029 |
0 |
0 |
T131 |
92178 |
882 |
0 |
0 |
T132 |
37569 |
145 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
576637868 |
7342 |
0 |
0 |
T74 |
1746 |
1 |
0 |
0 |
T88 |
76331 |
719 |
0 |
0 |
T104 |
11102 |
16 |
0 |
0 |
T108 |
6742 |
4 |
0 |
0 |
T111 |
3697 |
11 |
0 |
0 |
T128 |
7617 |
26 |
0 |
0 |
T129 |
9133 |
21 |
0 |
0 |
T130 |
107654 |
989 |
0 |
0 |
T131 |
92178 |
827 |
0 |
0 |
T132 |
37569 |
140 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
576637868 |
7006 |
0 |
0 |
T88 |
76331 |
577 |
0 |
0 |
T104 |
11102 |
64 |
0 |
0 |
T108 |
6742 |
29 |
0 |
0 |
T111 |
3697 |
35 |
0 |
0 |
T113 |
108976 |
683 |
0 |
0 |
T128 |
7617 |
12 |
0 |
0 |
T129 |
9133 |
36 |
0 |
0 |
T130 |
107654 |
890 |
0 |
0 |
T131 |
92178 |
696 |
0 |
0 |
T132 |
37569 |
140 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
576637868 |
7142 |
0 |
0 |
T74 |
1746 |
5 |
0 |
0 |
T88 |
76331 |
574 |
0 |
0 |
T104 |
11102 |
75 |
0 |
0 |
T108 |
6742 |
26 |
0 |
0 |
T113 |
108976 |
740 |
0 |
0 |
T128 |
7617 |
38 |
0 |
0 |
T129 |
9133 |
4 |
0 |
0 |
T130 |
107654 |
776 |
0 |
0 |
T131 |
92178 |
639 |
0 |
0 |
T132 |
37569 |
155 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
576637868 |
7443 |
0 |
0 |
T74 |
1746 |
1 |
0 |
0 |
T88 |
76331 |
464 |
0 |
0 |
T104 |
11102 |
134 |
0 |
0 |
T108 |
6742 |
60 |
0 |
0 |
T113 |
108976 |
724 |
0 |
0 |
T128 |
7617 |
10 |
0 |
0 |
T129 |
9133 |
19 |
0 |
0 |
T130 |
107654 |
1083 |
0 |
0 |
T131 |
92178 |
809 |
0 |
0 |
T132 |
37569 |
141 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
576637868 |
6853 |
0 |
0 |
T74 |
1746 |
3 |
0 |
0 |
T88 |
76331 |
640 |
0 |
0 |
T104 |
11102 |
103 |
0 |
0 |
T108 |
6742 |
31 |
0 |
0 |
T113 |
108976 |
719 |
0 |
0 |
T128 |
7617 |
12 |
0 |
0 |
T129 |
9133 |
20 |
0 |
0 |
T130 |
107654 |
784 |
0 |
0 |
T131 |
92178 |
612 |
0 |
0 |
T132 |
37569 |
121 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
576637868 |
7148 |
0 |
0 |
T74 |
1746 |
8 |
0 |
0 |
T88 |
76331 |
545 |
0 |
0 |
T104 |
11102 |
75 |
0 |
0 |
T108 |
6742 |
20 |
0 |
0 |
T111 |
3697 |
5 |
0 |
0 |
T128 |
7617 |
19 |
0 |
0 |
T129 |
9133 |
45 |
0 |
0 |
T130 |
107654 |
970 |
0 |
0 |
T131 |
92178 |
708 |
0 |
0 |
T132 |
37569 |
119 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
576637868 |
6881 |
0 |
0 |
T74 |
1746 |
6 |
0 |
0 |
T88 |
76331 |
480 |
0 |
0 |
T104 |
11102 |
14 |
0 |
0 |
T108 |
6742 |
8 |
0 |
0 |
T111 |
3697 |
1 |
0 |
0 |
T128 |
7617 |
17 |
0 |
0 |
T129 |
9133 |
19 |
0 |
0 |
T130 |
107654 |
780 |
0 |
0 |
T131 |
92178 |
781 |
0 |
0 |
T132 |
37569 |
124 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
576637868 |
7432 |
0 |
0 |
T88 |
76331 |
666 |
0 |
0 |
T104 |
11102 |
58 |
0 |
0 |
T108 |
6742 |
27 |
0 |
0 |
T111 |
3697 |
5 |
0 |
0 |
T113 |
108976 |
710 |
0 |
0 |
T128 |
7617 |
19 |
0 |
0 |
T129 |
9133 |
28 |
0 |
0 |
T130 |
107654 |
889 |
0 |
0 |
T131 |
92178 |
536 |
0 |
0 |
T132 |
37569 |
142 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
576637868 |
6903 |
0 |
0 |
T74 |
1746 |
10 |
0 |
0 |
T88 |
76331 |
429 |
0 |
0 |
T104 |
11102 |
19 |
0 |
0 |
T108 |
6742 |
52 |
0 |
0 |
T111 |
3697 |
19 |
0 |
0 |
T128 |
7617 |
27 |
0 |
0 |
T129 |
9133 |
34 |
0 |
0 |
T130 |
107654 |
735 |
0 |
0 |
T131 |
92178 |
831 |
0 |
0 |
T132 |
37569 |
174 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
576637868 |
7880 |
0 |
0 |
T88 |
76331 |
599 |
0 |
0 |
T104 |
11102 |
43 |
0 |
0 |
T108 |
6742 |
17 |
0 |
0 |
T111 |
3697 |
5 |
0 |
0 |
T113 |
108976 |
678 |
0 |
0 |
T128 |
7617 |
29 |
0 |
0 |
T129 |
9133 |
28 |
0 |
0 |
T130 |
107654 |
809 |
0 |
0 |
T131 |
92178 |
975 |
0 |
0 |
T132 |
37569 |
108 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
576637868 |
6707 |
0 |
0 |
T88 |
76331 |
641 |
0 |
0 |
T104 |
11102 |
7 |
0 |
0 |
T108 |
6742 |
6 |
0 |
0 |
T111 |
3697 |
5 |
0 |
0 |
T113 |
108976 |
664 |
0 |
0 |
T128 |
7617 |
17 |
0 |
0 |
T129 |
9133 |
21 |
0 |
0 |
T130 |
107654 |
707 |
0 |
0 |
T131 |
92178 |
807 |
0 |
0 |
T132 |
37569 |
129 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
576637868 |
7457 |
0 |
0 |
T88 |
76331 |
664 |
0 |
0 |
T104 |
11102 |
100 |
0 |
0 |
T111 |
3697 |
39 |
0 |
0 |
T113 |
108976 |
682 |
0 |
0 |
T128 |
7617 |
11 |
0 |
0 |
T129 |
9133 |
31 |
0 |
0 |
T130 |
107654 |
835 |
0 |
0 |
T131 |
92178 |
808 |
0 |
0 |
T132 |
37569 |
169 |
0 |
0 |
T133 |
100165 |
1043 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
576637868 |
7187 |
0 |
0 |
T74 |
1746 |
6 |
0 |
0 |
T88 |
76331 |
588 |
0 |
0 |
T104 |
11102 |
92 |
0 |
0 |
T108 |
6742 |
17 |
0 |
0 |
T113 |
108976 |
698 |
0 |
0 |
T128 |
7617 |
11 |
0 |
0 |
T129 |
9133 |
15 |
0 |
0 |
T130 |
107654 |
819 |
0 |
0 |
T131 |
92178 |
564 |
0 |
0 |
T132 |
37569 |
138 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
576637868 |
6256 |
0 |
0 |
T74 |
1746 |
1 |
0 |
0 |
T88 |
76331 |
637 |
0 |
0 |
T104 |
11102 |
46 |
0 |
0 |
T108 |
6742 |
39 |
0 |
0 |
T113 |
108976 |
727 |
0 |
0 |
T128 |
7617 |
12 |
0 |
0 |
T129 |
9133 |
51 |
0 |
0 |
T130 |
107654 |
565 |
0 |
0 |
T131 |
92178 |
699 |
0 |
0 |
T132 |
37569 |
162 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
576637868 |
7098 |
0 |
0 |
T88 |
76331 |
634 |
0 |
0 |
T104 |
11102 |
56 |
0 |
0 |
T108 |
6742 |
77 |
0 |
0 |
T111 |
3697 |
31 |
0 |
0 |
T113 |
108976 |
732 |
0 |
0 |
T128 |
7617 |
38 |
0 |
0 |
T129 |
9133 |
18 |
0 |
0 |
T130 |
107654 |
663 |
0 |
0 |
T131 |
92178 |
541 |
0 |
0 |
T132 |
37569 |
139 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
576637868 |
7072 |
0 |
0 |
T74 |
1746 |
7 |
0 |
0 |
T88 |
76331 |
734 |
0 |
0 |
T104 |
11102 |
64 |
0 |
0 |
T108 |
6742 |
29 |
0 |
0 |
T111 |
3697 |
4 |
0 |
0 |
T128 |
7617 |
13 |
0 |
0 |
T129 |
9133 |
47 |
0 |
0 |
T130 |
107654 |
862 |
0 |
0 |
T131 |
92178 |
561 |
0 |
0 |
T132 |
37569 |
146 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
576637868 |
6344 |
0 |
0 |
T88 |
76331 |
681 |
0 |
0 |
T104 |
11102 |
78 |
0 |
0 |
T108 |
6742 |
7 |
0 |
0 |
T113 |
108976 |
640 |
0 |
0 |
T128 |
7617 |
18 |
0 |
0 |
T129 |
9133 |
26 |
0 |
0 |
T130 |
107654 |
639 |
0 |
0 |
T131 |
92178 |
536 |
0 |
0 |
T132 |
37569 |
131 |
0 |
0 |
T133 |
100165 |
644 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
576637868 |
6754 |
0 |
0 |
T74 |
1746 |
1 |
0 |
0 |
T88 |
76331 |
581 |
0 |
0 |
T104 |
11102 |
16 |
0 |
0 |
T108 |
6742 |
26 |
0 |
0 |
T111 |
3697 |
24 |
0 |
0 |
T128 |
7617 |
6 |
0 |
0 |
T129 |
9133 |
46 |
0 |
0 |
T130 |
107654 |
443 |
0 |
0 |
T131 |
92178 |
810 |
0 |
0 |
T132 |
37569 |
129 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
576637868 |
6708 |
0 |
0 |
T88 |
76331 |
576 |
0 |
0 |
T104 |
11102 |
11 |
0 |
0 |
T108 |
6742 |
34 |
0 |
0 |
T111 |
3697 |
43 |
0 |
0 |
T113 |
108976 |
780 |
0 |
0 |
T128 |
7617 |
21 |
0 |
0 |
T129 |
9133 |
14 |
0 |
0 |
T130 |
107654 |
634 |
0 |
0 |
T131 |
92178 |
590 |
0 |
0 |
T132 |
37569 |
150 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
576637868 |
7478 |
0 |
0 |
T88 |
76331 |
534 |
0 |
0 |
T104 |
11102 |
51 |
0 |
0 |
T108 |
6742 |
55 |
0 |
0 |
T111 |
3697 |
3 |
0 |
0 |
T113 |
108976 |
742 |
0 |
0 |
T128 |
7617 |
53 |
0 |
0 |
T129 |
9133 |
26 |
0 |
0 |
T130 |
107654 |
946 |
0 |
0 |
T131 |
92178 |
662 |
0 |
0 |
T132 |
37569 |
136 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
576637868 |
7725 |
0 |
0 |
T88 |
76331 |
456 |
0 |
0 |
T104 |
11102 |
57 |
0 |
0 |
T108 |
6742 |
41 |
0 |
0 |
T113 |
108976 |
745 |
0 |
0 |
T128 |
7617 |
16 |
0 |
0 |
T130 |
107654 |
946 |
0 |
0 |
T131 |
92178 |
919 |
0 |
0 |
T132 |
37569 |
128 |
0 |
0 |
T133 |
100165 |
897 |
0 |
0 |
T134 |
21880 |
77 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
576637868 |
3400 |
0 |
0 |
T88 |
76331 |
109 |
0 |
0 |
T104 |
11102 |
7 |
0 |
0 |
T108 |
6742 |
8 |
0 |
0 |
T111 |
3697 |
1 |
0 |
0 |
T113 |
108976 |
664 |
0 |
0 |
T128 |
7617 |
24 |
0 |
0 |
T129 |
9133 |
8 |
0 |
0 |
T130 |
107654 |
193 |
0 |
0 |
T131 |
92178 |
169 |
0 |
0 |
T132 |
37569 |
153 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
576637868 |
3482 |
0 |
0 |
T88 |
76331 |
107 |
0 |
0 |
T104 |
11102 |
21 |
0 |
0 |
T108 |
6742 |
7 |
0 |
0 |
T113 |
108976 |
745 |
0 |
0 |
T128 |
7617 |
17 |
0 |
0 |
T129 |
9133 |
10 |
0 |
0 |
T130 |
107654 |
177 |
0 |
0 |
T131 |
92178 |
160 |
0 |
0 |
T132 |
37569 |
136 |
0 |
0 |
T133 |
100165 |
155 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
576637868 |
3426 |
0 |
0 |
T74 |
1746 |
9 |
0 |
0 |
T88 |
76331 |
104 |
0 |
0 |
T104 |
11102 |
20 |
0 |
0 |
T108 |
6742 |
4 |
0 |
0 |
T111 |
3697 |
2 |
0 |
0 |
T128 |
7617 |
10 |
0 |
0 |
T129 |
9133 |
2 |
0 |
0 |
T130 |
107654 |
170 |
0 |
0 |
T131 |
92178 |
165 |
0 |
0 |
T132 |
37569 |
159 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
576637868 |
3577 |
0 |
0 |
T74 |
1746 |
6 |
0 |
0 |
T88 |
76331 |
132 |
0 |
0 |
T104 |
11102 |
15 |
0 |
0 |
T108 |
6742 |
7 |
0 |
0 |
T113 |
108976 |
711 |
0 |
0 |
T129 |
9133 |
18 |
0 |
0 |
T130 |
107654 |
136 |
0 |
0 |
T131 |
92178 |
178 |
0 |
0 |
T132 |
37569 |
164 |
0 |
0 |
T133 |
100165 |
174 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
576637868 |
3914 |
0 |
0 |
T88 |
76331 |
247 |
0 |
0 |
T104 |
11102 |
26 |
0 |
0 |
T108 |
6742 |
7 |
0 |
0 |
T113 |
108976 |
726 |
0 |
0 |
T128 |
7617 |
21 |
0 |
0 |
T129 |
9133 |
18 |
0 |
0 |
T130 |
107654 |
269 |
0 |
0 |
T131 |
92178 |
216 |
0 |
0 |
T132 |
37569 |
118 |
0 |
0 |
T133 |
100165 |
264 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
576637868 |
6263 |
0 |
0 |
T66 |
9706 |
0 |
0 |
0 |
T135 |
215948 |
32 |
0 |
0 |
T136 |
0 |
19 |
0 |
0 |
T137 |
0 |
4 |
0 |
0 |
T138 |
0 |
42 |
0 |
0 |
T139 |
0 |
12 |
0 |
0 |
T140 |
0 |
13 |
0 |
0 |
T141 |
0 |
51 |
0 |
0 |
T142 |
0 |
55 |
0 |
0 |
T143 |
0 |
22 |
0 |
0 |
T144 |
0 |
36 |
0 |
0 |
T145 |
47982 |
0 |
0 |
0 |
T146 |
1348 |
0 |
0 |
0 |
T147 |
12624 |
0 |
0 |
0 |
T148 |
306575 |
0 |
0 |
0 |
T149 |
1728 |
0 |
0 |
0 |
T150 |
1665 |
0 |
0 |
0 |
T151 |
877 |
0 |
0 |
0 |
T152 |
770132 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
576637868 |
3502 |
0 |
0 |
T74 |
1746 |
4 |
0 |
0 |
T88 |
76331 |
119 |
0 |
0 |
T104 |
11102 |
20 |
0 |
0 |
T108 |
6742 |
7 |
0 |
0 |
T111 |
3697 |
6 |
0 |
0 |
T128 |
7617 |
25 |
0 |
0 |
T129 |
9133 |
7 |
0 |
0 |
T130 |
107654 |
200 |
0 |
0 |
T131 |
92178 |
130 |
0 |
0 |
T132 |
37569 |
125 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
576637868 |
3476 |
0 |
0 |
T88 |
76331 |
151 |
0 |
0 |
T104 |
11102 |
21 |
0 |
0 |
T108 |
6742 |
8 |
0 |
0 |
T111 |
3697 |
10 |
0 |
0 |
T113 |
108976 |
675 |
0 |
0 |
T128 |
7617 |
25 |
0 |
0 |
T130 |
107654 |
207 |
0 |
0 |
T131 |
92178 |
134 |
0 |
0 |
T132 |
37569 |
111 |
0 |
0 |
T133 |
100165 |
176 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
576637868 |
3296 |
0 |
0 |
T88 |
76331 |
86 |
0 |
0 |
T104 |
11102 |
14 |
0 |
0 |
T108 |
6742 |
6 |
0 |
0 |
T113 |
108976 |
694 |
0 |
0 |
T128 |
7617 |
20 |
0 |
0 |
T129 |
9133 |
23 |
0 |
0 |
T130 |
107654 |
118 |
0 |
0 |
T131 |
92178 |
140 |
0 |
0 |
T132 |
37569 |
124 |
0 |
0 |
T133 |
100165 |
102 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
576637868 |
3115 |
0 |
0 |
T88 |
76331 |
82 |
0 |
0 |
T104 |
11102 |
16 |
0 |
0 |
T111 |
3697 |
8 |
0 |
0 |
T113 |
108976 |
710 |
0 |
0 |
T128 |
7617 |
5 |
0 |
0 |
T129 |
9133 |
6 |
0 |
0 |
T130 |
107654 |
123 |
0 |
0 |
T131 |
92178 |
139 |
0 |
0 |
T132 |
37569 |
153 |
0 |
0 |
T133 |
100165 |
82 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
576637868 |
2945 |
0 |
0 |
T88 |
76331 |
72 |
0 |
0 |
T104 |
11102 |
10 |
0 |
0 |
T108 |
6742 |
5 |
0 |
0 |
T113 |
108976 |
617 |
0 |
0 |
T128 |
7617 |
6 |
0 |
0 |
T129 |
9133 |
12 |
0 |
0 |
T130 |
107654 |
110 |
0 |
0 |
T131 |
92178 |
82 |
0 |
0 |
T132 |
37569 |
121 |
0 |
0 |
T133 |
100165 |
130 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
576637868 |
3134 |
0 |
0 |
T74 |
1746 |
6 |
0 |
0 |
T88 |
76331 |
66 |
0 |
0 |
T104 |
11102 |
25 |
0 |
0 |
T113 |
108976 |
649 |
0 |
0 |
T128 |
7617 |
36 |
0 |
0 |
T129 |
9133 |
11 |
0 |
0 |
T130 |
107654 |
131 |
0 |
0 |
T131 |
92178 |
113 |
0 |
0 |
T132 |
37569 |
147 |
0 |
0 |
T133 |
100165 |
113 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
576637868 |
4165 |
0 |
0 |
T74 |
1746 |
3 |
0 |
0 |
T88 |
76331 |
177 |
0 |
0 |
T104 |
11102 |
20 |
0 |
0 |
T108 |
6742 |
6 |
0 |
0 |
T111 |
3697 |
1 |
0 |
0 |
T128 |
7617 |
26 |
0 |
0 |
T129 |
9133 |
15 |
0 |
0 |
T130 |
107654 |
267 |
0 |
0 |
T131 |
92178 |
219 |
0 |
0 |
T132 |
37569 |
141 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
576637868 |
3367 |
0 |
0 |
T88 |
76331 |
68 |
0 |
0 |
T108 |
6742 |
1 |
0 |
0 |
T113 |
108976 |
784 |
0 |
0 |
T128 |
7617 |
29 |
0 |
0 |
T129 |
9133 |
2 |
0 |
0 |
T130 |
107654 |
131 |
0 |
0 |
T131 |
92178 |
116 |
0 |
0 |
T132 |
37569 |
142 |
0 |
0 |
T133 |
100165 |
121 |
0 |
0 |
T134 |
21880 |
87 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
576637868 |
4511 |
0 |
0 |
T74 |
1746 |
2 |
0 |
0 |
T88 |
76331 |
225 |
0 |
0 |
T104 |
11102 |
8 |
0 |
0 |
T108 |
6742 |
33 |
0 |
0 |
T113 |
108976 |
630 |
0 |
0 |
T128 |
7617 |
30 |
0 |
0 |
T129 |
9133 |
17 |
0 |
0 |
T130 |
107654 |
365 |
0 |
0 |
T131 |
92178 |
368 |
0 |
0 |
T132 |
37569 |
165 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
576637868 |
3403 |
0 |
0 |
T88 |
76331 |
113 |
0 |
0 |
T104 |
11102 |
19 |
0 |
0 |
T108 |
6742 |
6 |
0 |
0 |
T111 |
3697 |
10 |
0 |
0 |
T113 |
108976 |
677 |
0 |
0 |
T128 |
7617 |
45 |
0 |
0 |
T129 |
9133 |
2 |
0 |
0 |
T130 |
107654 |
158 |
0 |
0 |
T131 |
92178 |
178 |
0 |
0 |
T132 |
37569 |
120 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
576637868 |
3032 |
0 |
0 |
T88 |
76331 |
78 |
0 |
0 |
T104 |
11102 |
11 |
0 |
0 |
T108 |
6742 |
4 |
0 |
0 |
T113 |
108976 |
666 |
0 |
0 |
T128 |
7617 |
37 |
0 |
0 |
T129 |
9133 |
8 |
0 |
0 |
T130 |
107654 |
93 |
0 |
0 |
T131 |
92178 |
93 |
0 |
0 |
T132 |
37569 |
147 |
0 |
0 |
T133 |
100165 |
106 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
576637868 |
3092 |
0 |
0 |
T74 |
1746 |
4 |
0 |
0 |
T88 |
76331 |
71 |
0 |
0 |
T104 |
11102 |
16 |
0 |
0 |
T108 |
6742 |
2 |
0 |
0 |
T111 |
3697 |
1 |
0 |
0 |
T128 |
7617 |
40 |
0 |
0 |
T129 |
9133 |
8 |
0 |
0 |
T130 |
107654 |
121 |
0 |
0 |
T131 |
92178 |
100 |
0 |
0 |
T132 |
37569 |
87 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
576637868 |
3161 |
0 |
0 |
T74 |
1746 |
6 |
0 |
0 |
T88 |
76331 |
84 |
0 |
0 |
T104 |
11102 |
20 |
0 |
0 |
T108 |
6742 |
2 |
0 |
0 |
T111 |
3697 |
1 |
0 |
0 |
T113 |
108976 |
666 |
0 |
0 |
T128 |
7617 |
41 |
0 |
0 |
T130 |
107654 |
107 |
0 |
0 |
T131 |
92178 |
102 |
0 |
0 |
T132 |
37569 |
115 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
576637868 |
3020 |
0 |
0 |
T74 |
1746 |
9 |
0 |
0 |
T88 |
76331 |
89 |
0 |
0 |
T104 |
11102 |
12 |
0 |
0 |
T113 |
108976 |
679 |
0 |
0 |
T128 |
7617 |
8 |
0 |
0 |
T129 |
9133 |
6 |
0 |
0 |
T130 |
107654 |
119 |
0 |
0 |
T131 |
92178 |
105 |
0 |
0 |
T132 |
37569 |
132 |
0 |
0 |
T133 |
100165 |
125 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
576637868 |
3372 |
0 |
0 |
T88 |
76331 |
81 |
0 |
0 |
T104 |
11102 |
22 |
0 |
0 |
T108 |
6742 |
1 |
0 |
0 |
T113 |
108976 |
782 |
0 |
0 |
T128 |
7617 |
28 |
0 |
0 |
T129 |
9133 |
8 |
0 |
0 |
T130 |
107654 |
152 |
0 |
0 |
T131 |
92178 |
120 |
0 |
0 |
T132 |
37569 |
139 |
0 |
0 |
T133 |
100165 |
108 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
576637868 |
3128 |
0 |
0 |
T88 |
76331 |
75 |
0 |
0 |
T104 |
11102 |
7 |
0 |
0 |
T111 |
3697 |
9 |
0 |
0 |
T113 |
108976 |
677 |
0 |
0 |
T128 |
7617 |
50 |
0 |
0 |
T129 |
9133 |
16 |
0 |
0 |
T130 |
107654 |
89 |
0 |
0 |
T131 |
92178 |
93 |
0 |
0 |
T132 |
37569 |
122 |
0 |
0 |
T133 |
100165 |
120 |
0 |
0 |