Unified Coverage Report :: Module :: spi_cmdparse

Module : spi_cmdparse

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.74	100.00	87.80		100.00	95.92	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_cmdparse.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_cmdparse	96.74	100.00	87.80		100.00	95.92	100.00

---

Module Instance : tb.dut.u_cmdparse

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.74	100.00	87.80		100.00	95.92	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.74	100.00	87.80		100.00	95.92	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.69	94.25	84.31	96.94		87.50	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : spi_cmdparse

	Line No.	Total	Covered	Percent
TOTAL		108	108	100.00
CONT_ASSIGN	81	1	1	100.00
ALWAYS	86	3	3	100.00
CONT_ASSIGN	152	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
ALWAYS	181	4	4	100.00
CONT_ASSIGN	190	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	198	1	1	100.00
CONT_ASSIGN	200	1	1	100.00
ALWAYS	204	4	4	100.00
ALWAYS	214	6	6	100.00
ALWAYS	229	7	7	100.00
CONT_ASSIGN	249	1	1	100.00
CONT_ASSIGN	250	1	1	100.00
ALWAYS	259	5	5	100.00
CONT_ASSIGN	275	1	1	100.00
ALWAYS	279	11	11	100.00
CONT_ASSIGN	291	1	1	100.00
CONT_ASSIGN	298	1	1	100.00
CONT_ASSIGN	299	1	1	100.00
CONT_ASSIGN	300	1	1	100.00
ALWAYS	303	4	4	100.00
ALWAYS	311	48	48	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_cmdparse.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_cmdparse.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
81	1	1
86	1	1
87	1	1
88	1	1
152	1	1
156	1	1
181	1	1
182	1	1
183	1	1
185	1	1
			MISSING_ELSE
190	1	1
192	1	1
194	1	1
196	1	1
198	1	1
200	1	1
204	1	1
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
214	1	1
215	1	1
221	1	1
222	1	1
223	1	1
224	1	1
			MISSING_ELSE
229	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1
240	1	1
			MISSING_ELSE
			MISSING_ELSE
249	1	1
250	1	1
259	1	1
265	1	1
267	1	1
268	1	1
269	1	1
			MISSING_ELSE
275	1	1
279	1	1
280	1	1
281	1	1
282	1	1
283	1	1
284	2	2
			MISSING_ELSE
285	2	2
			MISSING_ELSE
286	2	2
			MISSING_ELSE
			MISSING_ELSE
291	1	1
298	1	1
299	1	1
300	1	1
303	1	1
304	1	1
305	1	1
306	1	1
			==> MISSING_ELSE
311	1	1
313	1	1
314	1	1
316	1	1
317	1	1
319	1	1
321	1	1
323	1	1
325	1	1
326	1	1
328	1	1
330	1	1
331	1	1
332	1	1
333	1	1
334	1	1
336	1	1
341	1	1
342	1	1
343	1	1
344	1	1
345	1	1
347	1	1
353	1	1
354	1	1
355	1	1
356	1	1
357	1	1
360	1	1
368	1	1
372	1	1
373	1	1
377	1	1
380	1	1
384	1	1
387	1	1
397	1	1
399	1	1
400	1	1
			MISSING_ELSE
405	1	1
407	1	1
409	1	1
411	1	1
413	1	1
415	1	1
417	1	1
420	1	1
422	1	1

---

Cond Coverage for Module : spi_cmdparse

	Total	Covered	Percent
Conditions	82	72	87.80
Logical	82	72	87.80
Non-Logical	0	0
Event	0	0

 LINE       183
 EXPRESSION (cmd_info_i[(CmdInfoReadStatus1 + i)].valid && (data_i == cmd_info_i[(CmdInfoReadStatus1 + i)].opcode))
             ---------------------1--------------------    ---------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T3,T5,T6

 LINE       183
 SUB-EXPRESSION (data_i == cmd_info_i[(CmdInfoReadStatus1 + i)].opcode)
                ---------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       190
 EXPRESSION (cmd_info_i[CmdInfoReadJedecId].valid && (data_i == cmd_info_i[CmdInfoReadJedecId].opcode))
             ------------------1-----------------    ------------------------2------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T3,T5,T6

 LINE       190
 SUB-EXPRESSION (data_i == cmd_info_i[CmdInfoReadJedecId].opcode)
                ------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       192
 EXPRESSION (cmd_info_i[CmdInfoReadSfdp].valid && (data_i == cmd_info_i[CmdInfoReadSfdp].opcode))
             ----------------1----------------    -----------------------2----------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T3,T5,T6

 LINE       192
 SUB-EXPRESSION (data_i == cmd_info_i[CmdInfoReadSfdp].opcode)
                -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       194
 EXPRESSION (cmd_info_i[CmdInfoEn4B].valid && (data_i == cmd_info_i[CmdInfoEn4B].opcode))
             --------------1--------------    ---------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T9
1	1	Covered	T3,T5,T9

 LINE       194
 SUB-EXPRESSION (data_i == cmd_info_i[CmdInfoEn4B].opcode)
                ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       196
 EXPRESSION (cmd_info_i[CmdInfoEx4B].valid && (data_i == cmd_info_i[CmdInfoEx4B].opcode))
             --------------1--------------    ---------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T9,T10
1	1	Covered	T3,T9,T10

 LINE       196
 SUB-EXPRESSION (data_i == cmd_info_i[CmdInfoEx4B].opcode)
                ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       198
 EXPRESSION (cmd_info_i[CmdInfoWrEn].valid && (data_i == cmd_info_i[CmdInfoWrEn].opcode))
             --------------1--------------    ---------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T14
1	1	Covered	T3,T5,T14

 LINE       198
 SUB-EXPRESSION (data_i == cmd_info_i[CmdInfoWrEn].opcode)
                ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       200
 EXPRESSION (cmd_info_i[CmdInfoWrDi].valid && (data_i == cmd_info_i[CmdInfoWrDi].opcode))
             --------------1--------------    ---------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T14,T15
1	1	Covered	T3,T14,T15

 LINE       200
 SUB-EXPRESSION (data_i == cmd_info_i[CmdInfoWrDi].opcode)
                ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       206
 EXPRESSION (cmd_info_i[i].valid && (data_i == cmd_info_i[i].opcode))
             ---------1---------    ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T3,T5,T6

 LINE       206
 SUB-EXPRESSION (data_i == cmd_info_i[i].opcode)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION ((st == StIdle) && module_active && data_valid_i)
             -------1------    ------2------    ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T5,T6
1	0	1	Not Covered
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T3,T5,T6

 LINE       236
 SUB-EXPRESSION (st == StIdle)
                -------1------

-1-	Status	Tests
0	Covered	T3,T5,T6
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (cmd_info_i[i].valid && (data_i == cmd_info_i[i].opcode))
             ---------1---------    ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T28,T36,T83
1	0	Covered	T3,T5,T6
1	1	Covered	T3,T5,T6

 LINE       238
 SUB-EXPRESSION (data_i == cmd_info_i[i].opcode)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T3,T5,T6
1	Covered	T3,T5,T6

 LINE       267
 EXPRESSION ((st == StIdle) && module_active && data_valid_i)
             -------1------    ------2------    ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T5,T6
1	0	1	Not Covered
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T3,T5,T6

 LINE       267
 SUB-EXPRESSION (st == StIdle)
                -------1------

-1-	Status	Tests
0	Covered	T3,T5,T6
1	Covered	T1,T2,T3

 LINE       291
 EXPRESSION ((cmd_info_q.read_pipeline_mode == RdPipeTwoStageHalfCycle) || (cmd_info_q.read_pipeline_mode == RdPipeTwoStageFullCycle))
             -----------------------------1----------------------------    -----------------------------2----------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       291
 SUB-EXPRESSION (cmd_info_q.read_pipeline_mode == RdPipeTwoStageHalfCycle)
                -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       291
 SUB-EXPRESSION (cmd_info_q.read_pipeline_mode == RdPipeTwoStageFullCycle)
                -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       298
 EXPRESSION (spi_mode_i == FlashMode)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       299
 EXPRESSION (spi_mode_i == PassThrough)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T9,T10

 LINE       300
 EXPRESSION (in_flashmode || in_passthrough)
             ------1-----    -------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T5,T9,T10
1	0	Covered	T1,T2,T3

 LINE       323
 EXPRESSION (module_active && data_valid_i && cmd_info_d.valid)
             ------1------    ------2-----    --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Covered	T3,T5,T9
1	1	1	Covered	T3,T5,T6

 LINE       380
 EXPRESSION (opcode_en4b ? DpEn4B : DpEx4B)
             -----1-----

-1-	Status	Tests
0	Covered	T3,T14,T15
1	Covered	T3,T5,T14

 LINE       387
 EXPRESSION (opcode_wren ? DpWrEn : DpWrDi)
             -----1-----

-1-	Status	Tests
0	Covered	T3,T14,T15
1	Covered	T3,T5,T14

 LINE       397
 EXPRESSION (module_active && data_valid_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T5,T9

---

FSM Coverage for Module : spi_cmdparse

Summary for FSM :: st

	Total	Covered	Percent
States	9	9	100.00	(Not included in score)
Transitions	8	8	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StAddr4B	377	Covered	T3,T5,T14
StIdle	236	Covered	T1,T2,T3
StJedec	342	Covered	T3,T14,T15
StReadCmd	368	Covered	T3,T6,T9
StSfdp	354	Covered	T3,T14,T22
StStatus	331	Covered	T3,T10,T14
StUpload	372	Covered	T3,T14,T22
StWait	336	Covered	T3,T5,T9
StWrEn	384	Covered	T3,T5,T14

transitions	Line No.	Covered	Tests
StIdle->StAddr4B	377	Covered	T3,T5,T14
StIdle->StJedec	342	Covered	T3,T14,T15
StIdle->StReadCmd	368	Covered	T3,T6,T9
StIdle->StSfdp	354	Covered	T3,T14,T22
StIdle->StStatus	331	Covered	T3,T10,T14
StIdle->StUpload	372	Covered	T3,T14,T22
StIdle->StWait	336	Covered	T3,T5,T9
StIdle->StWrEn	384	Covered	T3,T5,T14

---

Branch Coverage for Module : spi_cmdparse

	Line No.	Total	Covered	Percent
Branches		49	47	95.92
IF	183	2	2	100.00
IF	206	2	2	100.00
IF	214	3	3	100.00
IF	236	2	2	100.00
IF	267	2	2	100.00
IF	279	8	8	100.00
IF	303	3	2	66.67
CASE	321	27	26	96.30

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_cmdparse.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_cmdparse.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	183	if ((cmd_info_i[(CmdInfoReadStatus1 + i)].valid && (data_i == cmd_info_i[(CmdInfoReadStatus1 + i)].opcode)))

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	206	if ((cmd_info_i[i].valid && (data_i == cmd_info_i[i].opcode)))

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	214	if ((!rst_ni))
-2-:	222	if (latch_cmdinfo)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T5,T6
0	0	Covered	T3,T5,T6

	LineNo.	Expression
-1-:	236	if ((((st == StIdle) && module_active) && data_valid_i))

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	267	if ((((st == StIdle) && module_active) && data_valid_i))

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	279	if ((!rst_ni))
-2-:	283	if (intercept_d)
-3-:	284	if (opcode_readstatus)
-4-:	285	if (opcode_readjedec)
-5-:	286	if (opcode_readsfdp)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	1	-	-	Covered	T10,T15,T23
0	1	0	-	-	Covered	T15,T23,T24
0	1	-	1	-	Covered	T15,T23,T24
0	1	-	0	-	Covered	T10,T15,T23
0	1	-	-	1	Covered	T23,T24,T83
0	1	-	-	0	Covered	T10,T15,T23
0	0	-	-	-	Covered	T3,T5,T6

	LineNo.	Expression
-1-:	303	if ((!rst_ni))
-2-:	305	if (module_active)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T5,T6
0	0	Not Covered

	LineNo.	Expression
-1-:	321	case (st)
-2-:	323	if (((module_active && data_valid_i) && cmd_info_d.valid))
-3-:	328	case (1'b1)
-4-:	330	if (in_flashmode)
-5-:	332	if (cfg_intercept_en_status_i)
-6-:	341	if (in_flashmode)
-7-:	343	if (cfg_intercept_en_jedec_i)
-8-:	353	if (in_flashmode)
-9-:	355	if (cfg_intercept_en_sfdp_i)
-10-:	380	(opcode_en4b) ? 
-11-:	387	(opcode_wren) ? 
-12-:	397	if ((module_active && data_valid_i))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	Status	Tests
StIdle	1	opcode_readstatus	1	-	-	-	-	-	-	-	-	Covered	T3,T14,T22
StIdle	1	opcode_readstatus	0	1	-	-	-	-	-	-	-	Covered	T10,T15,T23
StIdle	1	opcode_readstatus	0	0	-	-	-	-	-	-	-	Covered	T28,T29,T84
StIdle	1	opcode_readjedec	-	-	1	-	-	-	-	-	-	Covered	T3,T14,T22
StIdle	1	opcode_readjedec	-	-	0	1	-	-	-	-	-	Covered	T15,T23,T24
StIdle	1	opcode_readjedec	-	-	0	0	-	-	-	-	-	Covered	T23,T24,T26
StIdle	1	opcode_readsfdp	-	-	-	-	1	-	-	-	-	Covered	T3,T14,T22
StIdle	1	opcode_readsfdp	-	-	-	-	0	1	-	-	-	Covered	T23,T24,T83
StIdle	1	opcode_readsfdp	-	-	-	-	0	0	-	-	-	Covered	T9,T12,T11
StIdle	1	opcode_readcmd	-	-	-	-	-	-	-	-	-	Covered	T3,T6,T9
StIdle	1	upload	-	-	-	-	-	-	-	-	-	Covered	T3,T14,T22
StIdle	1	opcode_en4b opcode_ex4b	-	-	-	-	-	-	1	-	-	Covered	T3,T5,T14
StIdle	1	opcode_en4b opcode_ex4b	-	-	-	-	-	-	0	-	-	Covered	T3,T14,T15
StIdle	1	opcode_wren opcode_wrdi	-	-	-	-	-	-	-	1	-	Covered	T3,T5,T14
StIdle	1	opcode_wren opcode_wrdi	-	-	-	-	-	-	-	0	-	Covered	T3,T14,T15
StIdle	1	default	-	-	-	-	-	-	-	-	-	Covered	T3,T9,T10
StIdle	0	-	-	-	-	-	-	-	-	-	1	Covered	T3,T5,T9
StIdle	0	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
StStatus	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T10,T14
StJedec	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T14,T15
StSfdp	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T14,T22
StReadCmd	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T6,T9
StUpload	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T14,T22
StAddr4B	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T14
StWrEn	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T14
StWait	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T9
default	-	-	-	-	-	-	-	-	-	-	-	Not Covered

---

Assert Coverage for Module : spi_cmdparse

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CmdOnlySelDpKnown_A	193546521	148491681	0	0
OnlyOneDatapath_A	193546521	72298	0	0
SelDpKnown_A	193546521	148491681	0	0
StKnown_A	193546521	148491681	0	0

CmdOnlySelDpKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193546521	148491681	0	0
T3	629757	405520	0	0
T4	118850	0	0	0
T5	31504	31504	0	0
T6	17905	17502	0	0
T9	23212	23212	0	0
T10	47666	47188	0	0
T11	53748	53748	0	0
T12	82827	82530	0	0
T13	194272	193786	0	0
T14	0	504708	0	0
T15	0	92754	0	0
T16	178040	0	0	0

OnlyOneDatapath_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193546521	72298	0	0
T3	629757	307	0	0
T4	118850	0	0	0
T5	31504	36	0	0
T6	17905	8	0	0
T9	23212	8	0	0
T10	47666	10	0	0
T11	53748	26	0	0
T12	82827	18	0	0
T13	194272	32	0	0
T14	0	416	0	0
T15	0	40	0	0
T16	178040	0	0	0

SelDpKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193546521	148491681	0	0
T3	629757	405520	0	0
T4	118850	0	0	0
T5	31504	31504	0	0
T6	17905	17502	0	0
T9	23212	23212	0	0
T10	47666	47188	0	0
T11	53748	53748	0	0
T12	82827	82530	0	0
T13	194272	193786	0	0
T14	0	504708	0	0
T15	0	92754	0	0
T16	178040	0	0	0

StKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193546521	148491681	0	0
T3	629757	405520	0	0
T4	118850	0	0	0
T5	31504	31504	0	0
T6	17905	17502	0	0
T9	23212	23212	0	0
T10	47666	47188	0	0
T11	53748	53748	0	0
T12	82827	82530	0	0
T13	194272	193786	0	0
T14	0	504708	0	0
T15	0	92754	0	0
T16	178040	0	0	0