| T814 |
/workspace/coverage/default/6.spi_device_csb_read.2979346213 |
|
|
Mar 26 03:04:58 PM PDT 24 |
Mar 26 03:04:58 PM PDT 24 |
22606167 ps |
| T815 |
/workspace/coverage/default/18.spi_device_csb_read.3565961411 |
|
|
Mar 26 03:05:49 PM PDT 24 |
Mar 26 03:05:50 PM PDT 24 |
51893360 ps |
| T816 |
/workspace/coverage/default/47.spi_device_flash_mode.2593565806 |
|
|
Mar 26 03:07:35 PM PDT 24 |
Mar 26 03:07:56 PM PDT 24 |
45406268725 ps |
| T817 |
/workspace/coverage/default/25.spi_device_mailbox.4119527955 |
|
|
Mar 26 03:06:16 PM PDT 24 |
Mar 26 03:06:34 PM PDT 24 |
16860430133 ps |
| T141 |
/workspace/coverage/default/30.spi_device_stress_all.1834026921 |
|
|
Mar 26 03:06:36 PM PDT 24 |
Mar 26 03:07:48 PM PDT 24 |
6316820482 ps |
| T818 |
/workspace/coverage/default/17.spi_device_tpm_all.1480167817 |
|
|
Mar 26 03:05:54 PM PDT 24 |
Mar 26 03:06:05 PM PDT 24 |
13034510022 ps |
| T52 |
/workspace/coverage/default/1.spi_device_flash_and_tpm.2970046044 |
|
|
Mar 26 03:04:44 PM PDT 24 |
Mar 26 03:07:54 PM PDT 24 |
41306783276 ps |
| T142 |
/workspace/coverage/default/45.spi_device_stress_all.2335500610 |
|
|
Mar 26 03:07:24 PM PDT 24 |
Mar 26 03:11:59 PM PDT 24 |
685986470577 ps |
| T819 |
/workspace/coverage/default/30.spi_device_mailbox.2126504201 |
|
|
Mar 26 03:06:28 PM PDT 24 |
Mar 26 03:06:55 PM PDT 24 |
35523135304 ps |
| T820 |
/workspace/coverage/default/26.spi_device_intercept.348792388 |
|
|
Mar 26 03:06:15 PM PDT 24 |
Mar 26 03:06:18 PM PDT 24 |
75606112 ps |
| T254 |
/workspace/coverage/default/31.spi_device_flash_and_tpm.4163230781 |
|
|
Mar 26 03:06:40 PM PDT 24 |
Mar 26 03:09:39 PM PDT 24 |
20910506601 ps |
| T821 |
/workspace/coverage/default/12.spi_device_flash_mode.3284929089 |
|
|
Mar 26 03:05:26 PM PDT 24 |
Mar 26 03:05:41 PM PDT 24 |
4070315285 ps |
| T822 |
/workspace/coverage/default/13.spi_device_flash_and_tpm.2814060158 |
|
|
Mar 26 03:05:26 PM PDT 24 |
Mar 26 03:06:29 PM PDT 24 |
22953744211 ps |
| T823 |
/workspace/coverage/default/30.spi_device_alert_test.3469533004 |
|
|
Mar 26 03:06:41 PM PDT 24 |
Mar 26 03:06:42 PM PDT 24 |
31808402 ps |
| T257 |
/workspace/coverage/default/49.spi_device_stress_all.2270142658 |
|
|
Mar 26 03:07:42 PM PDT 24 |
Mar 26 03:10:12 PM PDT 24 |
7895744338 ps |
| T824 |
/workspace/coverage/default/23.spi_device_upload.3292658451 |
|
|
Mar 26 03:06:08 PM PDT 24 |
Mar 26 03:06:37 PM PDT 24 |
9593568127 ps |
| T825 |
/workspace/coverage/default/47.spi_device_alert_test.1167394868 |
|
|
Mar 26 03:07:33 PM PDT 24 |
Mar 26 03:07:36 PM PDT 24 |
21519504 ps |
| T826 |
/workspace/coverage/default/4.spi_device_pass_cmd_filtering.2852529893 |
|
|
Mar 26 03:04:45 PM PDT 24 |
Mar 26 03:04:56 PM PDT 24 |
3111576219 ps |
| T143 |
/workspace/coverage/default/33.spi_device_stress_all.111248231 |
|
|
Mar 26 03:06:55 PM PDT 24 |
Mar 26 03:12:16 PM PDT 24 |
187784482366 ps |
| T827 |
/workspace/coverage/default/43.spi_device_read_buffer_direct.1073967258 |
|
|
Mar 26 03:07:13 PM PDT 24 |
Mar 26 03:07:18 PM PDT 24 |
406996114 ps |
| T828 |
/workspace/coverage/default/41.spi_device_alert_test.2176120052 |
|
|
Mar 26 03:07:13 PM PDT 24 |
Mar 26 03:07:15 PM PDT 24 |
57643747 ps |
| T829 |
/workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.1173105148 |
|
|
Mar 26 03:06:53 PM PDT 24 |
Mar 26 03:11:33 PM PDT 24 |
30103053460 ps |
| T144 |
/workspace/coverage/default/17.spi_device_stress_all.1674873463 |
|
|
Mar 26 03:05:48 PM PDT 24 |
Mar 26 03:10:26 PM PDT 24 |
28529904196 ps |
| T830 |
/workspace/coverage/default/8.spi_device_stress_all.3049759156 |
|
|
Mar 26 03:05:18 PM PDT 24 |
Mar 26 03:05:19 PM PDT 24 |
75892211 ps |
| T831 |
/workspace/coverage/default/28.spi_device_flash_all.3934754595 |
|
|
Mar 26 03:06:30 PM PDT 24 |
Mar 26 03:09:20 PM PDT 24 |
58952428102 ps |
| T832 |
/workspace/coverage/default/14.spi_device_ram_cfg.1721079751 |
|
|
Mar 26 03:05:31 PM PDT 24 |
Mar 26 03:05:33 PM PDT 24 |
43736452 ps |
| T833 |
/workspace/coverage/default/38.spi_device_flash_and_tpm.1591807211 |
|
|
Mar 26 03:06:57 PM PDT 24 |
Mar 26 03:07:42 PM PDT 24 |
3905645137 ps |
| T834 |
/workspace/coverage/default/40.spi_device_tpm_sts_read.1625413012 |
|
|
Mar 26 03:07:06 PM PDT 24 |
Mar 26 03:07:07 PM PDT 24 |
37898806 ps |
| T835 |
/workspace/coverage/default/41.spi_device_read_buffer_direct.3014114111 |
|
|
Mar 26 03:07:14 PM PDT 24 |
Mar 26 03:07:19 PM PDT 24 |
881114916 ps |
| T836 |
/workspace/coverage/default/43.spi_device_alert_test.2860412381 |
|
|
Mar 26 03:07:14 PM PDT 24 |
Mar 26 03:07:15 PM PDT 24 |
15230604 ps |
| T837 |
/workspace/coverage/default/35.spi_device_alert_test.1969430175 |
|
|
Mar 26 03:06:52 PM PDT 24 |
Mar 26 03:06:54 PM PDT 24 |
44303415 ps |
| T838 |
/workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.1162536962 |
|
|
Mar 26 03:06:28 PM PDT 24 |
Mar 26 03:11:17 PM PDT 24 |
148333715039 ps |
| T839 |
/workspace/coverage/default/39.spi_device_flash_and_tpm.2132332936 |
|
|
Mar 26 03:07:06 PM PDT 24 |
Mar 26 03:08:53 PM PDT 24 |
257918170180 ps |
| T68 |
/workspace/coverage/default/4.spi_device_sec_cm.3746561718 |
|
|
Mar 26 03:04:54 PM PDT 24 |
Mar 26 03:04:56 PM PDT 24 |
271901127 ps |
| T840 |
/workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.1417487507 |
|
|
Mar 26 03:04:42 PM PDT 24 |
Mar 26 03:06:08 PM PDT 24 |
24175561627 ps |
| T841 |
/workspace/coverage/default/25.spi_device_pass_cmd_filtering.1063967493 |
|
|
Mar 26 03:06:17 PM PDT 24 |
Mar 26 03:06:20 PM PDT 24 |
129357802 ps |
| T842 |
/workspace/coverage/default/36.spi_device_flash_mode.990667085 |
|
|
Mar 26 03:06:54 PM PDT 24 |
Mar 26 03:07:29 PM PDT 24 |
47450359045 ps |
| T843 |
/workspace/coverage/default/12.spi_device_alert_test.1500921399 |
|
|
Mar 26 03:05:30 PM PDT 24 |
Mar 26 03:05:31 PM PDT 24 |
23899166 ps |
| T844 |
/workspace/coverage/default/41.spi_device_tpm_all.3994191257 |
|
|
Mar 26 03:07:06 PM PDT 24 |
Mar 26 03:07:23 PM PDT 24 |
27591176635 ps |
| T845 |
/workspace/coverage/default/48.spi_device_pass_cmd_filtering.679597942 |
|
|
Mar 26 03:07:32 PM PDT 24 |
Mar 26 03:07:36 PM PDT 24 |
379650568 ps |
| T846 |
/workspace/coverage/default/41.spi_device_flash_mode.2993640566 |
|
|
Mar 26 03:07:13 PM PDT 24 |
Mar 26 03:07:22 PM PDT 24 |
1691953480 ps |
| T847 |
/workspace/coverage/default/33.spi_device_tpm_all.2596473670 |
|
|
Mar 26 03:06:41 PM PDT 24 |
Mar 26 03:07:38 PM PDT 24 |
12272027283 ps |
| T848 |
/workspace/coverage/default/4.spi_device_cfg_cmd.1209366197 |
|
|
Mar 26 03:04:53 PM PDT 24 |
Mar 26 03:04:57 PM PDT 24 |
110280960 ps |
| T849 |
/workspace/coverage/default/39.spi_device_tpm_sts_read.713985657 |
|
|
Mar 26 03:07:09 PM PDT 24 |
Mar 26 03:07:09 PM PDT 24 |
31996034 ps |
| T850 |
/workspace/coverage/default/14.spi_device_pass_addr_payload_swap.52581046 |
|
|
Mar 26 03:05:28 PM PDT 24 |
Mar 26 03:05:34 PM PDT 24 |
4516573840 ps |
| T851 |
/workspace/coverage/default/11.spi_device_pass_cmd_filtering.3092181132 |
|
|
Mar 26 03:05:25 PM PDT 24 |
Mar 26 03:05:45 PM PDT 24 |
5976912132 ps |
| T852 |
/workspace/coverage/default/24.spi_device_mailbox.1293799605 |
|
|
Mar 26 03:06:17 PM PDT 24 |
Mar 26 03:06:32 PM PDT 24 |
12954533426 ps |
| T853 |
/workspace/coverage/default/7.spi_device_pass_cmd_filtering.3911983667 |
|
|
Mar 26 03:05:09 PM PDT 24 |
Mar 26 03:05:35 PM PDT 24 |
40848679211 ps |
| T854 |
/workspace/coverage/default/38.spi_device_tpm_sts_read.516610872 |
|
|
Mar 26 03:06:59 PM PDT 24 |
Mar 26 03:07:01 PM PDT 24 |
159195923 ps |
| T855 |
/workspace/coverage/default/32.spi_device_stress_all.1801671907 |
|
|
Mar 26 03:06:36 PM PDT 24 |
Mar 26 03:07:10 PM PDT 24 |
11202254258 ps |
| T856 |
/workspace/coverage/default/29.spi_device_tpm_all.2965262244 |
|
|
Mar 26 03:06:28 PM PDT 24 |
Mar 26 03:07:01 PM PDT 24 |
25398215184 ps |
| T857 |
/workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.2181475892 |
|
|
Mar 26 03:06:28 PM PDT 24 |
Mar 26 03:10:51 PM PDT 24 |
35162241598 ps |
| T858 |
/workspace/coverage/default/16.spi_device_read_buffer_direct.3010363462 |
|
|
Mar 26 03:05:42 PM PDT 24 |
Mar 26 03:05:47 PM PDT 24 |
1154878258 ps |
| T259 |
/workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.2869167881 |
|
|
Mar 26 03:07:40 PM PDT 24 |
Mar 26 03:16:12 PM PDT 24 |
64839476082 ps |
| T859 |
/workspace/coverage/default/7.spi_device_tpm_read_hw_reg.132980399 |
|
|
Mar 26 03:05:06 PM PDT 24 |
Mar 26 03:05:24 PM PDT 24 |
4690058889 ps |
| T860 |
/workspace/coverage/default/15.spi_device_ram_cfg.2717899221 |
|
|
Mar 26 03:05:39 PM PDT 24 |
Mar 26 03:05:40 PM PDT 24 |
36216015 ps |
| T861 |
/workspace/coverage/default/45.spi_device_read_buffer_direct.993677753 |
|
|
Mar 26 03:07:22 PM PDT 24 |
Mar 26 03:07:27 PM PDT 24 |
2905075509 ps |
| T862 |
/workspace/coverage/default/33.spi_device_flash_and_tpm.2907034108 |
|
|
Mar 26 03:06:46 PM PDT 24 |
Mar 26 03:11:25 PM PDT 24 |
40015635387 ps |
| T863 |
/workspace/coverage/default/42.spi_device_alert_test.129009303 |
|
|
Mar 26 03:07:16 PM PDT 24 |
Mar 26 03:07:17 PM PDT 24 |
14708263 ps |
| T864 |
/workspace/coverage/default/16.spi_device_ram_cfg.1267613906 |
|
|
Mar 26 03:05:39 PM PDT 24 |
Mar 26 03:05:40 PM PDT 24 |
44154007 ps |
| T865 |
/workspace/coverage/default/18.spi_device_upload.3481510234 |
|
|
Mar 26 03:05:44 PM PDT 24 |
Mar 26 03:05:51 PM PDT 24 |
10228192893 ps |
| T866 |
/workspace/coverage/default/10.spi_device_flash_and_tpm.1385896628 |
|
|
Mar 26 03:05:24 PM PDT 24 |
Mar 26 03:07:14 PM PDT 24 |
17775446219 ps |
| T867 |
/workspace/coverage/default/23.spi_device_stress_all.2025092402 |
|
|
Mar 26 03:06:04 PM PDT 24 |
Mar 26 03:09:36 PM PDT 24 |
20073425658 ps |
| T868 |
/workspace/coverage/default/42.spi_device_mailbox.4253089565 |
|
|
Mar 26 03:07:15 PM PDT 24 |
Mar 26 03:07:28 PM PDT 24 |
8799389385 ps |
| T869 |
/workspace/coverage/default/34.spi_device_tpm_sts_read.1487861488 |
|
|
Mar 26 03:06:45 PM PDT 24 |
Mar 26 03:06:47 PM PDT 24 |
155533711 ps |
| T870 |
/workspace/coverage/default/9.spi_device_tpm_read_hw_reg.3499581702 |
|
|
Mar 26 03:05:19 PM PDT 24 |
Mar 26 03:05:22 PM PDT 24 |
846068671 ps |
| T871 |
/workspace/coverage/default/26.spi_device_mailbox.2765493041 |
|
|
Mar 26 03:06:17 PM PDT 24 |
Mar 26 03:06:32 PM PDT 24 |
7262668598 ps |
| T872 |
/workspace/coverage/default/17.spi_device_tpm_rw.3923955891 |
|
|
Mar 26 03:05:47 PM PDT 24 |
Mar 26 03:05:49 PM PDT 24 |
48819234 ps |
| T873 |
/workspace/coverage/default/5.spi_device_flash_mode.2476654357 |
|
|
Mar 26 03:04:53 PM PDT 24 |
Mar 26 03:05:41 PM PDT 24 |
8674551444 ps |
| T874 |
/workspace/coverage/default/30.spi_device_tpm_sts_read.4093291745 |
|
|
Mar 26 03:06:29 PM PDT 24 |
Mar 26 03:06:30 PM PDT 24 |
122023486 ps |
| T875 |
/workspace/coverage/default/3.spi_device_pass_addr_payload_swap.845340928 |
|
|
Mar 26 03:04:46 PM PDT 24 |
Mar 26 03:04:58 PM PDT 24 |
30287421619 ps |
| T876 |
/workspace/coverage/default/37.spi_device_intercept.520675749 |
|
|
Mar 26 03:06:56 PM PDT 24 |
Mar 26 03:06:59 PM PDT 24 |
56565184 ps |
| T877 |
/workspace/coverage/default/30.spi_device_intercept.3258484621 |
|
|
Mar 26 03:06:33 PM PDT 24 |
Mar 26 03:06:38 PM PDT 24 |
171840678 ps |
| T878 |
/workspace/coverage/default/48.spi_device_intercept.2380584053 |
|
|
Mar 26 03:07:34 PM PDT 24 |
Mar 26 03:07:39 PM PDT 24 |
2050135963 ps |
| T247 |
/workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.3196884758 |
|
|
Mar 26 03:06:38 PM PDT 24 |
Mar 26 03:11:46 PM PDT 24 |
84414388186 ps |
| T879 |
/workspace/coverage/default/36.spi_device_alert_test.1255337291 |
|
|
Mar 26 03:06:55 PM PDT 24 |
Mar 26 03:06:56 PM PDT 24 |
31349453 ps |
| T880 |
/workspace/coverage/default/40.spi_device_mailbox.1573718391 |
|
|
Mar 26 03:07:12 PM PDT 24 |
Mar 26 03:07:18 PM PDT 24 |
1530547674 ps |
| T881 |
/workspace/coverage/default/22.spi_device_pass_cmd_filtering.11794007 |
|
|
Mar 26 03:06:08 PM PDT 24 |
Mar 26 03:06:24 PM PDT 24 |
5557270677 ps |
| T882 |
/workspace/coverage/default/11.spi_device_tpm_all.1067099284 |
|
|
Mar 26 03:05:25 PM PDT 24 |
Mar 26 03:05:40 PM PDT 24 |
13077735159 ps |
| T883 |
/workspace/coverage/default/0.spi_device_pass_cmd_filtering.1293002867 |
|
|
Mar 26 03:04:38 PM PDT 24 |
Mar 26 03:04:42 PM PDT 24 |
194464298 ps |
| T884 |
/workspace/coverage/default/3.spi_device_ram_cfg.3999608935 |
|
|
Mar 26 03:04:42 PM PDT 24 |
Mar 26 03:04:43 PM PDT 24 |
16046760 ps |
| T885 |
/workspace/coverage/default/7.spi_device_pass_addr_payload_swap.2067050010 |
|
|
Mar 26 03:05:06 PM PDT 24 |
Mar 26 03:05:14 PM PDT 24 |
4514326187 ps |
| T886 |
/workspace/coverage/default/9.spi_device_csb_read.252695272 |
|
|
Mar 26 03:05:16 PM PDT 24 |
Mar 26 03:05:17 PM PDT 24 |
25407249 ps |
| T887 |
/workspace/coverage/default/6.spi_device_intercept.2498995780 |
|
|
Mar 26 03:04:56 PM PDT 24 |
Mar 26 03:05:07 PM PDT 24 |
10726904945 ps |
| T888 |
/workspace/coverage/default/17.spi_device_flash_mode.1932369350 |
|
|
Mar 26 03:05:45 PM PDT 24 |
Mar 26 03:06:01 PM PDT 24 |
2555914653 ps |
| T889 |
/workspace/coverage/default/41.spi_device_flash_all.2372922723 |
|
|
Mar 26 03:07:15 PM PDT 24 |
Mar 26 03:07:35 PM PDT 24 |
17805850351 ps |
| T890 |
/workspace/coverage/default/6.spi_device_ram_cfg.1811479407 |
|
|
Mar 26 03:04:53 PM PDT 24 |
Mar 26 03:04:55 PM PDT 24 |
50159244 ps |
| T891 |
/workspace/coverage/default/39.spi_device_tpm_rw.3216581349 |
|
|
Mar 26 03:07:05 PM PDT 24 |
Mar 26 03:07:09 PM PDT 24 |
286585629 ps |
| T892 |
/workspace/coverage/default/15.spi_device_csb_read.1440075351 |
|
|
Mar 26 03:05:37 PM PDT 24 |
Mar 26 03:05:39 PM PDT 24 |
32964586 ps |
| T893 |
/workspace/coverage/default/6.spi_device_flash_all.1980488604 |
|
|
Mar 26 03:05:07 PM PDT 24 |
Mar 26 03:05:41 PM PDT 24 |
1885347348 ps |
| T894 |
/workspace/coverage/default/16.spi_device_pass_cmd_filtering.3228849252 |
|
|
Mar 26 03:05:39 PM PDT 24 |
Mar 26 03:05:43 PM PDT 24 |
624381308 ps |
| T895 |
/workspace/coverage/default/0.spi_device_flash_mode.760639082 |
|
|
Mar 26 03:04:31 PM PDT 24 |
Mar 26 03:05:00 PM PDT 24 |
7586543180 ps |
| T896 |
/workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.3606245235 |
|
|
Mar 26 03:04:51 PM PDT 24 |
Mar 26 03:07:12 PM PDT 24 |
85590195369 ps |
| T897 |
/workspace/coverage/default/14.spi_device_cfg_cmd.2009726095 |
|
|
Mar 26 03:05:29 PM PDT 24 |
Mar 26 03:05:40 PM PDT 24 |
2422154098 ps |
| T898 |
/workspace/coverage/default/11.spi_device_cfg_cmd.1750332114 |
|
|
Mar 26 03:05:21 PM PDT 24 |
Mar 26 03:05:23 PM PDT 24 |
51322889 ps |
| T899 |
/workspace/coverage/default/47.spi_device_read_buffer_direct.302559573 |
|
|
Mar 26 03:07:34 PM PDT 24 |
Mar 26 03:07:39 PM PDT 24 |
251250764 ps |
| T900 |
/workspace/coverage/default/13.spi_device_mailbox.1339286935 |
|
|
Mar 26 03:05:26 PM PDT 24 |
Mar 26 03:05:29 PM PDT 24 |
98926876 ps |
| T901 |
/workspace/coverage/default/24.spi_device_tpm_read_hw_reg.1495893914 |
|
|
Mar 26 03:06:08 PM PDT 24 |
Mar 26 03:06:18 PM PDT 24 |
2416543660 ps |
| T902 |
/workspace/coverage/default/15.spi_device_flash_and_tpm.1111551 |
|
|
Mar 26 03:05:37 PM PDT 24 |
Mar 26 03:06:58 PM PDT 24 |
6577601319 ps |
| T903 |
/workspace/coverage/default/6.spi_device_upload.1033867438 |
|
|
Mar 26 03:05:07 PM PDT 24 |
Mar 26 03:05:16 PM PDT 24 |
3786293857 ps |
| T904 |
/workspace/coverage/default/21.spi_device_tpm_rw.841883713 |
|
|
Mar 26 03:05:58 PM PDT 24 |
Mar 26 03:06:02 PM PDT 24 |
714838631 ps |
| T905 |
/workspace/coverage/default/11.spi_device_tpm_sts_read.3992881876 |
|
|
Mar 26 03:05:25 PM PDT 24 |
Mar 26 03:05:26 PM PDT 24 |
235125742 ps |
| T906 |
/workspace/coverage/default/10.spi_device_read_buffer_direct.2399327400 |
|
|
Mar 26 03:05:20 PM PDT 24 |
Mar 26 03:05:24 PM PDT 24 |
567457565 ps |
| T907 |
/workspace/coverage/default/42.spi_device_upload.1044429543 |
|
|
Mar 26 03:07:17 PM PDT 24 |
Mar 26 03:07:27 PM PDT 24 |
766870711 ps |
| T908 |
/workspace/coverage/default/29.spi_device_tpm_sts_read.223877428 |
|
|
Mar 26 03:06:30 PM PDT 24 |
Mar 26 03:06:31 PM PDT 24 |
207838120 ps |
| T909 |
/workspace/coverage/default/3.spi_device_flash_mode.1690240663 |
|
|
Mar 26 03:04:48 PM PDT 24 |
Mar 26 03:05:24 PM PDT 24 |
24832146739 ps |
| T910 |
/workspace/coverage/default/35.spi_device_stress_all.1550522608 |
|
|
Mar 26 03:06:47 PM PDT 24 |
Mar 26 03:16:33 PM PDT 24 |
99158506335 ps |
| T911 |
/workspace/coverage/default/19.spi_device_alert_test.1808282614 |
|
|
Mar 26 03:05:58 PM PDT 24 |
Mar 26 03:05:59 PM PDT 24 |
16761599 ps |
| T912 |
/workspace/coverage/default/4.spi_device_alert_test.3072668725 |
|
|
Mar 26 03:04:52 PM PDT 24 |
Mar 26 03:04:53 PM PDT 24 |
14267823 ps |
| T913 |
/workspace/coverage/default/11.spi_device_csb_read.1372071789 |
|
|
Mar 26 03:05:23 PM PDT 24 |
Mar 26 03:05:24 PM PDT 24 |
79222129 ps |
| T914 |
/workspace/coverage/default/31.spi_device_tpm_all.3992161329 |
|
|
Mar 26 03:06:36 PM PDT 24 |
Mar 26 03:06:42 PM PDT 24 |
2480394255 ps |
| T915 |
/workspace/coverage/default/10.spi_device_pass_addr_payload_swap.1720637618 |
|
|
Mar 26 03:05:18 PM PDT 24 |
Mar 26 03:05:25 PM PDT 24 |
1689714301 ps |
| T916 |
/workspace/coverage/default/16.spi_device_stress_all.3717976608 |
|
|
Mar 26 03:05:39 PM PDT 24 |
Mar 26 03:14:48 PM PDT 24 |
192566928868 ps |
| T917 |
/workspace/coverage/default/17.spi_device_ram_cfg.3141866121 |
|
|
Mar 26 03:05:47 PM PDT 24 |
Mar 26 03:05:47 PM PDT 24 |
29975130 ps |
| T918 |
/workspace/coverage/default/24.spi_device_alert_test.990041695 |
|
|
Mar 26 03:06:15 PM PDT 24 |
Mar 26 03:06:16 PM PDT 24 |
32654956 ps |
| T919 |
/workspace/coverage/default/49.spi_device_flash_mode.2041953460 |
|
|
Mar 26 03:07:41 PM PDT 24 |
Mar 26 03:08:03 PM PDT 24 |
24488755898 ps |
| T920 |
/workspace/coverage/default/0.spi_device_flash_and_tpm.4143694056 |
|
|
Mar 26 03:04:30 PM PDT 24 |
Mar 26 03:05:37 PM PDT 24 |
5117509584 ps |
| T921 |
/workspace/coverage/default/25.spi_device_tpm_rw.1023080822 |
|
|
Mar 26 03:06:18 PM PDT 24 |
Mar 26 03:06:19 PM PDT 24 |
54491854 ps |
| T922 |
/workspace/coverage/default/47.spi_device_intercept.1325053116 |
|
|
Mar 26 03:07:31 PM PDT 24 |
Mar 26 03:07:42 PM PDT 24 |
3028240284 ps |
| T923 |
/workspace/coverage/default/30.spi_device_pass_cmd_filtering.1374687013 |
|
|
Mar 26 03:06:30 PM PDT 24 |
Mar 26 03:06:37 PM PDT 24 |
1023381330 ps |
| T924 |
/workspace/coverage/default/22.spi_device_intercept.1026499563 |
|
|
Mar 26 03:06:05 PM PDT 24 |
Mar 26 03:06:09 PM PDT 24 |
128474711 ps |
| T925 |
/workspace/coverage/default/5.spi_device_ram_cfg.53476819 |
|
|
Mar 26 03:04:50 PM PDT 24 |
Mar 26 03:04:51 PM PDT 24 |
21649171 ps |
| T926 |
/workspace/coverage/default/29.spi_device_pass_cmd_filtering.1074372880 |
|
|
Mar 26 03:06:29 PM PDT 24 |
Mar 26 03:06:45 PM PDT 24 |
68096833823 ps |
| T927 |
/workspace/coverage/default/0.spi_device_ram_cfg.3422754573 |
|
|
Mar 26 03:04:32 PM PDT 24 |
Mar 26 03:04:32 PM PDT 24 |
28280634 ps |
| T928 |
/workspace/coverage/default/5.spi_device_tpm_rw.3115640994 |
|
|
Mar 26 03:04:54 PM PDT 24 |
Mar 26 03:04:56 PM PDT 24 |
199370490 ps |
| T929 |
/workspace/coverage/default/43.spi_device_upload.564697412 |
|
|
Mar 26 03:07:15 PM PDT 24 |
Mar 26 03:07:35 PM PDT 24 |
15377449835 ps |
| T930 |
/workspace/coverage/default/3.spi_device_read_buffer_direct.4100896398 |
|
|
Mar 26 03:04:48 PM PDT 24 |
Mar 26 03:04:53 PM PDT 24 |
626716234 ps |
| T931 |
/workspace/coverage/default/34.spi_device_upload.3199211042 |
|
|
Mar 26 03:06:55 PM PDT 24 |
Mar 26 03:07:02 PM PDT 24 |
1049293765 ps |
| T932 |
/workspace/coverage/default/15.spi_device_flash_mode.2929805270 |
|
|
Mar 26 03:05:37 PM PDT 24 |
Mar 26 03:06:24 PM PDT 24 |
8275450488 ps |
| T933 |
/workspace/coverage/default/37.spi_device_tpm_rw.157838717 |
|
|
Mar 26 03:06:55 PM PDT 24 |
Mar 26 03:06:56 PM PDT 24 |
213128387 ps |
| T934 |
/workspace/coverage/default/2.spi_device_pass_cmd_filtering.2193063837 |
|
|
Mar 26 03:04:45 PM PDT 24 |
Mar 26 03:04:55 PM PDT 24 |
5615523625 ps |
| T935 |
/workspace/coverage/default/31.spi_device_intercept.1683887171 |
|
|
Mar 26 03:06:38 PM PDT 24 |
Mar 26 03:06:45 PM PDT 24 |
2394920882 ps |
| T936 |
/workspace/coverage/default/13.spi_device_ram_cfg.3049263212 |
|
|
Mar 26 03:05:28 PM PDT 24 |
Mar 26 03:05:29 PM PDT 24 |
54932438 ps |
| T937 |
/workspace/coverage/default/38.spi_device_stress_all.2890377231 |
|
|
Mar 26 03:07:04 PM PDT 24 |
Mar 26 03:09:02 PM PDT 24 |
36820562853 ps |
| T938 |
/workspace/coverage/default/18.spi_device_flash_and_tpm.4266306337 |
|
|
Mar 26 03:05:45 PM PDT 24 |
Mar 26 03:07:04 PM PDT 24 |
8735083452 ps |
| T939 |
/workspace/coverage/default/9.spi_device_read_buffer_direct.799338463 |
|
|
Mar 26 03:05:22 PM PDT 24 |
Mar 26 03:05:27 PM PDT 24 |
4200667081 ps |
| T940 |
/workspace/coverage/default/6.spi_device_tpm_rw.2237429050 |
|
|
Mar 26 03:04:51 PM PDT 24 |
Mar 26 03:04:53 PM PDT 24 |
45415313 ps |
| T941 |
/workspace/coverage/default/27.spi_device_stress_all.1240036156 |
|
|
Mar 26 03:06:29 PM PDT 24 |
Mar 26 03:16:53 PM PDT 24 |
520907800229 ps |
| T942 |
/workspace/coverage/default/7.spi_device_alert_test.2073911342 |
|
|
Mar 26 03:05:05 PM PDT 24 |
Mar 26 03:05:06 PM PDT 24 |
41809386 ps |
| T943 |
/workspace/coverage/default/41.spi_device_tpm_read_hw_reg.4068688739 |
|
|
Mar 26 03:07:03 PM PDT 24 |
Mar 26 03:07:12 PM PDT 24 |
1567520377 ps |
| T944 |
/workspace/coverage/default/38.spi_device_mailbox.3543748129 |
|
|
Mar 26 03:06:56 PM PDT 24 |
Mar 26 03:07:25 PM PDT 24 |
51417415561 ps |
| T945 |
/workspace/coverage/default/7.spi_device_upload.505112533 |
|
|
Mar 26 03:05:08 PM PDT 24 |
Mar 26 03:05:27 PM PDT 24 |
9674903812 ps |
| T946 |
/workspace/coverage/default/44.spi_device_cfg_cmd.935407520 |
|
|
Mar 26 03:07:23 PM PDT 24 |
Mar 26 03:07:25 PM PDT 24 |
112494260 ps |
| T947 |
/workspace/coverage/default/11.spi_device_flash_all.394410428 |
|
|
Mar 26 03:05:16 PM PDT 24 |
Mar 26 03:06:11 PM PDT 24 |
49064457131 ps |
| T948 |
/workspace/coverage/default/3.spi_device_tpm_sts_read.1885593000 |
|
|
Mar 26 03:04:44 PM PDT 24 |
Mar 26 03:04:46 PM PDT 24 |
282718868 ps |
| T949 |
/workspace/coverage/default/34.spi_device_read_buffer_direct.1166761415 |
|
|
Mar 26 03:06:46 PM PDT 24 |
Mar 26 03:06:51 PM PDT 24 |
2777271300 ps |
| T950 |
/workspace/coverage/default/34.spi_device_flash_mode.3433926415 |
|
|
Mar 26 03:06:47 PM PDT 24 |
Mar 26 03:07:07 PM PDT 24 |
2985743130 ps |
| T951 |
/workspace/coverage/default/24.spi_device_intercept.4162379125 |
|
|
Mar 26 03:06:14 PM PDT 24 |
Mar 26 03:06:18 PM PDT 24 |
271295166 ps |
| T952 |
/workspace/coverage/default/3.spi_device_pass_cmd_filtering.2545133720 |
|
|
Mar 26 03:04:48 PM PDT 24 |
Mar 26 03:05:14 PM PDT 24 |
12666205813 ps |
| T953 |
/workspace/coverage/default/19.spi_device_mailbox.1436496810 |
|
|
Mar 26 03:06:00 PM PDT 24 |
Mar 26 03:06:11 PM PDT 24 |
7423456184 ps |
| T954 |
/workspace/coverage/default/39.spi_device_stress_all.3898898174 |
|
|
Mar 26 03:07:06 PM PDT 24 |
Mar 26 03:09:31 PM PDT 24 |
20864194400 ps |
| T955 |
/workspace/coverage/default/15.spi_device_pass_addr_payload_swap.1528447848 |
|
|
Mar 26 03:05:38 PM PDT 24 |
Mar 26 03:05:42 PM PDT 24 |
3763551735 ps |
| T956 |
/workspace/coverage/default/2.spi_device_ram_cfg.1414259977 |
|
|
Mar 26 03:04:43 PM PDT 24 |
Mar 26 03:04:44 PM PDT 24 |
125516700 ps |
| T240 |
/workspace/coverage/default/15.spi_device_stress_all.906934032 |
|
|
Mar 26 03:05:36 PM PDT 24 |
Mar 26 03:07:29 PM PDT 24 |
16814635099 ps |
| T957 |
/workspace/coverage/default/8.spi_device_alert_test.1889185614 |
|
|
Mar 26 03:05:18 PM PDT 24 |
Mar 26 03:05:18 PM PDT 24 |
20776610 ps |
| T958 |
/workspace/coverage/default/15.spi_device_upload.2486482733 |
|
|
Mar 26 03:05:44 PM PDT 24 |
Mar 26 03:05:51 PM PDT 24 |
426544693 ps |
| T959 |
/workspace/coverage/default/10.spi_device_mailbox.2481225456 |
|
|
Mar 26 03:05:20 PM PDT 24 |
Mar 26 03:05:33 PM PDT 24 |
3497967826 ps |
| T960 |
/workspace/coverage/default/4.spi_device_flash_and_tpm.1230351349 |
|
|
Mar 26 03:04:55 PM PDT 24 |
Mar 26 03:06:03 PM PDT 24 |
50139865877 ps |
| T961 |
/workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.28586251 |
|
|
Mar 26 03:07:15 PM PDT 24 |
Mar 26 03:09:44 PM PDT 24 |
11810894762 ps |
| T962 |
/workspace/coverage/default/33.spi_device_flash_all.1811858393 |
|
|
Mar 26 03:06:47 PM PDT 24 |
Mar 26 03:06:58 PM PDT 24 |
1298823111 ps |
| T963 |
/workspace/coverage/default/27.spi_device_tpm_rw.1709420386 |
|
|
Mar 26 03:06:28 PM PDT 24 |
Mar 26 03:06:30 PM PDT 24 |
99771322 ps |
| T964 |
/workspace/coverage/default/0.spi_device_upload.3054313750 |
|
|
Mar 26 03:04:30 PM PDT 24 |
Mar 26 03:04:38 PM PDT 24 |
1432212220 ps |
| T965 |
/workspace/coverage/default/5.spi_device_mailbox.321644417 |
|
|
Mar 26 03:04:56 PM PDT 24 |
Mar 26 03:05:08 PM PDT 24 |
742939832 ps |
| T966 |
/workspace/coverage/default/29.spi_device_mailbox.478018996 |
|
|
Mar 26 03:06:28 PM PDT 24 |
Mar 26 03:07:08 PM PDT 24 |
16036733895 ps |
| T967 |
/workspace/coverage/default/12.spi_device_intercept.3535597737 |
|
|
Mar 26 03:05:32 PM PDT 24 |
Mar 26 03:05:39 PM PDT 24 |
3961519971 ps |
| T968 |
/workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.3678830461 |
|
|
Mar 26 03:06:08 PM PDT 24 |
Mar 26 03:08:15 PM PDT 24 |
29255301169 ps |
| T969 |
/workspace/coverage/default/1.spi_device_tpm_read_hw_reg.2620940840 |
|
|
Mar 26 03:04:33 PM PDT 24 |
Mar 26 03:04:39 PM PDT 24 |
919700828 ps |
| T970 |
/workspace/coverage/default/35.spi_device_read_buffer_direct.3564085818 |
|
|
Mar 26 03:06:47 PM PDT 24 |
Mar 26 03:06:52 PM PDT 24 |
2953854497 ps |
| T971 |
/workspace/coverage/default/30.spi_device_read_buffer_direct.1933186930 |
|
|
Mar 26 03:06:39 PM PDT 24 |
Mar 26 03:06:47 PM PDT 24 |
5582003153 ps |
| T972 |
/workspace/coverage/default/14.spi_device_upload.1416879050 |
|
|
Mar 26 03:05:28 PM PDT 24 |
Mar 26 03:05:42 PM PDT 24 |
16739952662 ps |
| T973 |
/workspace/coverage/default/32.spi_device_intercept.157744663 |
|
|
Mar 26 03:06:38 PM PDT 24 |
Mar 26 03:06:43 PM PDT 24 |
1558955422 ps |
| T974 |
/workspace/coverage/default/33.spi_device_flash_mode.4185435549 |
|
|
Mar 26 03:06:46 PM PDT 24 |
Mar 26 03:07:09 PM PDT 24 |
12890673809 ps |
| T59 |
/workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3161082077 |
|
|
Mar 26 02:56:14 PM PDT 24 |
Mar 26 02:56:21 PM PDT 24 |
5282774005 ps |
| T60 |
/workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2754387372 |
|
|
Mar 26 02:54:49 PM PDT 24 |
Mar 26 02:54:53 PM PDT 24 |
139175232 ps |
| T975 |
/workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1734635395 |
|
|
Mar 26 02:55:04 PM PDT 24 |
Mar 26 02:55:06 PM PDT 24 |
87165747 ps |
| T61 |
/workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2021314697 |
|
|
Mar 26 02:56:11 PM PDT 24 |
Mar 26 02:56:17 PM PDT 24 |
427480602 ps |
| T107 |
/workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2140191447 |
|
|
Mar 26 02:54:44 PM PDT 24 |
Mar 26 02:54:46 PM PDT 24 |
20095347 ps |
| T85 |
/workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1019279650 |
|
|
Mar 26 02:54:49 PM PDT 24 |
Mar 26 02:54:51 PM PDT 24 |
107527185 ps |
| T86 |
/workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1563628466 |
|
|
Mar 26 02:54:56 PM PDT 24 |
Mar 26 02:54:58 PM PDT 24 |
69804278 ps |
| T108 |
/workspace/coverage/cover_reg_top/9.spi_device_csr_rw.4120063437 |
|
|
Mar 26 02:55:07 PM PDT 24 |
Mar 26 02:55:09 PM PDT 24 |
281015166 ps |
| T976 |
/workspace/coverage/cover_reg_top/24.spi_device_intr_test.568993782 |
|
|
Mar 26 02:54:49 PM PDT 24 |
Mar 26 02:54:50 PM PDT 24 |
20069016 ps |
| T87 |
/workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3412815697 |
|
|
Mar 26 02:54:56 PM PDT 24 |
Mar 26 02:54:58 PM PDT 24 |
68600981 ps |
| T977 |
/workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1718094132 |
|
|
Mar 26 02:54:49 PM PDT 24 |
Mar 26 02:54:51 PM PDT 24 |
65490179 ps |
| T978 |
/workspace/coverage/cover_reg_top/14.spi_device_intr_test.917978984 |
|
|
Mar 26 02:54:54 PM PDT 24 |
Mar 26 02:54:55 PM PDT 24 |
59903928 ps |
| T89 |
/workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1729834368 |
|
|
Mar 26 02:54:48 PM PDT 24 |
Mar 26 02:54:52 PM PDT 24 |
60437678 ps |
| T979 |
/workspace/coverage/cover_reg_top/7.spi_device_intr_test.3090904878 |
|
|
Mar 26 02:54:50 PM PDT 24 |
Mar 26 02:54:51 PM PDT 24 |
17950007 ps |
| T980 |
/workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.385541510 |
|
|
Mar 26 02:54:50 PM PDT 24 |
Mar 26 02:54:53 PM PDT 24 |
46052330 ps |
| T109 |
/workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1989864961 |
|
|
Mar 26 02:54:55 PM PDT 24 |
Mar 26 02:55:19 PM PDT 24 |
3489422179 ps |
| T103 |
/workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2235100380 |
|
|
Mar 26 02:54:53 PM PDT 24 |
Mar 26 02:54:57 PM PDT 24 |
166528009 ps |
| T95 |
/workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2514468760 |
|
|
Mar 26 02:55:06 PM PDT 24 |
Mar 26 02:55:11 PM PDT 24 |
166226106 ps |
| T110 |
/workspace/coverage/cover_reg_top/4.spi_device_csr_rw.4218841456 |
|
|
Mar 26 02:54:51 PM PDT 24 |
Mar 26 02:54:54 PM PDT 24 |
35536601 ps |
| T96 |
/workspace/coverage/cover_reg_top/8.spi_device_tl_errors.32873013 |
|
|
Mar 26 02:54:53 PM PDT 24 |
Mar 26 02:54:56 PM PDT 24 |
43612132 ps |
| T981 |
/workspace/coverage/cover_reg_top/39.spi_device_intr_test.718510324 |
|
|
Mar 26 02:56:20 PM PDT 24 |
Mar 26 02:56:22 PM PDT 24 |
37339921 ps |
| T128 |
/workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1467139522 |
|
|
Mar 26 02:54:50 PM PDT 24 |
Mar 26 02:54:52 PM PDT 24 |
76959951 ps |
| T88 |
/workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1743947676 |
|
|
Mar 26 02:54:48 PM PDT 24 |
Mar 26 02:55:05 PM PDT 24 |
1659382648 ps |
| T982 |
/workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.4148519768 |
|
|
Mar 26 02:55:04 PM PDT 24 |
Mar 26 02:55:07 PM PDT 24 |
111104724 ps |
| T101 |
/workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3979436881 |
|
|
Mar 26 02:54:56 PM PDT 24 |
Mar 26 02:55:00 PM PDT 24 |
304634192 ps |
| T165 |
/workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1265183545 |
|
|
Mar 26 02:54:49 PM PDT 24 |
Mar 26 02:55:05 PM PDT 24 |
880084985 ps |
| T106 |
/workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2479810097 |
|
|
Mar 26 02:54:55 PM PDT 24 |
Mar 26 02:55:18 PM PDT 24 |
3333643917 ps |
| T111 |
/workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3655905732 |
|
|
Mar 26 02:54:51 PM PDT 24 |
Mar 26 02:54:52 PM PDT 24 |
154138414 ps |
| T129 |
/workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.4185736745 |
|
|
Mar 26 02:56:22 PM PDT 24 |
Mar 26 02:56:24 PM PDT 24 |
91357500 ps |
| T130 |
/workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1783738990 |
|
|
Mar 26 02:55:06 PM PDT 24 |
Mar 26 02:55:28 PM PDT 24 |
1281657210 ps |
| T94 |
/workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2885836456 |
|
|
Mar 26 02:54:52 PM PDT 24 |
Mar 26 02:54:55 PM PDT 24 |
35866855 ps |
| T983 |
/workspace/coverage/cover_reg_top/26.spi_device_intr_test.4077230117 |
|
|
Mar 26 02:55:03 PM PDT 24 |
Mar 26 02:55:03 PM PDT 24 |
38277503 ps |
| T984 |
/workspace/coverage/cover_reg_top/17.spi_device_intr_test.1523235290 |
|
|
Mar 26 02:54:57 PM PDT 24 |
Mar 26 02:54:58 PM PDT 24 |
44233416 ps |
| T131 |
/workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1764365584 |
|
|
Mar 26 02:54:53 PM PDT 24 |
Mar 26 02:55:14 PM PDT 24 |
15363465122 ps |
| T74 |
/workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1439637978 |
|
|
Mar 26 02:54:56 PM PDT 24 |
Mar 26 02:54:57 PM PDT 24 |
91956013 ps |
| T104 |
/workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.4205987082 |
|
|
Mar 26 02:54:51 PM PDT 24 |
Mar 26 02:54:54 PM PDT 24 |
113304952 ps |
| T985 |
/workspace/coverage/cover_reg_top/2.spi_device_intr_test.805110583 |
|
|
Mar 26 02:54:51 PM PDT 24 |
Mar 26 02:54:52 PM PDT 24 |
36875693 ps |
| T986 |
/workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3253690259 |
|
|
Mar 26 02:54:53 PM PDT 24 |
Mar 26 02:54:55 PM PDT 24 |
33176989 ps |
| T987 |
/workspace/coverage/cover_reg_top/0.spi_device_mem_walk.225465796 |
|
|
Mar 26 02:54:39 PM PDT 24 |
Mar 26 02:54:41 PM PDT 24 |
12307491 ps |
| T988 |
/workspace/coverage/cover_reg_top/9.spi_device_intr_test.2523056377 |
|
|
Mar 26 02:54:48 PM PDT 24 |
Mar 26 02:54:48 PM PDT 24 |
19890906 ps |
| T112 |
/workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.790188563 |
|
|
Mar 26 02:54:44 PM PDT 24 |
Mar 26 02:54:47 PM PDT 24 |
61243934 ps |
| T989 |
/workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2411713906 |
|
|
Mar 26 02:54:48 PM PDT 24 |
Mar 26 02:54:53 PM PDT 24 |
153190524 ps |
| T990 |
/workspace/coverage/cover_reg_top/19.spi_device_intr_test.862051552 |
|
|
Mar 26 02:54:56 PM PDT 24 |
Mar 26 02:54:56 PM PDT 24 |
46779635 ps |
| T132 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3459552206 |
|
|
Mar 26 02:54:53 PM PDT 24 |
Mar 26 02:55:01 PM PDT 24 |
375717759 ps |
| T991 |
/workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2682914633 |
|
|
Mar 26 02:54:43 PM PDT 24 |
Mar 26 02:54:46 PM PDT 24 |
209657526 ps |
| T113 |
/workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.4029207878 |
|
|
Mar 26 02:54:51 PM PDT 24 |
Mar 26 02:55:15 PM PDT 24 |
1147102632 ps |
| T114 |
/workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1876506169 |
|
|
Mar 26 02:54:52 PM PDT 24 |
Mar 26 02:54:55 PM PDT 24 |
79491256 ps |
| T133 |
/workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1007767239 |
|
|
Mar 26 02:54:53 PM PDT 24 |
Mar 26 02:55:17 PM PDT 24 |
2707169341 ps |
| T134 |
/workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3286876825 |
|
|
Mar 26 02:54:56 PM PDT 24 |
Mar 26 02:55:01 PM PDT 24 |
227955863 ps |
| T992 |
/workspace/coverage/cover_reg_top/16.spi_device_intr_test.738943436 |
|
|
Mar 26 02:54:54 PM PDT 24 |
Mar 26 02:54:55 PM PDT 24 |
11396019 ps |
| T993 |
/workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.4120124394 |
|
|
Mar 26 02:54:53 PM PDT 24 |
Mar 26 02:54:56 PM PDT 24 |
178185967 ps |
| T994 |
/workspace/coverage/cover_reg_top/5.spi_device_csr_rw.300836657 |
|
|
Mar 26 02:54:47 PM PDT 24 |
Mar 26 02:54:48 PM PDT 24 |
68320825 ps |
| T99 |
/workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2605779195 |
|
|
Mar 26 02:54:50 PM PDT 24 |
Mar 26 02:54:53 PM PDT 24 |
42924044 ps |
| T995 |
/workspace/coverage/cover_reg_top/20.spi_device_intr_test.1020672993 |
|
|
Mar 26 02:56:23 PM PDT 24 |
Mar 26 02:56:24 PM PDT 24 |
12677395 ps |
| T115 |
/workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.452232820 |
|
|
Mar 26 02:54:49 PM PDT 24 |
Mar 26 02:55:01 PM PDT 24 |
745513541 ps |
| T996 |
/workspace/coverage/cover_reg_top/11.spi_device_intr_test.3549493777 |
|
|
Mar 26 02:54:49 PM PDT 24 |
Mar 26 02:54:50 PM PDT 24 |
32165945 ps |
| T997 |
/workspace/coverage/cover_reg_top/0.spi_device_intr_test.3238236360 |
|
|
Mar 26 02:54:54 PM PDT 24 |
Mar 26 02:54:55 PM PDT 24 |
59635167 ps |
| T116 |
/workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3242324577 |
|
|
Mar 26 02:54:50 PM PDT 24 |
Mar 26 02:54:51 PM PDT 24 |
20701541 ps |
| T998 |
/workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1446399400 |
|
|
Mar 26 02:54:53 PM PDT 24 |
Mar 26 02:54:54 PM PDT 24 |
11846020 ps |
| T999 |
/workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2737121342 |
|
|
Mar 26 02:54:49 PM PDT 24 |
Mar 26 02:54:56 PM PDT 24 |
158200641 ps |
| T1000 |
/workspace/coverage/cover_reg_top/47.spi_device_intr_test.3923137651 |
|
|
Mar 26 02:54:51 PM PDT 24 |
Mar 26 02:54:51 PM PDT 24 |
12898616 ps |
| T117 |
/workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3122688575 |
|
|
Mar 26 02:54:54 PM PDT 24 |
Mar 26 02:54:55 PM PDT 24 |
41338513 ps |
| T1001 |
/workspace/coverage/cover_reg_top/42.spi_device_intr_test.3434318123 |
|
|
Mar 26 02:56:28 PM PDT 24 |
Mar 26 02:56:29 PM PDT 24 |
47066379 ps |
| T1002 |
/workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2569409047 |
|
|
Mar 26 02:55:54 PM PDT 24 |
Mar 26 02:55:56 PM PDT 24 |
101450019 ps |
| T118 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_rw.4264958332 |
|
|
Mar 26 02:54:44 PM PDT 24 |
Mar 26 02:54:46 PM PDT 24 |
36558872 ps |
| T1003 |
/workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3610502198 |
|
|
Mar 26 02:55:01 PM PDT 24 |
Mar 26 02:55:03 PM PDT 24 |
82487810 ps |
| T1004 |
/workspace/coverage/cover_reg_top/10.spi_device_intr_test.385504183 |
|
|
Mar 26 02:54:47 PM PDT 24 |
Mar 26 02:54:48 PM PDT 24 |
16183297 ps |
| T1005 |
/workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.4060420376 |
|
|
Mar 26 02:54:49 PM PDT 24 |
Mar 26 02:54:53 PM PDT 24 |
152330638 ps |
| T97 |
/workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3857548807 |
|
|
Mar 26 02:55:03 PM PDT 24 |
Mar 26 02:55:05 PM PDT 24 |
67311191 ps |
| T1006 |
/workspace/coverage/cover_reg_top/3.spi_device_intr_test.3623418125 |
|
|
Mar 26 02:56:19 PM PDT 24 |
Mar 26 02:56:20 PM PDT 24 |
11532598 ps |
| T1007 |
/workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2021010843 |
|
|
Mar 26 02:54:53 PM PDT 24 |
Mar 26 02:54:56 PM PDT 24 |
132866064 ps |
| T1008 |
/workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2708772156 |
|
|
Mar 26 02:54:48 PM PDT 24 |
Mar 26 02:54:51 PM PDT 24 |
148589642 ps |
| T1009 |
/workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.893189555 |
|
|
Mar 26 02:54:50 PM PDT 24 |
Mar 26 02:55:04 PM PDT 24 |
220097030 ps |
| T1010 |
/workspace/coverage/cover_reg_top/1.spi_device_mem_walk.999269327 |
|
|
Mar 26 02:54:47 PM PDT 24 |
Mar 26 02:54:48 PM PDT 24 |
31035586 ps |
| T1011 |
/workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2735701438 |
|
|
Mar 26 02:56:28 PM PDT 24 |
Mar 26 02:56:37 PM PDT 24 |
169118444 ps |
| T119 |
/workspace/coverage/cover_reg_top/14.spi_device_csr_rw.969179561 |
|
|
Mar 26 02:54:55 PM PDT 24 |
Mar 26 02:54:57 PM PDT 24 |
40781178 ps |
| T1012 |
/workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3711517911 |
|
|
Mar 26 02:54:49 PM PDT 24 |
Mar 26 02:54:50 PM PDT 24 |
26290473 ps |
| T1013 |
/workspace/coverage/cover_reg_top/40.spi_device_intr_test.3524923022 |
|
|
Mar 26 02:54:54 PM PDT 24 |
Mar 26 02:54:55 PM PDT 24 |
16170298 ps |