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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.92 98.30 94.07 98.61 89.36 97.00 95.84 98.22


Total test records in report: 1097
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T1014 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.580130802 Mar 26 02:54:56 PM PDT 24 Mar 26 02:54:57 PM PDT 24 18528453 ps
T1015 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3151578207 Mar 26 02:54:51 PM PDT 24 Mar 26 02:54:52 PM PDT 24 75065445 ps
T1016 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2845999355 Mar 26 02:54:51 PM PDT 24 Mar 26 02:54:53 PM PDT 24 483696684 ps
T1017 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2067009263 Mar 26 02:54:50 PM PDT 24 Mar 26 02:54:51 PM PDT 24 72211165 ps
T98 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.101487663 Mar 26 02:54:43 PM PDT 24 Mar 26 02:54:49 PM PDT 24 364663501 ps
T1018 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1765263147 Mar 26 02:56:14 PM PDT 24 Mar 26 02:56:16 PM PDT 24 292766325 ps
T166 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1715984459 Mar 26 02:54:44 PM PDT 24 Mar 26 02:55:07 PM PDT 24 4292821629 ps
T1019 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1012613043 Mar 26 02:54:52 PM PDT 24 Mar 26 02:54:54 PM PDT 24 130086682 ps
T1020 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3421265175 Mar 26 02:54:54 PM PDT 24 Mar 26 02:54:55 PM PDT 24 20155920 ps
T1021 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1094063692 Mar 26 02:54:57 PM PDT 24 Mar 26 02:54:59 PM PDT 24 76077600 ps
T1022 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1923213171 Mar 26 02:54:48 PM PDT 24 Mar 26 02:54:52 PM PDT 24 351434106 ps
T1023 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.573570424 Mar 26 02:54:51 PM PDT 24 Mar 26 02:54:55 PM PDT 24 107424297 ps
T1024 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.630388219 Mar 26 02:54:52 PM PDT 24 Mar 26 02:54:56 PM PDT 24 648885268 ps
T1025 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.4165498675 Mar 26 02:54:50 PM PDT 24 Mar 26 02:54:52 PM PDT 24 24044599 ps
T1026 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3070033190 Mar 26 02:54:49 PM PDT 24 Mar 26 02:54:50 PM PDT 24 20613800 ps
T1027 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1396491205 Mar 26 02:54:49 PM PDT 24 Mar 26 02:54:50 PM PDT 24 43228417 ps
T1028 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2351697656 Mar 26 02:54:47 PM PDT 24 Mar 26 02:54:50 PM PDT 24 357135907 ps
T1029 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1447878999 Mar 26 02:54:50 PM PDT 24 Mar 26 02:54:52 PM PDT 24 202010589 ps
T1030 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2650024688 Mar 26 02:54:52 PM PDT 24 Mar 26 02:55:26 PM PDT 24 524946392 ps
T1031 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2324736411 Mar 26 02:54:49 PM PDT 24 Mar 26 02:54:51 PM PDT 24 38075388 ps
T1032 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.510956508 Mar 26 02:54:51 PM PDT 24 Mar 26 02:54:55 PM PDT 24 528498747 ps
T1033 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3895449091 Mar 26 02:55:02 PM PDT 24 Mar 26 02:55:03 PM PDT 24 15363776 ps
T1034 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.367112635 Mar 26 02:54:49 PM PDT 24 Mar 26 02:54:57 PM PDT 24 280541424 ps
T75 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.683519281 Mar 26 02:54:51 PM PDT 24 Mar 26 02:54:52 PM PDT 24 42788314 ps
T76 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2035112940 Mar 26 02:54:52 PM PDT 24 Mar 26 02:54:54 PM PDT 24 161688082 ps
T1035 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3301735282 Mar 26 02:54:47 PM PDT 24 Mar 26 02:54:48 PM PDT 24 49119290 ps
T100 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2325562203 Mar 26 02:54:49 PM PDT 24 Mar 26 02:54:53 PM PDT 24 232442313 ps
T1036 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.896165088 Mar 26 02:54:56 PM PDT 24 Mar 26 02:55:00 PM PDT 24 617442360 ps
T163 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1872806450 Mar 26 02:55:02 PM PDT 24 Mar 26 02:55:09 PM PDT 24 106490490 ps
T1037 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.563493068 Mar 26 02:55:01 PM PDT 24 Mar 26 02:55:01 PM PDT 24 81777679 ps
T1038 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3517064652 Mar 26 02:55:02 PM PDT 24 Mar 26 02:55:05 PM PDT 24 45459321 ps
T1039 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3309995416 Mar 26 02:54:51 PM PDT 24 Mar 26 02:54:52 PM PDT 24 23834672 ps
T1040 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1897110024 Mar 26 02:54:51 PM PDT 24 Mar 26 02:54:52 PM PDT 24 82961101 ps
T1041 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2866368518 Mar 26 02:54:52 PM PDT 24 Mar 26 02:54:53 PM PDT 24 39130798 ps
T105 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.701171192 Mar 26 02:54:56 PM PDT 24 Mar 26 02:54:59 PM PDT 24 75723287 ps
T1042 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3242420723 Mar 26 02:54:46 PM PDT 24 Mar 26 02:54:50 PM PDT 24 393893317 ps
T1043 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.881462545 Mar 26 02:54:56 PM PDT 24 Mar 26 02:54:57 PM PDT 24 31868741 ps
T1044 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3653596903 Mar 26 02:55:26 PM PDT 24 Mar 26 02:55:28 PM PDT 24 114987700 ps
T102 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.577946916 Mar 26 02:54:47 PM PDT 24 Mar 26 02:54:50 PM PDT 24 33217579 ps
T1045 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3102456321 Mar 26 02:54:56 PM PDT 24 Mar 26 02:55:00 PM PDT 24 186203135 ps
T1046 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.1090071652 Mar 26 02:54:57 PM PDT 24 Mar 26 02:54:58 PM PDT 24 22870081 ps
T1047 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.4266418697 Mar 26 02:54:47 PM PDT 24 Mar 26 02:54:48 PM PDT 24 48754521 ps
T1048 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2690150941 Mar 26 02:54:53 PM PDT 24 Mar 26 02:55:33 PM PDT 24 2774927612 ps
T1049 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.841922281 Mar 26 02:54:54 PM PDT 24 Mar 26 02:55:00 PM PDT 24 78115420 ps
T1050 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1131257201 Mar 26 02:54:48 PM PDT 24 Mar 26 02:54:49 PM PDT 24 16777859 ps
T1051 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1445617670 Mar 26 02:54:49 PM PDT 24 Mar 26 02:54:51 PM PDT 24 62190895 ps
T1052 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3178502179 Mar 26 02:54:50 PM PDT 24 Mar 26 02:54:55 PM PDT 24 582496491 ps
T1053 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.891983944 Mar 26 02:56:25 PM PDT 24 Mar 26 02:56:26 PM PDT 24 18731601 ps
T164 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.11487543 Mar 26 02:54:49 PM PDT 24 Mar 26 02:55:09 PM PDT 24 1219564336 ps
T1054 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2395491788 Mar 26 02:54:50 PM PDT 24 Mar 26 02:54:59 PM PDT 24 1740254081 ps
T1055 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.306353679 Mar 26 02:56:12 PM PDT 24 Mar 26 02:56:13 PM PDT 24 16904134 ps
T1056 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2815539379 Mar 26 02:54:49 PM PDT 24 Mar 26 02:55:06 PM PDT 24 3042341999 ps
T167 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1343153303 Mar 26 02:54:48 PM PDT 24 Mar 26 02:55:10 PM PDT 24 831527439 ps
T1057 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2096690390 Mar 26 02:54:54 PM PDT 24 Mar 26 02:54:57 PM PDT 24 560019635 ps
T1058 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1282568231 Mar 26 02:54:49 PM PDT 24 Mar 26 02:54:50 PM PDT 24 29055367 ps
T1059 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2050088620 Mar 26 02:54:51 PM PDT 24 Mar 26 02:54:52 PM PDT 24 54137875 ps
T1060 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2344190995 Mar 26 02:56:18 PM PDT 24 Mar 26 02:56:19 PM PDT 24 12555758 ps
T1061 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1560592817 Mar 26 02:54:51 PM PDT 24 Mar 26 02:54:52 PM PDT 24 20124160 ps
T1062 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2526574879 Mar 26 02:54:51 PM PDT 24 Mar 26 02:54:57 PM PDT 24 82277452 ps
T1063 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.4078283326 Mar 26 02:56:14 PM PDT 24 Mar 26 02:56:15 PM PDT 24 27795949 ps
T1064 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.438340447 Mar 26 02:54:49 PM PDT 24 Mar 26 02:54:53 PM PDT 24 47667710 ps
T1065 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2561649678 Mar 26 02:54:47 PM PDT 24 Mar 26 02:54:50 PM PDT 24 590847791 ps
T1066 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1202327164 Mar 26 02:54:49 PM PDT 24 Mar 26 02:55:03 PM PDT 24 932023555 ps
T1067 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3731842013 Mar 26 02:54:47 PM PDT 24 Mar 26 02:54:48 PM PDT 24 14489653 ps
T1068 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3775567113 Mar 26 02:54:51 PM PDT 24 Mar 26 02:54:52 PM PDT 24 31010901 ps
T1069 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1894172661 Mar 26 02:54:53 PM PDT 24 Mar 26 02:54:55 PM PDT 24 55965533 ps
T1070 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3844009865 Mar 26 02:54:49 PM PDT 24 Mar 26 02:54:50 PM PDT 24 57599801 ps
T1071 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.329724777 Mar 26 02:54:52 PM PDT 24 Mar 26 02:54:54 PM PDT 24 68869563 ps
T1072 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2006178005 Mar 26 02:54:53 PM PDT 24 Mar 26 02:54:57 PM PDT 24 47028321 ps
T1073 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3019032121 Mar 26 02:54:53 PM PDT 24 Mar 26 02:55:12 PM PDT 24 300982267 ps
T1074 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1513886631 Mar 26 02:54:43 PM PDT 24 Mar 26 02:54:45 PM PDT 24 60213796 ps
T77 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2581661423 Mar 26 02:54:53 PM PDT 24 Mar 26 02:54:55 PM PDT 24 151839002 ps
T1075 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.80640108 Mar 26 02:54:50 PM PDT 24 Mar 26 02:54:52 PM PDT 24 83706138 ps
T1076 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1197676325 Mar 26 02:55:17 PM PDT 24 Mar 26 02:55:21 PM PDT 24 229042816 ps
T1077 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1007546886 Mar 26 02:54:58 PM PDT 24 Mar 26 02:55:12 PM PDT 24 1130501012 ps
T1078 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3915571637 Mar 26 02:54:55 PM PDT 24 Mar 26 02:54:57 PM PDT 24 33963481 ps
T1079 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3275843109 Mar 26 02:54:51 PM PDT 24 Mar 26 02:54:52 PM PDT 24 36119383 ps
T1080 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1196947102 Mar 26 02:54:58 PM PDT 24 Mar 26 02:54:59 PM PDT 24 62600861 ps
T1081 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1418063449 Mar 26 02:56:25 PM PDT 24 Mar 26 02:56:26 PM PDT 24 15822209 ps
T1082 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.4278053079 Mar 26 02:56:18 PM PDT 24 Mar 26 02:56:19 PM PDT 24 12341803 ps
T1083 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2960896946 Mar 26 02:54:53 PM PDT 24 Mar 26 02:55:02 PM PDT 24 2210472408 ps
T161 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1905004537 Mar 26 02:55:02 PM PDT 24 Mar 26 02:55:07 PM PDT 24 289947657 ps
T1084 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1966409882 Mar 26 02:55:02 PM PDT 24 Mar 26 02:55:03 PM PDT 24 16885770 ps
T1085 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.626067561 Mar 26 02:54:43 PM PDT 24 Mar 26 02:54:46 PM PDT 24 137464188 ps
T1086 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2542629252 Mar 26 02:54:52 PM PDT 24 Mar 26 02:55:06 PM PDT 24 1096891509 ps
T1087 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.3813494612 Mar 26 02:56:25 PM PDT 24 Mar 26 02:56:25 PM PDT 24 12464460 ps
T1088 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.4069559986 Mar 26 02:56:14 PM PDT 24 Mar 26 02:56:17 PM PDT 24 171007043 ps
T1089 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3674043178 Mar 26 02:56:20 PM PDT 24 Mar 26 02:56:22 PM PDT 24 19603474 ps
T1090 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1078821290 Mar 26 02:56:20 PM PDT 24 Mar 26 02:56:23 PM PDT 24 176264182 ps
T1091 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.781201790 Mar 26 02:54:46 PM PDT 24 Mar 26 02:54:48 PM PDT 24 57548607 ps
T1092 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2497324575 Mar 26 02:54:50 PM PDT 24 Mar 26 02:55:03 PM PDT 24 177495304 ps
T1093 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.65104994 Mar 26 02:54:46 PM PDT 24 Mar 26 02:54:54 PM PDT 24 422868370 ps
T1094 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.250290685 Mar 26 02:54:54 PM PDT 24 Mar 26 02:54:57 PM PDT 24 144449306 ps
T162 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1801531703 Mar 26 02:54:55 PM PDT 24 Mar 26 02:54:59 PM PDT 24 437755166 ps
T1095 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.112984929 Mar 26 02:54:51 PM PDT 24 Mar 26 02:54:52 PM PDT 24 75906478 ps
T1096 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3716857441 Mar 26 02:54:48 PM PDT 24 Mar 26 02:55:03 PM PDT 24 3232106419 ps
T1097 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3472913621 Mar 26 02:55:03 PM PDT 24 Mar 26 02:55:07 PM PDT 24 209415020 ps

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.567399822
Short name T3
Test name
Test status
Simulation time 19853729960 ps
CPU time 173.54 seconds
Started Mar 26 03:06:55 PM PDT 24
Finished Mar 26 03:09:49 PM PDT 24
Peak memory 257096 kb
Host smart-4159a4eb-a2a0-4c6d-99ca-d194a16fd6f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567399822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idle
.567399822
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.3214986149
Short name T23
Test name
Test status
Simulation time 23618464451 ps
CPU time 218.02 seconds
Started Mar 26 03:05:03 PM PDT 24
Finished Mar 26 03:08:42 PM PDT 24
Peak memory 289196 kb
Host smart-0e8dd197-18b2-48fb-b1a2-c9ebb90ad75d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214986149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.3214986149
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1743947676
Short name T88
Test name
Test status
Simulation time 1659382648 ps
CPU time 16.35 seconds
Started Mar 26 02:54:48 PM PDT 24
Finished Mar 26 02:55:05 PM PDT 24
Peak memory 215384 kb
Host smart-d78bc76b-0c8b-4734-a48b-f05911758444
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743947676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.1743947676
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.3681034708
Short name T136
Test name
Test status
Simulation time 78925106592 ps
CPU time 235.13 seconds
Started Mar 26 03:07:23 PM PDT 24
Finished Mar 26 03:11:19 PM PDT 24
Peak memory 274156 kb
Host smart-62cd110b-6821-4164-817d-b132438bb778
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681034708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.3681034708
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.467130201
Short name T154
Test name
Test status
Simulation time 202689571947 ps
CPU time 642.46 seconds
Started Mar 26 03:07:38 PM PDT 24
Finished Mar 26 03:18:21 PM PDT 24
Peak memory 270076 kb
Host smart-00c540e5-88c3-4cd1-8f7e-363a3ff7885b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467130201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stres
s_all.467130201
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_ram_cfg.2160738517
Short name T791
Test name
Test status
Simulation time 17021273 ps
CPU time 0.79 seconds
Started Mar 26 03:04:30 PM PDT 24
Finished Mar 26 03:04:31 PM PDT 24
Peak memory 216408 kb
Host smart-1ccafe80-fa25-4be2-b247-a28a370718a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160738517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_ram_cfg.2160738517
Directory /workspace/1.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.1129860205
Short name T32
Test name
Test status
Simulation time 84454400989 ps
CPU time 305.93 seconds
Started Mar 26 03:07:23 PM PDT 24
Finished Mar 26 03:12:29 PM PDT 24
Peak memory 257748 kb
Host smart-69ade15b-7908-4716-ba38-0e04cf348e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129860205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.1129860205
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1729834368
Short name T89
Test name
Test status
Simulation time 60437678 ps
CPU time 4.08 seconds
Started Mar 26 02:54:48 PM PDT 24
Finished Mar 26 02:54:52 PM PDT 24
Peak memory 215548 kb
Host smart-fca10913-901c-4d75-b4cd-6a8cede42cd5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729834368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
1729834368
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.1394972448
Short name T31
Test name
Test status
Simulation time 267878213599 ps
CPU time 475.69 seconds
Started Mar 26 03:05:37 PM PDT 24
Finished Mar 26 03:13:33 PM PDT 24
Peak memory 273368 kb
Host smart-3caaefc6-784c-4d1f-87c5-59698c9f8e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394972448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.1394972448
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.2568600646
Short name T46
Test name
Test status
Simulation time 443595689130 ps
CPU time 853.02 seconds
Started Mar 26 03:05:19 PM PDT 24
Finished Mar 26 03:19:32 PM PDT 24
Peak memory 283800 kb
Host smart-b6a7a3bc-0b91-4024-b88e-024d289d5491
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568600646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.2568600646
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.2718792703
Short name T58
Test name
Test status
Simulation time 90627482 ps
CPU time 1.07 seconds
Started Mar 26 03:04:29 PM PDT 24
Finished Mar 26 03:04:31 PM PDT 24
Peak memory 235348 kb
Host smart-07d554ca-e4d8-4bda-b64e-a8f189629216
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718792703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.2718792703
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.3028659249
Short name T36
Test name
Test status
Simulation time 7959638372 ps
CPU time 46.73 seconds
Started Mar 26 03:06:56 PM PDT 24
Finished Mar 26 03:07:43 PM PDT 24
Peak memory 247828 kb
Host smart-2432e767-67e9-41ec-87c5-6605ba5f169d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028659249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.3028659249
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.1495214432
Short name T79
Test name
Test status
Simulation time 6728129688 ps
CPU time 139.38 seconds
Started Mar 26 03:07:23 PM PDT 24
Finished Mar 26 03:09:43 PM PDT 24
Peak memory 265196 kb
Host smart-964adfbb-532b-4d65-be93-89c6b232ae66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495214432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.1495214432
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1989864961
Short name T109
Test name
Test status
Simulation time 3489422179 ps
CPU time 23.96 seconds
Started Mar 26 02:54:55 PM PDT 24
Finished Mar 26 02:55:19 PM PDT 24
Peak memory 215740 kb
Host smart-e6d9994c-4805-4484-9d41-a80142754796
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989864961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.1989864961
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.3664118949
Short name T152
Test name
Test status
Simulation time 308053178529 ps
CPU time 357.1 seconds
Started Mar 26 03:06:47 PM PDT 24
Finished Mar 26 03:12:45 PM PDT 24
Peak memory 257788 kb
Host smart-776cc2ad-280b-4767-86c9-66fcea14c84b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664118949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.3664118949
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.1983024744
Short name T190
Test name
Test status
Simulation time 44470138210 ps
CPU time 98.81 seconds
Started Mar 26 03:05:40 PM PDT 24
Finished Mar 26 03:07:18 PM PDT 24
Peak memory 256828 kb
Host smart-3977e556-c788-4712-b7ee-36b9db777bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983024744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.1983024744
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.719130334
Short name T24
Test name
Test status
Simulation time 41940493020 ps
CPU time 218.36 seconds
Started Mar 26 03:06:37 PM PDT 24
Finished Mar 26 03:10:18 PM PDT 24
Peak memory 265824 kb
Host smart-e92e2547-bd72-47c9-9372-d9c8ee2d0f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719130334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.719130334
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.3453035936
Short name T179
Test name
Test status
Simulation time 71016149448 ps
CPU time 361.26 seconds
Started Mar 26 03:07:25 PM PDT 24
Finished Mar 26 03:13:27 PM PDT 24
Peak memory 271828 kb
Host smart-c1753ce6-8476-404d-9b00-bce9a62574b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453035936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.3453035936
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.3758953282
Short name T47
Test name
Test status
Simulation time 132889381349 ps
CPU time 1089.33 seconds
Started Mar 26 03:04:53 PM PDT 24
Finished Mar 26 03:23:04 PM PDT 24
Peak memory 290572 kb
Host smart-7f01a4f1-9eb2-4cf8-b713-f8eee5253495
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758953282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.3758953282
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.4048555722
Short name T185
Test name
Test status
Simulation time 80324387371 ps
CPU time 217.22 seconds
Started Mar 26 03:06:04 PM PDT 24
Finished Mar 26 03:09:41 PM PDT 24
Peak memory 264476 kb
Host smart-01a035c6-f1e3-45c5-b395-7e028f14585e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048555722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.4048555722
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.4147863197
Short name T283
Test name
Test status
Simulation time 39034311 ps
CPU time 0.77 seconds
Started Mar 26 03:05:17 PM PDT 24
Finished Mar 26 03:05:18 PM PDT 24
Peak memory 205848 kb
Host smart-0e49fd0d-169e-4386-8cc1-88272350feb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147863197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
4147863197
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.1324091593
Short name T45
Test name
Test status
Simulation time 506297889973 ps
CPU time 876.72 seconds
Started Mar 26 03:06:28 PM PDT 24
Finished Mar 26 03:21:05 PM PDT 24
Peak memory 267856 kb
Host smart-7a2e2866-0ac0-42b9-a3e5-fa1f2da44d69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324091593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.1324091593
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.2164641519
Short name T34
Test name
Test status
Simulation time 236907909002 ps
CPU time 385.49 seconds
Started Mar 26 03:07:24 PM PDT 24
Finished Mar 26 03:13:50 PM PDT 24
Peak memory 251840 kb
Host smart-ae59285e-e883-40b7-9c7d-d40b282f6beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164641519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.2164641519
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.2994265722
Short name T82
Test name
Test status
Simulation time 7092748948 ps
CPU time 85.26 seconds
Started Mar 26 03:06:51 PM PDT 24
Finished Mar 26 03:08:17 PM PDT 24
Peak memory 255416 kb
Host smart-0ea424ee-1400-4168-999a-8aed71d7fac3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994265722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.2994265722
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.2104373719
Short name T2
Test name
Test status
Simulation time 2949770205 ps
CPU time 10.47 seconds
Started Mar 26 03:06:08 PM PDT 24
Finished Mar 26 03:06:19 PM PDT 24
Peak memory 216860 kb
Host smart-a0911fc0-9081-4956-bdcd-04313328905e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104373719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.2104373719
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.684835625
Short name T395
Test name
Test status
Simulation time 11438634208 ps
CPU time 26.07 seconds
Started Mar 26 03:05:18 PM PDT 24
Finished Mar 26 03:05:44 PM PDT 24
Peak memory 247192 kb
Host smart-28a174dd-6a61-43bb-80a6-1a4b26cb64e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684835625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.684835625
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.2665779299
Short name T221
Test name
Test status
Simulation time 331221397396 ps
CPU time 596.45 seconds
Started Mar 26 03:05:36 PM PDT 24
Finished Mar 26 03:15:33 PM PDT 24
Peak memory 264420 kb
Host smart-dea1839f-d649-4bfd-8aa0-ff698608444e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665779299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.2665779299
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.2025092402
Short name T867
Test name
Test status
Simulation time 20073425658 ps
CPU time 211.28 seconds
Started Mar 26 03:06:04 PM PDT 24
Finished Mar 26 03:09:36 PM PDT 24
Peak memory 282444 kb
Host smart-3b66ae93-a3d4-4bc2-998e-56978e3375f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025092402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.2025092402
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.101487663
Short name T98
Test name
Test status
Simulation time 364663501 ps
CPU time 4.52 seconds
Started Mar 26 02:54:43 PM PDT 24
Finished Mar 26 02:54:49 PM PDT 24
Peak memory 215732 kb
Host smart-f39bb940-984c-4293-9d6d-e152d328d474
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101487663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.101487663
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1715984459
Short name T166
Test name
Test status
Simulation time 4292821629 ps
CPU time 22.59 seconds
Started Mar 26 02:54:44 PM PDT 24
Finished Mar 26 02:55:07 PM PDT 24
Peak memory 215588 kb
Host smart-fdc0db7e-ffdb-4c74-9a66-dc65a9a09b7c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715984459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.1715984459
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.1928693089
Short name T246
Test name
Test status
Simulation time 13407156046 ps
CPU time 133.91 seconds
Started Mar 26 03:05:47 PM PDT 24
Finished Mar 26 03:08:01 PM PDT 24
Peak memory 274152 kb
Host smart-2e9b4bf4-2ce9-448b-895f-8c5e082641a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928693089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.1928693089
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.1395736096
Short name T193
Test name
Test status
Simulation time 431846714287 ps
CPU time 771.83 seconds
Started Mar 26 03:05:44 PM PDT 24
Finished Mar 26 03:18:36 PM PDT 24
Peak memory 282392 kb
Host smart-bbdcda1e-adbd-4888-800a-ffa2308001b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395736096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.1395736096
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.3330305165
Short name T182
Test name
Test status
Simulation time 171735188804 ps
CPU time 194.15 seconds
Started Mar 26 03:06:14 PM PDT 24
Finished Mar 26 03:09:29 PM PDT 24
Peak memory 257856 kb
Host smart-809da8f0-d646-414d-8ba5-0f563f7bc22d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330305165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.3330305165
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.1837733705
Short name T137
Test name
Test status
Simulation time 53992079600 ps
CPU time 209.63 seconds
Started Mar 26 03:06:37 PM PDT 24
Finished Mar 26 03:10:07 PM PDT 24
Peak memory 268084 kb
Host smart-a2f76eac-1da2-498d-af35-d7a80bad05f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837733705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.1837733705
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.1173105148
Short name T829
Test name
Test status
Simulation time 30103053460 ps
CPU time 279.53 seconds
Started Mar 26 03:06:53 PM PDT 24
Finished Mar 26 03:11:33 PM PDT 24
Peak memory 257760 kb
Host smart-e11d3979-046f-4dfb-8664-227831275e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173105148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.1173105148
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.3492518906
Short name T199
Test name
Test status
Simulation time 246701431505 ps
CPU time 299.11 seconds
Started Mar 26 03:07:35 PM PDT 24
Finished Mar 26 03:12:35 PM PDT 24
Peak memory 257764 kb
Host smart-64784b2f-a1b3-44ca-bd28-6b3de48caf6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492518906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.3492518906
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1801531703
Short name T162
Test name
Test status
Simulation time 437755166 ps
CPU time 3.37 seconds
Started Mar 26 02:54:55 PM PDT 24
Finished Mar 26 02:54:59 PM PDT 24
Peak memory 215608 kb
Host smart-71df0d85-0316-44d1-a733-2bf272d4938f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801531703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
1801531703
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.11487543
Short name T164
Test name
Test status
Simulation time 1219564336 ps
CPU time 19.38 seconds
Started Mar 26 02:54:49 PM PDT 24
Finished Mar 26 02:55:09 PM PDT 24
Peak memory 216116 kb
Host smart-a55ddadd-c864-4acb-9866-44a36b5d49ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11487543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_
tl_intg_err.11487543
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2479810097
Short name T106
Test name
Test status
Simulation time 3333643917 ps
CPU time 22.89 seconds
Started Mar 26 02:54:55 PM PDT 24
Finished Mar 26 02:55:18 PM PDT 24
Peak memory 215472 kb
Host smart-7c50baf2-3c95-4b1f-977c-493cef191f95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479810097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.2479810097
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.18272055
Short name T239
Test name
Test status
Simulation time 41952525677 ps
CPU time 105.85 seconds
Started Mar 26 03:04:31 PM PDT 24
Finished Mar 26 03:06:17 PM PDT 24
Peak memory 255764 kb
Host smart-65bd4c6e-135d-4667-8480-dce468f120c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18272055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.18272055
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.1239644258
Short name T250
Test name
Test status
Simulation time 150519709617 ps
CPU time 342.49 seconds
Started Mar 26 03:04:42 PM PDT 24
Finished Mar 26 03:10:25 PM PDT 24
Peak memory 252388 kb
Host smart-d5f2c634-a99c-4373-9b39-8d571d1f385f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239644258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.1239644258
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.80890974
Short name T265
Test name
Test status
Simulation time 7299320912 ps
CPU time 59.75 seconds
Started Mar 26 03:06:16 PM PDT 24
Finished Mar 26 03:07:15 PM PDT 24
Peak memory 250620 kb
Host smart-6e51c155-9e50-4959-9883-74f0d88ebdf8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80890974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stress
_all.80890974
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.3334975562
Short name T30
Test name
Test status
Simulation time 10722783588 ps
CPU time 33.59 seconds
Started Mar 26 03:04:31 PM PDT 24
Finished Mar 26 03:05:05 PM PDT 24
Peak memory 238464 kb
Host smart-239e0a1b-b716-42bc-809a-a1e88746a1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334975562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.3334975562
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.683519281
Short name T75
Test name
Test status
Simulation time 42788314 ps
CPU time 0.92 seconds
Started Mar 26 02:54:51 PM PDT 24
Finished Mar 26 02:54:52 PM PDT 24
Peak memory 207028 kb
Host smart-27902e0e-6ee2-4055-81bc-057e5db416f9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683519281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_hw_reset.683519281
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.574691664
Short name T237
Test name
Test status
Simulation time 21707086352 ps
CPU time 147.51 seconds
Started Mar 26 03:04:31 PM PDT 24
Finished Mar 26 03:06:59 PM PDT 24
Peak memory 273236 kb
Host smart-4b5b8d93-5ab5-497d-8bf9-19b2d650b927
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574691664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress
_all.574691664
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3979436881
Short name T101
Test name
Test status
Simulation time 304634192 ps
CPU time 3.26 seconds
Started Mar 26 02:54:56 PM PDT 24
Finished Mar 26 02:55:00 PM PDT 24
Peak memory 217848 kb
Host smart-3ee32bdf-6c33-434f-8c81-60384ba0dbe8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979436881 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.3979436881
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.2470732526
Short name T285
Test name
Test status
Simulation time 23024032 ps
CPU time 0.79 seconds
Started Mar 26 03:04:42 PM PDT 24
Finished Mar 26 03:04:43 PM PDT 24
Peak memory 207000 kb
Host smart-f6956d19-7a8d-473d-98d1-8a9d7f5ab847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470732526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.2470732526
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3459552206
Short name T132
Test name
Test status
Simulation time 375717759 ps
CPU time 8.33 seconds
Started Mar 26 02:54:53 PM PDT 24
Finished Mar 26 02:55:01 PM PDT 24
Peak memory 207176 kb
Host smart-b07e2dda-6f04-43a2-8fca-c8ba0aebe7c3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459552206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.3459552206
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3716857441
Short name T1096
Test name
Test status
Simulation time 3232106419 ps
CPU time 14.33 seconds
Started Mar 26 02:54:48 PM PDT 24
Finished Mar 26 02:55:03 PM PDT 24
Peak memory 215520 kb
Host smart-a23d27da-3267-44cc-a1c6-5c24595993a1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716857441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.3716857441
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1094063692
Short name T1021
Test name
Test status
Simulation time 76077600 ps
CPU time 1.52 seconds
Started Mar 26 02:54:57 PM PDT 24
Finished Mar 26 02:54:59 PM PDT 24
Peak memory 215548 kb
Host smart-2a780556-c7c7-4482-b240-0dc5683056fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094063692 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.1094063692
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.4264958332
Short name T118
Test name
Test status
Simulation time 36558872 ps
CPU time 1.2 seconds
Started Mar 26 02:54:44 PM PDT 24
Finished Mar 26 02:54:46 PM PDT 24
Peak memory 207092 kb
Host smart-7e01e7d8-92d8-4ae3-a8bb-6f4eda99ae59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264958332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.4
264958332
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3238236360
Short name T997
Test name
Test status
Simulation time 59635167 ps
CPU time 0.71 seconds
Started Mar 26 02:54:54 PM PDT 24
Finished Mar 26 02:54:55 PM PDT 24
Peak memory 203576 kb
Host smart-c49be396-ffa5-43e8-8517-df81a8ae3b97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238236360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.3
238236360
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3253690259
Short name T986
Test name
Test status
Simulation time 33176989 ps
CPU time 1.28 seconds
Started Mar 26 02:54:53 PM PDT 24
Finished Mar 26 02:54:55 PM PDT 24
Peak memory 215452 kb
Host smart-cd92ab65-6460-4629-b9c6-6b43a37a62c3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253690259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.3253690259
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.225465796
Short name T987
Test name
Test status
Simulation time 12307491 ps
CPU time 0.66 seconds
Started Mar 26 02:54:39 PM PDT 24
Finished Mar 26 02:54:41 PM PDT 24
Peak memory 203460 kb
Host smart-982df3fe-4e31-4833-bf8c-ce9ba5f7eca8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225465796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem
_walk.225465796
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2411713906
Short name T989
Test name
Test status
Simulation time 153190524 ps
CPU time 4.15 seconds
Started Mar 26 02:54:48 PM PDT 24
Finished Mar 26 02:54:53 PM PDT 24
Peak memory 215452 kb
Host smart-6226d15c-7c47-4f2f-9008-cea75d4a7214
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411713906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.2411713906
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.452232820
Short name T115
Test name
Test status
Simulation time 745513541 ps
CPU time 11.94 seconds
Started Mar 26 02:54:49 PM PDT 24
Finished Mar 26 02:55:01 PM PDT 24
Peak memory 207048 kb
Host smart-6e2491fa-c499-43e0-a26a-3735915f2b2a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452232820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_bit_bash.452232820
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2035112940
Short name T76
Test name
Test status
Simulation time 161688082 ps
CPU time 1.19 seconds
Started Mar 26 02:54:52 PM PDT 24
Finished Mar 26 02:54:54 PM PDT 24
Peak memory 207240 kb
Host smart-ad3d222a-a140-4bcb-997f-435a9bb393e3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035112940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.2035112940
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1923213171
Short name T1022
Test name
Test status
Simulation time 351434106 ps
CPU time 3.67 seconds
Started Mar 26 02:54:48 PM PDT 24
Finished Mar 26 02:54:52 PM PDT 24
Peak memory 217752 kb
Host smart-0e2bea65-15a5-4dad-930b-e2bd16b600b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923213171 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.1923213171
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2561649678
Short name T1065
Test name
Test status
Simulation time 590847791 ps
CPU time 2.74 seconds
Started Mar 26 02:54:47 PM PDT 24
Finished Mar 26 02:54:50 PM PDT 24
Peak memory 215408 kb
Host smart-a20831bb-04d6-4f90-923f-5ca9a6d2429b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561649678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.2
561649678
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3731842013
Short name T1067
Test name
Test status
Simulation time 14489653 ps
CPU time 0.77 seconds
Started Mar 26 02:54:47 PM PDT 24
Finished Mar 26 02:54:48 PM PDT 24
Peak memory 203660 kb
Host smart-86011e96-46cb-4e1a-a7dd-83440e8a0ec5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731842013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.3
731842013
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2140191447
Short name T107
Test name
Test status
Simulation time 20095347 ps
CPU time 1.35 seconds
Started Mar 26 02:54:44 PM PDT 24
Finished Mar 26 02:54:46 PM PDT 24
Peak memory 215412 kb
Host smart-002dc085-517d-4910-947e-c2b2b6323426
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140191447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.2140191447
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.999269327
Short name T1010
Test name
Test status
Simulation time 31035586 ps
CPU time 0.67 seconds
Started Mar 26 02:54:47 PM PDT 24
Finished Mar 26 02:54:48 PM PDT 24
Peak memory 203420 kb
Host smart-1c0dae45-89c4-44dd-81a9-fca0727d98c2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999269327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem
_walk.999269327
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3151578207
Short name T1015
Test name
Test status
Simulation time 75065445 ps
CPU time 1.75 seconds
Started Mar 26 02:54:51 PM PDT 24
Finished Mar 26 02:54:52 PM PDT 24
Peak memory 207404 kb
Host smart-94caf3a2-c597-4cec-a468-309a4a9a12a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151578207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.3151578207
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.438340447
Short name T1064
Test name
Test status
Simulation time 47667710 ps
CPU time 3.48 seconds
Started Mar 26 02:54:49 PM PDT 24
Finished Mar 26 02:54:53 PM PDT 24
Peak memory 215556 kb
Host smart-fe439712-af55-42c6-921c-de4ae484ae93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438340447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.438340447
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2096690390
Short name T1057
Test name
Test status
Simulation time 560019635 ps
CPU time 2.71 seconds
Started Mar 26 02:54:54 PM PDT 24
Finished Mar 26 02:54:57 PM PDT 24
Peak memory 216572 kb
Host smart-bf4e4134-cc48-42bb-8adb-51f3a938209a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096690390 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.2096690390
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3242324577
Short name T116
Test name
Test status
Simulation time 20701541 ps
CPU time 1.33 seconds
Started Mar 26 02:54:50 PM PDT 24
Finished Mar 26 02:54:51 PM PDT 24
Peak memory 207180 kb
Host smart-47cb020e-d534-468e-8a77-f0e86dbda743
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242324577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
3242324577
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.385504183
Short name T1004
Test name
Test status
Simulation time 16183297 ps
CPU time 0.72 seconds
Started Mar 26 02:54:47 PM PDT 24
Finished Mar 26 02:54:48 PM PDT 24
Peak memory 203540 kb
Host smart-bd41d8a3-034a-4dcf-9b46-92ef285b6cf3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385504183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.385504183
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.4148519768
Short name T982
Test name
Test status
Simulation time 111104724 ps
CPU time 2.97 seconds
Started Mar 26 02:55:04 PM PDT 24
Finished Mar 26 02:55:07 PM PDT 24
Peak memory 215492 kb
Host smart-fd6bb7bc-a4bc-49a5-8664-4ecc75804e63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148519768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.4148519768
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1872806450
Short name T163
Test name
Test status
Simulation time 106490490 ps
CPU time 6.81 seconds
Started Mar 26 02:55:02 PM PDT 24
Finished Mar 26 02:55:09 PM PDT 24
Peak memory 215508 kb
Host smart-1730bbc6-29f9-48bc-8dfc-bab259830093
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872806450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.1872806450
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.4165498675
Short name T1025
Test name
Test status
Simulation time 24044599 ps
CPU time 1.56 seconds
Started Mar 26 02:54:50 PM PDT 24
Finished Mar 26 02:54:52 PM PDT 24
Peak memory 215512 kb
Host smart-66426573-f0e2-4305-b004-84b4b2af94fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165498675 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.4165498675
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.250290685
Short name T1094
Test name
Test status
Simulation time 144449306 ps
CPU time 2.72 seconds
Started Mar 26 02:54:54 PM PDT 24
Finished Mar 26 02:54:57 PM PDT 24
Peak memory 215404 kb
Host smart-6858e8cb-7fa5-474b-b72d-dd80428d0d99
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250290685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.250290685
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3549493777
Short name T996
Test name
Test status
Simulation time 32165945 ps
CPU time 0.72 seconds
Started Mar 26 02:54:49 PM PDT 24
Finished Mar 26 02:54:50 PM PDT 24
Peak memory 203480 kb
Host smart-a4ad44e0-779d-4ea8-843e-4a7d28754123
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549493777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
3549493777
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.4060420376
Short name T1005
Test name
Test status
Simulation time 152330638 ps
CPU time 3.9 seconds
Started Mar 26 02:54:49 PM PDT 24
Finished Mar 26 02:54:53 PM PDT 24
Peak memory 215448 kb
Host smart-0b6e8e33-9e43-4c51-b87c-338e3f3e8fd7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060420376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.4060420376
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2754387372
Short name T60
Test name
Test status
Simulation time 139175232 ps
CPU time 3.87 seconds
Started Mar 26 02:54:49 PM PDT 24
Finished Mar 26 02:54:53 PM PDT 24
Peak memory 216688 kb
Host smart-73ad91d0-07bc-4f0c-bdaf-d71ecd462ef3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754387372 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.2754387372
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2324736411
Short name T1031
Test name
Test status
Simulation time 38075388 ps
CPU time 1.39 seconds
Started Mar 26 02:54:49 PM PDT 24
Finished Mar 26 02:54:51 PM PDT 24
Peak memory 215468 kb
Host smart-f4b33cab-3607-4e25-baf8-3cc14c70098d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324736411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
2324736411
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3275843109
Short name T1079
Test name
Test status
Simulation time 36119383 ps
CPU time 0.71 seconds
Started Mar 26 02:54:51 PM PDT 24
Finished Mar 26 02:54:52 PM PDT 24
Peak memory 203592 kb
Host smart-2c874157-9b12-4e15-b9ee-08996a1e94d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275843109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
3275843109
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.385541510
Short name T980
Test name
Test status
Simulation time 46052330 ps
CPU time 3.08 seconds
Started Mar 26 02:54:50 PM PDT 24
Finished Mar 26 02:54:53 PM PDT 24
Peak memory 215748 kb
Host smart-e925f71a-3f95-450d-a654-1e04a9f848f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385541510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.s
pi_device_same_csr_outstanding.385541510
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2605779195
Short name T99
Test name
Test status
Simulation time 42924044 ps
CPU time 2.65 seconds
Started Mar 26 02:54:50 PM PDT 24
Finished Mar 26 02:54:53 PM PDT 24
Peak memory 216544 kb
Host smart-521b0e91-a74a-4613-b634-3e3964d7460d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605779195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
2605779195
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1197676325
Short name T1076
Test name
Test status
Simulation time 229042816 ps
CPU time 3.67 seconds
Started Mar 26 02:55:17 PM PDT 24
Finished Mar 26 02:55:21 PM PDT 24
Peak memory 217316 kb
Host smart-02b27772-a1ae-48f4-b8ab-faa253ff1105
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197676325 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.1197676325
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3915571637
Short name T1078
Test name
Test status
Simulation time 33963481 ps
CPU time 2.02 seconds
Started Mar 26 02:54:55 PM PDT 24
Finished Mar 26 02:54:57 PM PDT 24
Peak memory 215288 kb
Host smart-45fec1a9-a4c9-4551-b059-3785caaacfe0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915571637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
3915571637
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.4078283326
Short name T1063
Test name
Test status
Simulation time 27795949 ps
CPU time 0.72 seconds
Started Mar 26 02:56:14 PM PDT 24
Finished Mar 26 02:56:15 PM PDT 24
Peak memory 203360 kb
Host smart-f1be7f01-2f29-4121-baf8-cba2454170df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078283326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
4078283326
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2845999355
Short name T1016
Test name
Test status
Simulation time 483696684 ps
CPU time 1.94 seconds
Started Mar 26 02:54:51 PM PDT 24
Finished Mar 26 02:54:53 PM PDT 24
Peak memory 215428 kb
Host smart-c18e1ae9-7da8-4c37-913c-1b31f322c86a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845999355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.2845999355
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.577946916
Short name T102
Test name
Test status
Simulation time 33217579 ps
CPU time 2.17 seconds
Started Mar 26 02:54:47 PM PDT 24
Finished Mar 26 02:54:50 PM PDT 24
Peak memory 215532 kb
Host smart-d2a906a9-2ba4-44f8-b7e2-99f1f8a1a48d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577946916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.577946916
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3019032121
Short name T1073
Test name
Test status
Simulation time 300982267 ps
CPU time 18.81 seconds
Started Mar 26 02:54:53 PM PDT 24
Finished Mar 26 02:55:12 PM PDT 24
Peak memory 215528 kb
Host smart-e6ebc1b7-aa6b-4497-8829-dd4b124cbd80
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019032121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.3019032121
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.969179561
Short name T119
Test name
Test status
Simulation time 40781178 ps
CPU time 1.33 seconds
Started Mar 26 02:54:55 PM PDT 24
Finished Mar 26 02:54:57 PM PDT 24
Peak memory 207116 kb
Host smart-0cf26442-77f7-426d-a5cb-0176dbd09821
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969179561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.969179561
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.917978984
Short name T978
Test name
Test status
Simulation time 59903928 ps
CPU time 0.69 seconds
Started Mar 26 02:54:54 PM PDT 24
Finished Mar 26 02:54:55 PM PDT 24
Peak memory 203608 kb
Host smart-525f8a53-7786-4cc9-95f6-8f1d8461ac3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917978984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.917978984
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.630388219
Short name T1024
Test name
Test status
Simulation time 648885268 ps
CPU time 4.22 seconds
Started Mar 26 02:54:52 PM PDT 24
Finished Mar 26 02:54:56 PM PDT 24
Peak memory 215464 kb
Host smart-033ba527-36d5-448d-8da0-7eb163fe0134
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630388219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.s
pi_device_same_csr_outstanding.630388219
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2885836456
Short name T94
Test name
Test status
Simulation time 35866855 ps
CPU time 2.4 seconds
Started Mar 26 02:54:52 PM PDT 24
Finished Mar 26 02:54:55 PM PDT 24
Peak memory 215592 kb
Host smart-5d12afd3-9dfc-4df3-bd35-e985c037d8e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885836456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
2885836456
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1007546886
Short name T1077
Test name
Test status
Simulation time 1130501012 ps
CPU time 14.53 seconds
Started Mar 26 02:54:58 PM PDT 24
Finished Mar 26 02:55:12 PM PDT 24
Peak memory 215612 kb
Host smart-b048d33a-13b7-48c2-a957-1da9b51af1ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007546886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.1007546886
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3610502198
Short name T1003
Test name
Test status
Simulation time 82487810 ps
CPU time 1.7 seconds
Started Mar 26 02:55:01 PM PDT 24
Finished Mar 26 02:55:03 PM PDT 24
Peak memory 215620 kb
Host smart-a0667b1f-4275-4745-a81a-f8fcd02e557e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610502198 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.3610502198
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1894172661
Short name T1069
Test name
Test status
Simulation time 55965533 ps
CPU time 1.79 seconds
Started Mar 26 02:54:53 PM PDT 24
Finished Mar 26 02:54:55 PM PDT 24
Peak memory 215432 kb
Host smart-b46029b0-cb57-430e-95ea-3e4856455405
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894172661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
1894172661
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.881462545
Short name T1043
Test name
Test status
Simulation time 31868741 ps
CPU time 0.67 seconds
Started Mar 26 02:54:56 PM PDT 24
Finished Mar 26 02:54:57 PM PDT 24
Peak memory 203600 kb
Host smart-089a2016-166a-437c-88bd-b1eaf012af75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881462545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.881462545
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3286876825
Short name T134
Test name
Test status
Simulation time 227955863 ps
CPU time 4.5 seconds
Started Mar 26 02:54:56 PM PDT 24
Finished Mar 26 02:55:01 PM PDT 24
Peak memory 215412 kb
Host smart-13f437d9-d343-4dc1-b01d-d2fe594bb7eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286876825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.3286876825
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2325562203
Short name T100
Test name
Test status
Simulation time 232442313 ps
CPU time 4.04 seconds
Started Mar 26 02:54:49 PM PDT 24
Finished Mar 26 02:54:53 PM PDT 24
Peak memory 215556 kb
Host smart-d47f00ea-bf8b-490f-926e-782d1b291839
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325562203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
2325562203
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.367112635
Short name T1034
Test name
Test status
Simulation time 280541424 ps
CPU time 7.61 seconds
Started Mar 26 02:54:49 PM PDT 24
Finished Mar 26 02:54:57 PM PDT 24
Peak memory 215288 kb
Host smart-ffa4d938-2141-46d8-9bca-1ba64a6289c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367112635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device
_tl_intg_err.367112635
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2006178005
Short name T1072
Test name
Test status
Simulation time 47028321 ps
CPU time 3.23 seconds
Started Mar 26 02:54:53 PM PDT 24
Finished Mar 26 02:54:57 PM PDT 24
Peak memory 216748 kb
Host smart-fef11e25-9ff1-412a-bd3d-14f63e439918
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006178005 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.2006178005
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.80640108
Short name T1075
Test name
Test status
Simulation time 83706138 ps
CPU time 2.58 seconds
Started Mar 26 02:54:50 PM PDT 24
Finished Mar 26 02:54:52 PM PDT 24
Peak memory 215420 kb
Host smart-d1f4ccad-0806-4bae-bb02-8a74926dd63a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80640108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.80640108
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.738943436
Short name T992
Test name
Test status
Simulation time 11396019 ps
CPU time 0.68 seconds
Started Mar 26 02:54:54 PM PDT 24
Finished Mar 26 02:54:55 PM PDT 24
Peak memory 203552 kb
Host smart-bf5ca2cd-69c7-4845-b8b6-a63aa7ae0ca6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738943436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.738943436
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2569409047
Short name T1002
Test name
Test status
Simulation time 101450019 ps
CPU time 1.86 seconds
Started Mar 26 02:55:54 PM PDT 24
Finished Mar 26 02:55:56 PM PDT 24
Peak memory 214468 kb
Host smart-162f142f-1ba8-462e-80e5-e96ee2b15c35
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569409047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.2569409047
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1563628466
Short name T86
Test name
Test status
Simulation time 69804278 ps
CPU time 1.84 seconds
Started Mar 26 02:54:56 PM PDT 24
Finished Mar 26 02:54:58 PM PDT 24
Peak memory 216620 kb
Host smart-743c01d2-2a31-4b4c-942c-3a6fcf1be2fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563628466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
1563628466
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.893189555
Short name T1009
Test name
Test status
Simulation time 220097030 ps
CPU time 13.74 seconds
Started Mar 26 02:54:50 PM PDT 24
Finished Mar 26 02:55:04 PM PDT 24
Peak memory 215644 kb
Host smart-7a6dedaa-2a5a-402f-a49f-eb9a3c0bce4f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893189555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device
_tl_intg_err.893189555
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1019279650
Short name T85
Test name
Test status
Simulation time 107527185 ps
CPU time 1.85 seconds
Started Mar 26 02:54:49 PM PDT 24
Finished Mar 26 02:54:51 PM PDT 24
Peak memory 216544 kb
Host smart-c6710312-0375-42ed-b53e-30d7e6badac0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019279650 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.1019279650
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3655905732
Short name T111
Test name
Test status
Simulation time 154138414 ps
CPU time 1.28 seconds
Started Mar 26 02:54:51 PM PDT 24
Finished Mar 26 02:54:52 PM PDT 24
Peak memory 207028 kb
Host smart-ad43b5ba-ee66-4ca2-b79d-271764d80691
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655905732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
3655905732
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1523235290
Short name T984
Test name
Test status
Simulation time 44233416 ps
CPU time 0.71 seconds
Started Mar 26 02:54:57 PM PDT 24
Finished Mar 26 02:54:58 PM PDT 24
Peak memory 203616 kb
Host smart-3323279e-417f-4488-8897-f2d602250acb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523235290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
1523235290
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2735701438
Short name T1011
Test name
Test status
Simulation time 169118444 ps
CPU time 4.33 seconds
Started Mar 26 02:56:28 PM PDT 24
Finished Mar 26 02:56:37 PM PDT 24
Peak memory 215256 kb
Host smart-134e4377-3de8-4a68-b44f-bf07d315e2d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735701438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.2735701438
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3857548807
Short name T97
Test name
Test status
Simulation time 67311191 ps
CPU time 1.96 seconds
Started Mar 26 02:55:03 PM PDT 24
Finished Mar 26 02:55:05 PM PDT 24
Peak memory 215592 kb
Host smart-00f72eaa-4f7b-4174-8d90-d916c0ff260a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857548807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
3857548807
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2815539379
Short name T1056
Test name
Test status
Simulation time 3042341999 ps
CPU time 16.79 seconds
Started Mar 26 02:54:49 PM PDT 24
Finished Mar 26 02:55:06 PM PDT 24
Peak memory 215576 kb
Host smart-17ce9f93-5969-4f02-89e9-39b168140b9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815539379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.2815539379
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2497324575
Short name T1092
Test name
Test status
Simulation time 177495304 ps
CPU time 2.74 seconds
Started Mar 26 02:54:50 PM PDT 24
Finished Mar 26 02:55:03 PM PDT 24
Peak memory 218108 kb
Host smart-3ef6c194-25f6-4435-9a95-fe15e44e53e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497324575 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.2497324575
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1765263147
Short name T1018
Test name
Test status
Simulation time 292766325 ps
CPU time 1.24 seconds
Started Mar 26 02:56:14 PM PDT 24
Finished Mar 26 02:56:16 PM PDT 24
Peak memory 206892 kb
Host smart-0e3170a2-8395-4a0c-851e-c8da47516ac2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765263147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
1765263147
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1196947102
Short name T1080
Test name
Test status
Simulation time 62600861 ps
CPU time 0.67 seconds
Started Mar 26 02:54:58 PM PDT 24
Finished Mar 26 02:54:59 PM PDT 24
Peak memory 203532 kb
Host smart-fc6b8784-fa07-4724-be59-c65b548dcfa2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196947102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
1196947102
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1467139522
Short name T128
Test name
Test status
Simulation time 76959951 ps
CPU time 1.9 seconds
Started Mar 26 02:54:50 PM PDT 24
Finished Mar 26 02:54:52 PM PDT 24
Peak memory 207200 kb
Host smart-a3091b5e-e085-4e85-af9e-bcd7cf93c8a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467139522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.1467139522
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3412815697
Short name T87
Test name
Test status
Simulation time 68600981 ps
CPU time 1.56 seconds
Started Mar 26 02:54:56 PM PDT 24
Finished Mar 26 02:54:58 PM PDT 24
Peak memory 215536 kb
Host smart-a02813e7-04d6-4538-b840-13333ad304a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412815697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
3412815697
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2737121342
Short name T999
Test name
Test status
Simulation time 158200641 ps
CPU time 7.01 seconds
Started Mar 26 02:54:49 PM PDT 24
Finished Mar 26 02:54:56 PM PDT 24
Peak memory 215344 kb
Host smart-afe21210-2282-40f1-98d5-754a874fb476
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737121342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.2737121342
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.4120124394
Short name T993
Test name
Test status
Simulation time 178185967 ps
CPU time 2.95 seconds
Started Mar 26 02:54:53 PM PDT 24
Finished Mar 26 02:54:56 PM PDT 24
Peak memory 216812 kb
Host smart-b2b79834-d66b-4690-b52e-932dbe659467
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120124394 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.4120124394
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1734635395
Short name T975
Test name
Test status
Simulation time 87165747 ps
CPU time 1.49 seconds
Started Mar 26 02:55:04 PM PDT 24
Finished Mar 26 02:55:06 PM PDT 24
Peak memory 207168 kb
Host smart-26391314-50fa-460c-8c32-e1a00422a27f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734635395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
1734635395
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.862051552
Short name T990
Test name
Test status
Simulation time 46779635 ps
CPU time 0.69 seconds
Started Mar 26 02:54:56 PM PDT 24
Finished Mar 26 02:54:56 PM PDT 24
Peak memory 203516 kb
Host smart-38eadaef-94f2-402a-9017-d78a02596aea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862051552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.862051552
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.4069559986
Short name T1088
Test name
Test status
Simulation time 171007043 ps
CPU time 2.79 seconds
Started Mar 26 02:56:14 PM PDT 24
Finished Mar 26 02:56:17 PM PDT 24
Peak memory 215200 kb
Host smart-19ec835a-aab7-4201-9104-fd7732316fdf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069559986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.4069559986
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2021010843
Short name T1007
Test name
Test status
Simulation time 132866064 ps
CPU time 2.69 seconds
Started Mar 26 02:54:53 PM PDT 24
Finished Mar 26 02:54:56 PM PDT 24
Peak memory 215664 kb
Host smart-72732dfd-11e5-4999-9471-6bede0c5ebcd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021010843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
2021010843
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1764365584
Short name T131
Test name
Test status
Simulation time 15363465122 ps
CPU time 21.48 seconds
Started Mar 26 02:54:53 PM PDT 24
Finished Mar 26 02:55:14 PM PDT 24
Peak memory 215716 kb
Host smart-f226e6c4-0289-49e5-a11c-ed63bf078c90
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764365584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.1764365584
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.4029207878
Short name T113
Test name
Test status
Simulation time 1147102632 ps
CPU time 23.91 seconds
Started Mar 26 02:54:51 PM PDT 24
Finished Mar 26 02:55:15 PM PDT 24
Peak memory 207080 kb
Host smart-b620c328-ee3a-4d78-9a91-410eb040efc3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029207878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.4029207878
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2650024688
Short name T1030
Test name
Test status
Simulation time 524946392 ps
CPU time 33.99 seconds
Started Mar 26 02:54:52 PM PDT 24
Finished Mar 26 02:55:26 PM PDT 24
Peak memory 207248 kb
Host smart-0eda7a97-8df1-4037-becb-418fd83c2022
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650024688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.2650024688
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2581661423
Short name T77
Test name
Test status
Simulation time 151839002 ps
CPU time 1.42 seconds
Started Mar 26 02:54:53 PM PDT 24
Finished Mar 26 02:54:55 PM PDT 24
Peak memory 215392 kb
Host smart-5ccf6be2-c219-4c23-8ac8-82e567718534
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581661423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.2581661423
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.4185736745
Short name T129
Test name
Test status
Simulation time 91357500 ps
CPU time 2.3 seconds
Started Mar 26 02:56:22 PM PDT 24
Finished Mar 26 02:56:24 PM PDT 24
Peak memory 217508 kb
Host smart-e928febb-b333-4438-be63-4ef6055d107a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185736745 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.4185736745
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.112984929
Short name T1095
Test name
Test status
Simulation time 75906478 ps
CPU time 1.37 seconds
Started Mar 26 02:54:51 PM PDT 24
Finished Mar 26 02:54:52 PM PDT 24
Peak memory 215416 kb
Host smart-47ed2b56-d6b9-426f-9ff0-7e6a1bd32313
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112984929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.112984929
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.805110583
Short name T985
Test name
Test status
Simulation time 36875693 ps
CPU time 0.71 seconds
Started Mar 26 02:54:51 PM PDT 24
Finished Mar 26 02:54:52 PM PDT 24
Peak memory 203616 kb
Host smart-426f8806-e3be-434c-ac96-e3ef6b307c70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805110583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.805110583
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3653596903
Short name T1044
Test name
Test status
Simulation time 114987700 ps
CPU time 2.24 seconds
Started Mar 26 02:55:26 PM PDT 24
Finished Mar 26 02:55:28 PM PDT 24
Peak memory 215284 kb
Host smart-49cac05c-6653-48fb-858d-2d6af1f87be5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653596903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.3653596903
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.4278053079
Short name T1082
Test name
Test status
Simulation time 12341803 ps
CPU time 0.64 seconds
Started Mar 26 02:56:18 PM PDT 24
Finished Mar 26 02:56:19 PM PDT 24
Peak memory 203196 kb
Host smart-4b89e798-27b3-40de-982e-45664c184afd
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278053079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.4278053079
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2682914633
Short name T991
Test name
Test status
Simulation time 209657526 ps
CPU time 2.98 seconds
Started Mar 26 02:54:43 PM PDT 24
Finished Mar 26 02:54:46 PM PDT 24
Peak memory 215324 kb
Host smart-367b7045-4955-4830-a3c0-ffaae0096ee2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682914633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.2682914633
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2514468760
Short name T95
Test name
Test status
Simulation time 166226106 ps
CPU time 4.6 seconds
Started Mar 26 02:55:06 PM PDT 24
Finished Mar 26 02:55:11 PM PDT 24
Peak memory 215728 kb
Host smart-a0b1eb3e-6086-43f3-91c6-1bf5d56826da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514468760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.2
514468760
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.65104994
Short name T1093
Test name
Test status
Simulation time 422868370 ps
CPU time 7.02 seconds
Started Mar 26 02:54:46 PM PDT 24
Finished Mar 26 02:54:54 PM PDT 24
Peak memory 215736 kb
Host smart-523f2c4f-1812-4c5b-b5f2-1d56636af28f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65104994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_t
l_intg_err.65104994
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1020672993
Short name T995
Test name
Test status
Simulation time 12677395 ps
CPU time 0.68 seconds
Started Mar 26 02:56:23 PM PDT 24
Finished Mar 26 02:56:24 PM PDT 24
Peak memory 203368 kb
Host smart-5d56b954-c4c0-46bd-89eb-b8728c5c559a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020672993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
1020672993
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3844009865
Short name T1070
Test name
Test status
Simulation time 57599801 ps
CPU time 0.74 seconds
Started Mar 26 02:54:49 PM PDT 24
Finished Mar 26 02:54:50 PM PDT 24
Peak memory 203552 kb
Host smart-193f15c7-df6b-461c-85e3-ceb70fda790f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844009865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
3844009865
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1282568231
Short name T1058
Test name
Test status
Simulation time 29055367 ps
CPU time 0.74 seconds
Started Mar 26 02:54:49 PM PDT 24
Finished Mar 26 02:54:50 PM PDT 24
Peak memory 203536 kb
Host smart-e798ba55-a712-4bd5-ae25-5eb41723e925
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282568231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
1282568231
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.3813494612
Short name T1087
Test name
Test status
Simulation time 12464460 ps
CPU time 0.7 seconds
Started Mar 26 02:56:25 PM PDT 24
Finished Mar 26 02:56:25 PM PDT 24
Peak memory 203336 kb
Host smart-8d8d8ca2-7a8f-4ab9-8f15-14a3d715db8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813494612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
3813494612
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.568993782
Short name T976
Test name
Test status
Simulation time 20069016 ps
CPU time 0.78 seconds
Started Mar 26 02:54:49 PM PDT 24
Finished Mar 26 02:54:50 PM PDT 24
Peak memory 203652 kb
Host smart-8c60a79b-e427-4ca3-b8c3-25b4402104ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568993782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.568993782
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3895449091
Short name T1033
Test name
Test status
Simulation time 15363776 ps
CPU time 0.76 seconds
Started Mar 26 02:55:02 PM PDT 24
Finished Mar 26 02:55:03 PM PDT 24
Peak memory 203788 kb
Host smart-887353d1-9614-4c51-a35d-8fcb3a50f02c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895449091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
3895449091
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.4077230117
Short name T983
Test name
Test status
Simulation time 38277503 ps
CPU time 0.7 seconds
Started Mar 26 02:55:03 PM PDT 24
Finished Mar 26 02:55:03 PM PDT 24
Peak memory 203560 kb
Host smart-4e82d7ad-b844-4eb1-bc56-ebaf187f0bc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077230117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
4077230117
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3301735282
Short name T1035
Test name
Test status
Simulation time 49119290 ps
CPU time 0.71 seconds
Started Mar 26 02:54:47 PM PDT 24
Finished Mar 26 02:54:48 PM PDT 24
Peak memory 203648 kb
Host smart-0a0b4272-52ce-4346-8a7e-558868987e8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301735282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
3301735282
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1966409882
Short name T1084
Test name
Test status
Simulation time 16885770 ps
CPU time 0.79 seconds
Started Mar 26 02:55:02 PM PDT 24
Finished Mar 26 02:55:03 PM PDT 24
Peak memory 203648 kb
Host smart-13041cc4-c324-41e3-96d2-ccabb53d5607
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966409882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
1966409882
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2067009263
Short name T1017
Test name
Test status
Simulation time 72211165 ps
CPU time 0.7 seconds
Started Mar 26 02:54:50 PM PDT 24
Finished Mar 26 02:54:51 PM PDT 24
Peak memory 203600 kb
Host smart-9f479964-0a84-4c4e-bca8-592a05ee1d14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067009263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
2067009263
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2960896946
Short name T1083
Test name
Test status
Simulation time 2210472408 ps
CPU time 8.76 seconds
Started Mar 26 02:54:53 PM PDT 24
Finished Mar 26 02:55:02 PM PDT 24
Peak memory 215528 kb
Host smart-f30a75f0-0292-4cbe-ae08-ad063890b22e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960896946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.2960896946
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1202327164
Short name T1066
Test name
Test status
Simulation time 932023555 ps
CPU time 13.65 seconds
Started Mar 26 02:54:49 PM PDT 24
Finished Mar 26 02:55:03 PM PDT 24
Peak memory 207000 kb
Host smart-787cf8a9-199a-48f7-aa6f-da2dab1219b0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202327164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.1202327164
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1439637978
Short name T74
Test name
Test status
Simulation time 91956013 ps
CPU time 0.97 seconds
Started Mar 26 02:54:56 PM PDT 24
Finished Mar 26 02:54:57 PM PDT 24
Peak memory 206844 kb
Host smart-834a8b91-b6b7-4ef5-902c-524143bdbdf5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439637978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.1439637978
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2351697656
Short name T1028
Test name
Test status
Simulation time 357135907 ps
CPU time 2.5 seconds
Started Mar 26 02:54:47 PM PDT 24
Finished Mar 26 02:54:50 PM PDT 24
Peak memory 215508 kb
Host smart-2434ee03-a871-45d5-b9e3-c090459c4c80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351697656 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.2351697656
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1876506169
Short name T114
Test name
Test status
Simulation time 79491256 ps
CPU time 2.66 seconds
Started Mar 26 02:54:52 PM PDT 24
Finished Mar 26 02:54:55 PM PDT 24
Peak memory 207152 kb
Host smart-2da7de35-726e-4a40-8dd9-5fbda99a498a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876506169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.1
876506169
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3623418125
Short name T1006
Test name
Test status
Simulation time 11532598 ps
CPU time 0.68 seconds
Started Mar 26 02:56:19 PM PDT 24
Finished Mar 26 02:56:20 PM PDT 24
Peak memory 203344 kb
Host smart-63502596-5fc3-490e-afbf-bdec170756c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623418125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.3
623418125
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.329724777
Short name T1071
Test name
Test status
Simulation time 68869563 ps
CPU time 1.17 seconds
Started Mar 26 02:54:52 PM PDT 24
Finished Mar 26 02:54:54 PM PDT 24
Peak memory 215408 kb
Host smart-12ac8ef1-3878-4f38-8a56-e0c35d6d32cf
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329724777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_
device_mem_partial_access.329724777
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1446399400
Short name T998
Test name
Test status
Simulation time 11846020 ps
CPU time 0.68 seconds
Started Mar 26 02:54:53 PM PDT 24
Finished Mar 26 02:54:54 PM PDT 24
Peak memory 203464 kb
Host smart-2297f3ca-1f44-4331-a45d-12a0171761d2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446399400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.1446399400
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1447878999
Short name T1029
Test name
Test status
Simulation time 202010589 ps
CPU time 1.83 seconds
Started Mar 26 02:54:50 PM PDT 24
Finished Mar 26 02:54:52 PM PDT 24
Peak memory 215480 kb
Host smart-d614f019-3531-4fe0-937c-61d80dc99592
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447878999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.1447878999
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.841922281
Short name T1049
Test name
Test status
Simulation time 78115420 ps
CPU time 5.04 seconds
Started Mar 26 02:54:54 PM PDT 24
Finished Mar 26 02:55:00 PM PDT 24
Peak memory 215720 kb
Host smart-34cda65e-caf8-4e4d-a892-a9628ffbb0b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841922281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.841922281
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1265183545
Short name T165
Test name
Test status
Simulation time 880084985 ps
CPU time 15.56 seconds
Started Mar 26 02:54:49 PM PDT 24
Finished Mar 26 02:55:05 PM PDT 24
Peak memory 215500 kb
Host smart-b72b4061-cde3-4ab1-9b78-975b6778aef8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265183545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.1265183545
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.580130802
Short name T1014
Test name
Test status
Simulation time 18528453 ps
CPU time 0.7 seconds
Started Mar 26 02:54:56 PM PDT 24
Finished Mar 26 02:54:57 PM PDT 24
Peak memory 203556 kb
Host smart-625e229d-ed2e-4762-a817-ccfe2a148140
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580130802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.580130802
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1897110024
Short name T1040
Test name
Test status
Simulation time 82961101 ps
CPU time 0.67 seconds
Started Mar 26 02:54:51 PM PDT 24
Finished Mar 26 02:54:52 PM PDT 24
Peak memory 203560 kb
Host smart-b0873e9d-0508-47fe-bbc8-5ba1c6934050
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897110024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
1897110024
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.1090071652
Short name T1046
Test name
Test status
Simulation time 22870081 ps
CPU time 0.7 seconds
Started Mar 26 02:54:57 PM PDT 24
Finished Mar 26 02:54:58 PM PDT 24
Peak memory 203532 kb
Host smart-b265f3cb-e5ae-453f-a040-d22381edb66a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090071652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
1090071652
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3309995416
Short name T1039
Test name
Test status
Simulation time 23834672 ps
CPU time 0.74 seconds
Started Mar 26 02:54:51 PM PDT 24
Finished Mar 26 02:54:52 PM PDT 24
Peak memory 203572 kb
Host smart-154996f3-825a-474d-9707-8251e388683d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309995416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
3309995416
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.781201790
Short name T1091
Test name
Test status
Simulation time 57548607 ps
CPU time 0.73 seconds
Started Mar 26 02:54:46 PM PDT 24
Finished Mar 26 02:54:48 PM PDT 24
Peak memory 203700 kb
Host smart-96a8155a-3e2c-4b0f-844c-28d73995fa3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781201790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.781201790
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.563493068
Short name T1037
Test name
Test status
Simulation time 81777679 ps
CPU time 0.69 seconds
Started Mar 26 02:55:01 PM PDT 24
Finished Mar 26 02:55:01 PM PDT 24
Peak memory 203588 kb
Host smart-9cf378ad-5925-42f0-bc07-5a0b1f90c736
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563493068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.563493068
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1418063449
Short name T1081
Test name
Test status
Simulation time 15822209 ps
CPU time 0.69 seconds
Started Mar 26 02:56:25 PM PDT 24
Finished Mar 26 02:56:26 PM PDT 24
Peak memory 203372 kb
Host smart-53af5f92-8e3a-4741-968d-cd1eb56c8fbf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418063449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
1418063449
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.891983944
Short name T1053
Test name
Test status
Simulation time 18731601 ps
CPU time 0.74 seconds
Started Mar 26 02:56:25 PM PDT 24
Finished Mar 26 02:56:26 PM PDT 24
Peak memory 203408 kb
Host smart-c718b0e7-f02c-4dc3-b61b-ddf5ac12af43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891983944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.891983944
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.306353679
Short name T1055
Test name
Test status
Simulation time 16904134 ps
CPU time 0.72 seconds
Started Mar 26 02:56:12 PM PDT 24
Finished Mar 26 02:56:13 PM PDT 24
Peak memory 203432 kb
Host smart-167e0de7-e157-4876-bc83-b4aea9d9e8dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306353679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.306353679
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.718510324
Short name T981
Test name
Test status
Simulation time 37339921 ps
CPU time 0.69 seconds
Started Mar 26 02:56:20 PM PDT 24
Finished Mar 26 02:56:22 PM PDT 24
Peak memory 203432 kb
Host smart-69b8485f-e143-4376-ae14-229cff4a54a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718510324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.718510324
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2395491788
Short name T1054
Test name
Test status
Simulation time 1740254081 ps
CPU time 8.99 seconds
Started Mar 26 02:54:50 PM PDT 24
Finished Mar 26 02:54:59 PM PDT 24
Peak memory 207100 kb
Host smart-dd28fe0e-1ed6-4bf1-831f-8aafde2ba06f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395491788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.2395491788
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2690150941
Short name T1048
Test name
Test status
Simulation time 2774927612 ps
CPU time 40.21 seconds
Started Mar 26 02:54:53 PM PDT 24
Finished Mar 26 02:55:33 PM PDT 24
Peak memory 207272 kb
Host smart-4966af24-d46d-486a-8d67-b5af638988fd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690150941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.2690150941
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1513886631
Short name T1074
Test name
Test status
Simulation time 60213796 ps
CPU time 1.19 seconds
Started Mar 26 02:54:43 PM PDT 24
Finished Mar 26 02:54:45 PM PDT 24
Peak memory 207084 kb
Host smart-bd988561-5296-41af-955f-70a2a24a8a16
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513886631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.1513886631
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3472913621
Short name T1097
Test name
Test status
Simulation time 209415020 ps
CPU time 3.83 seconds
Started Mar 26 02:55:03 PM PDT 24
Finished Mar 26 02:55:07 PM PDT 24
Peak memory 216972 kb
Host smart-3282fcd1-7f4c-4c65-9887-6825f1f13b64
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472913621 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.3472913621
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.4218841456
Short name T110
Test name
Test status
Simulation time 35536601 ps
CPU time 2.43 seconds
Started Mar 26 02:54:51 PM PDT 24
Finished Mar 26 02:54:54 PM PDT 24
Peak memory 207080 kb
Host smart-40101874-ff21-4932-9f2e-81165d5f0892
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218841456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.4
218841456
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2050088620
Short name T1059
Test name
Test status
Simulation time 54137875 ps
CPU time 0.72 seconds
Started Mar 26 02:54:51 PM PDT 24
Finished Mar 26 02:54:52 PM PDT 24
Peak memory 203560 kb
Host smart-60e6b338-9301-4d81-9b7b-297f7ea9d0b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050088620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.2
050088620
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.790188563
Short name T112
Test name
Test status
Simulation time 61243934 ps
CPU time 2.33 seconds
Started Mar 26 02:54:44 PM PDT 24
Finished Mar 26 02:54:47 PM PDT 24
Peak memory 215404 kb
Host smart-5c11afe1-76af-4e03-a95b-951bda8f65de
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790188563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_
device_mem_partial_access.790188563
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3711517911
Short name T1012
Test name
Test status
Simulation time 26290473 ps
CPU time 0.66 seconds
Started Mar 26 02:54:49 PM PDT 24
Finished Mar 26 02:54:50 PM PDT 24
Peak memory 203448 kb
Host smart-a06789e2-ade2-45f2-bbe7-97be85482f51
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711517911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.3711517911
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.896165088
Short name T1036
Test name
Test status
Simulation time 617442360 ps
CPU time 4.11 seconds
Started Mar 26 02:54:56 PM PDT 24
Finished Mar 26 02:55:00 PM PDT 24
Peak memory 215384 kb
Host smart-d678b866-6a91-41da-aeb6-44d23d4f53b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896165088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sp
i_device_same_csr_outstanding.896165088
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1078821290
Short name T1090
Test name
Test status
Simulation time 176264182 ps
CPU time 3.2 seconds
Started Mar 26 02:56:20 PM PDT 24
Finished Mar 26 02:56:23 PM PDT 24
Peak memory 215460 kb
Host smart-ff97a381-475a-412e-8cdf-db2ea15c0f2b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078821290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.1
078821290
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2021314697
Short name T61
Test name
Test status
Simulation time 427480602 ps
CPU time 6.29 seconds
Started Mar 26 02:56:11 PM PDT 24
Finished Mar 26 02:56:17 PM PDT 24
Peak memory 215336 kb
Host smart-ecd27b37-b250-47bc-b9be-7e2b254e9623
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021314697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.2021314697
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3524923022
Short name T1013
Test name
Test status
Simulation time 16170298 ps
CPU time 0.7 seconds
Started Mar 26 02:54:54 PM PDT 24
Finished Mar 26 02:54:55 PM PDT 24
Peak memory 203596 kb
Host smart-6b8f52c5-1077-4973-a555-c165cc2882a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524923022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
3524923022
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2344190995
Short name T1060
Test name
Test status
Simulation time 12555758 ps
CPU time 0.68 seconds
Started Mar 26 02:56:18 PM PDT 24
Finished Mar 26 02:56:19 PM PDT 24
Peak memory 203356 kb
Host smart-c728cabe-e190-4c56-a1ea-0854eadc2a83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344190995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
2344190995
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3434318123
Short name T1001
Test name
Test status
Simulation time 47066379 ps
CPU time 0.7 seconds
Started Mar 26 02:56:28 PM PDT 24
Finished Mar 26 02:56:29 PM PDT 24
Peak memory 203388 kb
Host smart-d26c3cc6-2bea-4841-9927-b915a7e1df4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434318123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
3434318123
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3775567113
Short name T1068
Test name
Test status
Simulation time 31010901 ps
CPU time 0.69 seconds
Started Mar 26 02:54:51 PM PDT 24
Finished Mar 26 02:54:52 PM PDT 24
Peak memory 203588 kb
Host smart-37c038f3-dfc0-4f80-bd66-6402935288b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775567113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
3775567113
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2866368518
Short name T1041
Test name
Test status
Simulation time 39130798 ps
CPU time 0.71 seconds
Started Mar 26 02:54:52 PM PDT 24
Finished Mar 26 02:54:53 PM PDT 24
Peak memory 203568 kb
Host smart-b7675031-b038-4b44-84b7-6142b6e71b4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866368518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
2866368518
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3674043178
Short name T1089
Test name
Test status
Simulation time 19603474 ps
CPU time 0.71 seconds
Started Mar 26 02:56:20 PM PDT 24
Finished Mar 26 02:56:22 PM PDT 24
Peak memory 203448 kb
Host smart-c1d64b8a-5ce0-480d-b78c-311cce6806c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674043178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
3674043178
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2526574879
Short name T1062
Test name
Test status
Simulation time 82277452 ps
CPU time 0.8 seconds
Started Mar 26 02:54:51 PM PDT 24
Finished Mar 26 02:54:57 PM PDT 24
Peak memory 203576 kb
Host smart-d43fa5e3-98c3-4695-9787-3b2753cb11c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526574879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
2526574879
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3923137651
Short name T1000
Test name
Test status
Simulation time 12898616 ps
CPU time 0.7 seconds
Started Mar 26 02:54:51 PM PDT 24
Finished Mar 26 02:54:51 PM PDT 24
Peak memory 203620 kb
Host smart-12f6e86f-c318-40f0-b448-2e31b268d186
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923137651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
3923137651
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3070033190
Short name T1026
Test name
Test status
Simulation time 20613800 ps
CPU time 0.72 seconds
Started Mar 26 02:54:49 PM PDT 24
Finished Mar 26 02:54:50 PM PDT 24
Peak memory 203632 kb
Host smart-6cdd80c8-f15b-499d-980c-7162a083ff97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070033190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
3070033190
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1396491205
Short name T1027
Test name
Test status
Simulation time 43228417 ps
CPU time 0.71 seconds
Started Mar 26 02:54:49 PM PDT 24
Finished Mar 26 02:54:50 PM PDT 24
Peak memory 203556 kb
Host smart-c390e435-3a22-4478-9584-a714a8b56dc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396491205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
1396491205
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2235100380
Short name T103
Test name
Test status
Simulation time 166528009 ps
CPU time 3.45 seconds
Started Mar 26 02:54:53 PM PDT 24
Finished Mar 26 02:54:57 PM PDT 24
Peak memory 217864 kb
Host smart-016a87af-f75b-416a-825e-f1b0ac51cdf0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235100380 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.2235100380
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.300836657
Short name T994
Test name
Test status
Simulation time 68320825 ps
CPU time 1.23 seconds
Started Mar 26 02:54:47 PM PDT 24
Finished Mar 26 02:54:48 PM PDT 24
Peak memory 215440 kb
Host smart-fdaa0b26-d7ee-42a7-9138-10163b71d08b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300836657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.300836657
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1131257201
Short name T1050
Test name
Test status
Simulation time 16777859 ps
CPU time 0.75 seconds
Started Mar 26 02:54:48 PM PDT 24
Finished Mar 26 02:54:49 PM PDT 24
Peak memory 203608 kb
Host smart-bf1b5ff6-20a9-4c72-9be4-3cc7e6ae62b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131257201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.1
131257201
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3178502179
Short name T1052
Test name
Test status
Simulation time 582496491 ps
CPU time 4.28 seconds
Started Mar 26 02:54:50 PM PDT 24
Finished Mar 26 02:54:55 PM PDT 24
Peak memory 215468 kb
Host smart-bd7b6923-6c79-4505-87f2-da5518b4d003
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178502179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.3178502179
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1905004537
Short name T161
Test name
Test status
Simulation time 289947657 ps
CPU time 5.28 seconds
Started Mar 26 02:55:02 PM PDT 24
Finished Mar 26 02:55:07 PM PDT 24
Peak memory 215680 kb
Host smart-fef2d0f2-c319-4820-8116-84dffea0b8db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905004537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.1
905004537
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1007767239
Short name T133
Test name
Test status
Simulation time 2707169341 ps
CPU time 24.14 seconds
Started Mar 26 02:54:53 PM PDT 24
Finished Mar 26 02:55:17 PM PDT 24
Peak memory 215544 kb
Host smart-a4f2ea6a-6081-471c-a7dc-dd94d21c96ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007767239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.1007767239
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3242420723
Short name T1042
Test name
Test status
Simulation time 393893317 ps
CPU time 3.76 seconds
Started Mar 26 02:54:46 PM PDT 24
Finished Mar 26 02:54:50 PM PDT 24
Peak memory 216684 kb
Host smart-6f95517a-94f2-48de-854d-d00f1f7cdae4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242420723 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.3242420723
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1012613043
Short name T1019
Test name
Test status
Simulation time 130086682 ps
CPU time 2.19 seconds
Started Mar 26 02:54:52 PM PDT 24
Finished Mar 26 02:54:54 PM PDT 24
Peak memory 215460 kb
Host smart-554c2428-837f-4439-b6fa-5aa75202023d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012613043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.1
012613043
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.4266418697
Short name T1047
Test name
Test status
Simulation time 48754521 ps
CPU time 0.77 seconds
Started Mar 26 02:54:47 PM PDT 24
Finished Mar 26 02:54:48 PM PDT 24
Peak memory 203672 kb
Host smart-23e17e5c-37b9-46a6-91a9-d75de005399f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266418697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.4
266418697
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.510956508
Short name T1032
Test name
Test status
Simulation time 528498747 ps
CPU time 3.97 seconds
Started Mar 26 02:54:51 PM PDT 24
Finished Mar 26 02:54:55 PM PDT 24
Peak memory 215332 kb
Host smart-70aa287b-a683-4b3d-87e7-857824600533
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510956508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sp
i_device_same_csr_outstanding.510956508
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3517064652
Short name T1038
Test name
Test status
Simulation time 45459321 ps
CPU time 2.92 seconds
Started Mar 26 02:55:02 PM PDT 24
Finished Mar 26 02:55:05 PM PDT 24
Peak memory 215580 kb
Host smart-ba9fd259-2986-4b9d-b994-ef4bcf472af6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517064652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.3
517064652
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2542629252
Short name T1086
Test name
Test status
Simulation time 1096891509 ps
CPU time 13.97 seconds
Started Mar 26 02:54:52 PM PDT 24
Finished Mar 26 02:55:06 PM PDT 24
Peak memory 215876 kb
Host smart-0966f216-686a-457c-aa30-5c7b11031459
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542629252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.2542629252
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.4205987082
Short name T104
Test name
Test status
Simulation time 113304952 ps
CPU time 2.73 seconds
Started Mar 26 02:54:51 PM PDT 24
Finished Mar 26 02:54:54 PM PDT 24
Peak memory 216488 kb
Host smart-679e3651-a975-4781-a3e9-ca22127d1cba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205987082 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.4205987082
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3122688575
Short name T117
Test name
Test status
Simulation time 41338513 ps
CPU time 1.45 seconds
Started Mar 26 02:54:54 PM PDT 24
Finished Mar 26 02:54:55 PM PDT 24
Peak memory 215396 kb
Host smart-71dc62ef-8804-4fbf-8abc-00962d186493
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122688575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.3
122688575
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3090904878
Short name T979
Test name
Test status
Simulation time 17950007 ps
CPU time 0.74 seconds
Started Mar 26 02:54:50 PM PDT 24
Finished Mar 26 02:54:51 PM PDT 24
Peak memory 203584 kb
Host smart-dec402e6-6b09-493f-86d6-2816b77d8dc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090904878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.3
090904878
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.626067561
Short name T1085
Test name
Test status
Simulation time 137464188 ps
CPU time 1.92 seconds
Started Mar 26 02:54:43 PM PDT 24
Finished Mar 26 02:54:46 PM PDT 24
Peak memory 207296 kb
Host smart-a9046d7b-bda4-4394-96cc-ba0b42d3522b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626067561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sp
i_device_same_csr_outstanding.626067561
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.701171192
Short name T105
Test name
Test status
Simulation time 75723287 ps
CPU time 2.84 seconds
Started Mar 26 02:54:56 PM PDT 24
Finished Mar 26 02:54:59 PM PDT 24
Peak memory 215528 kb
Host smart-2b1f0c8e-4cf6-4f15-90af-94cf2ce4bc35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701171192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.701171192
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3161082077
Short name T59
Test name
Test status
Simulation time 5282774005 ps
CPU time 6.84 seconds
Started Mar 26 02:56:14 PM PDT 24
Finished Mar 26 02:56:21 PM PDT 24
Peak memory 215268 kb
Host smart-cc4ddd90-d0e2-4e33-a4c9-644a70dd30ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161082077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.3161082077
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.573570424
Short name T1023
Test name
Test status
Simulation time 107424297 ps
CPU time 3.66 seconds
Started Mar 26 02:54:51 PM PDT 24
Finished Mar 26 02:54:55 PM PDT 24
Peak memory 217100 kb
Host smart-e96fda4e-cae0-44f5-9ce5-5cf74e4934c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573570424 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.573570424
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3421265175
Short name T1020
Test name
Test status
Simulation time 20155920 ps
CPU time 1.19 seconds
Started Mar 26 02:54:54 PM PDT 24
Finished Mar 26 02:54:55 PM PDT 24
Peak memory 207212 kb
Host smart-eabd0420-392c-4ec2-a023-7eb9c9d641b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421265175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.3
421265175
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1560592817
Short name T1061
Test name
Test status
Simulation time 20124160 ps
CPU time 0.71 seconds
Started Mar 26 02:54:51 PM PDT 24
Finished Mar 26 02:54:52 PM PDT 24
Peak memory 203604 kb
Host smart-4d8a40e8-864e-470c-8b19-96ee578658a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560592817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.1
560592817
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1718094132
Short name T977
Test name
Test status
Simulation time 65490179 ps
CPU time 1.9 seconds
Started Mar 26 02:54:49 PM PDT 24
Finished Mar 26 02:54:51 PM PDT 24
Peak memory 215416 kb
Host smart-d7e752d1-9b11-433f-8c0b-32e082b817b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718094132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.1718094132
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.32873013
Short name T96
Test name
Test status
Simulation time 43612132 ps
CPU time 3.07 seconds
Started Mar 26 02:54:53 PM PDT 24
Finished Mar 26 02:54:56 PM PDT 24
Peak memory 215488 kb
Host smart-69362c62-27af-4310-aced-5dc78d69c830
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32873013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.32873013
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1343153303
Short name T167
Test name
Test status
Simulation time 831527439 ps
CPU time 21.44 seconds
Started Mar 26 02:54:48 PM PDT 24
Finished Mar 26 02:55:10 PM PDT 24
Peak memory 215480 kb
Host smart-937c4c3e-0eda-465e-8735-4fb1bdaa987c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343153303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.1343153303
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2708772156
Short name T1008
Test name
Test status
Simulation time 148589642 ps
CPU time 2.9 seconds
Started Mar 26 02:54:48 PM PDT 24
Finished Mar 26 02:54:51 PM PDT 24
Peak memory 216820 kb
Host smart-ab866d33-f76d-4212-b621-44eef9dab8c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708772156 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.2708772156
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.4120063437
Short name T108
Test name
Test status
Simulation time 281015166 ps
CPU time 1.96 seconds
Started Mar 26 02:55:07 PM PDT 24
Finished Mar 26 02:55:09 PM PDT 24
Peak memory 207156 kb
Host smart-bb5024cd-a1ac-4dd0-a105-9259d62bf25f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120063437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.4
120063437
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2523056377
Short name T988
Test name
Test status
Simulation time 19890906 ps
CPU time 0.69 seconds
Started Mar 26 02:54:48 PM PDT 24
Finished Mar 26 02:54:48 PM PDT 24
Peak memory 203588 kb
Host smart-7ab39276-39a8-4438-bc17-52ded522ec41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523056377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.2
523056377
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1445617670
Short name T1051
Test name
Test status
Simulation time 62190895 ps
CPU time 1.97 seconds
Started Mar 26 02:54:49 PM PDT 24
Finished Mar 26 02:54:51 PM PDT 24
Peak memory 207228 kb
Host smart-57d2f4d3-2db6-45c5-bbda-1eb7b2fc2454
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445617670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.1445617670
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3102456321
Short name T1045
Test name
Test status
Simulation time 186203135 ps
CPU time 3.81 seconds
Started Mar 26 02:54:56 PM PDT 24
Finished Mar 26 02:55:00 PM PDT 24
Peak memory 219060 kb
Host smart-e894b539-1906-4bb8-96e1-574bfcc13f96
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102456321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.3
102456321
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1783738990
Short name T130
Test name
Test status
Simulation time 1281657210 ps
CPU time 22.05 seconds
Started Mar 26 02:55:06 PM PDT 24
Finished Mar 26 02:55:28 PM PDT 24
Peak memory 215700 kb
Host smart-cbce3a84-ac2d-4726-ab89-12a01e5d0ec6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783738990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.1783738990
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.829431192
Short name T646
Test name
Test status
Simulation time 30571899 ps
CPU time 0.71 seconds
Started Mar 26 03:04:36 PM PDT 24
Finished Mar 26 03:04:38 PM PDT 24
Peak memory 205248 kb
Host smart-791e0745-897c-43ad-b76e-f4e92c7df9d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829431192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.829431192
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.1422994584
Short name T217
Test name
Test status
Simulation time 412828805 ps
CPU time 2.59 seconds
Started Mar 26 03:04:30 PM PDT 24
Finished Mar 26 03:04:33 PM PDT 24
Peak memory 224928 kb
Host smart-2adc015a-bc29-410d-a2ae-0dfff0f504d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422994584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.1422994584
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.4203059101
Short name T598
Test name
Test status
Simulation time 23369927 ps
CPU time 0.78 seconds
Started Mar 26 03:04:30 PM PDT 24
Finished Mar 26 03:04:31 PM PDT 24
Peak memory 206992 kb
Host smart-e901d2bc-5bbd-4b17-bb88-d8155c07b222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203059101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.4203059101
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.4143694056
Short name T920
Test name
Test status
Simulation time 5117509584 ps
CPU time 67.03 seconds
Started Mar 26 03:04:30 PM PDT 24
Finished Mar 26 03:05:37 PM PDT 24
Peak memory 264232 kb
Host smart-c3017341-a023-4a6c-a0d3-bc0115bade83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143694056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.4143694056
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.3822837823
Short name T660
Test name
Test status
Simulation time 5391642816 ps
CPU time 86.04 seconds
Started Mar 26 03:04:33 PM PDT 24
Finished Mar 26 03:06:00 PM PDT 24
Peak memory 260328 kb
Host smart-f8320cca-709b-4f2f-bf0f-781b7a1c40a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822837823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.3822837823
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.760639082
Short name T895
Test name
Test status
Simulation time 7586543180 ps
CPU time 29.47 seconds
Started Mar 26 03:04:31 PM PDT 24
Finished Mar 26 03:05:00 PM PDT 24
Peak memory 224848 kb
Host smart-19737685-cbb2-4724-9752-b14995e1c8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760639082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.760639082
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.680812317
Short name T523
Test name
Test status
Simulation time 285096155 ps
CPU time 3.3 seconds
Started Mar 26 03:04:32 PM PDT 24
Finished Mar 26 03:04:35 PM PDT 24
Peak memory 219140 kb
Host smart-318673e3-eaa6-44ae-a63e-a1ef144de312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680812317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.680812317
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.2390038969
Short name T445
Test name
Test status
Simulation time 8449484514 ps
CPU time 17.69 seconds
Started Mar 26 03:04:29 PM PDT 24
Finished Mar 26 03:04:47 PM PDT 24
Peak memory 251016 kb
Host smart-dac2b26d-dc70-46d6-9ab4-bb34971b98e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390038969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.2390038969
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.1293002867
Short name T883
Test name
Test status
Simulation time 194464298 ps
CPU time 3.77 seconds
Started Mar 26 03:04:38 PM PDT 24
Finished Mar 26 03:04:42 PM PDT 24
Peak memory 220092 kb
Host smart-87d44e7b-0e62-4d9c-9d70-aa37a7731f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293002867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.1293002867
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.3422754573
Short name T927
Test name
Test status
Simulation time 28280634 ps
CPU time 0.74 seconds
Started Mar 26 03:04:32 PM PDT 24
Finished Mar 26 03:04:32 PM PDT 24
Peak memory 216500 kb
Host smart-46decbd8-0f05-494a-b352-5487e5139278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422754573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.3422754573
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.3022279258
Short name T696
Test name
Test status
Simulation time 3089271449 ps
CPU time 5.18 seconds
Started Mar 26 03:04:33 PM PDT 24
Finished Mar 26 03:04:39 PM PDT 24
Peak memory 219584 kb
Host smart-c7b805c6-fcba-4ba9-96bf-126b4b5fb733
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3022279258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.3022279258
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.2302716932
Short name T406
Test name
Test status
Simulation time 28618393933 ps
CPU time 43.64 seconds
Started Mar 26 03:04:31 PM PDT 24
Finished Mar 26 03:05:14 PM PDT 24
Peak memory 216844 kb
Host smart-3f71b14b-9270-4623-9eb2-99cca8a8d65d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302716932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.2302716932
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.1849585769
Short name T563
Test name
Test status
Simulation time 2683748855 ps
CPU time 14.46 seconds
Started Mar 26 03:04:31 PM PDT 24
Finished Mar 26 03:04:45 PM PDT 24
Peak memory 216788 kb
Host smart-8e1a0e55-528f-4bab-8a0e-d00f6b464d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849585769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.1849585769
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.985197609
Short name T433
Test name
Test status
Simulation time 3920734112 ps
CPU time 2.92 seconds
Started Mar 26 03:04:32 PM PDT 24
Finished Mar 26 03:04:35 PM PDT 24
Peak memory 216784 kb
Host smart-c6c69e43-f31a-416b-bc2d-4aadae309707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985197609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.985197609
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.2694819187
Short name T336
Test name
Test status
Simulation time 27779773 ps
CPU time 0.77 seconds
Started Mar 26 03:04:31 PM PDT 24
Finished Mar 26 03:04:32 PM PDT 24
Peak memory 206156 kb
Host smart-32a4a3ca-a5ba-4709-a6d2-980155c75834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694819187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.2694819187
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.3054313750
Short name T964
Test name
Test status
Simulation time 1432212220 ps
CPU time 8.47 seconds
Started Mar 26 03:04:30 PM PDT 24
Finished Mar 26 03:04:38 PM PDT 24
Peak memory 221488 kb
Host smart-075ec3d1-1961-47fc-9a26-c4b988c2421f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054313750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.3054313750
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.3792380873
Short name T549
Test name
Test status
Simulation time 35613752 ps
CPU time 0.8 seconds
Started Mar 26 03:04:44 PM PDT 24
Finished Mar 26 03:04:46 PM PDT 24
Peak memory 205132 kb
Host smart-df08a0c2-afe1-4d6e-b95e-fe98615b99d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792380873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.3
792380873
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.3279647986
Short name T703
Test name
Test status
Simulation time 3443126585 ps
CPU time 8.81 seconds
Started Mar 26 03:04:41 PM PDT 24
Finished Mar 26 03:04:50 PM PDT 24
Peak memory 220388 kb
Host smart-80ec9e96-1888-4acd-a511-c343dab18644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279647986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.3279647986
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.143921367
Short name T326
Test name
Test status
Simulation time 57910318 ps
CPU time 0.73 seconds
Started Mar 26 03:04:31 PM PDT 24
Finished Mar 26 03:04:32 PM PDT 24
Peak memory 206308 kb
Host smart-11e7f176-d03c-4167-bc9f-7599ce6a8584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143921367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.143921367
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.2970046044
Short name T52
Test name
Test status
Simulation time 41306783276 ps
CPU time 189.11 seconds
Started Mar 26 03:04:44 PM PDT 24
Finished Mar 26 03:07:54 PM PDT 24
Peak memory 263644 kb
Host smart-7e47e20c-ee77-47aa-872b-ebba31252aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970046044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.2970046044
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.1417487507
Short name T840
Test name
Test status
Simulation time 24175561627 ps
CPU time 85.34 seconds
Started Mar 26 03:04:42 PM PDT 24
Finished Mar 26 03:06:08 PM PDT 24
Peak memory 250532 kb
Host smart-12a9d32e-4cdf-450c-976c-6213a9408db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417487507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.1417487507
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.3642393394
Short name T763
Test name
Test status
Simulation time 7084834708 ps
CPU time 39.55 seconds
Started Mar 26 03:04:42 PM PDT 24
Finished Mar 26 03:05:22 PM PDT 24
Peak memory 226632 kb
Host smart-3eda4683-d065-4d5e-9f50-749d324dfded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642393394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.3642393394
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.2272947993
Short name T91
Test name
Test status
Simulation time 1972754227 ps
CPU time 4.8 seconds
Started Mar 26 03:04:42 PM PDT 24
Finished Mar 26 03:04:47 PM PDT 24
Peak memory 234000 kb
Host smart-2e312426-e10d-42d3-a70b-7a4d04e97932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272947993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.2272947993
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.304058243
Short name T670
Test name
Test status
Simulation time 554467914 ps
CPU time 3.89 seconds
Started Mar 26 03:04:47 PM PDT 24
Finished Mar 26 03:04:51 PM PDT 24
Peak memory 237352 kb
Host smart-9302090a-ebbd-40db-8e7c-8261ad15e989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304058243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.304058243
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.2102422090
Short name T29
Test name
Test status
Simulation time 5850990485 ps
CPU time 9.34 seconds
Started Mar 26 03:04:43 PM PDT 24
Finished Mar 26 03:04:52 PM PDT 24
Peak memory 234748 kb
Host smart-47caa333-7c45-4630-a072-25f0124369a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102422090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.2102422090
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.1469227557
Short name T750
Test name
Test status
Simulation time 3309402422 ps
CPU time 10.83 seconds
Started Mar 26 03:04:42 PM PDT 24
Finished Mar 26 03:04:53 PM PDT 24
Peak memory 233200 kb
Host smart-e0df1438-6d17-44b9-af61-fb0067d9a17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469227557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.1469227557
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.3636769561
Short name T522
Test name
Test status
Simulation time 738800487 ps
CPU time 5.53 seconds
Started Mar 26 03:04:41 PM PDT 24
Finished Mar 26 03:04:47 PM PDT 24
Peak memory 223260 kb
Host smart-8162b7c1-cbbf-4ca0-856a-2629dfbabad2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3636769561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.3636769561
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.4229773351
Short name T65
Test name
Test status
Simulation time 145367653 ps
CPU time 1.12 seconds
Started Mar 26 03:04:43 PM PDT 24
Finished Mar 26 03:04:44 PM PDT 24
Peak memory 235568 kb
Host smart-0a434ab5-8452-476c-bd55-edd6e45738e8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229773351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.4229773351
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.1559313698
Short name T757
Test name
Test status
Simulation time 7144165908 ps
CPU time 71.17 seconds
Started Mar 26 03:04:41 PM PDT 24
Finished Mar 26 03:05:53 PM PDT 24
Peak memory 249596 kb
Host smart-0f7b6342-4b8b-49df-bc60-a631b11ff54b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559313698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.1559313698
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.2602295485
Short name T796
Test name
Test status
Simulation time 57712202195 ps
CPU time 75.85 seconds
Started Mar 26 03:04:30 PM PDT 24
Finished Mar 26 03:05:46 PM PDT 24
Peak memory 216732 kb
Host smart-ea28668b-1b1c-4060-9efa-b622b5c344f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602295485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.2602295485
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.2620940840
Short name T969
Test name
Test status
Simulation time 919700828 ps
CPU time 6.28 seconds
Started Mar 26 03:04:33 PM PDT 24
Finished Mar 26 03:04:39 PM PDT 24
Peak memory 216612 kb
Host smart-ee37533b-6184-4f6e-a269-1a67dda5f184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620940840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.2620940840
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.2455026180
Short name T320
Test name
Test status
Simulation time 95700973 ps
CPU time 1.22 seconds
Started Mar 26 03:04:43 PM PDT 24
Finished Mar 26 03:04:46 PM PDT 24
Peak memory 216696 kb
Host smart-38473c76-8ce5-45ee-965f-a63fe39805c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455026180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2455026180
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.2123446766
Short name T767
Test name
Test status
Simulation time 155056158 ps
CPU time 0.86 seconds
Started Mar 26 03:04:41 PM PDT 24
Finished Mar 26 03:04:42 PM PDT 24
Peak memory 206144 kb
Host smart-162eeb91-0087-471f-9bbd-6e0342a1a668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123446766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.2123446766
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.1993914278
Short name T357
Test name
Test status
Simulation time 392812458 ps
CPU time 2.23 seconds
Started Mar 26 03:04:41 PM PDT 24
Finished Mar 26 03:04:43 PM PDT 24
Peak memory 216692 kb
Host smart-f899be06-d126-44db-a259-0ca3f3c372a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993914278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.1993914278
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.3031175170
Short name T457
Test name
Test status
Simulation time 45104340 ps
CPU time 2.53 seconds
Started Mar 26 03:05:18 PM PDT 24
Finished Mar 26 03:05:20 PM PDT 24
Peak memory 234012 kb
Host smart-0f588d47-38ad-4e25-a47f-0b7d2724c45f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031175170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.3031175170
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.4290931026
Short name T695
Test name
Test status
Simulation time 54965349 ps
CPU time 0.79 seconds
Started Mar 26 03:05:19 PM PDT 24
Finished Mar 26 03:05:20 PM PDT 24
Peak memory 205952 kb
Host smart-27f8b6f3-1bf7-4357-9ea2-792cc3dddf9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290931026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.4290931026
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.1869794384
Short name T35
Test name
Test status
Simulation time 80494333056 ps
CPU time 416.19 seconds
Started Mar 26 03:05:18 PM PDT 24
Finished Mar 26 03:12:15 PM PDT 24
Peak memory 254068 kb
Host smart-288b7d8b-05fb-4f00-ba52-ab4d72bd5618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869794384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.1869794384
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.1385896628
Short name T866
Test name
Test status
Simulation time 17775446219 ps
CPU time 109.5 seconds
Started Mar 26 03:05:24 PM PDT 24
Finished Mar 26 03:07:14 PM PDT 24
Peak memory 257260 kb
Host smart-2bd04744-bb30-4be8-bf21-81186c9673aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385896628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.1385896628
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.1734024575
Short name T532
Test name
Test status
Simulation time 7029222054 ps
CPU time 80.56 seconds
Started Mar 26 03:05:16 PM PDT 24
Finished Mar 26 03:06:36 PM PDT 24
Peak memory 253180 kb
Host smart-34b85021-d4d9-46f1-b51c-8639746de770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734024575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.1734024575
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_intercept.3951792104
Short name T727
Test name
Test status
Simulation time 396670169 ps
CPU time 4.04 seconds
Started Mar 26 03:05:18 PM PDT 24
Finished Mar 26 03:05:23 PM PDT 24
Peak memory 236528 kb
Host smart-5fb1568f-e9a9-41c7-afa3-acb4ea15ad74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951792104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.3951792104
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.2481225456
Short name T959
Test name
Test status
Simulation time 3497967826 ps
CPU time 13.47 seconds
Started Mar 26 03:05:20 PM PDT 24
Finished Mar 26 03:05:33 PM PDT 24
Peak memory 224824 kb
Host smart-5622b692-3bab-495a-87fa-06dcd6d72e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481225456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.2481225456
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.1720637618
Short name T915
Test name
Test status
Simulation time 1689714301 ps
CPU time 6.77 seconds
Started Mar 26 03:05:18 PM PDT 24
Finished Mar 26 03:05:25 PM PDT 24
Peak memory 218788 kb
Host smart-7716e5aa-44b7-43c2-97e5-b0eaa6ab3aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720637618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.1720637618
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.796126969
Short name T71
Test name
Test status
Simulation time 524645595 ps
CPU time 2.35 seconds
Started Mar 26 03:05:18 PM PDT 24
Finished Mar 26 03:05:20 PM PDT 24
Peak memory 217072 kb
Host smart-662d4937-fb62-463c-846b-5905f6e95e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796126969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.796126969
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_ram_cfg.3427983395
Short name T7
Test name
Test status
Simulation time 22007901 ps
CPU time 0.76 seconds
Started Mar 26 03:05:17 PM PDT 24
Finished Mar 26 03:05:18 PM PDT 24
Peak memory 216512 kb
Host smart-337bce14-dd5c-438d-b3a3-f7939cae4346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427983395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_ram_cfg.3427983395
Directory /workspace/10.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.2399327400
Short name T906
Test name
Test status
Simulation time 567457565 ps
CPU time 3.62 seconds
Started Mar 26 03:05:20 PM PDT 24
Finished Mar 26 03:05:24 PM PDT 24
Peak memory 220908 kb
Host smart-07fcf3ba-1cbb-4d49-bd0c-15a276bf3680
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2399327400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.2399327400
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.596926007
Short name T521
Test name
Test status
Simulation time 52005876975 ps
CPU time 57.99 seconds
Started Mar 26 03:05:19 PM PDT 24
Finished Mar 26 03:06:18 PM PDT 24
Peak memory 216668 kb
Host smart-6516fb93-497c-41ec-b791-899f6321d122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596926007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.596926007
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.3966191551
Short name T669
Test name
Test status
Simulation time 25822898996 ps
CPU time 21.44 seconds
Started Mar 26 03:05:19 PM PDT 24
Finished Mar 26 03:05:41 PM PDT 24
Peak memory 216700 kb
Host smart-c363ff74-7911-41c4-98c5-f5049af8a17c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966191551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.3966191551
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.819100040
Short name T596
Test name
Test status
Simulation time 44933325 ps
CPU time 1.03 seconds
Started Mar 26 03:05:24 PM PDT 24
Finished Mar 26 03:05:26 PM PDT 24
Peak memory 207592 kb
Host smart-c252c14c-30ce-4446-a893-182451d1c1be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819100040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.819100040
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.1948065455
Short name T443
Test name
Test status
Simulation time 211649262 ps
CPU time 1.11 seconds
Started Mar 26 03:05:23 PM PDT 24
Finished Mar 26 03:05:24 PM PDT 24
Peak memory 206172 kb
Host smart-3d1515c1-8f46-4211-a9aa-ae4082f9e83c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948065455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.1948065455
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.1539515042
Short name T487
Test name
Test status
Simulation time 5322553769 ps
CPU time 12.87 seconds
Started Mar 26 03:05:20 PM PDT 24
Finished Mar 26 03:05:34 PM PDT 24
Peak memory 239664 kb
Host smart-96c79ea4-7837-4b7b-9d54-c3ad2ffbf20c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539515042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.1539515042
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.2068445506
Short name T672
Test name
Test status
Simulation time 34501152 ps
CPU time 0.74 seconds
Started Mar 26 03:05:26 PM PDT 24
Finished Mar 26 03:05:26 PM PDT 24
Peak memory 205128 kb
Host smart-bc85c329-b06b-4dda-805f-e6972e0b6cff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068445506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
2068445506
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.1750332114
Short name T898
Test name
Test status
Simulation time 51322889 ps
CPU time 2.54 seconds
Started Mar 26 03:05:21 PM PDT 24
Finished Mar 26 03:05:23 PM PDT 24
Peak memory 234044 kb
Host smart-6ede290d-ef47-4306-8388-cbac81f6240c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750332114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.1750332114
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.1372071789
Short name T913
Test name
Test status
Simulation time 79222129 ps
CPU time 0.77 seconds
Started Mar 26 03:05:23 PM PDT 24
Finished Mar 26 03:05:24 PM PDT 24
Peak memory 206292 kb
Host smart-d8ce731e-08fe-4233-9110-974041a2be50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372071789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.1372071789
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.394410428
Short name T947
Test name
Test status
Simulation time 49064457131 ps
CPU time 55.55 seconds
Started Mar 26 03:05:16 PM PDT 24
Finished Mar 26 03:06:11 PM PDT 24
Peak memory 241380 kb
Host smart-775d676b-17d5-4b33-be30-5498133b84e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394410428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.394410428
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.2914069166
Short name T155
Test name
Test status
Simulation time 96983480806 ps
CPU time 310.77 seconds
Started Mar 26 03:05:17 PM PDT 24
Finished Mar 26 03:10:28 PM PDT 24
Peak memory 249456 kb
Host smart-7f7671e6-6580-46f4-87d8-0a39c3ab174a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914069166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.2914069166
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.46131190
Short name T20
Test name
Test status
Simulation time 73757059566 ps
CPU time 302.84 seconds
Started Mar 26 03:05:27 PM PDT 24
Finished Mar 26 03:10:30 PM PDT 24
Peak memory 265956 kb
Host smart-a92e936f-06b0-46ad-b5b2-7ec1df1fb17c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46131190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle.46131190
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.4130662103
Short name T475
Test name
Test status
Simulation time 13967713854 ps
CPU time 23.03 seconds
Started Mar 26 03:05:24 PM PDT 24
Finished Mar 26 03:05:47 PM PDT 24
Peak memory 237096 kb
Host smart-55bba685-7ca3-448b-b869-2a5120de8fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130662103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.4130662103
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.844021325
Short name T638
Test name
Test status
Simulation time 3742014410 ps
CPU time 12.21 seconds
Started Mar 26 03:05:25 PM PDT 24
Finished Mar 26 03:05:37 PM PDT 24
Peak memory 234128 kb
Host smart-38998ba5-5eee-4db9-a0c7-c00a52a6a924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844021325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.844021325
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.2708979778
Short name T178
Test name
Test status
Simulation time 1057096839 ps
CPU time 8.8 seconds
Started Mar 26 03:05:24 PM PDT 24
Finished Mar 26 03:05:33 PM PDT 24
Peak memory 219316 kb
Host smart-74dac48c-f25b-4747-a4c1-43a4ade9755d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708979778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.2708979778
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.3600035675
Short name T181
Test name
Test status
Simulation time 20775649082 ps
CPU time 15.62 seconds
Started Mar 26 03:05:22 PM PDT 24
Finished Mar 26 03:05:38 PM PDT 24
Peak memory 233672 kb
Host smart-2ed735cd-7d00-4c8f-b068-2b098d6eb87f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600035675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.3600035675
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.3092181132
Short name T851
Test name
Test status
Simulation time 5976912132 ps
CPU time 19.57 seconds
Started Mar 26 03:05:25 PM PDT 24
Finished Mar 26 03:05:45 PM PDT 24
Peak memory 237260 kb
Host smart-d6e0134a-a0ec-4cc3-99d3-7036b79a7342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092181132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.3092181132
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_ram_cfg.316369626
Short name T595
Test name
Test status
Simulation time 18818637 ps
CPU time 0.77 seconds
Started Mar 26 03:05:25 PM PDT 24
Finished Mar 26 03:05:26 PM PDT 24
Peak memory 216408 kb
Host smart-1322be89-f668-46b3-9513-8d9215633ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316369626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_ram_cfg.316369626
Directory /workspace/11.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.2836353829
Short name T561
Test name
Test status
Simulation time 1376468698 ps
CPU time 7.03 seconds
Started Mar 26 03:05:24 PM PDT 24
Finished Mar 26 03:05:31 PM PDT 24
Peak memory 222572 kb
Host smart-f26e74b1-c546-4608-b75a-9529515532d2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2836353829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.2836353829
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.2698751734
Short name T809
Test name
Test status
Simulation time 44963211 ps
CPU time 0.98 seconds
Started Mar 26 03:05:30 PM PDT 24
Finished Mar 26 03:05:31 PM PDT 24
Peak memory 207572 kb
Host smart-68d357e2-606c-45dd-b9bc-6de9af41aa8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698751734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.2698751734
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.1067099284
Short name T882
Test name
Test status
Simulation time 13077735159 ps
CPU time 14.44 seconds
Started Mar 26 03:05:25 PM PDT 24
Finished Mar 26 03:05:40 PM PDT 24
Peak memory 217072 kb
Host smart-b6a6536e-7126-4be9-bf4c-eb7dd1132d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067099284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.1067099284
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.2127589833
Short name T442
Test name
Test status
Simulation time 115243799 ps
CPU time 1.05 seconds
Started Mar 26 03:05:24 PM PDT 24
Finished Mar 26 03:05:25 PM PDT 24
Peak memory 206860 kb
Host smart-3c7412fa-2e60-41ce-a11e-b0533145225b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127589833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.2127589833
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.2314750736
Short name T706
Test name
Test status
Simulation time 110849699 ps
CPU time 2.61 seconds
Started Mar 26 03:05:23 PM PDT 24
Finished Mar 26 03:05:26 PM PDT 24
Peak memory 216664 kb
Host smart-81cffea4-da0f-4304-801e-0c5726dc43cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314750736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.2314750736
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.3992881876
Short name T905
Test name
Test status
Simulation time 235125742 ps
CPU time 0.93 seconds
Started Mar 26 03:05:25 PM PDT 24
Finished Mar 26 03:05:26 PM PDT 24
Peak memory 206104 kb
Host smart-065d12ec-380d-4705-860b-7930426eefd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992881876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.3992881876
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.1468448045
Short name T398
Test name
Test status
Simulation time 13397054108 ps
CPU time 12.98 seconds
Started Mar 26 03:05:18 PM PDT 24
Finished Mar 26 03:05:31 PM PDT 24
Peak memory 227768 kb
Host smart-0c153671-c8a8-464f-9611-612a66b73d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468448045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.1468448045
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.1500921399
Short name T843
Test name
Test status
Simulation time 23899166 ps
CPU time 0.75 seconds
Started Mar 26 03:05:30 PM PDT 24
Finished Mar 26 03:05:31 PM PDT 24
Peak memory 205820 kb
Host smart-266da82a-8066-4ee9-adf8-e1634bc9949e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500921399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
1500921399
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.1163621994
Short name T709
Test name
Test status
Simulation time 589550732 ps
CPU time 2.69 seconds
Started Mar 26 03:05:28 PM PDT 24
Finished Mar 26 03:05:31 PM PDT 24
Peak memory 233920 kb
Host smart-50d45155-8a2c-4542-8f74-be6ca1df2042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163621994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.1163621994
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.3168837924
Short name T150
Test name
Test status
Simulation time 87757936 ps
CPU time 0.81 seconds
Started Mar 26 03:05:27 PM PDT 24
Finished Mar 26 03:05:28 PM PDT 24
Peak memory 206932 kb
Host smart-06ccb0b5-d072-4230-8f4c-28f46296da64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168837924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.3168837924
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.819335058
Short name T345
Test name
Test status
Simulation time 9642352432 ps
CPU time 31.99 seconds
Started Mar 26 03:05:28 PM PDT 24
Finished Mar 26 03:06:00 PM PDT 24
Peak memory 241240 kb
Host smart-472227e1-b917-4596-8b85-65dca82413b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819335058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.819335058
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.1302291336
Short name T169
Test name
Test status
Simulation time 79200842880 ps
CPU time 241.47 seconds
Started Mar 26 03:05:28 PM PDT 24
Finished Mar 26 03:09:30 PM PDT 24
Peak memory 273308 kb
Host smart-295d5c56-c261-4463-b16c-2374b4bdfada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302291336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.1302291336
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.1734122503
Short name T253
Test name
Test status
Simulation time 355639352316 ps
CPU time 651.15 seconds
Started Mar 26 03:05:29 PM PDT 24
Finished Mar 26 03:16:20 PM PDT 24
Peak memory 256480 kb
Host smart-85b953cf-971d-4d9c-9e5b-0b02bccb863e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734122503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.1734122503
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.3284929089
Short name T821
Test name
Test status
Simulation time 4070315285 ps
CPU time 14.11 seconds
Started Mar 26 03:05:26 PM PDT 24
Finished Mar 26 03:05:41 PM PDT 24
Peak memory 248576 kb
Host smart-98ac2dc3-22ad-45b0-88d9-8fd581a38885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284929089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.3284929089
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.3535597737
Short name T967
Test name
Test status
Simulation time 3961519971 ps
CPU time 5.7 seconds
Started Mar 26 03:05:32 PM PDT 24
Finished Mar 26 03:05:39 PM PDT 24
Peak memory 235664 kb
Host smart-ba675793-e8cf-42fb-93ee-58ab9e9d6f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535597737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.3535597737
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.3934755636
Short name T378
Test name
Test status
Simulation time 706116519 ps
CPU time 3.89 seconds
Started Mar 26 03:05:29 PM PDT 24
Finished Mar 26 03:05:33 PM PDT 24
Peak memory 234536 kb
Host smart-8f7a1c32-9086-43f8-9209-334d355569ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934755636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.3934755636
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.2795750580
Short name T574
Test name
Test status
Simulation time 165337739 ps
CPU time 3.6 seconds
Started Mar 26 03:05:26 PM PDT 24
Finished Mar 26 03:05:30 PM PDT 24
Peak memory 236032 kb
Host smart-d8772504-bdfc-4810-9dcf-7bbd0d6a1c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795750580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.2795750580
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.4270689672
Short name T712
Test name
Test status
Simulation time 7438397416 ps
CPU time 29.75 seconds
Started Mar 26 03:05:27 PM PDT 24
Finished Mar 26 03:05:57 PM PDT 24
Peak memory 235904 kb
Host smart-f3842914-07e4-4eff-b4e8-1d6baf318a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270689672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.4270689672
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_ram_cfg.427315290
Short name T751
Test name
Test status
Simulation time 26510570 ps
CPU time 0.73 seconds
Started Mar 26 03:05:26 PM PDT 24
Finished Mar 26 03:05:26 PM PDT 24
Peak memory 216464 kb
Host smart-46306ab9-a6be-4e62-9dec-29782b7f62e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427315290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_ram_cfg.427315290
Directory /workspace/12.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.2708915310
Short name T624
Test name
Test status
Simulation time 3338743515 ps
CPU time 5.21 seconds
Started Mar 26 03:05:29 PM PDT 24
Finished Mar 26 03:05:36 PM PDT 24
Peak memory 223384 kb
Host smart-c7c19619-f46b-404b-b768-bd95569cbb9a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2708915310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.2708915310
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.1904876209
Short name T753
Test name
Test status
Simulation time 15672537745 ps
CPU time 91.11 seconds
Started Mar 26 03:05:28 PM PDT 24
Finished Mar 26 03:06:59 PM PDT 24
Peak memory 252344 kb
Host smart-1517904d-1fc3-4080-966d-930e4f3f1cf5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904876209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.1904876209
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.981537238
Short name T656
Test name
Test status
Simulation time 353818365 ps
CPU time 4.67 seconds
Started Mar 26 03:05:33 PM PDT 24
Finished Mar 26 03:05:38 PM PDT 24
Peak memory 216788 kb
Host smart-ce2765fa-a6ca-4fc8-9bd9-07ad332010a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981537238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.981537238
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.438936043
Short name T702
Test name
Test status
Simulation time 26108472419 ps
CPU time 12.84 seconds
Started Mar 26 03:05:27 PM PDT 24
Finished Mar 26 03:05:40 PM PDT 24
Peak memory 216728 kb
Host smart-3258cfcf-6fa7-465e-9eaf-422d6bcf2d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438936043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.438936043
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.1878863443
Short name T611
Test name
Test status
Simulation time 1138997497 ps
CPU time 5.58 seconds
Started Mar 26 03:05:27 PM PDT 24
Finished Mar 26 03:05:33 PM PDT 24
Peak memory 216716 kb
Host smart-3ed3167b-f8b7-4262-b503-39d71a4c581a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878863443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.1878863443
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.3933585860
Short name T18
Test name
Test status
Simulation time 285424567 ps
CPU time 0.93 seconds
Started Mar 26 03:05:28 PM PDT 24
Finished Mar 26 03:05:29 PM PDT 24
Peak memory 205976 kb
Host smart-ee104980-05ff-45cd-a97e-1c09c7da9467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933585860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.3933585860
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.774472930
Short name T733
Test name
Test status
Simulation time 2167693409 ps
CPU time 7.73 seconds
Started Mar 26 03:05:29 PM PDT 24
Finished Mar 26 03:05:38 PM PDT 24
Peak memory 218020 kb
Host smart-848892b8-670f-410e-b7b3-beb3c67af490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774472930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.774472930
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.1663276940
Short name T281
Test name
Test status
Simulation time 45985193 ps
CPU time 0.73 seconds
Started Mar 26 03:05:27 PM PDT 24
Finished Mar 26 03:05:28 PM PDT 24
Peak memory 205228 kb
Host smart-9e67eab7-078d-4456-8187-e005e673fccb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663276940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
1663276940
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.2671801067
Short name T209
Test name
Test status
Simulation time 31953485 ps
CPU time 2.48 seconds
Started Mar 26 03:05:26 PM PDT 24
Finished Mar 26 03:05:29 PM PDT 24
Peak memory 234064 kb
Host smart-bb5ae306-bb4f-4ed9-8c03-2b36ee3f0a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671801067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.2671801067
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.2917588833
Short name T422
Test name
Test status
Simulation time 20696101 ps
CPU time 0.82 seconds
Started Mar 26 03:05:29 PM PDT 24
Finished Mar 26 03:05:31 PM PDT 24
Peak memory 206972 kb
Host smart-8040f6af-70d0-40fd-bbfa-7c91d400262a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917588833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.2917588833
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.3179546324
Short name T249
Test name
Test status
Simulation time 58646387349 ps
CPU time 138.67 seconds
Started Mar 26 03:05:26 PM PDT 24
Finished Mar 26 03:07:44 PM PDT 24
Peak memory 265972 kb
Host smart-77b92e77-98ef-4aaa-bbe2-705628188f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179546324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.3179546324
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.2814060158
Short name T822
Test name
Test status
Simulation time 22953744211 ps
CPU time 63.68 seconds
Started Mar 26 03:05:26 PM PDT 24
Finished Mar 26 03:06:29 PM PDT 24
Peak memory 235220 kb
Host smart-d3df9d3c-bcfc-4409-b3c9-60f7c09f9c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814060158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.2814060158
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.4010558165
Short name T566
Test name
Test status
Simulation time 2199868835 ps
CPU time 37.05 seconds
Started Mar 26 03:05:28 PM PDT 24
Finished Mar 26 03:06:05 PM PDT 24
Peak memory 241616 kb
Host smart-a3362723-f3b4-4f60-950c-bcb61421d853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010558165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.4010558165
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.239973816
Short name T711
Test name
Test status
Simulation time 9332957087 ps
CPU time 44.99 seconds
Started Mar 26 03:05:34 PM PDT 24
Finished Mar 26 03:06:19 PM PDT 24
Peak memory 232772 kb
Host smart-f334cb95-e250-466e-af98-63b6a92ad08e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239973816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.239973816
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.3875664443
Short name T699
Test name
Test status
Simulation time 2766805735 ps
CPU time 4.15 seconds
Started Mar 26 03:05:29 PM PDT 24
Finished Mar 26 03:05:35 PM PDT 24
Peak memory 218996 kb
Host smart-fc25ec76-d682-4b3e-916b-52f79c39816b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875664443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.3875664443
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.1339286935
Short name T900
Test name
Test status
Simulation time 98926876 ps
CPU time 3.42 seconds
Started Mar 26 03:05:26 PM PDT 24
Finished Mar 26 03:05:29 PM PDT 24
Peak memory 234628 kb
Host smart-97359bcc-a3dd-405d-bf6f-d4fc92ddb121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339286935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.1339286935
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.2517554241
Short name T238
Test name
Test status
Simulation time 13670471525 ps
CPU time 16.44 seconds
Started Mar 26 03:05:29 PM PDT 24
Finished Mar 26 03:05:45 PM PDT 24
Peak memory 244700 kb
Host smart-4e015260-58d5-4760-b51c-8219d456e3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517554241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.2517554241
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.1189021336
Short name T363
Test name
Test status
Simulation time 452461972 ps
CPU time 5.23 seconds
Started Mar 26 03:05:30 PM PDT 24
Finished Mar 26 03:05:36 PM PDT 24
Peak memory 238148 kb
Host smart-886182dd-4158-45f5-b8f4-dc14c365ebeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189021336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.1189021336
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_ram_cfg.3049263212
Short name T936
Test name
Test status
Simulation time 54932438 ps
CPU time 0.76 seconds
Started Mar 26 03:05:28 PM PDT 24
Finished Mar 26 03:05:29 PM PDT 24
Peak memory 216424 kb
Host smart-ab0a20da-3651-46d7-a82e-3747d16d9f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049263212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_ram_cfg.3049263212
Directory /workspace/13.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.2765060260
Short name T556
Test name
Test status
Simulation time 279190021 ps
CPU time 3.34 seconds
Started Mar 26 03:05:33 PM PDT 24
Finished Mar 26 03:05:37 PM PDT 24
Peak memory 219188 kb
Host smart-0dd9832d-dde7-4562-ae0f-d641db77076c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2765060260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.2765060260
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.2340988789
Short name T386
Test name
Test status
Simulation time 11692377526 ps
CPU time 101.86 seconds
Started Mar 26 03:05:27 PM PDT 24
Finished Mar 26 03:07:09 PM PDT 24
Peak memory 257772 kb
Host smart-707c6c40-dae3-4525-8fc5-7acc96367cd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340988789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.2340988789
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.2384378870
Short name T589
Test name
Test status
Simulation time 922512974 ps
CPU time 8.96 seconds
Started Mar 26 03:05:27 PM PDT 24
Finished Mar 26 03:05:36 PM PDT 24
Peak memory 216632 kb
Host smart-bc202136-12c3-4463-8e10-c33d51607ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384378870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.2384378870
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.1121166970
Short name T286
Test name
Test status
Simulation time 32413984521 ps
CPU time 12.8 seconds
Started Mar 26 03:05:26 PM PDT 24
Finished Mar 26 03:05:39 PM PDT 24
Peak memory 216764 kb
Host smart-e8c65ed9-e4ea-4523-8ba0-7a034829383b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121166970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.1121166970
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.1836639771
Short name T764
Test name
Test status
Simulation time 374474442 ps
CPU time 2.19 seconds
Started Mar 26 03:05:33 PM PDT 24
Finished Mar 26 03:05:35 PM PDT 24
Peak memory 216660 kb
Host smart-99e4f72f-befd-43a1-b26f-65ff5df7b2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836639771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.1836639771
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.3418413553
Short name T497
Test name
Test status
Simulation time 24423578 ps
CPU time 0.74 seconds
Started Mar 26 03:05:28 PM PDT 24
Finished Mar 26 03:05:29 PM PDT 24
Peak memory 206080 kb
Host smart-1050264e-4f06-41ae-ac6d-9893c712b05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418413553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.3418413553
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.1791582666
Short name T213
Test name
Test status
Simulation time 1192213655 ps
CPU time 7.74 seconds
Started Mar 26 03:05:37 PM PDT 24
Finished Mar 26 03:05:45 PM PDT 24
Peak memory 221036 kb
Host smart-7b7ffae3-e327-4e8f-afed-8e1bacee59f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791582666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.1791582666
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.1186427993
Short name T518
Test name
Test status
Simulation time 14806962 ps
CPU time 0.73 seconds
Started Mar 26 03:05:38 PM PDT 24
Finished Mar 26 03:05:39 PM PDT 24
Peak memory 205804 kb
Host smart-9d4a4a2c-87fc-4179-bf9d-c026ff739d5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186427993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
1186427993
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.2009726095
Short name T897
Test name
Test status
Simulation time 2422154098 ps
CPU time 9.98 seconds
Started Mar 26 03:05:29 PM PDT 24
Finished Mar 26 03:05:40 PM PDT 24
Peak memory 234632 kb
Host smart-10a8a3fc-85a2-441d-832a-5d97237c89b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009726095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.2009726095
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.2474754577
Short name T662
Test name
Test status
Simulation time 98230875 ps
CPU time 0.84 seconds
Started Mar 26 03:05:28 PM PDT 24
Finished Mar 26 03:05:29 PM PDT 24
Peak memory 207060 kb
Host smart-1d9b68be-23c6-43f3-a028-06fce27b9648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474754577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.2474754577
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.872304922
Short name T564
Test name
Test status
Simulation time 410504772 ps
CPU time 4.23 seconds
Started Mar 26 03:05:37 PM PDT 24
Finished Mar 26 03:05:41 PM PDT 24
Peak memory 219960 kb
Host smart-00c2fb03-fd25-419a-a58d-fd207788ba06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872304922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.872304922
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.3676890833
Short name T183
Test name
Test status
Simulation time 73340419509 ps
CPU time 121.16 seconds
Started Mar 26 03:05:45 PM PDT 24
Finished Mar 26 03:07:46 PM PDT 24
Peak memory 233900 kb
Host smart-b1d87ae5-609e-4449-9d98-ed1febbb8eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676890833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.3676890833
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.2810202516
Short name T806
Test name
Test status
Simulation time 420779156 ps
CPU time 13.94 seconds
Started Mar 26 03:05:28 PM PDT 24
Finished Mar 26 03:05:43 PM PDT 24
Peak memory 235688 kb
Host smart-299aa74a-b4f4-43c2-a18c-0f0afee2b96a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810202516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.2810202516
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.2559721365
Short name T700
Test name
Test status
Simulation time 526508142 ps
CPU time 3.25 seconds
Started Mar 26 03:05:27 PM PDT 24
Finished Mar 26 03:05:30 PM PDT 24
Peak memory 220132 kb
Host smart-03c8a15a-6b37-4c1b-9c66-c3ff35919f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559721365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.2559721365
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.542496902
Short name T70
Test name
Test status
Simulation time 254355079 ps
CPU time 5.72 seconds
Started Mar 26 03:05:29 PM PDT 24
Finished Mar 26 03:05:36 PM PDT 24
Peak memory 229612 kb
Host smart-368080bb-b60b-4ba0-a614-286b0410589f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542496902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.542496902
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.52581046
Short name T850
Test name
Test status
Simulation time 4516573840 ps
CPU time 5.75 seconds
Started Mar 26 03:05:28 PM PDT 24
Finished Mar 26 03:05:34 PM PDT 24
Peak memory 233184 kb
Host smart-7fe34b14-d312-4628-ba18-41677330b4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52581046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap.52581046
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.2614031482
Short name T439
Test name
Test status
Simulation time 13623984113 ps
CPU time 12.89 seconds
Started Mar 26 03:05:25 PM PDT 24
Finished Mar 26 03:05:38 PM PDT 24
Peak memory 233928 kb
Host smart-b2064a71-687a-4177-98b4-a28b5c158b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614031482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.2614031482
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_ram_cfg.1721079751
Short name T832
Test name
Test status
Simulation time 43736452 ps
CPU time 0.77 seconds
Started Mar 26 03:05:31 PM PDT 24
Finished Mar 26 03:05:33 PM PDT 24
Peak memory 216492 kb
Host smart-030aa7c7-069e-4654-a9eb-029b5e4a5749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721079751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_ram_cfg.1721079751
Directory /workspace/14.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.1113545090
Short name T533
Test name
Test status
Simulation time 1475204938 ps
CPU time 3.99 seconds
Started Mar 26 03:05:39 PM PDT 24
Finished Mar 26 03:05:44 PM PDT 24
Peak memory 223388 kb
Host smart-1554cca7-92bb-48eb-87a3-9812de31f0b2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1113545090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.1113545090
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.2576546631
Short name T755
Test name
Test status
Simulation time 52677533 ps
CPU time 1.01 seconds
Started Mar 26 03:05:45 PM PDT 24
Finished Mar 26 03:05:47 PM PDT 24
Peak memory 207556 kb
Host smart-62634e45-6c50-4e07-8943-79c6588a57a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576546631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.2576546631
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.1759157691
Short name T557
Test name
Test status
Simulation time 155248521278 ps
CPU time 72.54 seconds
Started Mar 26 03:05:27 PM PDT 24
Finished Mar 26 03:06:40 PM PDT 24
Peak memory 216740 kb
Host smart-2b66f157-bd7d-4926-8904-74aae497e51f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759157691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.1759157691
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.3200222704
Short name T338
Test name
Test status
Simulation time 1342170999 ps
CPU time 3.85 seconds
Started Mar 26 03:05:28 PM PDT 24
Finished Mar 26 03:05:32 PM PDT 24
Peak memory 216616 kb
Host smart-c0bb95e9-bebb-4cb3-bb91-1bab054b9779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200222704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.3200222704
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.1518325087
Short name T332
Test name
Test status
Simulation time 792501425 ps
CPU time 6.46 seconds
Started Mar 26 03:05:27 PM PDT 24
Finished Mar 26 03:05:34 PM PDT 24
Peak memory 216592 kb
Host smart-e24eed4d-93c3-4459-8bdc-3f51ba52eef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518325087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.1518325087
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.1250457506
Short name T417
Test name
Test status
Simulation time 150785135 ps
CPU time 1 seconds
Started Mar 26 03:05:28 PM PDT 24
Finished Mar 26 03:05:29 PM PDT 24
Peak memory 206152 kb
Host smart-0918f40c-93c3-412f-bdf0-8736618d0317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250457506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.1250457506
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.1416879050
Short name T972
Test name
Test status
Simulation time 16739952662 ps
CPU time 14 seconds
Started Mar 26 03:05:28 PM PDT 24
Finished Mar 26 03:05:42 PM PDT 24
Peak memory 234588 kb
Host smart-16aa3b88-7fee-49cd-9240-0350d4a97735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416879050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.1416879050
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.3360875820
Short name T707
Test name
Test status
Simulation time 37985303 ps
CPU time 0.73 seconds
Started Mar 26 03:05:43 PM PDT 24
Finished Mar 26 03:05:44 PM PDT 24
Peak memory 206020 kb
Host smart-1b61d551-7395-4882-b152-c010046210f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360875820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
3360875820
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.1251442723
Short name T234
Test name
Test status
Simulation time 1080094159 ps
CPU time 3.56 seconds
Started Mar 26 03:05:40 PM PDT 24
Finished Mar 26 03:05:43 PM PDT 24
Peak memory 235156 kb
Host smart-c3227b9a-cb5a-4119-85ab-cb5b7680fad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251442723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.1251442723
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.1440075351
Short name T892
Test name
Test status
Simulation time 32964586 ps
CPU time 0.75 seconds
Started Mar 26 03:05:37 PM PDT 24
Finished Mar 26 03:05:39 PM PDT 24
Peak memory 206200 kb
Host smart-7d8f4d0d-c5e3-4e86-bbed-64b492e4982e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440075351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.1440075351
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.1111551
Short name T902
Test name
Test status
Simulation time 6577601319 ps
CPU time 80.44 seconds
Started Mar 26 03:05:37 PM PDT 24
Finished Mar 26 03:06:58 PM PDT 24
Peak memory 253608 kb
Host smart-db77f0f9-c4cb-4d7b-af21-964c3cefe615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.1111551
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.1901182966
Short name T423
Test name
Test status
Simulation time 77718498592 ps
CPU time 259.74 seconds
Started Mar 26 03:05:39 PM PDT 24
Finished Mar 26 03:09:59 PM PDT 24
Peak memory 249668 kb
Host smart-58c24379-c7f1-4c98-83ce-ecfa7d2f3cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901182966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.1901182966
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.2929805270
Short name T932
Test name
Test status
Simulation time 8275450488 ps
CPU time 46.73 seconds
Started Mar 26 03:05:37 PM PDT 24
Finished Mar 26 03:06:24 PM PDT 24
Peak memory 235316 kb
Host smart-dfb2baf3-2e19-4e4d-a4ec-bd825ca7780e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929805270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.2929805270
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.2759838590
Short name T630
Test name
Test status
Simulation time 11844122618 ps
CPU time 12.11 seconds
Started Mar 26 03:05:36 PM PDT 24
Finished Mar 26 03:05:48 PM PDT 24
Peak memory 222648 kb
Host smart-d419303d-576e-43c6-8648-849d375bf193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759838590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.2759838590
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.3685599124
Short name T341
Test name
Test status
Simulation time 893930020 ps
CPU time 10.07 seconds
Started Mar 26 03:05:42 PM PDT 24
Finished Mar 26 03:05:53 PM PDT 24
Peak memory 246932 kb
Host smart-29cbe716-d5ce-4328-be78-5bf2bec21179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685599124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.3685599124
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.1528447848
Short name T955
Test name
Test status
Simulation time 3763551735 ps
CPU time 3.23 seconds
Started Mar 26 03:05:38 PM PDT 24
Finished Mar 26 03:05:42 PM PDT 24
Peak memory 219120 kb
Host smart-bc2ae40a-6bef-4fc3-b6f6-1f938bd29ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528447848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.1528447848
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.204605038
Short name T483
Test name
Test status
Simulation time 1109786309 ps
CPU time 5.08 seconds
Started Mar 26 03:05:36 PM PDT 24
Finished Mar 26 03:05:42 PM PDT 24
Peak memory 233096 kb
Host smart-3261869e-ecee-4e25-b665-b526bf1398ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204605038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.204605038
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_ram_cfg.2717899221
Short name T860
Test name
Test status
Simulation time 36216015 ps
CPU time 0.76 seconds
Started Mar 26 03:05:39 PM PDT 24
Finished Mar 26 03:05:40 PM PDT 24
Peak memory 216476 kb
Host smart-5b1c287b-ebc5-4178-a43c-18e575719fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717899221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_ram_cfg.2717899221
Directory /workspace/15.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.1842855378
Short name T600
Test name
Test status
Simulation time 769401449 ps
CPU time 3.88 seconds
Started Mar 26 03:05:36 PM PDT 24
Finished Mar 26 03:05:40 PM PDT 24
Peak memory 220644 kb
Host smart-5c9ddcd2-f9fb-46e2-a64d-ffdeb6726802
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1842855378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.1842855378
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.906934032
Short name T240
Test name
Test status
Simulation time 16814635099 ps
CPU time 112.38 seconds
Started Mar 26 03:05:36 PM PDT 24
Finished Mar 26 03:07:29 PM PDT 24
Peak memory 252652 kb
Host smart-f439ac5d-035e-4c87-a5f6-f2157b5e54ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906934032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stres
s_all.906934032
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.2096104450
Short name T786
Test name
Test status
Simulation time 17970948937 ps
CPU time 13.43 seconds
Started Mar 26 03:05:42 PM PDT 24
Finished Mar 26 03:05:56 PM PDT 24
Peak memory 220452 kb
Host smart-de778651-94a0-4eac-bcaa-4b042cac765e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096104450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.2096104450
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.2405363729
Short name T778
Test name
Test status
Simulation time 529289844 ps
CPU time 2.38 seconds
Started Mar 26 03:05:45 PM PDT 24
Finished Mar 26 03:05:48 PM PDT 24
Peak memory 208196 kb
Host smart-caf22f38-a0da-45b7-ab9a-935aa4b021e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405363729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.2405363729
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.9580963
Short name T676
Test name
Test status
Simulation time 27737872 ps
CPU time 1.05 seconds
Started Mar 26 03:05:39 PM PDT 24
Finished Mar 26 03:05:41 PM PDT 24
Peak memory 207548 kb
Host smart-1bf752ed-c4ab-41ad-bfe3-75ed79e70411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9580963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.9580963
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.3671886401
Short name T421
Test name
Test status
Simulation time 78713749 ps
CPU time 0.81 seconds
Started Mar 26 03:05:42 PM PDT 24
Finished Mar 26 03:05:43 PM PDT 24
Peak memory 206176 kb
Host smart-52212007-0342-4ce7-b768-d64126e0a47c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671886401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.3671886401
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.2486482733
Short name T958
Test name
Test status
Simulation time 426544693 ps
CPU time 6.89 seconds
Started Mar 26 03:05:44 PM PDT 24
Finished Mar 26 03:05:51 PM PDT 24
Peak memory 217900 kb
Host smart-66823906-f7df-4540-840b-e5e5951f98d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486482733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.2486482733
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.3494996672
Short name T55
Test name
Test status
Simulation time 11318194 ps
CPU time 0.74 seconds
Started Mar 26 03:05:41 PM PDT 24
Finished Mar 26 03:05:42 PM PDT 24
Peak memory 205852 kb
Host smart-f44a065a-e8f7-4508-8e06-567db0e1f8e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494996672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
3494996672
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.3123549675
Short name T577
Test name
Test status
Simulation time 885913841 ps
CPU time 4.16 seconds
Started Mar 26 03:05:37 PM PDT 24
Finished Mar 26 03:05:41 PM PDT 24
Peak memory 237280 kb
Host smart-82cc485f-a333-4812-b438-5d0c06c17da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123549675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.3123549675
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.3485783606
Short name T456
Test name
Test status
Simulation time 60493861 ps
CPU time 0.74 seconds
Started Mar 26 03:05:39 PM PDT 24
Finished Mar 26 03:05:40 PM PDT 24
Peak memory 205864 kb
Host smart-974f3205-e9d2-437f-84d5-4952b3d64fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485783606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.3485783606
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.2489491550
Short name T583
Test name
Test status
Simulation time 5588870053 ps
CPU time 18.1 seconds
Started Mar 26 03:05:39 PM PDT 24
Finished Mar 26 03:05:58 PM PDT 24
Peak memory 224980 kb
Host smart-1a4cbb48-caba-4e3e-b5f7-0563336a2411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489491550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.2489491550
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.287067808
Short name T49
Test name
Test status
Simulation time 30708165856 ps
CPU time 175.72 seconds
Started Mar 26 03:05:42 PM PDT 24
Finished Mar 26 03:08:38 PM PDT 24
Peak memory 269864 kb
Host smart-10e4f8ed-c2bd-4416-bb6f-b1f2e25a70af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287067808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.287067808
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.742465752
Short name T418
Test name
Test status
Simulation time 4768671328 ps
CPU time 18.61 seconds
Started Mar 26 03:05:38 PM PDT 24
Finished Mar 26 03:05:57 PM PDT 24
Peak memory 240196 kb
Host smart-1b737108-825e-44bb-bafd-e730c4e94e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742465752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.742465752
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.174900376
Short name T680
Test name
Test status
Simulation time 355793660 ps
CPU time 3.29 seconds
Started Mar 26 03:05:37 PM PDT 24
Finished Mar 26 03:05:41 PM PDT 24
Peak memory 220472 kb
Host smart-689cd763-f403-41f7-b601-94a040543560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174900376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.174900376
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.397177078
Short name T358
Test name
Test status
Simulation time 11627477947 ps
CPU time 11.16 seconds
Started Mar 26 03:05:36 PM PDT 24
Finished Mar 26 03:05:47 PM PDT 24
Peak memory 243992 kb
Host smart-f4936596-157b-443d-bbcb-f916de897b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397177078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.397177078
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.859258106
Short name T749
Test name
Test status
Simulation time 5316048293 ps
CPU time 20.02 seconds
Started Mar 26 03:05:45 PM PDT 24
Finished Mar 26 03:06:06 PM PDT 24
Peak memory 247616 kb
Host smart-4627ad07-cbf1-4524-b12e-96fea0fad1df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859258106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swap
.859258106
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.3228849252
Short name T894
Test name
Test status
Simulation time 624381308 ps
CPU time 4.2 seconds
Started Mar 26 03:05:39 PM PDT 24
Finished Mar 26 03:05:43 PM PDT 24
Peak memory 221436 kb
Host smart-907a1392-640a-41a9-ad62-a2eb2a6db013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228849252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.3228849252
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_ram_cfg.1267613906
Short name T864
Test name
Test status
Simulation time 44154007 ps
CPU time 0.78 seconds
Started Mar 26 03:05:39 PM PDT 24
Finished Mar 26 03:05:40 PM PDT 24
Peak memory 216476 kb
Host smart-46ebed0c-367d-4629-ab7f-acc6bca7cf23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267613906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_ram_cfg.1267613906
Directory /workspace/16.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.3010363462
Short name T858
Test name
Test status
Simulation time 1154878258 ps
CPU time 5.34 seconds
Started Mar 26 03:05:42 PM PDT 24
Finished Mar 26 03:05:47 PM PDT 24
Peak memory 219712 kb
Host smart-64e4f7b8-9a00-460a-b678-15391d185bc6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3010363462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.3010363462
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.3717976608
Short name T916
Test name
Test status
Simulation time 192566928868 ps
CPU time 548.9 seconds
Started Mar 26 03:05:39 PM PDT 24
Finished Mar 26 03:14:48 PM PDT 24
Peak memory 270372 kb
Host smart-084b2ab0-a5b6-42bf-9c8a-c8b074f26d7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717976608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.3717976608
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.1004024304
Short name T717
Test name
Test status
Simulation time 2205174480 ps
CPU time 14.65 seconds
Started Mar 26 03:05:40 PM PDT 24
Finished Mar 26 03:05:54 PM PDT 24
Peak memory 216800 kb
Host smart-fe737997-8e36-4e1f-9d0f-8f52aed4cf8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004024304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.1004024304
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.2811571979
Short name T356
Test name
Test status
Simulation time 1394160594 ps
CPU time 3.78 seconds
Started Mar 26 03:05:36 PM PDT 24
Finished Mar 26 03:05:39 PM PDT 24
Peak memory 216552 kb
Host smart-f993fb83-b0aa-4378-bdbc-19f5ab304c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811571979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.2811571979
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.93383728
Short name T802
Test name
Test status
Simulation time 55506977 ps
CPU time 1.38 seconds
Started Mar 26 03:05:38 PM PDT 24
Finished Mar 26 03:05:39 PM PDT 24
Peak memory 216632 kb
Host smart-6fed0f8a-9d0d-4e47-94e0-74fad1417c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93383728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.93383728
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.307463407
Short name T282
Test name
Test status
Simulation time 405953523 ps
CPU time 1.13 seconds
Started Mar 26 03:05:38 PM PDT 24
Finished Mar 26 03:05:39 PM PDT 24
Peak memory 207200 kb
Host smart-74f804c0-2884-4fd2-8b51-c37881a91ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307463407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.307463407
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.3281950019
Short name T233
Test name
Test status
Simulation time 5335407736 ps
CPU time 8.43 seconds
Started Mar 26 03:05:38 PM PDT 24
Finished Mar 26 03:05:47 PM PDT 24
Peak memory 218908 kb
Host smart-d84c7d9c-e11c-4206-8411-667bccfd5a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281950019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.3281950019
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.542407200
Short name T790
Test name
Test status
Simulation time 45178371 ps
CPU time 0.72 seconds
Started Mar 26 03:05:46 PM PDT 24
Finished Mar 26 03:05:47 PM PDT 24
Peak memory 205304 kb
Host smart-d178d0e4-2403-4b48-b9de-ca43e3bc1fe6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542407200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.542407200
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.2509982511
Short name T300
Test name
Test status
Simulation time 507755063 ps
CPU time 4.08 seconds
Started Mar 26 03:05:48 PM PDT 24
Finished Mar 26 03:05:53 PM PDT 24
Peak memory 235232 kb
Host smart-fc328696-2ee7-41d4-bd76-ace8cf54331d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509982511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.2509982511
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.354267144
Short name T304
Test name
Test status
Simulation time 49375462 ps
CPU time 0.79 seconds
Started Mar 26 03:05:39 PM PDT 24
Finished Mar 26 03:05:40 PM PDT 24
Peak memory 205824 kb
Host smart-e1f7f743-328a-4f7d-b136-3d96919d80ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354267144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.354267144
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.2421348078
Short name T615
Test name
Test status
Simulation time 2578636132 ps
CPU time 32.92 seconds
Started Mar 26 03:05:54 PM PDT 24
Finished Mar 26 03:06:27 PM PDT 24
Peak memory 238504 kb
Host smart-19d339a8-4d92-4ad6-945b-7bc191fea3a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421348078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.2421348078
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.3753511876
Short name T243
Test name
Test status
Simulation time 31496447472 ps
CPU time 104.55 seconds
Started Mar 26 03:05:53 PM PDT 24
Finished Mar 26 03:07:38 PM PDT 24
Peak memory 289624 kb
Host smart-003d90f8-7a3c-49e1-aee1-69e1707fbb9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753511876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.3753511876
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.1932369350
Short name T888
Test name
Test status
Simulation time 2555914653 ps
CPU time 15.73 seconds
Started Mar 26 03:05:45 PM PDT 24
Finished Mar 26 03:06:01 PM PDT 24
Peak memory 232184 kb
Host smart-23bcc42b-6749-43da-a366-311d530d144a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932369350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.1932369350
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.3635298506
Short name T643
Test name
Test status
Simulation time 1514440775 ps
CPU time 6.58 seconds
Started Mar 26 03:05:47 PM PDT 24
Finished Mar 26 03:05:53 PM PDT 24
Peak memory 233880 kb
Host smart-18aa76be-67ab-43dd-ba06-9649168ee6ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635298506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.3635298506
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.3493017383
Short name T811
Test name
Test status
Simulation time 215604054398 ps
CPU time 37.64 seconds
Started Mar 26 03:05:48 PM PDT 24
Finished Mar 26 03:06:26 PM PDT 24
Peak memory 233448 kb
Host smart-637fc50c-0552-4ab7-83c1-ab58413280f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493017383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.3493017383
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.2805437317
Short name T227
Test name
Test status
Simulation time 742606472 ps
CPU time 7.18 seconds
Started Mar 26 03:05:46 PM PDT 24
Finished Mar 26 03:05:53 PM PDT 24
Peak memory 237968 kb
Host smart-80596d6e-ece4-467a-8ada-3a98ffbddd14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805437317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.2805437317
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.3639275778
Short name T498
Test name
Test status
Simulation time 8011256238 ps
CPU time 10.08 seconds
Started Mar 26 03:05:46 PM PDT 24
Finished Mar 26 03:05:57 PM PDT 24
Peak memory 248264 kb
Host smart-d1686472-7118-49be-abbb-023e7dfca96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639275778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.3639275778
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_ram_cfg.3141866121
Short name T917
Test name
Test status
Simulation time 29975130 ps
CPU time 0.75 seconds
Started Mar 26 03:05:47 PM PDT 24
Finished Mar 26 03:05:47 PM PDT 24
Peak memory 216528 kb
Host smart-61e1b671-08fc-47ed-a223-95504a23a23e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141866121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_ram_cfg.3141866121
Directory /workspace/17.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.413811368
Short name T351
Test name
Test status
Simulation time 727419934 ps
CPU time 4.26 seconds
Started Mar 26 03:05:47 PM PDT 24
Finished Mar 26 03:05:52 PM PDT 24
Peak memory 220268 kb
Host smart-b3f91780-3978-4f13-8130-5cb93ac93014
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=413811368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dire
ct.413811368
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.1674873463
Short name T144
Test name
Test status
Simulation time 28529904196 ps
CPU time 277.13 seconds
Started Mar 26 03:05:48 PM PDT 24
Finished Mar 26 03:10:26 PM PDT 24
Peak memory 269988 kb
Host smart-30587241-a8ff-44ca-8d02-37876366e443
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674873463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.1674873463
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.1480167817
Short name T818
Test name
Test status
Simulation time 13034510022 ps
CPU time 11.57 seconds
Started Mar 26 03:05:54 PM PDT 24
Finished Mar 26 03:06:05 PM PDT 24
Peak memory 216772 kb
Host smart-080ac243-cd90-49b6-ae3e-d91fbd1b0b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480167817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.1480167817
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.3844758718
Short name T306
Test name
Test status
Simulation time 2299284409 ps
CPU time 12.5 seconds
Started Mar 26 03:05:50 PM PDT 24
Finished Mar 26 03:06:02 PM PDT 24
Peak memory 216776 kb
Host smart-a0d00e27-ab5e-4bf1-9275-015829359f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844758718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.3844758718
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.3923955891
Short name T872
Test name
Test status
Simulation time 48819234 ps
CPU time 1.54 seconds
Started Mar 26 03:05:47 PM PDT 24
Finished Mar 26 03:05:49 PM PDT 24
Peak memory 216676 kb
Host smart-776c5dbc-fde9-427b-855d-3d3f2c842b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923955891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.3923955891
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.4043406298
Short name T1
Test name
Test status
Simulation time 50513328 ps
CPU time 0.91 seconds
Started Mar 26 03:05:46 PM PDT 24
Finished Mar 26 03:05:47 PM PDT 24
Peak memory 207080 kb
Host smart-7415b538-240f-41ae-a33f-cde84a365789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043406298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.4043406298
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.250908291
Short name T800
Test name
Test status
Simulation time 24458253403 ps
CPU time 26.25 seconds
Started Mar 26 03:05:47 PM PDT 24
Finished Mar 26 03:06:14 PM PDT 24
Peak memory 240872 kb
Host smart-e42a8993-72ce-4bf2-a47b-23cf9b30a40f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250908291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.250908291
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.1012791731
Short name T151
Test name
Test status
Simulation time 35158784 ps
CPU time 0.72 seconds
Started Mar 26 03:05:47 PM PDT 24
Finished Mar 26 03:05:48 PM PDT 24
Peak memory 205212 kb
Host smart-f22b470c-90e8-40f5-8ed8-f71121acabd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012791731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
1012791731
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.2726101532
Short name T208
Test name
Test status
Simulation time 455816745 ps
CPU time 3.75 seconds
Started Mar 26 03:05:48 PM PDT 24
Finished Mar 26 03:05:52 PM PDT 24
Peak memory 234316 kb
Host smart-b0b615d6-d1ee-4785-8211-8d9ad030beac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726101532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.2726101532
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.3565961411
Short name T815
Test name
Test status
Simulation time 51893360 ps
CPU time 0.8 seconds
Started Mar 26 03:05:49 PM PDT 24
Finished Mar 26 03:05:50 PM PDT 24
Peak memory 205964 kb
Host smart-e9042a66-4d5c-457f-bf49-e2e10c87d656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565961411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.3565961411
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.4266306337
Short name T938
Test name
Test status
Simulation time 8735083452 ps
CPU time 78.13 seconds
Started Mar 26 03:05:45 PM PDT 24
Finished Mar 26 03:07:04 PM PDT 24
Peak memory 257680 kb
Host smart-2f4a577e-ced6-4244-87db-074c26887c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266306337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.4266306337
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.2303494579
Short name T120
Test name
Test status
Simulation time 28342934048 ps
CPU time 88.4 seconds
Started Mar 26 03:05:48 PM PDT 24
Finished Mar 26 03:07:17 PM PDT 24
Peak memory 252284 kb
Host smart-55c2d05c-c358-42e1-80a8-bece41e5a776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303494579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.2303494579
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.168469881
Short name T537
Test name
Test status
Simulation time 15859575993 ps
CPU time 81.54 seconds
Started Mar 26 03:05:45 PM PDT 24
Finished Mar 26 03:07:07 PM PDT 24
Peak memory 249504 kb
Host smart-f27f2774-02cc-417f-b2e8-8d76f0b25ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168469881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.168469881
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.3166868376
Short name T168
Test name
Test status
Simulation time 3205449536 ps
CPU time 7.2 seconds
Started Mar 26 03:05:52 PM PDT 24
Finished Mar 26 03:06:00 PM PDT 24
Peak memory 233520 kb
Host smart-e02f9bf4-85a1-467f-adaa-397325afa4b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166868376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.3166868376
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.3985740800
Short name T584
Test name
Test status
Simulation time 6234907002 ps
CPU time 19.98 seconds
Started Mar 26 03:05:44 PM PDT 24
Finished Mar 26 03:06:04 PM PDT 24
Peak memory 241236 kb
Host smart-3a75bfe6-681b-42d0-8123-6ed7396eba21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985740800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.3985740800
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.3009781429
Short name T307
Test name
Test status
Simulation time 274293451 ps
CPU time 3.2 seconds
Started Mar 26 03:05:46 PM PDT 24
Finished Mar 26 03:05:49 PM PDT 24
Peak memory 233944 kb
Host smart-7ef0cef1-3295-481c-9c40-d99c33c10350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009781429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.3009781429
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.1510325164
Short name T530
Test name
Test status
Simulation time 3361464791 ps
CPU time 6.15 seconds
Started Mar 26 03:05:49 PM PDT 24
Finished Mar 26 03:05:56 PM PDT 24
Peak memory 224912 kb
Host smart-f15c6596-98b2-45e9-8f7f-d06e68bcf1a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510325164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1510325164
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_ram_cfg.3198384626
Short name T661
Test name
Test status
Simulation time 31986909 ps
CPU time 0.76 seconds
Started Mar 26 03:05:47 PM PDT 24
Finished Mar 26 03:05:48 PM PDT 24
Peak memory 216532 kb
Host smart-603ae2ba-c3e3-4c1b-90d6-2ebf385a7685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198384626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_ram_cfg.3198384626
Directory /workspace/18.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.794835176
Short name T122
Test name
Test status
Simulation time 162868183 ps
CPU time 3.52 seconds
Started Mar 26 03:05:45 PM PDT 24
Finished Mar 26 03:05:48 PM PDT 24
Peak memory 219600 kb
Host smart-5a447471-cef5-4c08-aad1-7a44acf17769
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=794835176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dire
ct.794835176
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.824083773
Short name T275
Test name
Test status
Simulation time 60268993797 ps
CPU time 78.24 seconds
Started Mar 26 03:05:45 PM PDT 24
Finished Mar 26 03:07:04 PM PDT 24
Peak memory 216828 kb
Host smart-6ea38a4a-caaa-4e02-a95a-b3b1e6f43e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824083773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.824083773
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.4208486061
Short name T434
Test name
Test status
Simulation time 39735457839 ps
CPU time 27.13 seconds
Started Mar 26 03:05:43 PM PDT 24
Finished Mar 26 03:06:10 PM PDT 24
Peak memory 216792 kb
Host smart-6a98c310-8c4f-4d22-a581-4d8d4945cbed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208486061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.4208486061
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.2564819779
Short name T671
Test name
Test status
Simulation time 76705514 ps
CPU time 0.82 seconds
Started Mar 26 03:05:46 PM PDT 24
Finished Mar 26 03:05:46 PM PDT 24
Peak memory 206184 kb
Host smart-083ba2c3-a785-4b65-a5ee-40792238399b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564819779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.2564819779
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.1923197653
Short name T389
Test name
Test status
Simulation time 43415291 ps
CPU time 0.79 seconds
Started Mar 26 03:05:47 PM PDT 24
Finished Mar 26 03:05:48 PM PDT 24
Peak memory 206156 kb
Host smart-cf51f905-7291-45ab-ad6a-cd089122df6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923197653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.1923197653
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.3481510234
Short name T865
Test name
Test status
Simulation time 10228192893 ps
CPU time 6.35 seconds
Started Mar 26 03:05:44 PM PDT 24
Finished Mar 26 03:05:51 PM PDT 24
Peak memory 233900 kb
Host smart-491e4f7a-4b3a-482a-b457-a0abc0129f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481510234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.3481510234
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.1808282614
Short name T911
Test name
Test status
Simulation time 16761599 ps
CPU time 0.68 seconds
Started Mar 26 03:05:58 PM PDT 24
Finished Mar 26 03:05:59 PM PDT 24
Peak memory 205248 kb
Host smart-561a17c1-9ab5-44a6-8aca-6f47bb11dd4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808282614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
1808282614
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.1716725260
Short name T558
Test name
Test status
Simulation time 695057359 ps
CPU time 3.91 seconds
Started Mar 26 03:05:56 PM PDT 24
Finished Mar 26 03:06:00 PM PDT 24
Peak memory 218700 kb
Host smart-cd8b00c7-3b08-4348-ae8d-03e0dec709b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716725260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.1716725260
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.3958647570
Short name T788
Test name
Test status
Simulation time 14321795 ps
CPU time 0.79 seconds
Started Mar 26 03:05:56 PM PDT 24
Finished Mar 26 03:05:57 PM PDT 24
Peak memory 207304 kb
Host smart-4e0f5384-f900-4fc4-a031-e1278d9dc3b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958647570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.3958647570
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.659369321
Short name T203
Test name
Test status
Simulation time 3065810026 ps
CPU time 6.52 seconds
Started Mar 26 03:05:56 PM PDT 24
Finished Mar 26 03:06:03 PM PDT 24
Peak memory 233212 kb
Host smart-cfd53889-0628-4494-8ee5-e0269ab1c0a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659369321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.659369321
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.3858341732
Short name T633
Test name
Test status
Simulation time 58172764516 ps
CPU time 107.76 seconds
Started Mar 26 03:05:58 PM PDT 24
Finished Mar 26 03:07:46 PM PDT 24
Peak memory 241392 kb
Host smart-a5e9e361-5ef9-4aa8-aed8-3cc1330c6552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858341732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.3858341732
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.1393952740
Short name T245
Test name
Test status
Simulation time 490871549806 ps
CPU time 439.1 seconds
Started Mar 26 03:05:58 PM PDT 24
Finished Mar 26 03:13:17 PM PDT 24
Peak memory 257264 kb
Host smart-b6e5239e-4fc4-4823-a4e2-318f6dc4ad01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393952740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.1393952740
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.3122122336
Short name T362
Test name
Test status
Simulation time 26370788015 ps
CPU time 39.95 seconds
Started Mar 26 03:05:56 PM PDT 24
Finished Mar 26 03:06:37 PM PDT 24
Peak memory 254892 kb
Host smart-69758b07-ed02-4ab5-89d7-aa37fd50a0bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122122336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.3122122336
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.1326373590
Short name T211
Test name
Test status
Simulation time 3276393405 ps
CPU time 4.17 seconds
Started Mar 26 03:05:55 PM PDT 24
Finished Mar 26 03:06:00 PM PDT 24
Peak memory 220208 kb
Host smart-0b2b9f19-dadb-4a94-9993-0e18e4fd3ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326373590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.1326373590
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.1436496810
Short name T953
Test name
Test status
Simulation time 7423456184 ps
CPU time 10.07 seconds
Started Mar 26 03:06:00 PM PDT 24
Finished Mar 26 03:06:11 PM PDT 24
Peak memory 223196 kb
Host smart-56ccac5c-b195-4adc-a345-ce5e30e0a1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436496810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.1436496810
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.1147941225
Short name T808
Test name
Test status
Simulation time 202989401 ps
CPU time 3.21 seconds
Started Mar 26 03:05:56 PM PDT 24
Finished Mar 26 03:06:00 PM PDT 24
Peak memory 221096 kb
Host smart-8630a4c5-1fd9-4a15-9a77-0c64cd89fe53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147941225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.1147941225
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.986148830
Short name T148
Test name
Test status
Simulation time 12774102311 ps
CPU time 11.11 seconds
Started Mar 26 03:05:56 PM PDT 24
Finished Mar 26 03:06:07 PM PDT 24
Peak memory 235500 kb
Host smart-6e54703c-7221-40f0-9344-7844c026a6c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986148830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.986148830
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_ram_cfg.1296805392
Short name T732
Test name
Test status
Simulation time 15367878 ps
CPU time 0.77 seconds
Started Mar 26 03:05:59 PM PDT 24
Finished Mar 26 03:05:59 PM PDT 24
Peak memory 216484 kb
Host smart-b4e976da-4469-410e-a7de-94b0b2120c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296805392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_ram_cfg.1296805392
Directory /workspace/19.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.1133567087
Short name T716
Test name
Test status
Simulation time 121703605 ps
CPU time 3.34 seconds
Started Mar 26 03:05:57 PM PDT 24
Finished Mar 26 03:06:00 PM PDT 24
Peak memory 219444 kb
Host smart-1e50ee5a-8b31-4e8a-873a-2e09feaf7299
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1133567087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.1133567087
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.2737071938
Short name T139
Test name
Test status
Simulation time 55571853 ps
CPU time 0.97 seconds
Started Mar 26 03:05:55 PM PDT 24
Finished Mar 26 03:05:57 PM PDT 24
Peak memory 207456 kb
Host smart-f33053c3-9a15-480b-bc7b-4b9db02d2e48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737071938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.2737071938
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.3544606598
Short name T482
Test name
Test status
Simulation time 6154096183 ps
CPU time 39.53 seconds
Started Mar 26 03:05:57 PM PDT 24
Finished Mar 26 03:06:37 PM PDT 24
Peak memory 216724 kb
Host smart-71391fac-dcc5-4a8a-aedd-58da581bcf44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544606598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.3544606598
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.1559299675
Short name T810
Test name
Test status
Simulation time 944496035 ps
CPU time 3.41 seconds
Started Mar 26 03:05:55 PM PDT 24
Finished Mar 26 03:05:59 PM PDT 24
Peak memory 208252 kb
Host smart-2c594fe0-1ccc-4930-a200-eaaa8c38fe01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559299675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.1559299675
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.3679210820
Short name T407
Test name
Test status
Simulation time 105348266 ps
CPU time 3.93 seconds
Started Mar 26 03:05:58 PM PDT 24
Finished Mar 26 03:06:02 PM PDT 24
Peak memory 216288 kb
Host smart-c0e1d336-31c8-46db-a98f-2a9dbe92b481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679210820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.3679210820
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.3870760004
Short name T499
Test name
Test status
Simulation time 25816726 ps
CPU time 0.77 seconds
Started Mar 26 03:05:58 PM PDT 24
Finished Mar 26 03:05:59 PM PDT 24
Peak memory 206076 kb
Host smart-dd7e7823-d643-4876-af86-b206602cacfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870760004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.3870760004
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.1215159359
Short name T431
Test name
Test status
Simulation time 22023520650 ps
CPU time 21.26 seconds
Started Mar 26 03:05:56 PM PDT 24
Finished Mar 26 03:06:17 PM PDT 24
Peak memory 220524 kb
Host smart-267c5c8e-21f6-4d59-9c06-dd6ae2aebb86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215159359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.1215159359
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.3808849020
Short name T413
Test name
Test status
Simulation time 25550247 ps
CPU time 0.71 seconds
Started Mar 26 03:04:43 PM PDT 24
Finished Mar 26 03:04:44 PM PDT 24
Peak memory 205276 kb
Host smart-16985d20-32ee-4a41-827c-ecca73ed25e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808849020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.3
808849020
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.1896272292
Short name T299
Test name
Test status
Simulation time 991119285 ps
CPU time 4.63 seconds
Started Mar 26 03:04:47 PM PDT 24
Finished Mar 26 03:04:52 PM PDT 24
Peak memory 220160 kb
Host smart-7328d6ed-3b5d-4295-b32e-0826e670d662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896272292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.1896272292
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.784801966
Short name T403
Test name
Test status
Simulation time 79388650642 ps
CPU time 97.82 seconds
Started Mar 26 03:04:44 PM PDT 24
Finished Mar 26 03:06:23 PM PDT 24
Peak memory 249564 kb
Host smart-f5117e5c-1e26-4216-8f30-56c21d5fe3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784801966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.784801966
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.3644267681
Short name T693
Test name
Test status
Simulation time 27510538882 ps
CPU time 199.1 seconds
Started Mar 26 03:04:44 PM PDT 24
Finished Mar 26 03:08:04 PM PDT 24
Peak memory 240672 kb
Host smart-d29c9f34-efef-45ee-bf29-0ead994ca889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644267681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.3644267681
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.3339619031
Short name T50
Test name
Test status
Simulation time 36494975098 ps
CPU time 243.89 seconds
Started Mar 26 03:04:41 PM PDT 24
Finished Mar 26 03:08:45 PM PDT 24
Peak memory 251668 kb
Host smart-515bbf5a-dda9-43d7-af63-32f396878701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339619031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.3339619031
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.2135543828
Short name T473
Test name
Test status
Simulation time 3442724232 ps
CPU time 27.15 seconds
Started Mar 26 03:04:45 PM PDT 24
Finished Mar 26 03:05:12 PM PDT 24
Peak memory 257636 kb
Host smart-3ef50916-88cc-49b5-9ea4-618bfe2cba84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135543828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.2135543828
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.1838144680
Short name T599
Test name
Test status
Simulation time 1864740629 ps
CPU time 6.14 seconds
Started Mar 26 03:04:41 PM PDT 24
Finished Mar 26 03:04:48 PM PDT 24
Peak memory 218984 kb
Host smart-e22b0a65-9a3b-48cc-aa1a-671e4318042d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838144680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.1838144680
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.2084702137
Short name T692
Test name
Test status
Simulation time 1551122277 ps
CPU time 4.02 seconds
Started Mar 26 03:04:44 PM PDT 24
Finished Mar 26 03:04:49 PM PDT 24
Peak memory 224724 kb
Host smart-08c29214-904d-4209-93fe-522f81e87be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084702137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.2084702137
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.2789397839
Short name T468
Test name
Test status
Simulation time 192982249 ps
CPU time 2.99 seconds
Started Mar 26 03:04:42 PM PDT 24
Finished Mar 26 03:04:45 PM PDT 24
Peak memory 234016 kb
Host smart-af8f284f-36a7-436d-967e-44bb284e3434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789397839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.2789397839
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.2193063837
Short name T934
Test name
Test status
Simulation time 5615523625 ps
CPU time 10.42 seconds
Started Mar 26 03:04:45 PM PDT 24
Finished Mar 26 03:04:55 PM PDT 24
Peak memory 234004 kb
Host smart-dc21f165-7747-4db2-98dc-9c0c81d2b16f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193063837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.2193063837
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_ram_cfg.1414259977
Short name T956
Test name
Test status
Simulation time 125516700 ps
CPU time 0.72 seconds
Started Mar 26 03:04:43 PM PDT 24
Finished Mar 26 03:04:44 PM PDT 24
Peak memory 216516 kb
Host smart-e1aa6e9a-30e0-4866-a7ab-7a4543e6a1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414259977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_ram_cfg.1414259977
Directory /workspace/2.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.3173950660
Short name T666
Test name
Test status
Simulation time 942919106 ps
CPU time 4.96 seconds
Started Mar 26 03:04:42 PM PDT 24
Finished Mar 26 03:04:47 PM PDT 24
Peak memory 220392 kb
Host smart-899f010c-48ae-4b86-ab06-a64fbb53be7a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3173950660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.3173950660
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.3230150594
Short name T66
Test name
Test status
Simulation time 101137562 ps
CPU time 1.17 seconds
Started Mar 26 03:04:46 PM PDT 24
Finished Mar 26 03:04:47 PM PDT 24
Peak memory 235592 kb
Host smart-095b82c7-ced6-4a8d-ab53-81ea358773a5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230150594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.3230150594
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.3251653324
Short name T495
Test name
Test status
Simulation time 242892817929 ps
CPU time 196.97 seconds
Started Mar 26 03:04:42 PM PDT 24
Finished Mar 26 03:07:59 PM PDT 24
Peak memory 252136 kb
Host smart-eca9057c-9856-4849-a54a-3e2c87c374af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251653324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.3251653324
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.856125454
Short name T360
Test name
Test status
Simulation time 42177721466 ps
CPU time 54.62 seconds
Started Mar 26 03:04:41 PM PDT 24
Finished Mar 26 03:05:36 PM PDT 24
Peak memory 216904 kb
Host smart-8992b96c-02b8-4609-abe8-41ce6c733562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856125454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.856125454
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.2952816386
Short name T335
Test name
Test status
Simulation time 7160052023 ps
CPU time 22.25 seconds
Started Mar 26 03:04:42 PM PDT 24
Finished Mar 26 03:05:04 PM PDT 24
Peak memory 216724 kb
Host smart-249796be-8277-4046-8bef-8cf541a1c101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952816386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.2952816386
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.4078272120
Short name T309
Test name
Test status
Simulation time 783944431 ps
CPU time 3.93 seconds
Started Mar 26 03:04:41 PM PDT 24
Finished Mar 26 03:04:45 PM PDT 24
Peak memory 216804 kb
Host smart-7c9b6d31-0f14-4b28-9eb2-590e9c14a162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078272120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.4078272120
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.2099885338
Short name T391
Test name
Test status
Simulation time 23595774 ps
CPU time 0.82 seconds
Started Mar 26 03:04:42 PM PDT 24
Finished Mar 26 03:04:43 PM PDT 24
Peak memory 206152 kb
Host smart-7299ac93-058c-4018-aadd-47d3e847aeae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099885338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.2099885338
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.1403834583
Short name T170
Test name
Test status
Simulation time 2066990581 ps
CPU time 7.88 seconds
Started Mar 26 03:04:47 PM PDT 24
Finished Mar 26 03:04:55 PM PDT 24
Peak memory 217616 kb
Host smart-dbd4171d-5f2c-433a-927a-d601b1f5e779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403834583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.1403834583
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.3420632798
Short name T399
Test name
Test status
Simulation time 16152164 ps
CPU time 0.75 seconds
Started Mar 26 03:05:56 PM PDT 24
Finished Mar 26 03:05:57 PM PDT 24
Peak memory 205816 kb
Host smart-a7ec543a-99db-4500-b41f-c7f585f62910
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420632798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
3420632798
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.221047396
Short name T726
Test name
Test status
Simulation time 3310863568 ps
CPU time 4.51 seconds
Started Mar 26 03:05:56 PM PDT 24
Finished Mar 26 03:06:01 PM PDT 24
Peak memory 219344 kb
Host smart-25494784-79e9-43ef-bddd-8456727c5717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221047396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.221047396
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.1764031759
Short name T146
Test name
Test status
Simulation time 14212182 ps
CPU time 0.79 seconds
Started Mar 26 03:05:58 PM PDT 24
Finished Mar 26 03:05:59 PM PDT 24
Peak memory 207332 kb
Host smart-e11a3951-d886-432b-8ddc-8f8ded76cbac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764031759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.1764031759
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.2200109192
Short name T526
Test name
Test status
Simulation time 63373471102 ps
CPU time 104.74 seconds
Started Mar 26 03:05:58 PM PDT 24
Finished Mar 26 03:07:43 PM PDT 24
Peak memory 252928 kb
Host smart-0bb22a9c-8ee9-46f9-9481-8c71dcd135fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200109192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.2200109192
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.3918996691
Short name T44
Test name
Test status
Simulation time 11688118183 ps
CPU time 124.39 seconds
Started Mar 26 03:05:55 PM PDT 24
Finished Mar 26 03:08:00 PM PDT 24
Peak memory 249700 kb
Host smart-818296ca-3640-4fda-aab2-17d271eda38a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918996691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.3918996691
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.2488298256
Short name T261
Test name
Test status
Simulation time 106340310123 ps
CPU time 219.22 seconds
Started Mar 26 03:05:55 PM PDT 24
Finished Mar 26 03:09:34 PM PDT 24
Peak memory 274060 kb
Host smart-0f150484-0151-450b-b35a-16d22e9bd099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488298256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.2488298256
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.2274538244
Short name T513
Test name
Test status
Simulation time 6914957907 ps
CPU time 32.23 seconds
Started Mar 26 03:05:55 PM PDT 24
Finished Mar 26 03:06:27 PM PDT 24
Peak memory 240684 kb
Host smart-559c0c62-ff2a-4cfb-8dbf-2daff2749059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274538244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.2274538244
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.2233402466
Short name T503
Test name
Test status
Simulation time 1830419011 ps
CPU time 7.05 seconds
Started Mar 26 03:05:58 PM PDT 24
Finished Mar 26 03:06:05 PM PDT 24
Peak memory 216780 kb
Host smart-5dceda1f-f73c-4e3a-b562-84fa28a82885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233402466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.2233402466
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.2497826299
Short name T334
Test name
Test status
Simulation time 18964508180 ps
CPU time 29.54 seconds
Started Mar 26 03:05:57 PM PDT 24
Finished Mar 26 03:06:27 PM PDT 24
Peak memory 246796 kb
Host smart-a14143c0-d99f-4072-8523-c719fa7b6c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497826299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.2497826299
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.853278478
Short name T604
Test name
Test status
Simulation time 331450180 ps
CPU time 3.39 seconds
Started Mar 26 03:05:59 PM PDT 24
Finished Mar 26 03:06:02 PM PDT 24
Peak memory 233360 kb
Host smart-d2830998-21d9-4e6c-ba9b-9e68b45b1c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853278478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap
.853278478
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.1080250210
Short name T214
Test name
Test status
Simulation time 65053379 ps
CPU time 2.49 seconds
Started Mar 26 03:05:55 PM PDT 24
Finished Mar 26 03:05:57 PM PDT 24
Peak memory 217272 kb
Host smart-5a267cdd-508a-4d8a-ad63-551a604cce2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080250210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.1080250210
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.1299198466
Short name T687
Test name
Test status
Simulation time 614122331 ps
CPU time 4.48 seconds
Started Mar 26 03:05:57 PM PDT 24
Finished Mar 26 03:06:02 PM PDT 24
Peak memory 219824 kb
Host smart-0001395f-756c-4b3d-b3ed-91bdc3ae14cb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1299198466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.1299198466
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.3960767876
Short name T153
Test name
Test status
Simulation time 69091531 ps
CPU time 0.98 seconds
Started Mar 26 03:05:57 PM PDT 24
Finished Mar 26 03:05:58 PM PDT 24
Peak memory 207124 kb
Host smart-6e14dfbe-b703-4ac1-9012-8943dabdb78b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960767876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.3960767876
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.413578800
Short name T805
Test name
Test status
Simulation time 1632151066 ps
CPU time 16.28 seconds
Started Mar 26 03:05:58 PM PDT 24
Finished Mar 26 03:06:14 PM PDT 24
Peak memory 216652 kb
Host smart-06d9f558-7d06-401c-b31e-daf9a7235f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413578800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.413578800
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.1154159336
Short name T441
Test name
Test status
Simulation time 4682560860 ps
CPU time 16.77 seconds
Started Mar 26 03:05:58 PM PDT 24
Finished Mar 26 03:06:15 PM PDT 24
Peak memory 216476 kb
Host smart-19050267-dd14-434f-8707-9c504cd60335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154159336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.1154159336
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.2984166063
Short name T160
Test name
Test status
Simulation time 669183688 ps
CPU time 2.65 seconds
Started Mar 26 03:05:57 PM PDT 24
Finished Mar 26 03:06:00 PM PDT 24
Peak memory 216680 kb
Host smart-d3646075-6a67-4225-bfdc-bcf4f4f42a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984166063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.2984166063
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.2680296111
Short name T748
Test name
Test status
Simulation time 37421253 ps
CPU time 0.8 seconds
Started Mar 26 03:05:56 PM PDT 24
Finished Mar 26 03:05:57 PM PDT 24
Peak memory 206180 kb
Host smart-8d140f9f-5cb4-4b5f-a39f-e37b1099e630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680296111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.2680296111
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.4174572096
Short name T542
Test name
Test status
Simulation time 1424779334 ps
CPU time 5.11 seconds
Started Mar 26 03:05:57 PM PDT 24
Finished Mar 26 03:06:02 PM PDT 24
Peak memory 219816 kb
Host smart-dc188ee0-2843-4d55-8112-f487fed132d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174572096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.4174572096
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.3671758143
Short name T659
Test name
Test status
Simulation time 47199142 ps
CPU time 0.71 seconds
Started Mar 26 03:06:12 PM PDT 24
Finished Mar 26 03:06:13 PM PDT 24
Peak memory 205240 kb
Host smart-65847445-ec73-4dec-8f90-5b6005a1d2cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671758143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
3671758143
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.811977369
Short name T361
Test name
Test status
Simulation time 1317028588 ps
CPU time 6.8 seconds
Started Mar 26 03:06:08 PM PDT 24
Finished Mar 26 03:06:16 PM PDT 24
Peak memory 234524 kb
Host smart-cea01c4e-6e08-4988-ba0b-2e88722b8bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811977369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.811977369
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.1629898906
Short name T743
Test name
Test status
Simulation time 19295717 ps
CPU time 0.76 seconds
Started Mar 26 03:05:58 PM PDT 24
Finished Mar 26 03:05:59 PM PDT 24
Peak memory 205976 kb
Host smart-5376af98-2b46-43ec-8172-dbd046ecf490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629898906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.1629898906
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.585660057
Short name T25
Test name
Test status
Simulation time 2964875924 ps
CPU time 50.72 seconds
Started Mar 26 03:06:08 PM PDT 24
Finished Mar 26 03:06:59 PM PDT 24
Peak memory 249428 kb
Host smart-f8e6d4ca-6204-4209-8386-485cdaae1935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585660057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.585660057
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.3495728679
Short name T762
Test name
Test status
Simulation time 7155995582 ps
CPU time 17.25 seconds
Started Mar 26 03:06:04 PM PDT 24
Finished Mar 26 03:06:21 PM PDT 24
Peak memory 237176 kb
Host smart-82c6c2d9-d3c5-49b5-87ad-0f29d5790f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495728679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.3495728679
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.4101503328
Short name T772
Test name
Test status
Simulation time 341612100218 ps
CPU time 497.68 seconds
Started Mar 26 03:06:03 PM PDT 24
Finished Mar 26 03:14:21 PM PDT 24
Peak memory 258628 kb
Host smart-3db79aab-3893-4027-8b69-cf1f167a052d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101503328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.4101503328
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.3767805709
Short name T721
Test name
Test status
Simulation time 14538129066 ps
CPU time 19.78 seconds
Started Mar 26 03:06:05 PM PDT 24
Finished Mar 26 03:06:26 PM PDT 24
Peak memory 245948 kb
Host smart-7fbfea30-7bbe-4117-8e66-9b41a8f490d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767805709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.3767805709
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.839606217
Short name T173
Test name
Test status
Simulation time 1934888337 ps
CPU time 4.46 seconds
Started Mar 26 03:06:05 PM PDT 24
Finished Mar 26 03:06:10 PM PDT 24
Peak memory 234088 kb
Host smart-a55f7732-03c8-4007-a35c-931f5b23f271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839606217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.839606217
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.2179852144
Short name T394
Test name
Test status
Simulation time 12534441802 ps
CPU time 27.81 seconds
Started Mar 26 03:06:09 PM PDT 24
Finished Mar 26 03:06:38 PM PDT 24
Peak memory 234404 kb
Host smart-807fc30a-a629-4e2a-bb87-ee5fdcabfbc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179852144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.2179852144
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.3502723034
Short name T251
Test name
Test status
Simulation time 3932634300 ps
CPU time 14.18 seconds
Started Mar 26 03:06:03 PM PDT 24
Finished Mar 26 03:06:18 PM PDT 24
Peak memory 228848 kb
Host smart-600a4769-760f-4810-9c98-359ef7862c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502723034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.3502723034
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.2398413791
Short name T409
Test name
Test status
Simulation time 425831355 ps
CPU time 3.65 seconds
Started Mar 26 03:05:58 PM PDT 24
Finished Mar 26 03:06:02 PM PDT 24
Peak memory 219156 kb
Host smart-ddc55d5f-526e-410d-9357-260c9e11d80d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398413791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.2398413791
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.2186105537
Short name T429
Test name
Test status
Simulation time 220068980 ps
CPU time 3.53 seconds
Started Mar 26 03:06:04 PM PDT 24
Finished Mar 26 03:06:08 PM PDT 24
Peak memory 220748 kb
Host smart-a8dc75c7-82f2-47ff-abe9-abb7b0c7001e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2186105537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.2186105537
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.147195702
Short name T448
Test name
Test status
Simulation time 1073619945 ps
CPU time 6.75 seconds
Started Mar 26 03:05:56 PM PDT 24
Finished Mar 26 03:06:03 PM PDT 24
Peak memory 216580 kb
Host smart-093c03af-a7df-4d70-9468-b86e831832d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147195702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.147195702
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.2782366752
Short name T619
Test name
Test status
Simulation time 828508322 ps
CPU time 3.56 seconds
Started Mar 26 03:05:59 PM PDT 24
Finished Mar 26 03:06:03 PM PDT 24
Peak memory 216832 kb
Host smart-eed8c455-23bc-4e03-aee7-96902bd01fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782366752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.2782366752
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.841883713
Short name T904
Test name
Test status
Simulation time 714838631 ps
CPU time 3.89 seconds
Started Mar 26 03:05:58 PM PDT 24
Finished Mar 26 03:06:02 PM PDT 24
Peak memory 216656 kb
Host smart-7b51d7fd-966e-41cb-afb0-b65faade0185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841883713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.841883713
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.1874489404
Short name T349
Test name
Test status
Simulation time 176952633 ps
CPU time 0.96 seconds
Started Mar 26 03:05:55 PM PDT 24
Finished Mar 26 03:05:56 PM PDT 24
Peak memory 207104 kb
Host smart-6e27143f-1403-4216-8cc5-e4c5b324526b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874489404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.1874489404
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.1604311442
Short name T547
Test name
Test status
Simulation time 4121225623 ps
CPU time 15.73 seconds
Started Mar 26 03:06:05 PM PDT 24
Finished Mar 26 03:06:22 PM PDT 24
Peak memory 235380 kb
Host smart-2fc92235-42e6-4e6b-abb2-8d5ec2c23de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604311442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.1604311442
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.1504588956
Short name T412
Test name
Test status
Simulation time 14451495 ps
CPU time 0.74 seconds
Started Mar 26 03:06:04 PM PDT 24
Finished Mar 26 03:06:05 PM PDT 24
Peak memory 206152 kb
Host smart-1effb8c2-5d1b-4cc3-98b0-294e3c4699f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504588956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
1504588956
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.1618985586
Short name T729
Test name
Test status
Simulation time 2414878882 ps
CPU time 4.58 seconds
Started Mar 26 03:06:06 PM PDT 24
Finished Mar 26 03:06:12 PM PDT 24
Peak memory 221692 kb
Host smart-4c058275-00b3-488e-85be-f67ed505e8e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618985586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.1618985586
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.3261556154
Short name T289
Test name
Test status
Simulation time 64445116 ps
CPU time 0.81 seconds
Started Mar 26 03:06:08 PM PDT 24
Finished Mar 26 03:06:11 PM PDT 24
Peak memory 207076 kb
Host smart-0f61a75d-2d92-4185-89cc-018f04e32d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261556154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.3261556154
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.3243356106
Short name T520
Test name
Test status
Simulation time 12126821029 ps
CPU time 20.12 seconds
Started Mar 26 03:06:06 PM PDT 24
Finished Mar 26 03:06:27 PM PDT 24
Peak memory 238264 kb
Host smart-232a2a3a-3f11-435d-8513-b85bb9206f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243356106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.3243356106
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.3140216665
Short name T585
Test name
Test status
Simulation time 3183871662 ps
CPU time 34.91 seconds
Started Mar 26 03:06:06 PM PDT 24
Finished Mar 26 03:06:42 PM PDT 24
Peak memory 249564 kb
Host smart-8abf3a34-c9b2-45b6-8fd4-e909f39b2e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140216665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.3140216665
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.3678830461
Short name T968
Test name
Test status
Simulation time 29255301169 ps
CPU time 126.38 seconds
Started Mar 26 03:06:08 PM PDT 24
Finished Mar 26 03:08:15 PM PDT 24
Peak memory 251160 kb
Host smart-368bb81f-4b02-4474-8b4f-ce30ef97a77c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678830461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.3678830461
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.3617702638
Short name T270
Test name
Test status
Simulation time 968435802 ps
CPU time 13.01 seconds
Started Mar 26 03:06:05 PM PDT 24
Finished Mar 26 03:06:18 PM PDT 24
Peak memory 248748 kb
Host smart-ae17eb48-b36d-4644-9ce6-7517f4427db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617702638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.3617702638
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.1026499563
Short name T924
Test name
Test status
Simulation time 128474711 ps
CPU time 2.65 seconds
Started Mar 26 03:06:05 PM PDT 24
Finished Mar 26 03:06:09 PM PDT 24
Peak memory 218696 kb
Host smart-0b139757-6138-40ca-888d-f9b4b84c891b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026499563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.1026499563
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.2411902609
Short name T172
Test name
Test status
Simulation time 5072140867 ps
CPU time 10.19 seconds
Started Mar 26 03:06:05 PM PDT 24
Finished Mar 26 03:06:16 PM PDT 24
Peak memory 228428 kb
Host smart-98c495b2-7db3-44ba-ace4-f631c366fa46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411902609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.2411902609
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.2886505914
Short name T427
Test name
Test status
Simulation time 43764463 ps
CPU time 2.39 seconds
Started Mar 26 03:06:08 PM PDT 24
Finished Mar 26 03:06:11 PM PDT 24
Peak memory 233020 kb
Host smart-31b59afa-37eb-4fab-8718-0e8162e07eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886505914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.2886505914
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.11794007
Short name T881
Test name
Test status
Simulation time 5557270677 ps
CPU time 14.99 seconds
Started Mar 26 03:06:08 PM PDT 24
Finished Mar 26 03:06:24 PM PDT 24
Peak memory 233584 kb
Host smart-241ff745-39e8-4207-b7a4-72df5750ebc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11794007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.11794007
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.3126665265
Short name T502
Test name
Test status
Simulation time 791916162 ps
CPU time 3.69 seconds
Started Mar 26 03:06:04 PM PDT 24
Finished Mar 26 03:06:08 PM PDT 24
Peak memory 223476 kb
Host smart-59eb9ef0-8406-49a9-b76c-a2a543d25174
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3126665265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.3126665265
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.1571085517
Short name T416
Test name
Test status
Simulation time 143753206383 ps
CPU time 170.05 seconds
Started Mar 26 03:06:09 PM PDT 24
Finished Mar 26 03:09:00 PM PDT 24
Peak memory 251640 kb
Host smart-fd438aaa-d28a-4799-bb96-a32389a131fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571085517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.1571085517
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.3808785031
Short name T348
Test name
Test status
Simulation time 4905690724 ps
CPU time 29.03 seconds
Started Mar 26 03:06:08 PM PDT 24
Finished Mar 26 03:06:38 PM PDT 24
Peak memory 216796 kb
Host smart-20470bd3-4be5-4ada-8f80-e034486ff246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808785031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.3808785031
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.664818236
Short name T742
Test name
Test status
Simulation time 4299637714 ps
CPU time 14.64 seconds
Started Mar 26 03:06:04 PM PDT 24
Finished Mar 26 03:06:19 PM PDT 24
Peak memory 216732 kb
Host smart-1138864a-cf88-4cea-8bda-cc1820eb8b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664818236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.664818236
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.1165312059
Short name T795
Test name
Test status
Simulation time 243777603 ps
CPU time 1.31 seconds
Started Mar 26 03:06:03 PM PDT 24
Finished Mar 26 03:06:05 PM PDT 24
Peak memory 216600 kb
Host smart-375dfb8e-1955-4361-b781-e13b389cade1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165312059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.1165312059
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.1894725897
Short name T303
Test name
Test status
Simulation time 161776680 ps
CPU time 0.91 seconds
Started Mar 26 03:06:13 PM PDT 24
Finished Mar 26 03:06:14 PM PDT 24
Peak memory 207148 kb
Host smart-428f9caf-21d2-4751-98ff-bbd2ff5a6ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894725897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.1894725897
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.3911548069
Short name T404
Test name
Test status
Simulation time 1242292319 ps
CPU time 5.47 seconds
Started Mar 26 03:06:04 PM PDT 24
Finished Mar 26 03:06:10 PM PDT 24
Peak memory 219424 kb
Host smart-a2dd789f-fd95-4af4-a52b-ad21b4e40a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911548069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.3911548069
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.3732863923
Short name T364
Test name
Test status
Simulation time 47223717 ps
CPU time 0.72 seconds
Started Mar 26 03:06:13 PM PDT 24
Finished Mar 26 03:06:14 PM PDT 24
Peak memory 205240 kb
Host smart-96b9662d-b1a2-47f3-ad2b-271355c161f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732863923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
3732863923
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.1897695098
Short name T216
Test name
Test status
Simulation time 3218968290 ps
CPU time 8.9 seconds
Started Mar 26 03:06:05 PM PDT 24
Finished Mar 26 03:06:14 PM PDT 24
Peak memory 220792 kb
Host smart-fb4e7a1d-b4c2-4bd6-bb15-445fcf3312c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897695098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.1897695098
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.1838474502
Short name T277
Test name
Test status
Simulation time 23848856 ps
CPU time 0.77 seconds
Started Mar 26 03:06:09 PM PDT 24
Finished Mar 26 03:06:11 PM PDT 24
Peak memory 207380 kb
Host smart-efe65911-0720-4e16-884c-ec827d8a7bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838474502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.1838474502
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.1242736218
Short name T405
Test name
Test status
Simulation time 744422402 ps
CPU time 6.46 seconds
Started Mar 26 03:06:08 PM PDT 24
Finished Mar 26 03:06:15 PM PDT 24
Peak memory 219788 kb
Host smart-c0f16bc2-dae0-46b0-a901-7e9187221d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242736218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.1242736218
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.3480862510
Short name T607
Test name
Test status
Simulation time 8648342242 ps
CPU time 95.16 seconds
Started Mar 26 03:06:08 PM PDT 24
Finished Mar 26 03:07:44 PM PDT 24
Peak memory 257112 kb
Host smart-22f67694-819e-43cf-95ab-f44dd7342b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480862510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.3480862510
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.482517761
Short name T242
Test name
Test status
Simulation time 49472804276 ps
CPU time 185.72 seconds
Started Mar 26 03:06:06 PM PDT 24
Finished Mar 26 03:09:14 PM PDT 24
Peak memory 249628 kb
Host smart-20592044-5993-4b58-8aaa-6f4cf7d8d078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482517761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idle
.482517761
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.1670861484
Short name T492
Test name
Test status
Simulation time 306338983 ps
CPU time 9.97 seconds
Started Mar 26 03:06:08 PM PDT 24
Finished Mar 26 03:06:19 PM PDT 24
Peak memory 237384 kb
Host smart-eef224b1-76a5-477a-a687-0b504e648850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670861484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.1670861484
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.3340819730
Short name T147
Test name
Test status
Simulation time 148554785 ps
CPU time 3.18 seconds
Started Mar 26 03:06:07 PM PDT 24
Finished Mar 26 03:06:11 PM PDT 24
Peak memory 218168 kb
Host smart-e9943044-d7ad-4d91-bd6f-9f1de361f704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340819730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.3340819730
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.3576894999
Short name T555
Test name
Test status
Simulation time 490816256 ps
CPU time 5.16 seconds
Started Mar 26 03:06:12 PM PDT 24
Finished Mar 26 03:06:18 PM PDT 24
Peak memory 226936 kb
Host smart-3c34ba8f-c1cc-4522-835b-0e5c68014bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576894999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.3576894999
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.3876628257
Short name T244
Test name
Test status
Simulation time 1312002157 ps
CPU time 7.29 seconds
Started Mar 26 03:06:13 PM PDT 24
Finished Mar 26 03:06:21 PM PDT 24
Peak memory 234556 kb
Host smart-77461c49-7e23-4bf1-b778-c6e2627be47f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876628257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.3876628257
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.2852058576
Short name T754
Test name
Test status
Simulation time 132303934 ps
CPU time 3.27 seconds
Started Mar 26 03:06:20 PM PDT 24
Finished Mar 26 03:06:23 PM PDT 24
Peak memory 233964 kb
Host smart-114dacf0-cdb6-4942-9a39-3a9590fa22d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852058576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.2852058576
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.1845011760
Short name T127
Test name
Test status
Simulation time 112225595 ps
CPU time 3.7 seconds
Started Mar 26 03:06:14 PM PDT 24
Finished Mar 26 03:06:18 PM PDT 24
Peak memory 222316 kb
Host smart-9653068f-6d5c-4900-a212-04b07dc38df4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1845011760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.1845011760
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.2951053889
Short name T524
Test name
Test status
Simulation time 7848617037 ps
CPU time 37.75 seconds
Started Mar 26 03:06:03 PM PDT 24
Finished Mar 26 03:06:41 PM PDT 24
Peak memory 216972 kb
Host smart-5624c78a-d8e3-42ea-9da6-d7923700a3df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951053889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.2951053889
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.4162681175
Short name T367
Test name
Test status
Simulation time 658195778 ps
CPU time 4.67 seconds
Started Mar 26 03:06:05 PM PDT 24
Finished Mar 26 03:06:10 PM PDT 24
Peak memory 216696 kb
Host smart-599b78c4-6796-41a7-8758-bb081115b88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162681175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.4162681175
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.597697378
Short name T731
Test name
Test status
Simulation time 46403352 ps
CPU time 0.78 seconds
Started Mar 26 03:06:04 PM PDT 24
Finished Mar 26 03:06:06 PM PDT 24
Peak memory 206172 kb
Host smart-b7a75b9b-310c-4f84-b1a6-c56099e002c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597697378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.597697378
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.3292658451
Short name T824
Test name
Test status
Simulation time 9593568127 ps
CPU time 28.54 seconds
Started Mar 26 03:06:08 PM PDT 24
Finished Mar 26 03:06:37 PM PDT 24
Peak memory 234640 kb
Host smart-94b85905-624a-4067-9e98-06e4c4661db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292658451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.3292658451
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.990041695
Short name T918
Test name
Test status
Simulation time 32654956 ps
CPU time 0.74 seconds
Started Mar 26 03:06:15 PM PDT 24
Finished Mar 26 03:06:16 PM PDT 24
Peak memory 205276 kb
Host smart-7844be08-0f7c-415b-80e7-3ce5a171b30e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990041695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.990041695
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.3899982739
Short name T212
Test name
Test status
Simulation time 624928063 ps
CPU time 4.27 seconds
Started Mar 26 03:06:17 PM PDT 24
Finished Mar 26 03:06:21 PM PDT 24
Peak memory 234704 kb
Host smart-d5d6b97b-9979-4e1d-9e6c-f43b74e99e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899982739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.3899982739
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.4239662392
Short name T621
Test name
Test status
Simulation time 32685153 ps
CPU time 0.83 seconds
Started Mar 26 03:06:08 PM PDT 24
Finished Mar 26 03:06:10 PM PDT 24
Peak memory 206996 kb
Host smart-8b3d6a7f-db7a-4fbc-bc44-3d65b7e5d7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239662392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.4239662392
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.3874988260
Short name T197
Test name
Test status
Simulation time 36763506889 ps
CPU time 45.67 seconds
Started Mar 26 03:06:16 PM PDT 24
Finished Mar 26 03:07:02 PM PDT 24
Peak memory 235336 kb
Host smart-78ddbdc6-a1c2-4539-8a1c-b5980c0b1ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874988260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.3874988260
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.2726738138
Short name T223
Test name
Test status
Simulation time 49452767966 ps
CPU time 182.52 seconds
Started Mar 26 03:06:16 PM PDT 24
Finished Mar 26 03:09:19 PM PDT 24
Peak memory 245668 kb
Host smart-184ae657-269e-4f84-8df4-3fe6dfe8110a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726738138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.2726738138
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.2407676260
Short name T756
Test name
Test status
Simulation time 9332767450 ps
CPU time 48.18 seconds
Started Mar 26 03:06:16 PM PDT 24
Finished Mar 26 03:07:05 PM PDT 24
Peak memory 223248 kb
Host smart-16743ea4-cb15-4f39-8347-26cfd768130f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407676260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.2407676260
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.80624738
Short name T617
Test name
Test status
Simulation time 9317221678 ps
CPU time 19.45 seconds
Started Mar 26 03:06:15 PM PDT 24
Finished Mar 26 03:06:35 PM PDT 24
Peak memory 249616 kb
Host smart-357e39f7-ce5e-4beb-a7b4-6f33361677ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80624738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.80624738
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.4162379125
Short name T951
Test name
Test status
Simulation time 271295166 ps
CPU time 4.11 seconds
Started Mar 26 03:06:14 PM PDT 24
Finished Mar 26 03:06:18 PM PDT 24
Peak memory 234136 kb
Host smart-d445840f-1e21-4f63-a457-785344557a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162379125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.4162379125
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.1293799605
Short name T852
Test name
Test status
Simulation time 12954533426 ps
CPU time 14.58 seconds
Started Mar 26 03:06:17 PM PDT 24
Finished Mar 26 03:06:32 PM PDT 24
Peak memory 239928 kb
Host smart-0a112c12-e01a-4903-855e-28272c64853b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293799605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.1293799605
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.30853697
Short name T567
Test name
Test status
Simulation time 711780763 ps
CPU time 3.44 seconds
Started Mar 26 03:06:14 PM PDT 24
Finished Mar 26 03:06:18 PM PDT 24
Peak memory 234576 kb
Host smart-02f5a52c-b6f2-4ebb-9dff-e6a7c2a827e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30853697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap.30853697
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.2664900167
Short name T550
Test name
Test status
Simulation time 13801647839 ps
CPU time 20.97 seconds
Started Mar 26 03:06:17 PM PDT 24
Finished Mar 26 03:06:38 PM PDT 24
Peak memory 238732 kb
Host smart-033c1fa0-33fc-4550-99f2-f526ad8208ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664900167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.2664900167
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.93624276
Short name T125
Test name
Test status
Simulation time 163365430 ps
CPU time 3.32 seconds
Started Mar 26 03:06:15 PM PDT 24
Finished Mar 26 03:06:18 PM PDT 24
Peak memory 220448 kb
Host smart-4a41aa82-99b7-49f8-b805-f778969f3b0e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=93624276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_direc
t.93624276
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.4178378565
Short name T715
Test name
Test status
Simulation time 27888533354 ps
CPU time 45.36 seconds
Started Mar 26 03:06:17 PM PDT 24
Finished Mar 26 03:07:03 PM PDT 24
Peak memory 216176 kb
Host smart-98914302-0b0f-43b6-8d8f-2fe6c320d831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178378565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.4178378565
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.1495893914
Short name T901
Test name
Test status
Simulation time 2416543660 ps
CPU time 8.44 seconds
Started Mar 26 03:06:08 PM PDT 24
Finished Mar 26 03:06:18 PM PDT 24
Peak memory 216832 kb
Host smart-d4c1a256-02da-44e1-8216-83b60a489817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495893914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.1495893914
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.644052363
Short name T322
Test name
Test status
Simulation time 78555088 ps
CPU time 1.89 seconds
Started Mar 26 03:06:13 PM PDT 24
Finished Mar 26 03:06:15 PM PDT 24
Peak memory 216708 kb
Host smart-98840e88-14f5-441e-80dc-ac9994150b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644052363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.644052363
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.3956333886
Short name T458
Test name
Test status
Simulation time 83519372 ps
CPU time 0.95 seconds
Started Mar 26 03:06:14 PM PDT 24
Finished Mar 26 03:06:15 PM PDT 24
Peak memory 207204 kb
Host smart-98b1ee66-7fc6-452e-8c6d-19075236132e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956333886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.3956333886
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.9276765
Short name T481
Test name
Test status
Simulation time 438366182 ps
CPU time 8.28 seconds
Started Mar 26 03:06:15 PM PDT 24
Finished Mar 26 03:06:23 PM PDT 24
Peak memory 229088 kb
Host smart-64227516-473d-4666-b290-3f312c9fc178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9276765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.9276765
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.1428160091
Short name T529
Test name
Test status
Simulation time 13179177 ps
CPU time 0.75 seconds
Started Mar 26 03:06:22 PM PDT 24
Finished Mar 26 03:06:23 PM PDT 24
Peak memory 205820 kb
Host smart-27fba0a5-0f3a-43a9-b54b-fca56bfaca10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428160091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
1428160091
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.33245506
Short name T287
Test name
Test status
Simulation time 3171972773 ps
CPU time 6.44 seconds
Started Mar 26 03:06:15 PM PDT 24
Finished Mar 26 03:06:22 PM PDT 24
Peak memory 221532 kb
Host smart-2aa165f4-e7fa-4c68-b8e6-ad36179c0b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33245506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.33245506
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.3935016673
Short name T690
Test name
Test status
Simulation time 54088100 ps
CPU time 0.77 seconds
Started Mar 26 03:06:17 PM PDT 24
Finished Mar 26 03:06:18 PM PDT 24
Peak memory 206272 kb
Host smart-f03d112a-fe4b-4c33-89f7-9ba0142b5c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935016673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.3935016673
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.3778684621
Short name T496
Test name
Test status
Simulation time 198008138846 ps
CPU time 230.74 seconds
Started Mar 26 03:06:16 PM PDT 24
Finished Mar 26 03:10:07 PM PDT 24
Peak memory 257688 kb
Host smart-95fb6e58-239c-489e-ab81-9ad7ad1bd5f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778684621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.3778684621
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.1214496791
Short name T509
Test name
Test status
Simulation time 12906664073 ps
CPU time 101.43 seconds
Started Mar 26 03:06:16 PM PDT 24
Finished Mar 26 03:07:57 PM PDT 24
Peak memory 267988 kb
Host smart-c2223114-c4ff-422e-8160-4b5508ff3a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214496791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.1214496791
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.2931282707
Short name T569
Test name
Test status
Simulation time 13083248995 ps
CPU time 88.77 seconds
Started Mar 26 03:06:18 PM PDT 24
Finished Mar 26 03:07:47 PM PDT 24
Peak memory 255724 kb
Host smart-62c9aa9f-0315-46f3-b712-46168fe7b463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931282707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.2931282707
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.1898182101
Short name T609
Test name
Test status
Simulation time 1587168425 ps
CPU time 6.46 seconds
Started Mar 26 03:06:17 PM PDT 24
Finished Mar 26 03:06:24 PM PDT 24
Peak memory 224920 kb
Host smart-44de436c-3682-41c8-953e-1e94964f8741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898182101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.1898182101
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.1439564685
Short name T210
Test name
Test status
Simulation time 3030880164 ps
CPU time 7.38 seconds
Started Mar 26 03:06:14 PM PDT 24
Finished Mar 26 03:06:22 PM PDT 24
Peak memory 237796 kb
Host smart-33d1001e-4aca-4da9-ac15-716c7240374b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439564685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.1439564685
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.4119527955
Short name T817
Test name
Test status
Simulation time 16860430133 ps
CPU time 18.04 seconds
Started Mar 26 03:06:16 PM PDT 24
Finished Mar 26 03:06:34 PM PDT 24
Peak memory 241364 kb
Host smart-dd6ffb0a-f3b8-4965-9a2e-cad10dd4979c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119527955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.4119527955
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.4275806874
Short name T426
Test name
Test status
Simulation time 197965623 ps
CPU time 3.33 seconds
Started Mar 26 03:06:17 PM PDT 24
Finished Mar 26 03:06:20 PM PDT 24
Peak memory 218864 kb
Host smart-70da0cac-5d90-4467-9934-1867c087f976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275806874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.4275806874
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.1063967493
Short name T841
Test name
Test status
Simulation time 129357802 ps
CPU time 2.52 seconds
Started Mar 26 03:06:17 PM PDT 24
Finished Mar 26 03:06:20 PM PDT 24
Peak memory 219024 kb
Host smart-09aec3bb-a33d-480e-9c95-6f6281ad36d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063967493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.1063967493
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.2030232282
Short name T484
Test name
Test status
Simulation time 428953884 ps
CPU time 3.18 seconds
Started Mar 26 03:06:15 PM PDT 24
Finished Mar 26 03:06:18 PM PDT 24
Peak memory 219208 kb
Host smart-74981255-b7f9-4963-bde7-39350c157510
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2030232282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.2030232282
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.3442272934
Short name T641
Test name
Test status
Simulation time 172591304 ps
CPU time 1.07 seconds
Started Mar 26 03:06:16 PM PDT 24
Finished Mar 26 03:06:17 PM PDT 24
Peak memory 215868 kb
Host smart-502f062d-4381-433c-a921-246f677fd35d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442272934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.3442272934
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.2104837963
Short name T462
Test name
Test status
Simulation time 1542717578 ps
CPU time 8.42 seconds
Started Mar 26 03:06:15 PM PDT 24
Finished Mar 26 03:06:24 PM PDT 24
Peak memory 218816 kb
Host smart-e51d5828-4050-4608-a706-fe3e438acfb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104837963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.2104837963
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.3853493871
Short name T373
Test name
Test status
Simulation time 18295837073 ps
CPU time 20.65 seconds
Started Mar 26 03:06:18 PM PDT 24
Finished Mar 26 03:06:39 PM PDT 24
Peak memory 216808 kb
Host smart-53297d3b-d6c9-459b-8ff0-93d86b7e4409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853493871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.3853493871
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.1023080822
Short name T921
Test name
Test status
Simulation time 54491854 ps
CPU time 1.15 seconds
Started Mar 26 03:06:18 PM PDT 24
Finished Mar 26 03:06:19 PM PDT 24
Peak memory 208180 kb
Host smart-af879824-8387-4087-8552-2121cc543017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023080822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.1023080822
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.2901304895
Short name T737
Test name
Test status
Simulation time 470084892 ps
CPU time 1.1 seconds
Started Mar 26 03:06:15 PM PDT 24
Finished Mar 26 03:06:16 PM PDT 24
Peak memory 207180 kb
Host smart-6bb58cc0-e009-418b-9667-dc574a60240a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901304895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.2901304895
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.1581389723
Short name T774
Test name
Test status
Simulation time 6291176149 ps
CPU time 4.06 seconds
Started Mar 26 03:06:17 PM PDT 24
Finished Mar 26 03:06:21 PM PDT 24
Peak memory 216720 kb
Host smart-3f7f75b0-7311-4233-bf9e-69aea902f6bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581389723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.1581389723
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.1915317250
Short name T314
Test name
Test status
Simulation time 11868780 ps
CPU time 0.72 seconds
Started Mar 26 03:06:26 PM PDT 24
Finished Mar 26 03:06:27 PM PDT 24
Peak memory 205792 kb
Host smart-c0e2ae61-6fc4-4362-924d-2cf129e821f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915317250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
1915317250
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.1383839576
Short name T652
Test name
Test status
Simulation time 202534244 ps
CPU time 3.34 seconds
Started Mar 26 03:06:14 PM PDT 24
Finished Mar 26 03:06:18 PM PDT 24
Peak memory 233876 kb
Host smart-3d5acda5-5987-433d-9891-7b2cdfe77867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383839576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.1383839576
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.59168315
Short name T328
Test name
Test status
Simulation time 73146006 ps
CPU time 0.76 seconds
Started Mar 26 03:06:17 PM PDT 24
Finished Mar 26 03:06:18 PM PDT 24
Peak memory 206976 kb
Host smart-09304367-4d5a-432c-967c-67a24bf286d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59168315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.59168315
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.3280560837
Short name T766
Test name
Test status
Simulation time 21473754203 ps
CPU time 180.5 seconds
Started Mar 26 03:06:27 PM PDT 24
Finished Mar 26 03:09:27 PM PDT 24
Peak memory 249744 kb
Host smart-07ce06e8-f8dd-4cb9-bc90-61ab194ad77c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280560837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.3280560837
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.1162536962
Short name T838
Test name
Test status
Simulation time 148333715039 ps
CPU time 289.15 seconds
Started Mar 26 03:06:28 PM PDT 24
Finished Mar 26 03:11:17 PM PDT 24
Peak memory 252764 kb
Host smart-4f093c5b-995d-4d55-9e16-be8020dea7d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162536962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.1162536962
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_intercept.348792388
Short name T820
Test name
Test status
Simulation time 75606112 ps
CPU time 2.75 seconds
Started Mar 26 03:06:15 PM PDT 24
Finished Mar 26 03:06:18 PM PDT 24
Peak memory 235956 kb
Host smart-d9f7000e-f896-4295-b6b8-b6345d2ecfcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348792388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.348792388
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.2765493041
Short name T871
Test name
Test status
Simulation time 7262668598 ps
CPU time 15.35 seconds
Started Mar 26 03:06:17 PM PDT 24
Finished Mar 26 03:06:32 PM PDT 24
Peak memory 234128 kb
Host smart-96f52d3d-098f-44ee-8725-a8cca91c08aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765493041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.2765493041
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.63833531
Short name T93
Test name
Test status
Simulation time 23249079503 ps
CPU time 18.44 seconds
Started Mar 26 03:06:16 PM PDT 24
Finished Mar 26 03:06:35 PM PDT 24
Peak memory 240276 kb
Host smart-fd50617d-d48b-41a6-b076-ea4f25508f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63833531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap.63833531
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.204286639
Short name T218
Test name
Test status
Simulation time 2110546587 ps
CPU time 15.34 seconds
Started Mar 26 03:06:16 PM PDT 24
Finished Mar 26 03:06:31 PM PDT 24
Peak memory 246764 kb
Host smart-62fb270a-2605-4731-b7dc-1be6356814e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204286639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.204286639
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.3754274709
Short name T376
Test name
Test status
Simulation time 4372819333 ps
CPU time 6.1 seconds
Started Mar 26 03:06:18 PM PDT 24
Finished Mar 26 03:06:24 PM PDT 24
Peak memory 221216 kb
Host smart-2ddc80ad-2ac4-4da4-bc6e-dc100384c90a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3754274709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.3754274709
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.1666202822
Short name T453
Test name
Test status
Simulation time 2176553609 ps
CPU time 19.1 seconds
Started Mar 26 03:06:17 PM PDT 24
Finished Mar 26 03:06:36 PM PDT 24
Peak memory 216000 kb
Host smart-34038965-b123-4277-a941-5973b6bd857c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666202822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.1666202822
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.224215731
Short name T739
Test name
Test status
Simulation time 10354704392 ps
CPU time 10.53 seconds
Started Mar 26 03:06:14 PM PDT 24
Finished Mar 26 03:06:25 PM PDT 24
Peak memory 216752 kb
Host smart-2ce8399f-4993-4050-a730-d66f361a0526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224215731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.224215731
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.2021587377
Short name T379
Test name
Test status
Simulation time 204766901 ps
CPU time 1.73 seconds
Started Mar 26 03:06:19 PM PDT 24
Finished Mar 26 03:06:20 PM PDT 24
Peak memory 216656 kb
Host smart-0ce95d93-a249-4862-9a3f-639b06b8ebb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021587377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.2021587377
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.3890989563
Short name T365
Test name
Test status
Simulation time 461407797 ps
CPU time 1.26 seconds
Started Mar 26 03:06:17 PM PDT 24
Finished Mar 26 03:06:18 PM PDT 24
Peak memory 207128 kb
Host smart-5f27a633-f029-48f9-8654-b7bcf8141d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890989563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.3890989563
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.2978642123
Short name T305
Test name
Test status
Simulation time 502244672 ps
CPU time 2.96 seconds
Started Mar 26 03:06:19 PM PDT 24
Finished Mar 26 03:06:22 PM PDT 24
Peak memory 224852 kb
Host smart-b927e0ec-5165-41fa-855a-786201607e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978642123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.2978642123
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.3958180409
Short name T579
Test name
Test status
Simulation time 21559379 ps
CPU time 0.71 seconds
Started Mar 26 03:06:28 PM PDT 24
Finished Mar 26 03:06:28 PM PDT 24
Peak memory 205220 kb
Host smart-b00a5bd0-bc2a-41a9-a14d-f5d8274cbc18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958180409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
3958180409
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.2706390368
Short name T582
Test name
Test status
Simulation time 769079100 ps
CPU time 5.2 seconds
Started Mar 26 03:06:29 PM PDT 24
Finished Mar 26 03:06:34 PM PDT 24
Peak memory 234932 kb
Host smart-11bd5bf8-1bb9-450a-9df5-ee38b40d447f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706390368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.2706390368
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.4115481158
Short name T311
Test name
Test status
Simulation time 30331978 ps
CPU time 0.78 seconds
Started Mar 26 03:06:28 PM PDT 24
Finished Mar 26 03:06:29 PM PDT 24
Peak memory 205976 kb
Host smart-52e1007a-f40c-4728-bb68-cb54a28ebb3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115481158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.4115481158
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.1249192926
Short name T691
Test name
Test status
Simulation time 23119353068 ps
CPU time 108.13 seconds
Started Mar 26 03:06:29 PM PDT 24
Finished Mar 26 03:08:17 PM PDT 24
Peak memory 237972 kb
Host smart-ec0b628c-1e9d-4f58-92ce-66d9960ca27e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249192926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.1249192926
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.2933533670
Short name T37
Test name
Test status
Simulation time 70065944148 ps
CPU time 216.63 seconds
Started Mar 26 03:06:27 PM PDT 24
Finished Mar 26 03:10:04 PM PDT 24
Peak memory 266096 kb
Host smart-43f0db2d-68d9-4e9d-aa22-aacc72b1f4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933533670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.2933533670
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.3238161503
Short name T157
Test name
Test status
Simulation time 10869320713 ps
CPU time 70.64 seconds
Started Mar 26 03:06:27 PM PDT 24
Finished Mar 26 03:07:38 PM PDT 24
Peak memory 255256 kb
Host smart-baabd632-5ec2-4485-85ec-c580d9a82de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238161503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.3238161503
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.1707354719
Short name T408
Test name
Test status
Simulation time 3449532432 ps
CPU time 10.96 seconds
Started Mar 26 03:06:28 PM PDT 24
Finished Mar 26 03:06:39 PM PDT 24
Peak memory 224972 kb
Host smart-72c2b1cf-edad-4950-972d-1f2a66df6a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707354719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.1707354719
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.2785262524
Short name T628
Test name
Test status
Simulation time 993985868 ps
CPU time 3.45 seconds
Started Mar 26 03:06:29 PM PDT 24
Finished Mar 26 03:06:32 PM PDT 24
Peak memory 233956 kb
Host smart-b5b1ca7c-f13a-4d38-a3d8-6dd06d762d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785262524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.2785262524
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2634192378
Short name T385
Test name
Test status
Simulation time 1307377717 ps
CPU time 9.9 seconds
Started Mar 26 03:06:30 PM PDT 24
Finished Mar 26 03:06:39 PM PDT 24
Peak memory 250264 kb
Host smart-42b6ecbf-eda3-4fec-b313-cfe9210dbee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634192378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2634192378
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.1426244402
Short name T171
Test name
Test status
Simulation time 19322488554 ps
CPU time 29.59 seconds
Started Mar 26 03:06:28 PM PDT 24
Finished Mar 26 03:06:58 PM PDT 24
Peak memory 234324 kb
Host smart-72d90c68-2e97-40e6-b75e-b17f600fd5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426244402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.1426244402
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.4098496416
Short name T73
Test name
Test status
Simulation time 4695553512 ps
CPU time 12.03 seconds
Started Mar 26 03:06:29 PM PDT 24
Finished Mar 26 03:06:42 PM PDT 24
Peak memory 241388 kb
Host smart-df12237b-c7e7-446d-8c10-f0fc3d38dd35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098496416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.4098496416
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.1044186355
Short name T478
Test name
Test status
Simulation time 335762485 ps
CPU time 3.24 seconds
Started Mar 26 03:06:29 PM PDT 24
Finished Mar 26 03:06:32 PM PDT 24
Peak memory 220972 kb
Host smart-848db2b2-1f31-43ce-8f1c-8225271b2b2f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1044186355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.1044186355
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.1240036156
Short name T941
Test name
Test status
Simulation time 520907800229 ps
CPU time 624.37 seconds
Started Mar 26 03:06:29 PM PDT 24
Finished Mar 26 03:16:53 PM PDT 24
Peak memory 265308 kb
Host smart-45561b0f-0a5e-495a-ba1e-05950dea8dae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240036156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.1240036156
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.2644403623
Short name T493
Test name
Test status
Simulation time 11540410536 ps
CPU time 33.88 seconds
Started Mar 26 03:06:29 PM PDT 24
Finished Mar 26 03:07:03 PM PDT 24
Peak memory 216880 kb
Host smart-4aea241f-fae8-48a7-88a0-80cf9d45dd69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644403623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.2644403623
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.396366115
Short name T765
Test name
Test status
Simulation time 3261972395 ps
CPU time 12.25 seconds
Started Mar 26 03:06:29 PM PDT 24
Finished Mar 26 03:06:41 PM PDT 24
Peak memory 216832 kb
Host smart-2241be70-70a5-4345-8cd1-14f851893953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396366115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.396366115
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.1709420386
Short name T963
Test name
Test status
Simulation time 99771322 ps
CPU time 1.91 seconds
Started Mar 26 03:06:28 PM PDT 24
Finished Mar 26 03:06:30 PM PDT 24
Peak memory 216604 kb
Host smart-4cd7025e-d4fe-4c6a-92ab-af2bc817a4da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709420386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.1709420386
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.3449358447
Short name T705
Test name
Test status
Simulation time 417827800 ps
CPU time 0.9 seconds
Started Mar 26 03:06:27 PM PDT 24
Finished Mar 26 03:06:28 PM PDT 24
Peak memory 207140 kb
Host smart-1bd966b7-2809-4d18-956c-dc6c2c49ef8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449358447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.3449358447
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.3888054634
Short name T383
Test name
Test status
Simulation time 1453672005 ps
CPU time 2.88 seconds
Started Mar 26 03:06:26 PM PDT 24
Finished Mar 26 03:06:29 PM PDT 24
Peak memory 219284 kb
Host smart-2c9ebf02-be47-4316-84cf-40e9a128f068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888054634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.3888054634
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.4264480093
Short name T651
Test name
Test status
Simulation time 29369095 ps
CPU time 0.71 seconds
Started Mar 26 03:06:29 PM PDT 24
Finished Mar 26 03:06:29 PM PDT 24
Peak memory 206148 kb
Host smart-89072e2f-2004-463e-b620-02c2150855e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264480093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
4264480093
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.3751732296
Short name T673
Test name
Test status
Simulation time 1714152573 ps
CPU time 7.53 seconds
Started Mar 26 03:06:28 PM PDT 24
Finished Mar 26 03:06:35 PM PDT 24
Peak memory 224860 kb
Host smart-5478290b-7df7-4e98-8710-9f1c1701e0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751732296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.3751732296
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.2177354841
Short name T511
Test name
Test status
Simulation time 15936876 ps
CPU time 0.81 seconds
Started Mar 26 03:06:31 PM PDT 24
Finished Mar 26 03:06:32 PM PDT 24
Peak memory 206900 kb
Host smart-8cf8997f-aac0-4ee5-98b4-9d193f1491e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177354841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.2177354841
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.3934754595
Short name T831
Test name
Test status
Simulation time 58952428102 ps
CPU time 169.67 seconds
Started Mar 26 03:06:30 PM PDT 24
Finished Mar 26 03:09:20 PM PDT 24
Peak memory 252464 kb
Host smart-7c3c4921-3ff8-4813-b0ad-904a11fb8332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934754595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.3934754595
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.2856161108
Short name T587
Test name
Test status
Simulation time 17710956298 ps
CPU time 124.72 seconds
Started Mar 26 03:06:28 PM PDT 24
Finished Mar 26 03:08:33 PM PDT 24
Peak memory 256200 kb
Host smart-f7c96588-c658-4fc9-9e1d-838bbed24fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856161108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.2856161108
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.2181475892
Short name T857
Test name
Test status
Simulation time 35162241598 ps
CPU time 262.36 seconds
Started Mar 26 03:06:28 PM PDT 24
Finished Mar 26 03:10:51 PM PDT 24
Peak memory 259184 kb
Host smart-68897506-19cc-4e84-a8a1-69a974781c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181475892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.2181475892
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.1441467435
Short name T485
Test name
Test status
Simulation time 719496924 ps
CPU time 17.88 seconds
Started Mar 26 03:06:27 PM PDT 24
Finished Mar 26 03:06:45 PM PDT 24
Peak memory 240908 kb
Host smart-6868d55b-e791-4cf6-920c-c8f1614903b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441467435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.1441467435
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.3329823964
Short name T647
Test name
Test status
Simulation time 768140896 ps
CPU time 3.21 seconds
Started Mar 26 03:06:28 PM PDT 24
Finished Mar 26 03:06:31 PM PDT 24
Peak memory 234108 kb
Host smart-51b42fa8-1d37-457b-8c83-763dc775be3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329823964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.3329823964
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.1819434597
Short name T230
Test name
Test status
Simulation time 12147905379 ps
CPU time 10.51 seconds
Started Mar 26 03:06:27 PM PDT 24
Finished Mar 26 03:06:37 PM PDT 24
Peak memory 224844 kb
Host smart-132b264c-c0bc-46ff-adc6-f5e7fc33512e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819434597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.1819434597
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.1597019669
Short name T186
Test name
Test status
Simulation time 343362261 ps
CPU time 4.98 seconds
Started Mar 26 03:06:26 PM PDT 24
Finished Mar 26 03:06:32 PM PDT 24
Peak memory 219416 kb
Host smart-97800038-75da-4c6c-ac37-cf7eed5145c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597019669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.1597019669
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.2346752410
Short name T180
Test name
Test status
Simulation time 14716297131 ps
CPU time 32.33 seconds
Started Mar 26 03:06:27 PM PDT 24
Finished Mar 26 03:06:59 PM PDT 24
Peak memory 241060 kb
Host smart-919a1668-1a91-4893-96d2-f32df381c9b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346752410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.2346752410
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.2698102442
Short name T708
Test name
Test status
Simulation time 2322297502 ps
CPU time 5.48 seconds
Started Mar 26 03:06:30 PM PDT 24
Finished Mar 26 03:06:36 PM PDT 24
Peak memory 219632 kb
Host smart-6201d022-e42a-4511-a789-68e4970f643d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2698102442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.2698102442
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.4050993014
Short name T232
Test name
Test status
Simulation time 41983506999 ps
CPU time 80.51 seconds
Started Mar 26 03:06:27 PM PDT 24
Finished Mar 26 03:07:48 PM PDT 24
Peak memory 233572 kb
Host smart-7ef489d3-a265-4cf4-859a-cc5c8d949f97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050993014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.4050993014
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.593692320
Short name T642
Test name
Test status
Simulation time 511001923 ps
CPU time 4.19 seconds
Started Mar 26 03:06:30 PM PDT 24
Finished Mar 26 03:06:34 PM PDT 24
Peak memory 216688 kb
Host smart-1ab1f545-f0a3-404c-92d3-c36d68811e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593692320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.593692320
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.2351604427
Short name T501
Test name
Test status
Simulation time 5899143195 ps
CPU time 6.41 seconds
Started Mar 26 03:06:28 PM PDT 24
Finished Mar 26 03:06:34 PM PDT 24
Peak memory 216688 kb
Host smart-51fd5c24-fc8f-4128-a879-0bce73a49d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351604427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.2351604427
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.3759918643
Short name T668
Test name
Test status
Simulation time 54636160 ps
CPU time 0.99 seconds
Started Mar 26 03:06:28 PM PDT 24
Finished Mar 26 03:06:29 PM PDT 24
Peak memory 208236 kb
Host smart-97061d47-6ed1-49c0-ba00-4c8783cc4509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759918643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.3759918643
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.1962779523
Short name T594
Test name
Test status
Simulation time 18451404 ps
CPU time 0.75 seconds
Started Mar 26 03:06:26 PM PDT 24
Finished Mar 26 03:06:26 PM PDT 24
Peak memory 206188 kb
Host smart-440e5814-ce0a-4d1f-abc7-69fd99796972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962779523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.1962779523
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.3124751758
Short name T10
Test name
Test status
Simulation time 6742450003 ps
CPU time 10.67 seconds
Started Mar 26 03:06:27 PM PDT 24
Finished Mar 26 03:06:38 PM PDT 24
Peak memory 228364 kb
Host smart-97272ec9-f6d8-4cf8-8b17-ca9e30d4cd7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124751758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.3124751758
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.3280464195
Short name T813
Test name
Test status
Simulation time 12071206 ps
CPU time 0.73 seconds
Started Mar 26 03:06:29 PM PDT 24
Finished Mar 26 03:06:30 PM PDT 24
Peak memory 205808 kb
Host smart-a14d4bc6-a42b-4c65-80f7-3749e5a3e4c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280464195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
3280464195
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.3983748096
Short name T471
Test name
Test status
Simulation time 4244262642 ps
CPU time 5.68 seconds
Started Mar 26 03:06:28 PM PDT 24
Finished Mar 26 03:06:34 PM PDT 24
Peak memory 220068 kb
Host smart-f10e3a35-68f9-4bf8-8fbb-c9e14c2406a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983748096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.3983748096
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.2329165943
Short name T149
Test name
Test status
Simulation time 66567944 ps
CPU time 0.82 seconds
Started Mar 26 03:06:28 PM PDT 24
Finished Mar 26 03:06:29 PM PDT 24
Peak memory 206996 kb
Host smart-2ad17ae5-f742-40ed-92c2-9dc3182abf87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329165943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.2329165943
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.3247842193
Short name T33
Test name
Test status
Simulation time 59846731765 ps
CPU time 299.12 seconds
Started Mar 26 03:06:31 PM PDT 24
Finished Mar 26 03:11:30 PM PDT 24
Peak memory 257536 kb
Host smart-d1417159-2186-41a7-a8cc-0e43abd6cbf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247842193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.3247842193
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.1958939096
Short name T222
Test name
Test status
Simulation time 251701935707 ps
CPU time 429.41 seconds
Started Mar 26 03:06:31 PM PDT 24
Finished Mar 26 03:13:40 PM PDT 24
Peak memory 264516 kb
Host smart-6b16d8f3-3852-44ae-8b4a-bc5a5f508994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958939096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.1958939096
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.2489488820
Short name T226
Test name
Test status
Simulation time 5331402091 ps
CPU time 67.8 seconds
Started Mar 26 03:06:28 PM PDT 24
Finished Mar 26 03:07:36 PM PDT 24
Peak memory 256464 kb
Host smart-77e291bf-2d74-4651-8090-cba2285500c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489488820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.2489488820
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.3324010737
Short name T773
Test name
Test status
Simulation time 13277537951 ps
CPU time 41.18 seconds
Started Mar 26 03:06:29 PM PDT 24
Finished Mar 26 03:07:11 PM PDT 24
Peak memory 250360 kb
Host smart-9affbddb-8f8f-459d-b8eb-16e4acc52cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324010737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.3324010737
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.3427218491
Short name T486
Test name
Test status
Simulation time 949449514 ps
CPU time 5.32 seconds
Started Mar 26 03:06:28 PM PDT 24
Finished Mar 26 03:06:34 PM PDT 24
Peak memory 220184 kb
Host smart-86097105-1400-4286-a5d4-45d7f2027f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427218491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.3427218491
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.478018996
Short name T966
Test name
Test status
Simulation time 16036733895 ps
CPU time 39.47 seconds
Started Mar 26 03:06:28 PM PDT 24
Finished Mar 26 03:07:08 PM PDT 24
Peak memory 238532 kb
Host smart-49435fd2-d8c9-4172-ba7b-234efcd4dc44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478018996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.478018996
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.152922319
Short name T191
Test name
Test status
Simulation time 23663077366 ps
CPU time 21.74 seconds
Started Mar 26 03:06:28 PM PDT 24
Finished Mar 26 03:06:49 PM PDT 24
Peak memory 233432 kb
Host smart-9e90a4cc-1320-450e-9ba3-f9274aee9309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152922319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap
.152922319
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.1074372880
Short name T926
Test name
Test status
Simulation time 68096833823 ps
CPU time 15.95 seconds
Started Mar 26 03:06:29 PM PDT 24
Finished Mar 26 03:06:45 PM PDT 24
Peak memory 219100 kb
Host smart-c52bd783-a5a7-49c0-bf90-99a5925923c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074372880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.1074372880
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.3786693591
Short name T769
Test name
Test status
Simulation time 1743525067 ps
CPU time 7.9 seconds
Started Mar 26 03:06:28 PM PDT 24
Finished Mar 26 03:06:36 PM PDT 24
Peak memory 222856 kb
Host smart-2b40980b-9c57-461e-87f4-f1e89306a907
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3786693591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.3786693591
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.2669620558
Short name T140
Test name
Test status
Simulation time 25971011773 ps
CPU time 149.63 seconds
Started Mar 26 03:06:28 PM PDT 24
Finished Mar 26 03:08:57 PM PDT 24
Peak memory 273412 kb
Host smart-5b84b092-4900-4e7b-8b24-e4a83bb85013
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669620558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.2669620558
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.2965262244
Short name T856
Test name
Test status
Simulation time 25398215184 ps
CPU time 32.81 seconds
Started Mar 26 03:06:28 PM PDT 24
Finished Mar 26 03:07:01 PM PDT 24
Peak memory 216836 kb
Host smart-a387776b-ec0e-4321-9556-b1241772fce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965262244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.2965262244
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.471185097
Short name T81
Test name
Test status
Simulation time 77934548233 ps
CPU time 23.14 seconds
Started Mar 26 03:06:28 PM PDT 24
Finished Mar 26 03:06:52 PM PDT 24
Peak memory 216220 kb
Host smart-6b46bd2d-4dfa-4a9b-bba2-c66718512f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471185097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.471185097
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.1918961892
Short name T536
Test name
Test status
Simulation time 138732877 ps
CPU time 1.3 seconds
Started Mar 26 03:06:30 PM PDT 24
Finished Mar 26 03:06:32 PM PDT 24
Peak memory 208140 kb
Host smart-12c88b6b-e14d-4f97-9aeb-aec387fd292b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918961892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.1918961892
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.223877428
Short name T908
Test name
Test status
Simulation time 207838120 ps
CPU time 0.98 seconds
Started Mar 26 03:06:30 PM PDT 24
Finished Mar 26 03:06:31 PM PDT 24
Peak memory 207180 kb
Host smart-bcdd83cb-57f6-472b-b4f5-ee34c5723ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223877428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.223877428
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.1945363249
Short name T454
Test name
Test status
Simulation time 41451644699 ps
CPU time 31.93 seconds
Started Mar 26 03:06:27 PM PDT 24
Finished Mar 26 03:06:59 PM PDT 24
Peak memory 237208 kb
Host smart-6e072584-54db-41d9-bcbb-b97b45fdda51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945363249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.1945363249
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.1768844581
Short name T718
Test name
Test status
Simulation time 27616192 ps
CPU time 0.74 seconds
Started Mar 26 03:04:46 PM PDT 24
Finished Mar 26 03:04:47 PM PDT 24
Peak memory 205164 kb
Host smart-edf2718c-df71-49fb-95ad-eabe656b018e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768844581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.1
768844581
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.3332700502
Short name T205
Test name
Test status
Simulation time 3005876728 ps
CPU time 11.58 seconds
Started Mar 26 03:04:46 PM PDT 24
Finished Mar 26 03:04:58 PM PDT 24
Peak memory 234048 kb
Host smart-b43e68c0-b34e-4459-bea9-2b8156dd2b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332700502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.3332700502
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.3470263310
Short name T803
Test name
Test status
Simulation time 28500052 ps
CPU time 0.75 seconds
Started Mar 26 03:04:43 PM PDT 24
Finished Mar 26 03:04:43 PM PDT 24
Peak memory 205936 kb
Host smart-de2b5f9b-4d84-41b3-95ac-62f0090c4a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470263310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.3470263310
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.1620169217
Short name T236
Test name
Test status
Simulation time 325493042611 ps
CPU time 369.44 seconds
Started Mar 26 03:04:48 PM PDT 24
Finished Mar 26 03:10:57 PM PDT 24
Peak memory 265728 kb
Host smart-5c28243b-ca7e-4b08-b360-2f7ffa69fc26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620169217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.1620169217
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.1401216770
Short name T264
Test name
Test status
Simulation time 367050551061 ps
CPU time 664.48 seconds
Started Mar 26 03:04:47 PM PDT 24
Finished Mar 26 03:15:52 PM PDT 24
Peak memory 274188 kb
Host smart-55c55b37-080c-43ad-b4e7-3e0a73dd0b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401216770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.1401216770
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.2204703961
Short name T424
Test name
Test status
Simulation time 162579757046 ps
CPU time 300.39 seconds
Started Mar 26 03:04:46 PM PDT 24
Finished Mar 26 03:09:47 PM PDT 24
Peak memory 257792 kb
Host smart-9453f12d-4eba-4d4c-bd2a-27d9b625ce0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204703961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.2204703961
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.1690240663
Short name T909
Test name
Test status
Simulation time 24832146739 ps
CPU time 36.21 seconds
Started Mar 26 03:04:48 PM PDT 24
Finished Mar 26 03:05:24 PM PDT 24
Peak memory 240476 kb
Host smart-28ccb970-0f59-4e7d-bae2-48ed7b3c0751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690240663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.1690240663
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.3207107738
Short name T459
Test name
Test status
Simulation time 322245017 ps
CPU time 3.8 seconds
Started Mar 26 03:04:46 PM PDT 24
Finished Mar 26 03:04:50 PM PDT 24
Peak memory 233824 kb
Host smart-406ef7e1-911e-4327-a0db-de4ad9bf4a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207107738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.3207107738
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.1985362094
Short name T525
Test name
Test status
Simulation time 32832777956 ps
CPU time 49.9 seconds
Started Mar 26 03:04:43 PM PDT 24
Finished Mar 26 03:05:33 PM PDT 24
Peak memory 239668 kb
Host smart-ddc9bd05-ec51-4b88-91d5-0d1c45296b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985362094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.1985362094
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.845340928
Short name T875
Test name
Test status
Simulation time 30287421619 ps
CPU time 12.36 seconds
Started Mar 26 03:04:46 PM PDT 24
Finished Mar 26 03:04:58 PM PDT 24
Peak memory 218256 kb
Host smart-7dde96ec-009d-4efc-92ab-fedbff635907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845340928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.
845340928
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.2545133720
Short name T952
Test name
Test status
Simulation time 12666205813 ps
CPU time 26.26 seconds
Started Mar 26 03:04:48 PM PDT 24
Finished Mar 26 03:05:14 PM PDT 24
Peak memory 237276 kb
Host smart-d8d520f0-7042-43d7-ba28-3db7382115c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545133720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.2545133720
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_ram_cfg.3999608935
Short name T884
Test name
Test status
Simulation time 16046760 ps
CPU time 0.81 seconds
Started Mar 26 03:04:42 PM PDT 24
Finished Mar 26 03:04:43 PM PDT 24
Peak memory 216556 kb
Host smart-0e6218d4-d0a8-4c62-b07e-9f1d41c4800a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999608935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_ram_cfg.3999608935
Directory /workspace/3.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.4100896398
Short name T930
Test name
Test status
Simulation time 626716234 ps
CPU time 4.71 seconds
Started Mar 26 03:04:48 PM PDT 24
Finished Mar 26 03:04:53 PM PDT 24
Peak memory 222172 kb
Host smart-38fdf26e-7fd3-4f8e-bc8f-6072b6c79cc4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4100896398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.4100896398
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.4134914776
Short name T67
Test name
Test status
Simulation time 113701158 ps
CPU time 1.18 seconds
Started Mar 26 03:04:47 PM PDT 24
Finished Mar 26 03:04:48 PM PDT 24
Peak memory 235460 kb
Host smart-83a396e5-5db6-4a65-9de7-914217980739
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134914776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.4134914776
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.1960481030
Short name T252
Test name
Test status
Simulation time 43182141785 ps
CPU time 325.3 seconds
Started Mar 26 03:04:48 PM PDT 24
Finished Mar 26 03:10:14 PM PDT 24
Peak memory 273552 kb
Host smart-1e4c73e6-922d-411b-861c-99614190359e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960481030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.1960481030
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.1474423370
Short name T16
Test name
Test status
Simulation time 36448214408 ps
CPU time 67.82 seconds
Started Mar 26 03:04:43 PM PDT 24
Finished Mar 26 03:05:51 PM PDT 24
Peak memory 216772 kb
Host smart-8855d8c5-4217-4fce-bba1-dfc0a5b61836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474423370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.1474423370
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.2736836824
Short name T541
Test name
Test status
Simulation time 2353430530 ps
CPU time 12.46 seconds
Started Mar 26 03:04:47 PM PDT 24
Finished Mar 26 03:04:59 PM PDT 24
Peak memory 216748 kb
Host smart-61e049fe-0927-49c4-9344-38c26198b5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736836824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.2736836824
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.4035240275
Short name T571
Test name
Test status
Simulation time 137846313 ps
CPU time 1.45 seconds
Started Mar 26 03:04:46 PM PDT 24
Finished Mar 26 03:04:47 PM PDT 24
Peak memory 216572 kb
Host smart-07f05c62-e497-4a1b-9d37-cf3a7ec2831f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035240275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.4035240275
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.1885593000
Short name T948
Test name
Test status
Simulation time 282718868 ps
CPU time 1 seconds
Started Mar 26 03:04:44 PM PDT 24
Finished Mar 26 03:04:46 PM PDT 24
Peak memory 206248 kb
Host smart-39488e42-5d1b-4c36-b5a0-4abee536473f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885593000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.1885593000
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.902669025
Short name T206
Test name
Test status
Simulation time 14777590797 ps
CPU time 15.64 seconds
Started Mar 26 03:04:46 PM PDT 24
Finished Mar 26 03:05:02 PM PDT 24
Peak memory 237248 kb
Host smart-21686447-c422-4ce6-9a53-6019d46ca3ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902669025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.902669025
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.3469533004
Short name T823
Test name
Test status
Simulation time 31808402 ps
CPU time 0.76 seconds
Started Mar 26 03:06:41 PM PDT 24
Finished Mar 26 03:06:42 PM PDT 24
Peak memory 205904 kb
Host smart-55bcd472-2ec3-4a78-9c4c-477ad47bea4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469533004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
3469533004
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.1904220002
Short name T534
Test name
Test status
Simulation time 338310441 ps
CPU time 2.69 seconds
Started Mar 26 03:06:27 PM PDT 24
Finished Mar 26 03:06:30 PM PDT 24
Peak memory 219040 kb
Host smart-3f5dc724-6f85-4293-9c23-501b6ae0078b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904220002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.1904220002
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.1982672265
Short name T337
Test name
Test status
Simulation time 36241013 ps
CPU time 0.79 seconds
Started Mar 26 03:06:30 PM PDT 24
Finished Mar 26 03:06:32 PM PDT 24
Peak memory 206300 kb
Host smart-df0d4ffc-246b-443a-ba72-9bea7cf216b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982672265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.1982672265
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.2817444178
Short name T393
Test name
Test status
Simulation time 178844528109 ps
CPU time 285.93 seconds
Started Mar 26 03:06:40 PM PDT 24
Finished Mar 26 03:11:27 PM PDT 24
Peak memory 266712 kb
Host smart-3e8ec51f-f252-47e1-a55e-65e983e7a830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817444178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.2817444178
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.3196884758
Short name T247
Test name
Test status
Simulation time 84414388186 ps
CPU time 305.87 seconds
Started Mar 26 03:06:38 PM PDT 24
Finished Mar 26 03:11:46 PM PDT 24
Peak memory 274004 kb
Host smart-2429aabb-839e-4277-97c5-51083d189b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196884758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.3196884758
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.2012076498
Short name T271
Test name
Test status
Simulation time 2738411065 ps
CPU time 13.15 seconds
Started Mar 26 03:06:38 PM PDT 24
Finished Mar 26 03:06:53 PM PDT 24
Peak memory 257216 kb
Host smart-35731082-f761-4d1e-bd89-9c568a123ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012076498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.2012076498
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.3258484621
Short name T877
Test name
Test status
Simulation time 171840678 ps
CPU time 4.41 seconds
Started Mar 26 03:06:33 PM PDT 24
Finished Mar 26 03:06:38 PM PDT 24
Peak memory 234164 kb
Host smart-2fa19a93-9df4-40fd-a02b-9ec9fc5cd9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258484621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.3258484621
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.2126504201
Short name T819
Test name
Test status
Simulation time 35523135304 ps
CPU time 26.8 seconds
Started Mar 26 03:06:28 PM PDT 24
Finished Mar 26 03:06:55 PM PDT 24
Peak memory 235628 kb
Host smart-732636d4-2e96-41e7-b76d-df576682a40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126504201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.2126504201
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.2655498544
Short name T627
Test name
Test status
Simulation time 399056483 ps
CPU time 5.66 seconds
Started Mar 26 03:06:30 PM PDT 24
Finished Mar 26 03:06:35 PM PDT 24
Peak memory 234204 kb
Host smart-b452c19e-cf21-4a64-94b3-5f6c591887bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655498544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.2655498544
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.1374687013
Short name T923
Test name
Test status
Simulation time 1023381330 ps
CPU time 6.39 seconds
Started Mar 26 03:06:30 PM PDT 24
Finished Mar 26 03:06:37 PM PDT 24
Peak memory 233832 kb
Host smart-b17cad8e-6001-42de-8fb3-b77a0de5ff47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374687013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.1374687013
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.1933186930
Short name T971
Test name
Test status
Simulation time 5582003153 ps
CPU time 6.7 seconds
Started Mar 26 03:06:39 PM PDT 24
Finished Mar 26 03:06:47 PM PDT 24
Peak memory 220516 kb
Host smart-02ad987f-ae14-42c1-89c2-07218be0c3a2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1933186930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.1933186930
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.1834026921
Short name T141
Test name
Test status
Simulation time 6316820482 ps
CPU time 71.03 seconds
Started Mar 26 03:06:36 PM PDT 24
Finished Mar 26 03:07:48 PM PDT 24
Peak memory 241412 kb
Host smart-127b8296-126e-4880-a108-1df0934e85ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834026921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.1834026921
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.362616669
Short name T679
Test name
Test status
Simulation time 3613740101 ps
CPU time 35.81 seconds
Started Mar 26 03:06:32 PM PDT 24
Finished Mar 26 03:07:08 PM PDT 24
Peak memory 216844 kb
Host smart-d6568444-8d31-4b88-9ab4-2ecbfa5ea4ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362616669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.362616669
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.3960044228
Short name T435
Test name
Test status
Simulation time 5536765666 ps
CPU time 5.4 seconds
Started Mar 26 03:06:30 PM PDT 24
Finished Mar 26 03:06:36 PM PDT 24
Peak memory 216672 kb
Host smart-8eeb9304-7be1-4277-ac00-f346f6ac952d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960044228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.3960044228
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.3266292780
Short name T724
Test name
Test status
Simulation time 282907181 ps
CPU time 8.55 seconds
Started Mar 26 03:06:32 PM PDT 24
Finished Mar 26 03:06:40 PM PDT 24
Peak memory 216724 kb
Host smart-489b1ce4-acd4-4cfd-babd-0029b2d27846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266292780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.3266292780
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.4093291745
Short name T874
Test name
Test status
Simulation time 122023486 ps
CPU time 1.07 seconds
Started Mar 26 03:06:29 PM PDT 24
Finished Mar 26 03:06:30 PM PDT 24
Peak memory 207120 kb
Host smart-605c544a-ed4d-4eea-bf99-6f6b7e2397a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093291745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.4093291745
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.2957369517
Short name T414
Test name
Test status
Simulation time 10963253930 ps
CPU time 14.76 seconds
Started Mar 26 03:06:30 PM PDT 24
Finished Mar 26 03:06:45 PM PDT 24
Peak memory 234380 kb
Host smart-aaac44e9-49b5-4110-9a7e-10538fb9d351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957369517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.2957369517
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.2865167181
Short name T297
Test name
Test status
Simulation time 41820870 ps
CPU time 0.73 seconds
Started Mar 26 03:06:39 PM PDT 24
Finished Mar 26 03:06:41 PM PDT 24
Peak memory 205808 kb
Host smart-ce2038ca-92f2-4637-b464-dd9fcaf835a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865167181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
2865167181
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.3971969324
Short name T401
Test name
Test status
Simulation time 2067250463 ps
CPU time 5.25 seconds
Started Mar 26 03:06:40 PM PDT 24
Finished Mar 26 03:06:47 PM PDT 24
Peak memory 220024 kb
Host smart-7bbc9438-f358-4b29-83e0-bc1ac0387c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971969324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.3971969324
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.1179342580
Short name T476
Test name
Test status
Simulation time 21828046 ps
CPU time 0.78 seconds
Started Mar 26 03:06:37 PM PDT 24
Finished Mar 26 03:06:38 PM PDT 24
Peak memory 206012 kb
Host smart-d256ef08-ddec-455c-87cf-f204eebbfd89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179342580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.1179342580
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.2255356452
Short name T219
Test name
Test status
Simulation time 21858805637 ps
CPU time 99.94 seconds
Started Mar 26 03:06:41 PM PDT 24
Finished Mar 26 03:08:21 PM PDT 24
Peak memory 236204 kb
Host smart-87b2c05c-3559-4f9f-ba51-5749ff798e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255356452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.2255356452
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.4163230781
Short name T254
Test name
Test status
Simulation time 20910506601 ps
CPU time 179 seconds
Started Mar 26 03:06:40 PM PDT 24
Finished Mar 26 03:09:39 PM PDT 24
Peak memory 257768 kb
Host smart-c040f0a8-729f-41f9-9bdf-08c5ef53a9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163230781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.4163230781
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.3950191891
Short name T291
Test name
Test status
Simulation time 1456646937 ps
CPU time 11.76 seconds
Started Mar 26 03:06:42 PM PDT 24
Finished Mar 26 03:06:53 PM PDT 24
Peak memory 233152 kb
Host smart-a27feab6-6274-48e3-af87-f76a67e988d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950191891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.3950191891
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.3113247463
Short name T450
Test name
Test status
Simulation time 5413431602 ps
CPU time 21.99 seconds
Started Mar 26 03:06:38 PM PDT 24
Finished Mar 26 03:07:02 PM PDT 24
Peak memory 249228 kb
Host smart-d9a0550a-d60d-4448-a82f-2e655529d483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113247463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.3113247463
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.1683887171
Short name T935
Test name
Test status
Simulation time 2394920882 ps
CPU time 5.12 seconds
Started Mar 26 03:06:38 PM PDT 24
Finished Mar 26 03:06:45 PM PDT 24
Peak memory 218812 kb
Host smart-c85ce4ad-9456-48b1-9b17-589f8c307da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683887171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.1683887171
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.3166526960
Short name T580
Test name
Test status
Simulation time 4072044544 ps
CPU time 10.98 seconds
Started Mar 26 03:06:37 PM PDT 24
Finished Mar 26 03:06:51 PM PDT 24
Peak memory 217232 kb
Host smart-ae7ac23a-43db-494c-9d9d-386210bf80a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166526960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.3166526960
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.3927352703
Short name T158
Test name
Test status
Simulation time 2891710605 ps
CPU time 8.87 seconds
Started Mar 26 03:06:42 PM PDT 24
Finished Mar 26 03:06:51 PM PDT 24
Peak memory 224892 kb
Host smart-52d1d182-d02e-4eae-bc6a-48ecc346cc62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927352703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.3927352703
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.2458938132
Short name T776
Test name
Test status
Simulation time 5065700461 ps
CPU time 17.25 seconds
Started Mar 26 03:06:38 PM PDT 24
Finished Mar 26 03:06:57 PM PDT 24
Peak memory 233968 kb
Host smart-78e5fad8-7830-42c7-b047-cbf77cc6185e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458938132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.2458938132
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.210048346
Short name T655
Test name
Test status
Simulation time 1041550893 ps
CPU time 4.38 seconds
Started Mar 26 03:06:36 PM PDT 24
Finished Mar 26 03:06:40 PM PDT 24
Peak memory 219524 kb
Host smart-5565e3c0-0908-42ef-87ff-1daf1b8a6bae
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=210048346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dire
ct.210048346
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.3992161329
Short name T914
Test name
Test status
Simulation time 2480394255 ps
CPU time 5.85 seconds
Started Mar 26 03:06:36 PM PDT 24
Finished Mar 26 03:06:42 PM PDT 24
Peak memory 216796 kb
Host smart-c9556f57-a3af-4b71-9925-45994aab3ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992161329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.3992161329
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.3327789876
Short name T606
Test name
Test status
Simulation time 6012560459 ps
CPU time 7.85 seconds
Started Mar 26 03:06:39 PM PDT 24
Finished Mar 26 03:06:48 PM PDT 24
Peak memory 216760 kb
Host smart-d6865352-1f13-46be-b07e-0a16c852fa49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327789876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.3327789876
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.2200963087
Short name T610
Test name
Test status
Simulation time 30596441 ps
CPU time 1.19 seconds
Started Mar 26 03:06:40 PM PDT 24
Finished Mar 26 03:06:43 PM PDT 24
Peak memory 208244 kb
Host smart-876fd032-9bf0-4e79-abcc-9462e1a96c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200963087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.2200963087
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.40307910
Short name T280
Test name
Test status
Simulation time 181120364 ps
CPU time 0.8 seconds
Started Mar 26 03:06:36 PM PDT 24
Finished Mar 26 03:06:37 PM PDT 24
Peak memory 206084 kb
Host smart-0bf03707-f077-4d69-bb1a-66921febf738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40307910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.40307910
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.4237932057
Short name T377
Test name
Test status
Simulation time 658772264 ps
CPU time 3.56 seconds
Started Mar 26 03:06:38 PM PDT 24
Finished Mar 26 03:06:43 PM PDT 24
Peak memory 235232 kb
Host smart-5b4b385e-525b-464f-9f60-15ee8da864b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237932057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.4237932057
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.55785210
Short name T551
Test name
Test status
Simulation time 25060967 ps
CPU time 0.75 seconds
Started Mar 26 03:06:41 PM PDT 24
Finished Mar 26 03:06:42 PM PDT 24
Peak memory 205248 kb
Host smart-410d3711-8157-41b7-9938-e92d947edf0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55785210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.55785210
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.2012364287
Short name T622
Test name
Test status
Simulation time 3489439770 ps
CPU time 5.59 seconds
Started Mar 26 03:06:39 PM PDT 24
Finished Mar 26 03:06:45 PM PDT 24
Peak memory 237620 kb
Host smart-2ca28e8b-e06e-41b7-978e-e03980784332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012364287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.2012364287
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.3671884111
Short name T381
Test name
Test status
Simulation time 38151166 ps
CPU time 0.84 seconds
Started Mar 26 03:06:36 PM PDT 24
Finished Mar 26 03:06:38 PM PDT 24
Peak memory 205892 kb
Host smart-8b64a711-0ee9-4afc-81cf-c1c36ba19b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671884111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.3671884111
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.1219149359
Short name T451
Test name
Test status
Simulation time 1689080393 ps
CPU time 18.6 seconds
Started Mar 26 03:06:42 PM PDT 24
Finished Mar 26 03:07:00 PM PDT 24
Peak memory 233084 kb
Host smart-b86e29fa-ea65-43e8-9c9b-5163f28deb67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219149359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.1219149359
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.2510619012
Short name T176
Test name
Test status
Simulation time 31570162072 ps
CPU time 72.83 seconds
Started Mar 26 03:06:39 PM PDT 24
Finished Mar 26 03:07:53 PM PDT 24
Peak memory 235644 kb
Host smart-0ee89d4b-16f9-474e-8277-6b518a871759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510619012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.2510619012
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.205371573
Short name T626
Test name
Test status
Simulation time 97369422567 ps
CPU time 134.27 seconds
Started Mar 26 03:06:35 PM PDT 24
Finished Mar 26 03:08:49 PM PDT 24
Peak memory 233228 kb
Host smart-bb6ccc9c-2128-46dd-acc6-37d7ede08234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205371573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle
.205371573
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.950119704
Short name T781
Test name
Test status
Simulation time 10911666613 ps
CPU time 17.19 seconds
Started Mar 26 03:06:38 PM PDT 24
Finished Mar 26 03:06:57 PM PDT 24
Peak memory 237264 kb
Host smart-de2a1941-986b-4776-8ee3-1b2e42088946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950119704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.950119704
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.157744663
Short name T973
Test name
Test status
Simulation time 1558955422 ps
CPU time 3.05 seconds
Started Mar 26 03:06:38 PM PDT 24
Finished Mar 26 03:06:43 PM PDT 24
Peak memory 218072 kb
Host smart-37da7a8e-5a71-4afe-8968-7c649b72aaa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157744663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.157744663
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.955882541
Short name T515
Test name
Test status
Simulation time 108540437 ps
CPU time 2.26 seconds
Started Mar 26 03:06:39 PM PDT 24
Finished Mar 26 03:06:42 PM PDT 24
Peak memory 224792 kb
Host smart-6814762e-85f9-4423-a76d-858d8f7f2df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955882541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.955882541
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.372292842
Short name T266
Test name
Test status
Simulation time 14146329065 ps
CPU time 15 seconds
Started Mar 26 03:06:39 PM PDT 24
Finished Mar 26 03:06:55 PM PDT 24
Peak memory 234500 kb
Host smart-36e3b4cf-0ca4-417e-8220-f7897324d23b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372292842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap
.372292842
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.3864107743
Short name T13
Test name
Test status
Simulation time 3083380234 ps
CPU time 11.22 seconds
Started Mar 26 03:06:36 PM PDT 24
Finished Mar 26 03:06:48 PM PDT 24
Peak memory 248616 kb
Host smart-d7cf2945-d8c0-455c-864a-88c2c7571068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864107743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.3864107743
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.4290086992
Short name T388
Test name
Test status
Simulation time 2658413210 ps
CPU time 6.34 seconds
Started Mar 26 03:06:42 PM PDT 24
Finished Mar 26 03:06:48 PM PDT 24
Peak memory 223408 kb
Host smart-6802c070-2a7b-4f51-b74a-c9fca513b688
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4290086992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.4290086992
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.1801671907
Short name T855
Test name
Test status
Simulation time 11202254258 ps
CPU time 34.12 seconds
Started Mar 26 03:06:36 PM PDT 24
Finished Mar 26 03:07:10 PM PDT 24
Peak memory 241404 kb
Host smart-5ece9a59-b1b1-4594-b38a-ba9e27f81fb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801671907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.1801671907
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.2600523442
Short name T272
Test name
Test status
Simulation time 1040311686 ps
CPU time 8.45 seconds
Started Mar 26 03:06:41 PM PDT 24
Finished Mar 26 03:06:50 PM PDT 24
Peak memory 216500 kb
Host smart-7be2c821-d5b1-4d71-8868-f5b0d2b417e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600523442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.2600523442
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.3621474942
Short name T494
Test name
Test status
Simulation time 2822524019 ps
CPU time 8.8 seconds
Started Mar 26 03:06:34 PM PDT 24
Finished Mar 26 03:06:44 PM PDT 24
Peak memory 216720 kb
Host smart-c953efe9-2138-45f3-9f9b-e8aa0e4b843f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621474942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.3621474942
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.4013666038
Short name T616
Test name
Test status
Simulation time 176452092 ps
CPU time 1.18 seconds
Started Mar 26 03:06:38 PM PDT 24
Finished Mar 26 03:06:41 PM PDT 24
Peak memory 208264 kb
Host smart-3bfb18d0-9e89-45ca-8ac2-de1cf600f295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013666038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.4013666038
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.3860224146
Short name T528
Test name
Test status
Simulation time 127627423 ps
CPU time 0.81 seconds
Started Mar 26 03:06:37 PM PDT 24
Finished Mar 26 03:06:40 PM PDT 24
Peak memory 206148 kb
Host smart-088ded28-c90a-4601-a7e1-c96076a3ee40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860224146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.3860224146
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.1492969297
Short name T632
Test name
Test status
Simulation time 15763490385 ps
CPU time 11.73 seconds
Started Mar 26 03:06:36 PM PDT 24
Finished Mar 26 03:06:49 PM PDT 24
Peak memory 219020 kb
Host smart-6e640546-4e76-4305-bc6c-22699ad4b739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492969297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.1492969297
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.444941401
Short name T508
Test name
Test status
Simulation time 87525083 ps
CPU time 0.72 seconds
Started Mar 26 03:06:45 PM PDT 24
Finished Mar 26 03:06:46 PM PDT 24
Peak memory 205860 kb
Host smart-c2a20d82-8c23-4117-8ad6-d2060c6526a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444941401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.444941401
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.987470217
Short name T355
Test name
Test status
Simulation time 1215210463 ps
CPU time 6.33 seconds
Started Mar 26 03:06:47 PM PDT 24
Finished Mar 26 03:06:53 PM PDT 24
Peak memory 234660 kb
Host smart-268bd886-c7a4-4505-9b8d-e52e24ad463d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987470217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.987470217
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.2490777731
Short name T770
Test name
Test status
Simulation time 14574332 ps
CPU time 0.75 seconds
Started Mar 26 03:06:34 PM PDT 24
Finished Mar 26 03:06:36 PM PDT 24
Peak memory 206188 kb
Host smart-f8f54132-90f5-433a-8462-0e9770212964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490777731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.2490777731
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.1811858393
Short name T962
Test name
Test status
Simulation time 1298823111 ps
CPU time 10.59 seconds
Started Mar 26 03:06:47 PM PDT 24
Finished Mar 26 03:06:58 PM PDT 24
Peak memory 239560 kb
Host smart-55484a06-cf6a-4b08-af74-b2cb315da862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811858393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.1811858393
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.2907034108
Short name T862
Test name
Test status
Simulation time 40015635387 ps
CPU time 278.82 seconds
Started Mar 26 03:06:46 PM PDT 24
Finished Mar 26 03:11:25 PM PDT 24
Peak memory 249996 kb
Host smart-58a23958-c689-4a6a-8dd2-96bed14d5782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907034108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.2907034108
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.4185435549
Short name T974
Test name
Test status
Simulation time 12890673809 ps
CPU time 22.68 seconds
Started Mar 26 03:06:46 PM PDT 24
Finished Mar 26 03:07:09 PM PDT 24
Peak memory 240840 kb
Host smart-c335c042-02ce-4599-a7f8-28a11fc29fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185435549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.4185435549
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.2530688341
Short name T452
Test name
Test status
Simulation time 1027007259 ps
CPU time 4.06 seconds
Started Mar 26 03:06:41 PM PDT 24
Finished Mar 26 03:06:45 PM PDT 24
Peak memory 234148 kb
Host smart-1943aa4b-33a9-4d07-ab0b-06dfced3a836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530688341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.2530688341
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.2735953214
Short name T719
Test name
Test status
Simulation time 3647702083 ps
CPU time 20.76 seconds
Started Mar 26 03:06:45 PM PDT 24
Finished Mar 26 03:07:06 PM PDT 24
Peak memory 233956 kb
Host smart-e597f9fd-1054-4095-9331-92ef341e5f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735953214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.2735953214
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.2229624837
Short name T694
Test name
Test status
Simulation time 279684253 ps
CPU time 2.84 seconds
Started Mar 26 03:06:40 PM PDT 24
Finished Mar 26 03:06:44 PM PDT 24
Peak memory 233988 kb
Host smart-4656cfb9-2fcd-4b9f-a679-46418afd9816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229624837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.2229624837
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.4283321135
Short name T590
Test name
Test status
Simulation time 45803582738 ps
CPU time 25.38 seconds
Started Mar 26 03:06:39 PM PDT 24
Finished Mar 26 03:07:05 PM PDT 24
Peak memory 231916 kb
Host smart-20a51b3b-7792-453b-99b8-0ddf86ac4190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283321135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.4283321135
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.4012716505
Short name T597
Test name
Test status
Simulation time 259010298 ps
CPU time 3.05 seconds
Started Mar 26 03:06:49 PM PDT 24
Finished Mar 26 03:06:52 PM PDT 24
Peak memory 220248 kb
Host smart-f791c877-01c8-4d8c-8d64-5df0fb38fbee
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4012716505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.4012716505
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.111248231
Short name T143
Test name
Test status
Simulation time 187784482366 ps
CPU time 320.41 seconds
Started Mar 26 03:06:55 PM PDT 24
Finished Mar 26 03:12:16 PM PDT 24
Peak memory 254212 kb
Host smart-3e318a39-f0d6-49f9-a529-b4888b3b2706
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111248231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stres
s_all.111248231
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.2596473670
Short name T847
Test name
Test status
Simulation time 12272027283 ps
CPU time 56.85 seconds
Started Mar 26 03:06:41 PM PDT 24
Finished Mar 26 03:07:38 PM PDT 24
Peak memory 216672 kb
Host smart-146b4b72-1561-48ed-88bb-91cd123f0bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596473670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.2596473670
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.1131939323
Short name T4
Test name
Test status
Simulation time 7483358074 ps
CPU time 23.69 seconds
Started Mar 26 03:06:37 PM PDT 24
Finished Mar 26 03:07:03 PM PDT 24
Peak memory 216844 kb
Host smart-477b828e-1507-4888-ba6a-b291f4da4fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131939323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.1131939323
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.1885893450
Short name T455
Test name
Test status
Simulation time 150464128 ps
CPU time 1.67 seconds
Started Mar 26 03:06:37 PM PDT 24
Finished Mar 26 03:06:41 PM PDT 24
Peak memory 216612 kb
Host smart-3be488b6-55e2-4443-9a08-0cc096fb61e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885893450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.1885893450
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.3667413392
Short name T713
Test name
Test status
Simulation time 92439665 ps
CPU time 0.97 seconds
Started Mar 26 03:06:43 PM PDT 24
Finished Mar 26 03:06:44 PM PDT 24
Peak memory 206152 kb
Host smart-e2562021-8543-4e7c-9e51-e6c2e8eca941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667413392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.3667413392
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.2337279614
Short name T319
Test name
Test status
Simulation time 2238699281 ps
CPU time 3.9 seconds
Started Mar 26 03:06:49 PM PDT 24
Finished Mar 26 03:06:53 PM PDT 24
Peak memory 219592 kb
Host smart-512faa2f-40d8-4733-9503-342bb3a50837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337279614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.2337279614
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.1202284307
Short name T664
Test name
Test status
Simulation time 36032322 ps
CPU time 0.7 seconds
Started Mar 26 03:06:45 PM PDT 24
Finished Mar 26 03:06:47 PM PDT 24
Peak memory 205264 kb
Host smart-fe4605a0-b9ee-41ae-b45a-67387f785619
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202284307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
1202284307
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.660974267
Short name T310
Test name
Test status
Simulation time 630436108 ps
CPU time 4.09 seconds
Started Mar 26 03:06:46 PM PDT 24
Finished Mar 26 03:06:50 PM PDT 24
Peak memory 234684 kb
Host smart-997608c9-e541-44b5-8576-5a071be76e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660974267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.660974267
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.2377484266
Short name T634
Test name
Test status
Simulation time 75083597 ps
CPU time 0.81 seconds
Started Mar 26 03:06:46 PM PDT 24
Finished Mar 26 03:06:47 PM PDT 24
Peak memory 206928 kb
Host smart-a3ae5d36-457c-4870-a9c8-51e54e87bc5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377484266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.2377484266
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.3770306580
Short name T22
Test name
Test status
Simulation time 25950385677 ps
CPU time 55.16 seconds
Started Mar 26 03:06:47 PM PDT 24
Finished Mar 26 03:07:43 PM PDT 24
Peak memory 252412 kb
Host smart-2b67a2ad-5dac-495b-bfb2-626a9e3d7c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770306580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.3770306580
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.3969391389
Short name T156
Test name
Test status
Simulation time 8442079529 ps
CPU time 27.37 seconds
Started Mar 26 03:06:46 PM PDT 24
Finished Mar 26 03:07:14 PM PDT 24
Peak memory 235880 kb
Host smart-39102024-3fae-4b59-8cdd-775cdba1fbd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969391389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.3969391389
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.3433926415
Short name T950
Test name
Test status
Simulation time 2985743130 ps
CPU time 19.89 seconds
Started Mar 26 03:06:47 PM PDT 24
Finished Mar 26 03:07:07 PM PDT 24
Peak memory 234172 kb
Host smart-7438876e-9fd1-4416-af3d-3b978656c775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433926415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.3433926415
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.317806814
Short name T588
Test name
Test status
Simulation time 3940463545 ps
CPU time 6.07 seconds
Started Mar 26 03:06:48 PM PDT 24
Finished Mar 26 03:06:54 PM PDT 24
Peak memory 233948 kb
Host smart-36d191a7-392e-4317-9da6-0a721f36556f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317806814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.317806814
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.4224542771
Short name T312
Test name
Test status
Simulation time 131914131862 ps
CPU time 27.16 seconds
Started Mar 26 03:06:45 PM PDT 24
Finished Mar 26 03:07:12 PM PDT 24
Peak memory 241336 kb
Host smart-42e728fa-47d8-42b5-ab1e-e920987f428a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224542771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.4224542771
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.3771494775
Short name T684
Test name
Test status
Simulation time 62995826628 ps
CPU time 13.76 seconds
Started Mar 26 03:06:51 PM PDT 24
Finished Mar 26 03:07:05 PM PDT 24
Peak memory 233692 kb
Host smart-774c9799-0160-4b8b-979c-cc765d22073d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771494775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.3771494775
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.1274791687
Short name T602
Test name
Test status
Simulation time 3111548161 ps
CPU time 5.48 seconds
Started Mar 26 03:06:45 PM PDT 24
Finished Mar 26 03:06:50 PM PDT 24
Peak memory 219088 kb
Host smart-7a0b1786-59f8-40b4-99c0-3a91b4b86098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274791687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.1274791687
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.1166761415
Short name T949
Test name
Test status
Simulation time 2777271300 ps
CPU time 4.88 seconds
Started Mar 26 03:06:46 PM PDT 24
Finished Mar 26 03:06:51 PM PDT 24
Peak memory 220280 kb
Host smart-d9657a13-68c3-4635-8157-d24da1c70832
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1166761415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.1166761415
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.3413706449
Short name T787
Test name
Test status
Simulation time 89499638869 ps
CPU time 25.29 seconds
Started Mar 26 03:06:55 PM PDT 24
Finished Mar 26 03:07:20 PM PDT 24
Peak memory 220656 kb
Host smart-19093c9c-9668-4ae5-8353-0ff75f40d4dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413706449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.3413706449
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.1038404893
Short name T308
Test name
Test status
Simulation time 2083330545 ps
CPU time 7.46 seconds
Started Mar 26 03:06:46 PM PDT 24
Finished Mar 26 03:06:54 PM PDT 24
Peak memory 216612 kb
Host smart-17e52615-4722-424e-a646-7888211be9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038404893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.1038404893
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.1894717001
Short name T479
Test name
Test status
Simulation time 29472099 ps
CPU time 1.1 seconds
Started Mar 26 03:06:47 PM PDT 24
Finished Mar 26 03:06:49 PM PDT 24
Peak memory 207568 kb
Host smart-5b1f4907-2e43-4004-b6e7-53d2709f85bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894717001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.1894717001
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.1487861488
Short name T869
Test name
Test status
Simulation time 155533711 ps
CPU time 0.78 seconds
Started Mar 26 03:06:45 PM PDT 24
Finished Mar 26 03:06:47 PM PDT 24
Peak memory 206152 kb
Host smart-7d6362f5-2d9d-45a4-9d04-937b2df81bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487861488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.1487861488
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.3199211042
Short name T931
Test name
Test status
Simulation time 1049293765 ps
CPU time 7.18 seconds
Started Mar 26 03:06:55 PM PDT 24
Finished Mar 26 03:07:02 PM PDT 24
Peak memory 238628 kb
Host smart-765a329d-a00f-43f0-a49f-c5ce9c598eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199211042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.3199211042
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.1969430175
Short name T837
Test name
Test status
Simulation time 44303415 ps
CPU time 0.78 seconds
Started Mar 26 03:06:52 PM PDT 24
Finished Mar 26 03:06:54 PM PDT 24
Peak memory 205736 kb
Host smart-f87c6e31-595a-41c2-ac0d-7c8272ce145f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969430175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
1969430175
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.3825449530
Short name T793
Test name
Test status
Simulation time 116810585 ps
CPU time 2.64 seconds
Started Mar 26 03:06:45 PM PDT 24
Finished Mar 26 03:06:48 PM PDT 24
Peak memory 233052 kb
Host smart-69d71c0c-5478-4f0c-9df4-79279692af34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825449530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.3825449530
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.2993818135
Short name T382
Test name
Test status
Simulation time 28113370 ps
CPU time 0.8 seconds
Started Mar 26 03:06:47 PM PDT 24
Finished Mar 26 03:06:47 PM PDT 24
Peak memory 207236 kb
Host smart-2d5b8c41-0e52-4351-944c-c24d499126bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993818135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.2993818135
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.2317185008
Short name T256
Test name
Test status
Simulation time 11870424687 ps
CPU time 38.31 seconds
Started Mar 26 03:06:47 PM PDT 24
Finished Mar 26 03:07:26 PM PDT 24
Peak memory 254312 kb
Host smart-bbac2a81-2494-416f-9274-9c1db776bf81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317185008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.2317185008
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.2187821297
Short name T392
Test name
Test status
Simulation time 6295763221 ps
CPU time 74.49 seconds
Started Mar 26 03:06:45 PM PDT 24
Finished Mar 26 03:08:01 PM PDT 24
Peak memory 254084 kb
Host smart-e05d5889-dbdf-428d-8dda-9fc9dd8c2a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187821297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.2187821297
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.2563513794
Short name T812
Test name
Test status
Simulation time 4857119914 ps
CPU time 13.36 seconds
Started Mar 26 03:06:51 PM PDT 24
Finished Mar 26 03:07:05 PM PDT 24
Peak memory 224112 kb
Host smart-033526d6-cdb4-4b45-8b93-0cf78f98eb75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563513794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.2563513794
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.1709552169
Short name T461
Test name
Test status
Simulation time 142200111 ps
CPU time 2.67 seconds
Started Mar 26 03:06:46 PM PDT 24
Finished Mar 26 03:06:49 PM PDT 24
Peak memory 233108 kb
Host smart-57fd9389-c2ea-49c9-b231-8b6dc670248e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709552169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.1709552169
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.2683147457
Short name T771
Test name
Test status
Simulation time 9999837356 ps
CPU time 9.45 seconds
Started Mar 26 03:06:46 PM PDT 24
Finished Mar 26 03:06:56 PM PDT 24
Peak memory 228852 kb
Host smart-c42370a5-4cc6-49a4-bbe6-890ad95b7002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683147457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.2683147457
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.1120899739
Short name T177
Test name
Test status
Simulation time 3000041604 ps
CPU time 10.72 seconds
Started Mar 26 03:06:47 PM PDT 24
Finished Mar 26 03:06:58 PM PDT 24
Peak memory 224956 kb
Host smart-0f67a22b-3fc3-452c-865c-f5bbe58fdf79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120899739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.1120899739
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.1906437930
Short name T631
Test name
Test status
Simulation time 3380512048 ps
CPU time 11.18 seconds
Started Mar 26 03:06:47 PM PDT 24
Finished Mar 26 03:06:58 PM PDT 24
Peak memory 234224 kb
Host smart-841d884c-4418-40e0-bac6-839e620a8dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906437930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.1906437930
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.3564085818
Short name T970
Test name
Test status
Simulation time 2953854497 ps
CPU time 4.54 seconds
Started Mar 26 03:06:47 PM PDT 24
Finished Mar 26 03:06:52 PM PDT 24
Peak memory 221320 kb
Host smart-40880798-f054-4755-9687-f37b6f9b989b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3564085818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.3564085818
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.1550522608
Short name T910
Test name
Test status
Simulation time 99158506335 ps
CPU time 585.22 seconds
Started Mar 26 03:06:47 PM PDT 24
Finished Mar 26 03:16:33 PM PDT 24
Peak memory 282368 kb
Host smart-5ea3300d-01f5-4b13-bf59-67e18fe2213a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550522608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.1550522608
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.2785055050
Short name T273
Test name
Test status
Simulation time 8110957496 ps
CPU time 42.38 seconds
Started Mar 26 03:06:48 PM PDT 24
Finished Mar 26 03:07:31 PM PDT 24
Peak memory 216712 kb
Host smart-fa728bce-877e-47e9-8970-8536a051a348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785055050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.2785055050
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.3064888040
Short name T728
Test name
Test status
Simulation time 666207285 ps
CPU time 1.82 seconds
Started Mar 26 03:06:45 PM PDT 24
Finished Mar 26 03:06:48 PM PDT 24
Peak memory 208248 kb
Host smart-d1da3c2b-a292-44ca-ab76-c631425a2b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064888040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.3064888040
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.297518791
Short name T353
Test name
Test status
Simulation time 439510030 ps
CPU time 1.78 seconds
Started Mar 26 03:06:46 PM PDT 24
Finished Mar 26 03:06:48 PM PDT 24
Peak memory 216608 kb
Host smart-4c8d5fb8-1225-4c9d-a60a-e18d33271729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297518791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.297518791
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.4106584068
Short name T432
Test name
Test status
Simulation time 106780105 ps
CPU time 1.02 seconds
Started Mar 26 03:06:45 PM PDT 24
Finished Mar 26 03:06:47 PM PDT 24
Peak memory 207216 kb
Host smart-349ea1d8-4037-4c3f-8469-c40eda7a1d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106584068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.4106584068
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.1046752119
Short name T9
Test name
Test status
Simulation time 1052444777 ps
CPU time 5.57 seconds
Started Mar 26 03:06:55 PM PDT 24
Finished Mar 26 03:07:01 PM PDT 24
Peak memory 232960 kb
Host smart-fa86f17e-8c7a-43aa-85a1-c09cb27d3f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046752119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.1046752119
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.1255337291
Short name T879
Test name
Test status
Simulation time 31349453 ps
CPU time 0.71 seconds
Started Mar 26 03:06:55 PM PDT 24
Finished Mar 26 03:06:56 PM PDT 24
Peak memory 206176 kb
Host smart-7e237c8b-d0a1-4ab4-9c18-d5ddc022116d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255337291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
1255337291
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.2778760947
Short name T420
Test name
Test status
Simulation time 1053292985 ps
CPU time 5.55 seconds
Started Mar 26 03:06:55 PM PDT 24
Finished Mar 26 03:07:00 PM PDT 24
Peak memory 234064 kb
Host smart-65bdc524-412f-4edc-aeed-f53390db5635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778760947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.2778760947
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.2380811781
Short name T350
Test name
Test status
Simulation time 16012100 ps
CPU time 0.79 seconds
Started Mar 26 03:06:46 PM PDT 24
Finished Mar 26 03:06:47 PM PDT 24
Peak memory 206936 kb
Host smart-62e7619f-ed5e-449d-ac97-a2bba570a83f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380811781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.2380811781
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.2247368726
Short name T198
Test name
Test status
Simulation time 87644771745 ps
CPU time 157.15 seconds
Started Mar 26 03:06:54 PM PDT 24
Finished Mar 26 03:09:32 PM PDT 24
Peak memory 257788 kb
Host smart-88ff5bfe-256a-4813-89f6-b1a165a7faba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247368726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.2247368726
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.3201251657
Short name T747
Test name
Test status
Simulation time 26121929747 ps
CPU time 51.98 seconds
Started Mar 26 03:06:55 PM PDT 24
Finished Mar 26 03:07:47 PM PDT 24
Peak memory 233556 kb
Host smart-3099131b-d2e9-4fad-abd1-5cf0d39af65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201251657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.3201251657
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.3870682583
Short name T644
Test name
Test status
Simulation time 144758062158 ps
CPU time 231.76 seconds
Started Mar 26 03:06:55 PM PDT 24
Finished Mar 26 03:10:47 PM PDT 24
Peak memory 257028 kb
Host smart-75ebbe83-5078-4f1c-8b60-9b5a69fd2f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870682583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.3870682583
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.990667085
Short name T842
Test name
Test status
Simulation time 47450359045 ps
CPU time 33.89 seconds
Started Mar 26 03:06:54 PM PDT 24
Finished Mar 26 03:07:29 PM PDT 24
Peak memory 241272 kb
Host smart-d0c83106-e529-45c4-b0ba-e017200918e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990667085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.990667085
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.4025385376
Short name T369
Test name
Test status
Simulation time 4721352794 ps
CPU time 3.85 seconds
Started Mar 26 03:06:54 PM PDT 24
Finished Mar 26 03:06:58 PM PDT 24
Peak memory 218904 kb
Host smart-e046285b-fdc7-41b2-b0a1-3931f6481921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025385376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.4025385376
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.1048765663
Short name T704
Test name
Test status
Simulation time 596934839 ps
CPU time 8.06 seconds
Started Mar 26 03:06:54 PM PDT 24
Finished Mar 26 03:07:02 PM PDT 24
Peak memory 231212 kb
Host smart-db3121b6-d168-43b6-ae60-4c72ee2db05b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048765663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.1048765663
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.1266007556
Short name T467
Test name
Test status
Simulation time 35839942454 ps
CPU time 25.96 seconds
Started Mar 26 03:06:53 PM PDT 24
Finished Mar 26 03:07:20 PM PDT 24
Peak memory 241244 kb
Host smart-a3a4e987-d7c5-4cd3-9b4a-49fbba51cc80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266007556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.1266007556
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.3853416532
Short name T469
Test name
Test status
Simulation time 849951346 ps
CPU time 6.18 seconds
Started Mar 26 03:06:55 PM PDT 24
Finished Mar 26 03:07:01 PM PDT 24
Peak memory 227124 kb
Host smart-a972897a-132b-4c8e-9ed7-f9549aa57416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853416532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.3853416532
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.1547575577
Short name T531
Test name
Test status
Simulation time 2721036148 ps
CPU time 5.01 seconds
Started Mar 26 03:06:56 PM PDT 24
Finished Mar 26 03:07:01 PM PDT 24
Peak memory 222908 kb
Host smart-93e9e7e7-b64b-4560-8cea-6bcd6eb8ffa8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1547575577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.1547575577
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.3282902839
Short name T195
Test name
Test status
Simulation time 446141373820 ps
CPU time 862.37 seconds
Started Mar 26 03:06:56 PM PDT 24
Finished Mar 26 03:21:19 PM PDT 24
Peak memory 274228 kb
Host smart-d466dca9-bc95-474a-9a1c-504fe2cf2fd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282902839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.3282902839
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.714195366
Short name T512
Test name
Test status
Simulation time 18663246793 ps
CPU time 52.89 seconds
Started Mar 26 03:06:52 PM PDT 24
Finished Mar 26 03:07:47 PM PDT 24
Peak memory 216676 kb
Host smart-ee4e1127-ec5d-4102-b30c-2eca5f5b46be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714195366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.714195366
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.3355326856
Short name T380
Test name
Test status
Simulation time 236611912 ps
CPU time 1.45 seconds
Started Mar 26 03:06:53 PM PDT 24
Finished Mar 26 03:06:55 PM PDT 24
Peak memory 208256 kb
Host smart-22d7fe5a-ff2c-40ac-9aad-df314401bdef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355326856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.3355326856
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.3619228898
Short name T333
Test name
Test status
Simulation time 1997852248 ps
CPU time 6.15 seconds
Started Mar 26 03:06:51 PM PDT 24
Finished Mar 26 03:06:57 PM PDT 24
Peak memory 216644 kb
Host smart-a5e6230b-df55-4f0e-a9b7-a0ba579acae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619228898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.3619228898
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.726699087
Short name T72
Test name
Test status
Simulation time 48509630 ps
CPU time 0.85 seconds
Started Mar 26 03:06:53 PM PDT 24
Finished Mar 26 03:06:55 PM PDT 24
Peak memory 206164 kb
Host smart-2275689c-9388-4c29-9d35-28e4fb5becc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726699087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.726699087
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.1649913376
Short name T207
Test name
Test status
Simulation time 6047667309 ps
CPU time 25.85 seconds
Started Mar 26 03:06:55 PM PDT 24
Finished Mar 26 03:07:21 PM PDT 24
Peak memory 239812 kb
Host smart-21a77916-b829-4d10-9bab-fb093fb5594c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649913376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.1649913376
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.2532667985
Short name T460
Test name
Test status
Simulation time 13568999 ps
CPU time 0.71 seconds
Started Mar 26 03:06:58 PM PDT 24
Finished Mar 26 03:06:58 PM PDT 24
Peak memory 205852 kb
Host smart-cb27550c-0526-4fcf-b389-bc3ef0aedb64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532667985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
2532667985
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.1326008753
Short name T548
Test name
Test status
Simulation time 64508604 ps
CPU time 2.46 seconds
Started Mar 26 03:06:55 PM PDT 24
Finished Mar 26 03:06:58 PM PDT 24
Peak memory 233748 kb
Host smart-e9f33905-43f2-4afe-a8a5-fcb8fecf15f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326008753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.1326008753
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.3561610004
Short name T514
Test name
Test status
Simulation time 21366116 ps
CPU time 0.76 seconds
Started Mar 26 03:06:55 PM PDT 24
Finished Mar 26 03:06:56 PM PDT 24
Peak memory 206008 kb
Host smart-08a72249-9dbf-411c-9a67-c689f157796d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561610004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.3561610004
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.1468919678
Short name T654
Test name
Test status
Simulation time 717138776 ps
CPU time 5.33 seconds
Started Mar 26 03:06:59 PM PDT 24
Finished Mar 26 03:07:05 PM PDT 24
Peak memory 235912 kb
Host smart-ee3d8032-9f63-402b-a574-03dd3bdf48be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468919678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.1468919678
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.1194615141
Short name T19
Test name
Test status
Simulation time 15642136710 ps
CPU time 105.9 seconds
Started Mar 26 03:06:57 PM PDT 24
Finished Mar 26 03:08:43 PM PDT 24
Peak memory 265820 kb
Host smart-e77f64c7-a57f-4565-873c-77006c55bb4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194615141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.1194615141
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.3444464165
Short name T675
Test name
Test status
Simulation time 111797912201 ps
CPU time 253.71 seconds
Started Mar 26 03:06:57 PM PDT 24
Finished Mar 26 03:11:11 PM PDT 24
Peak memory 255172 kb
Host smart-cedd97e3-97d6-42b3-8d80-c0a2a307ce66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444464165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.3444464165
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.134493004
Short name T267
Test name
Test status
Simulation time 1104339323 ps
CPU time 9.94 seconds
Started Mar 26 03:06:55 PM PDT 24
Finished Mar 26 03:07:05 PM PDT 24
Peak memory 224860 kb
Host smart-316097ba-0a1c-46a7-9875-70a5e7f32d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134493004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.134493004
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.520675749
Short name T876
Test name
Test status
Simulation time 56565184 ps
CPU time 2.09 seconds
Started Mar 26 03:06:56 PM PDT 24
Finished Mar 26 03:06:59 PM PDT 24
Peak memory 219272 kb
Host smart-82d32c3d-1eee-4392-bfd6-148e79372cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520675749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.520675749
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.4287292500
Short name T683
Test name
Test status
Simulation time 449546284 ps
CPU time 9.66 seconds
Started Mar 26 03:06:54 PM PDT 24
Finished Mar 26 03:07:04 PM PDT 24
Peak memory 222440 kb
Host smart-204441c8-b00b-4377-9c8c-7e68027fee4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287292500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.4287292500
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.825095519
Short name T84
Test name
Test status
Simulation time 444189646 ps
CPU time 4.04 seconds
Started Mar 26 03:06:54 PM PDT 24
Finished Mar 26 03:06:59 PM PDT 24
Peak memory 233516 kb
Host smart-cea6224d-f0fe-428a-bd73-1c547b8e87d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825095519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swap
.825095519
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.1983630643
Short name T323
Test name
Test status
Simulation time 7433600596 ps
CPU time 8.1 seconds
Started Mar 26 03:06:55 PM PDT 24
Finished Mar 26 03:07:03 PM PDT 24
Peak memory 235496 kb
Host smart-c6f23ac4-6fc4-4f3d-807d-0794e010a220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983630643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.1983630643
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.3138347954
Short name T126
Test name
Test status
Simulation time 2501959863 ps
CPU time 6.07 seconds
Started Mar 26 03:06:56 PM PDT 24
Finished Mar 26 03:07:03 PM PDT 24
Peak memory 219964 kb
Host smart-34423dc7-ca5f-40ce-adad-5e260adb0537
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3138347954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.3138347954
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.1044531142
Short name T784
Test name
Test status
Simulation time 6848363148 ps
CPU time 30.19 seconds
Started Mar 26 03:06:57 PM PDT 24
Finished Mar 26 03:07:27 PM PDT 24
Peak memory 233208 kb
Host smart-6a4a1de0-0830-4c65-973b-61be32603a7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044531142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.1044531142
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.3959138128
Short name T779
Test name
Test status
Simulation time 3318789192 ps
CPU time 20.23 seconds
Started Mar 26 03:06:55 PM PDT 24
Finished Mar 26 03:07:16 PM PDT 24
Peak memory 216640 kb
Host smart-7d5b70c0-a588-45ee-bee4-f5d4251664b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959138128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.3959138128
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.2065267308
Short name T725
Test name
Test status
Simulation time 7605423578 ps
CPU time 18.02 seconds
Started Mar 26 03:06:59 PM PDT 24
Finished Mar 26 03:07:17 PM PDT 24
Peak memory 216824 kb
Host smart-9148007d-920d-4010-99f6-40ca79259b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065267308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.2065267308
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.157838717
Short name T933
Test name
Test status
Simulation time 213128387 ps
CPU time 1.02 seconds
Started Mar 26 03:06:55 PM PDT 24
Finished Mar 26 03:06:56 PM PDT 24
Peak memory 207804 kb
Host smart-fca9e9f8-18bc-4ff7-8feb-c0e848938dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157838717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.157838717
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.324007004
Short name T798
Test name
Test status
Simulation time 127643303 ps
CPU time 0.81 seconds
Started Mar 26 03:07:00 PM PDT 24
Finished Mar 26 03:07:01 PM PDT 24
Peak memory 206076 kb
Host smart-477f39f5-e88a-4ec8-bde9-0ed37b48736c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324007004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.324007004
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.3184107112
Short name T419
Test name
Test status
Simulation time 1263198862 ps
CPU time 4.49 seconds
Started Mar 26 03:06:55 PM PDT 24
Finished Mar 26 03:07:00 PM PDT 24
Peak memory 236140 kb
Host smart-cf78e140-2a89-4064-809e-5ada4f58adbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184107112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.3184107112
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.1195150927
Short name T500
Test name
Test status
Simulation time 21630856 ps
CPU time 0.76 seconds
Started Mar 26 03:07:04 PM PDT 24
Finished Mar 26 03:07:06 PM PDT 24
Peak memory 206196 kb
Host smart-f5a69b81-ae8d-44f6-80a9-4eeb57456ef1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195150927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
1195150927
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.1014400230
Short name T553
Test name
Test status
Simulation time 30675550 ps
CPU time 2.07 seconds
Started Mar 26 03:06:56 PM PDT 24
Finished Mar 26 03:06:58 PM PDT 24
Peak memory 218980 kb
Host smart-5afe348c-f9f4-4eb2-af7b-10633ccf140d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014400230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.1014400230
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.1123913088
Short name T411
Test name
Test status
Simulation time 17688974 ps
CPU time 0.75 seconds
Started Mar 26 03:06:57 PM PDT 24
Finished Mar 26 03:06:58 PM PDT 24
Peak memory 205968 kb
Host smart-c2515a96-c57b-4944-923d-a5cea190e1b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123913088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.1123913088
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.3663679759
Short name T570
Test name
Test status
Simulation time 4723814343 ps
CPU time 23.51 seconds
Started Mar 26 03:06:56 PM PDT 24
Finished Mar 26 03:07:20 PM PDT 24
Peak memory 219564 kb
Host smart-e20b086f-c2c8-4934-b3f5-6b32f78ebdff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663679759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.3663679759
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.1591807211
Short name T833
Test name
Test status
Simulation time 3905645137 ps
CPU time 44.83 seconds
Started Mar 26 03:06:57 PM PDT 24
Finished Mar 26 03:07:42 PM PDT 24
Peak memory 241016 kb
Host smart-d131bf41-a080-45d2-8533-835aab365198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591807211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.1591807211
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.1218170220
Short name T78
Test name
Test status
Simulation time 37822884353 ps
CPU time 80.5 seconds
Started Mar 26 03:07:03 PM PDT 24
Finished Mar 26 03:08:25 PM PDT 24
Peak memory 263116 kb
Host smart-4d13163d-d685-47e0-bab1-9d58785326ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218170220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.1218170220
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_intercept.3381707919
Short name T339
Test name
Test status
Simulation time 5215516423 ps
CPU time 10.11 seconds
Started Mar 26 03:07:04 PM PDT 24
Finished Mar 26 03:07:15 PM PDT 24
Peak memory 234128 kb
Host smart-33fb3709-41e3-4915-b912-adc17109dcf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381707919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.3381707919
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.3543748129
Short name T944
Test name
Test status
Simulation time 51417415561 ps
CPU time 27.62 seconds
Started Mar 26 03:06:56 PM PDT 24
Finished Mar 26 03:07:25 PM PDT 24
Peak memory 229024 kb
Host smart-9ea40606-3a1c-4091-8274-8d6b8584ad3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543748129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.3543748129
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.923742250
Short name T505
Test name
Test status
Simulation time 3903988001 ps
CPU time 4.15 seconds
Started Mar 26 03:06:57 PM PDT 24
Finished Mar 26 03:07:01 PM PDT 24
Peak memory 234144 kb
Host smart-ed9962da-94a8-40aa-b3c2-3f864ac41942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923742250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swap
.923742250
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.3094895514
Short name T761
Test name
Test status
Simulation time 7146923141 ps
CPU time 11.05 seconds
Started Mar 26 03:06:59 PM PDT 24
Finished Mar 26 03:07:11 PM PDT 24
Peak memory 249820 kb
Host smart-02fed755-e679-4cee-9132-c0a480959802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094895514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.3094895514
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.1914647457
Short name T124
Test name
Test status
Simulation time 440009317 ps
CPU time 3.26 seconds
Started Mar 26 03:06:55 PM PDT 24
Finished Mar 26 03:06:58 PM PDT 24
Peak memory 219004 kb
Host smart-c9983909-6446-46a6-a57f-f7a5152a0268
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1914647457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.1914647457
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.2890377231
Short name T937
Test name
Test status
Simulation time 36820562853 ps
CPU time 117.55 seconds
Started Mar 26 03:07:04 PM PDT 24
Finished Mar 26 03:09:02 PM PDT 24
Peak memory 257324 kb
Host smart-6ae2b14e-a658-41d1-9b0d-b35c80f6d22f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890377231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.2890377231
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.1518934489
Short name T329
Test name
Test status
Simulation time 11564617482 ps
CPU time 22.15 seconds
Started Mar 26 03:06:57 PM PDT 24
Finished Mar 26 03:07:20 PM PDT 24
Peak memory 216816 kb
Host smart-4bebe25b-a2c0-4170-a5ac-c73cf36bb22f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518934489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.1518934489
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.2970624119
Short name T720
Test name
Test status
Simulation time 2787064313 ps
CPU time 7.69 seconds
Started Mar 26 03:06:59 PM PDT 24
Finished Mar 26 03:07:07 PM PDT 24
Peak memory 216468 kb
Host smart-c649dd10-ca85-4a02-9ed2-1cdbc31b9463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970624119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.2970624119
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.3532285951
Short name T768
Test name
Test status
Simulation time 95661475 ps
CPU time 1.03 seconds
Started Mar 26 03:06:56 PM PDT 24
Finished Mar 26 03:06:58 PM PDT 24
Peak memory 207276 kb
Host smart-b1968117-ff7d-46b1-bed1-c94738e3048c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532285951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.3532285951
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.516610872
Short name T854
Test name
Test status
Simulation time 159195923 ps
CPU time 0.86 seconds
Started Mar 26 03:06:59 PM PDT 24
Finished Mar 26 03:07:01 PM PDT 24
Peak memory 206044 kb
Host smart-9ae7b816-3cb8-4ce2-af4b-37c96f84efee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516610872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.516610872
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.2204954473
Short name T192
Test name
Test status
Simulation time 4500445224 ps
CPU time 10.64 seconds
Started Mar 26 03:06:55 PM PDT 24
Finished Mar 26 03:07:06 PM PDT 24
Peak memory 219168 kb
Host smart-d1757a84-ec39-4944-a703-22d737c73ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204954473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.2204954473
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.2165177446
Short name T290
Test name
Test status
Simulation time 13803057 ps
CPU time 0.74 seconds
Started Mar 26 03:07:04 PM PDT 24
Finished Mar 26 03:07:06 PM PDT 24
Peak memory 205812 kb
Host smart-2ac5f6c4-1375-4d66-8661-af5b9aff534c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165177446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
2165177446
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.3498656958
Short name T69
Test name
Test status
Simulation time 1197375981 ps
CPU time 4.42 seconds
Started Mar 26 03:07:05 PM PDT 24
Finished Mar 26 03:07:09 PM PDT 24
Peak memory 218728 kb
Host smart-b1a81dbb-a523-4a56-87d8-6b9291053f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498656958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.3498656958
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.166195057
Short name T53
Test name
Test status
Simulation time 123955581 ps
CPU time 0.76 seconds
Started Mar 26 03:07:08 PM PDT 24
Finished Mar 26 03:07:09 PM PDT 24
Peak memory 207184 kb
Host smart-55c4287a-fe77-4926-981c-5f89c0d6a711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166195057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.166195057
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.3821100915
Short name T188
Test name
Test status
Simulation time 5874655489 ps
CPU time 56.38 seconds
Started Mar 26 03:07:05 PM PDT 24
Finished Mar 26 03:08:01 PM PDT 24
Peak memory 256092 kb
Host smart-9013bd9a-2bad-4c9a-bf20-28a0e41bb419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821100915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.3821100915
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.2132332936
Short name T839
Test name
Test status
Simulation time 257918170180 ps
CPU time 106.48 seconds
Started Mar 26 03:07:06 PM PDT 24
Finished Mar 26 03:08:53 PM PDT 24
Peak memory 233316 kb
Host smart-1c9c6ad4-852e-4c8d-872a-5478bfe91ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132332936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.2132332936
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.10852133
Short name T263
Test name
Test status
Simulation time 27036624476 ps
CPU time 116.99 seconds
Started Mar 26 03:07:05 PM PDT 24
Finished Mar 26 03:09:02 PM PDT 24
Peak memory 252904 kb
Host smart-fe0402ee-83d2-4a35-aa55-24df4cf3c413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10852133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle.10852133
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.2339410462
Short name T347
Test name
Test status
Simulation time 1714363998 ps
CPU time 8.44 seconds
Started Mar 26 03:07:04 PM PDT 24
Finished Mar 26 03:07:13 PM PDT 24
Peak memory 240880 kb
Host smart-70532016-72a6-4b84-88bb-e8f6ce1fee36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339410462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.2339410462
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.3943528555
Short name T759
Test name
Test status
Simulation time 3772328263 ps
CPU time 9.2 seconds
Started Mar 26 03:07:04 PM PDT 24
Finished Mar 26 03:07:14 PM PDT 24
Peak memory 235496 kb
Host smart-73eb5df0-c11c-4e1b-bea5-a928d8b2ebb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943528555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.3943528555
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.4078759909
Short name T510
Test name
Test status
Simulation time 4637419320 ps
CPU time 20.59 seconds
Started Mar 26 03:07:04 PM PDT 24
Finished Mar 26 03:07:26 PM PDT 24
Peak memory 250284 kb
Host smart-b394fee5-a8d4-4d0f-9d79-c3fabf31b6b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078759909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.4078759909
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.3860652195
Short name T92
Test name
Test status
Simulation time 205606024 ps
CPU time 4.06 seconds
Started Mar 26 03:07:11 PM PDT 24
Finished Mar 26 03:07:15 PM PDT 24
Peak memory 233708 kb
Host smart-bf74dea7-7e6d-4982-bfae-7e4d011281a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860652195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.3860652195
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.2974437510
Short name T613
Test name
Test status
Simulation time 2374003617 ps
CPU time 6.15 seconds
Started Mar 26 03:07:03 PM PDT 24
Finished Mar 26 03:07:11 PM PDT 24
Peak memory 234048 kb
Host smart-0e3b24d3-82e5-448c-88c4-c8473e9c8170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974437510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.2974437510
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.659776214
Short name T477
Test name
Test status
Simulation time 4489169273 ps
CPU time 5.71 seconds
Started Mar 26 03:07:04 PM PDT 24
Finished Mar 26 03:07:11 PM PDT 24
Peak memory 223360 kb
Host smart-58029c3e-01a9-4a74-83cb-4be9f1a48a60
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=659776214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dire
ct.659776214
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.3898898174
Short name T954
Test name
Test status
Simulation time 20864194400 ps
CPU time 145.47 seconds
Started Mar 26 03:07:06 PM PDT 24
Finished Mar 26 03:09:31 PM PDT 24
Peak memory 235208 kb
Host smart-709d6b5b-d3ae-48a3-b96d-a2faabc24192
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898898174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.3898898174
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.1444790425
Short name T352
Test name
Test status
Simulation time 10877957350 ps
CPU time 42.04 seconds
Started Mar 26 03:07:06 PM PDT 24
Finished Mar 26 03:07:49 PM PDT 24
Peak memory 216800 kb
Host smart-3059537d-cdba-4cc3-8906-eac69873549c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444790425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1444790425
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.4140675032
Short name T39
Test name
Test status
Simulation time 952625259 ps
CPU time 4.54 seconds
Started Mar 26 03:07:04 PM PDT 24
Finished Mar 26 03:07:10 PM PDT 24
Peak memory 216656 kb
Host smart-37ecf700-3e26-4b16-be96-b3e3d351d732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140675032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.4140675032
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.3216581349
Short name T891
Test name
Test status
Simulation time 286585629 ps
CPU time 3.64 seconds
Started Mar 26 03:07:05 PM PDT 24
Finished Mar 26 03:07:09 PM PDT 24
Peak memory 216636 kb
Host smart-d16e827b-1146-432d-b27d-7c886a5dede5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216581349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.3216581349
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.713985657
Short name T849
Test name
Test status
Simulation time 31996034 ps
CPU time 0.85 seconds
Started Mar 26 03:07:09 PM PDT 24
Finished Mar 26 03:07:09 PM PDT 24
Peak memory 206136 kb
Host smart-cc91238e-fff1-4a93-a4d1-f5199de0e1f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713985657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.713985657
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.1991789404
Short name T480
Test name
Test status
Simulation time 2111362599 ps
CPU time 11.48 seconds
Started Mar 26 03:07:07 PM PDT 24
Finished Mar 26 03:07:18 PM PDT 24
Peak memory 234628 kb
Host smart-e60b635a-16d3-4823-b7f4-fec221696df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991789404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.1991789404
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.3072668725
Short name T912
Test name
Test status
Simulation time 14267823 ps
CPU time 0.76 seconds
Started Mar 26 03:04:52 PM PDT 24
Finished Mar 26 03:04:53 PM PDT 24
Peak memory 205820 kb
Host smart-3b60dddb-93cb-4c30-9d6a-b772f0b5df06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072668725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.3
072668725
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.1209366197
Short name T848
Test name
Test status
Simulation time 110280960 ps
CPU time 3.41 seconds
Started Mar 26 03:04:53 PM PDT 24
Finished Mar 26 03:04:57 PM PDT 24
Peak memory 219796 kb
Host smart-928f94f4-df64-4e52-9cfc-989c7cc0a0e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209366197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.1209366197
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.2301333884
Short name T400
Test name
Test status
Simulation time 17320544 ps
CPU time 0.75 seconds
Started Mar 26 03:04:42 PM PDT 24
Finished Mar 26 03:04:42 PM PDT 24
Peak memory 207204 kb
Host smart-30875a01-6737-4029-a0b7-494b1931ebce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301333884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.2301333884
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.1333522924
Short name T573
Test name
Test status
Simulation time 239936958592 ps
CPU time 134.31 seconds
Started Mar 26 03:04:55 PM PDT 24
Finished Mar 26 03:07:10 PM PDT 24
Peak memory 250564 kb
Host smart-f0af6294-c842-4932-963e-2c2d2a29e4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333522924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.1333522924
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.1230351349
Short name T960
Test name
Test status
Simulation time 50139865877 ps
CPU time 67.06 seconds
Started Mar 26 03:04:55 PM PDT 24
Finished Mar 26 03:06:03 PM PDT 24
Peak memory 236668 kb
Host smart-529de442-cabc-4c9b-8ec2-800ac34bd9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230351349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.1230351349
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.3606245235
Short name T896
Test name
Test status
Simulation time 85590195369 ps
CPU time 140.65 seconds
Started Mar 26 03:04:51 PM PDT 24
Finished Mar 26 03:07:12 PM PDT 24
Peak memory 249656 kb
Host smart-634e47f9-67b7-4dd8-842c-0b69a98941ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606245235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.3606245235
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.2521624625
Short name T780
Test name
Test status
Simulation time 7504398485 ps
CPU time 33.24 seconds
Started Mar 26 03:04:54 PM PDT 24
Finished Mar 26 03:05:28 PM PDT 24
Peak memory 233140 kb
Host smart-985a3de8-bc5d-4627-9759-eeb41460783f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521624625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.2521624625
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.4176600963
Short name T640
Test name
Test status
Simulation time 828407432 ps
CPU time 4.23 seconds
Started Mar 26 03:04:45 PM PDT 24
Finished Mar 26 03:04:49 PM PDT 24
Peak memory 219888 kb
Host smart-e4321737-bd30-4f7c-9b8f-8638c8062533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176600963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.4176600963
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.4110323914
Short name T228
Test name
Test status
Simulation time 25050228763 ps
CPU time 20.17 seconds
Started Mar 26 03:04:44 PM PDT 24
Finished Mar 26 03:05:05 PM PDT 24
Peak memory 233176 kb
Host smart-8d0707fe-f57f-4e82-9f2f-137fa0ee99de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110323914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.4110323914
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.1676615600
Short name T11
Test name
Test status
Simulation time 218941738 ps
CPU time 5.38 seconds
Started Mar 26 03:04:42 PM PDT 24
Finished Mar 26 03:04:48 PM PDT 24
Peak memory 234128 kb
Host smart-8de4a130-5492-4fc4-a992-fed6b2ab58ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676615600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.1676615600
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.2852529893
Short name T826
Test name
Test status
Simulation time 3111576219 ps
CPU time 11.3 seconds
Started Mar 26 03:04:45 PM PDT 24
Finished Mar 26 03:04:56 PM PDT 24
Peak memory 239160 kb
Host smart-07037f06-e686-4dcd-8bc9-de3a7a7400e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852529893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2852529893
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_ram_cfg.1908633012
Short name T63
Test name
Test status
Simulation time 46354042 ps
CPU time 0.81 seconds
Started Mar 26 03:04:46 PM PDT 24
Finished Mar 26 03:04:47 PM PDT 24
Peak memory 216476 kb
Host smart-5f277d14-0f0d-4d71-9aab-ae3c825c6ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908633012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_ram_cfg.1908633012
Directory /workspace/4.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.3724659094
Short name T359
Test name
Test status
Simulation time 1105224263 ps
CPU time 4.23 seconds
Started Mar 26 03:04:58 PM PDT 24
Finished Mar 26 03:05:02 PM PDT 24
Peak memory 223532 kb
Host smart-da71188e-230a-48b7-ac56-e4a2e64e621e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3724659094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.3724659094
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.3746561718
Short name T68
Test name
Test status
Simulation time 271901127 ps
CPU time 1.17 seconds
Started Mar 26 03:04:54 PM PDT 24
Finished Mar 26 03:04:56 PM PDT 24
Peak memory 235560 kb
Host smart-59c7bc4a-8f06-4f63-b7e5-c43214597a1d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746561718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.3746561718
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.819414305
Short name T697
Test name
Test status
Simulation time 837908741 ps
CPU time 13.1 seconds
Started Mar 26 03:04:45 PM PDT 24
Finished Mar 26 03:04:58 PM PDT 24
Peak memory 216828 kb
Host smart-bef4f268-4a53-499d-8992-456f8599ef51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819414305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.819414305
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.671413350
Short name T301
Test name
Test status
Simulation time 35672853797 ps
CPU time 21.12 seconds
Started Mar 26 03:04:46 PM PDT 24
Finished Mar 26 03:05:08 PM PDT 24
Peak memory 216692 kb
Host smart-96f56e39-8604-403b-a3a8-0b9c49553839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671413350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.671413350
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.397280929
Short name T504
Test name
Test status
Simulation time 91364495 ps
CPU time 1.68 seconds
Started Mar 26 03:04:48 PM PDT 24
Finished Mar 26 03:04:50 PM PDT 24
Peak memory 216660 kb
Host smart-31dc4791-df74-46ff-adec-614acc2b2051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397280929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.397280929
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.3833270630
Short name T710
Test name
Test status
Simulation time 679644206 ps
CPU time 0.99 seconds
Started Mar 26 03:04:48 PM PDT 24
Finished Mar 26 03:04:49 PM PDT 24
Peak memory 206152 kb
Host smart-cbc760de-b47c-473f-b067-43ced4ae42df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833270630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.3833270630
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.2527954135
Short name T174
Test name
Test status
Simulation time 12357061380 ps
CPU time 22.69 seconds
Started Mar 26 03:04:51 PM PDT 24
Finished Mar 26 03:05:14 PM PDT 24
Peak memory 239824 kb
Host smart-fac27056-fcfe-4200-938d-b1486b924bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527954135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.2527954135
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.2647640792
Short name T463
Test name
Test status
Simulation time 19024755 ps
CPU time 0.73 seconds
Started Mar 26 03:07:05 PM PDT 24
Finished Mar 26 03:07:06 PM PDT 24
Peak memory 205248 kb
Host smart-7983c16b-34ec-48a0-bcd3-5096d5e739d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647640792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
2647640792
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.178215535
Short name T745
Test name
Test status
Simulation time 147816651 ps
CPU time 2.6 seconds
Started Mar 26 03:07:04 PM PDT 24
Finished Mar 26 03:07:08 PM PDT 24
Peak memory 232896 kb
Host smart-ad810e65-ca07-440e-88c1-4bbb7c0cff1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178215535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.178215535
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.1988510539
Short name T8
Test name
Test status
Simulation time 12799837 ps
CPU time 0.76 seconds
Started Mar 26 03:07:02 PM PDT 24
Finished Mar 26 03:07:06 PM PDT 24
Peak memory 205964 kb
Host smart-7e391906-e791-48e2-978c-b9e9b283fdef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988510539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.1988510539
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.2064687459
Short name T229
Test name
Test status
Simulation time 1250002445 ps
CPU time 13.64 seconds
Started Mar 26 03:07:09 PM PDT 24
Finished Mar 26 03:07:22 PM PDT 24
Peak memory 238176 kb
Host smart-5576d8fd-c5f3-4f7b-8d1e-c8a977424e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064687459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.2064687459
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.99917903
Short name T15
Test name
Test status
Simulation time 58042779655 ps
CPU time 96.31 seconds
Started Mar 26 03:07:08 PM PDT 24
Finished Mar 26 03:08:44 PM PDT 24
Peak memory 235388 kb
Host smart-77be9f1f-fbca-47c2-998f-a315a50a613a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99917903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.99917903
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.691772310
Short name T402
Test name
Test status
Simulation time 21465736684 ps
CPU time 166.47 seconds
Started Mar 26 03:07:08 PM PDT 24
Finished Mar 26 03:09:55 PM PDT 24
Peak memory 257116 kb
Host smart-e17e3941-2da6-4dee-a50c-b1634ddd9437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691772310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idle
.691772310
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.2153350765
Short name T159
Test name
Test status
Simulation time 1465094944 ps
CPU time 25.67 seconds
Started Mar 26 03:07:03 PM PDT 24
Finished Mar 26 03:07:31 PM PDT 24
Peak memory 249888 kb
Host smart-91d54a33-7926-42b5-aac6-dcb8c1197d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153350765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2153350765
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.3126758857
Short name T175
Test name
Test status
Simulation time 705507451 ps
CPU time 5.07 seconds
Started Mar 26 03:07:06 PM PDT 24
Finished Mar 26 03:07:11 PM PDT 24
Peak memory 224772 kb
Host smart-ba003ed3-7a38-4d18-bff7-8c43920d512c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126758857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.3126758857
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.1573718391
Short name T880
Test name
Test status
Simulation time 1530547674 ps
CPU time 5.76 seconds
Started Mar 26 03:07:12 PM PDT 24
Finished Mar 26 03:07:18 PM PDT 24
Peak memory 234188 kb
Host smart-0bc9d8df-9e38-46b2-9c91-730f273f59f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573718391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.1573718391
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.3713794309
Short name T224
Test name
Test status
Simulation time 70099916041 ps
CPU time 47.92 seconds
Started Mar 26 03:07:04 PM PDT 24
Finished Mar 26 03:07:53 PM PDT 24
Peak memory 246816 kb
Host smart-ac02750a-ca08-4bf8-88ac-0cd536e5b615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713794309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.3713794309
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.758094375
Short name T28
Test name
Test status
Simulation time 2816344589 ps
CPU time 9.31 seconds
Started Mar 26 03:07:04 PM PDT 24
Finished Mar 26 03:07:14 PM PDT 24
Peak memory 249884 kb
Host smart-2a959554-9806-43eb-9157-72046c951da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758094375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.758094375
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.1463629361
Short name T6
Test name
Test status
Simulation time 724347234 ps
CPU time 3.65 seconds
Started Mar 26 03:07:04 PM PDT 24
Finished Mar 26 03:07:09 PM PDT 24
Peak memory 221620 kb
Host smart-76bfc4a5-700f-4738-b953-92dbef379e18
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1463629361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.1463629361
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.1443094127
Short name T62
Test name
Test status
Simulation time 74978193420 ps
CPU time 108.41 seconds
Started Mar 26 03:07:05 PM PDT 24
Finished Mar 26 03:08:54 PM PDT 24
Peak memory 249952 kb
Host smart-405a3031-6d95-42f4-b617-a09e63919911
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443094127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.1443094127
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.1110805999
Short name T623
Test name
Test status
Simulation time 14630519912 ps
CPU time 19.32 seconds
Started Mar 26 03:07:04 PM PDT 24
Finished Mar 26 03:07:24 PM PDT 24
Peak memory 216768 kb
Host smart-4fd70c31-6e3b-4099-a7da-3a1d5db3c22a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110805999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.1110805999
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.668419542
Short name T674
Test name
Test status
Simulation time 50407766 ps
CPU time 0.98 seconds
Started Mar 26 03:07:04 PM PDT 24
Finished Mar 26 03:07:06 PM PDT 24
Peak memory 206272 kb
Host smart-41b77046-da22-4b44-a4c5-67313a197506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668419542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.668419542
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.434906677
Short name T390
Test name
Test status
Simulation time 17146024 ps
CPU time 0.82 seconds
Started Mar 26 03:07:07 PM PDT 24
Finished Mar 26 03:07:08 PM PDT 24
Peak memory 206208 kb
Host smart-d28d8961-6130-495c-997c-6a8c108b7cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434906677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.434906677
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.1625413012
Short name T834
Test name
Test status
Simulation time 37898806 ps
CPU time 0.75 seconds
Started Mar 26 03:07:06 PM PDT 24
Finished Mar 26 03:07:07 PM PDT 24
Peak memory 206116 kb
Host smart-4eae58ea-bfdd-43a8-9c2c-5318a00b5c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625413012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.1625413012
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.1201489784
Short name T554
Test name
Test status
Simulation time 6863915453 ps
CPU time 10.29 seconds
Started Mar 26 03:07:11 PM PDT 24
Finished Mar 26 03:07:22 PM PDT 24
Peak memory 249528 kb
Host smart-5b0f7cbf-012a-403b-8274-d83b5664e013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201489784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.1201489784
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.2176120052
Short name T828
Test name
Test status
Simulation time 57643747 ps
CPU time 0.71 seconds
Started Mar 26 03:07:13 PM PDT 24
Finished Mar 26 03:07:15 PM PDT 24
Peak memory 205856 kb
Host smart-165732fc-f0e1-4f04-8b53-33d1d643482b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176120052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
2176120052
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.2945809565
Short name T578
Test name
Test status
Simulation time 37835377 ps
CPU time 2.3 seconds
Started Mar 26 03:07:15 PM PDT 24
Finished Mar 26 03:07:17 PM PDT 24
Peak memory 234528 kb
Host smart-e810b68e-8b8d-4bad-8115-1b5f60b9db16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945809565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.2945809565
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.1623760800
Short name T723
Test name
Test status
Simulation time 223249747 ps
CPU time 0.83 seconds
Started Mar 26 03:07:10 PM PDT 24
Finished Mar 26 03:07:11 PM PDT 24
Peak memory 205940 kb
Host smart-746387c4-0af3-4312-a475-33f46bdc6276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623760800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.1623760800
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.2372922723
Short name T889
Test name
Test status
Simulation time 17805850351 ps
CPU time 18.82 seconds
Started Mar 26 03:07:15 PM PDT 24
Finished Mar 26 03:07:35 PM PDT 24
Peak memory 249612 kb
Host smart-f286aa29-e460-4726-8446-f8b4c9cc410a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372922723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.2372922723
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.1152955917
Short name T27
Test name
Test status
Simulation time 5338987753 ps
CPU time 50.38 seconds
Started Mar 26 03:07:14 PM PDT 24
Finished Mar 26 03:08:05 PM PDT 24
Peak memory 233076 kb
Host smart-2505a732-7be2-4fe0-a82d-8cd3d000f1df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152955917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.1152955917
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.28586251
Short name T961
Test name
Test status
Simulation time 11810894762 ps
CPU time 147.38 seconds
Started Mar 26 03:07:15 PM PDT 24
Finished Mar 26 03:09:44 PM PDT 24
Peak memory 265916 kb
Host smart-d4abba42-9ebc-4b8c-8353-8ebbe3f38a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28586251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idle.28586251
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.2993640566
Short name T846
Test name
Test status
Simulation time 1691953480 ps
CPU time 8.48 seconds
Started Mar 26 03:07:13 PM PDT 24
Finished Mar 26 03:07:22 PM PDT 24
Peak memory 229940 kb
Host smart-ab8440ee-8602-4519-8f4d-5cfe9ed0abfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993640566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.2993640566
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.223726027
Short name T83
Test name
Test status
Simulation time 2915022570 ps
CPU time 4.43 seconds
Started Mar 26 03:07:07 PM PDT 24
Finished Mar 26 03:07:12 PM PDT 24
Peak memory 225016 kb
Host smart-97c717b7-e03d-45ca-af04-2ecb2e8791ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223726027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.223726027
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.1221564596
Short name T446
Test name
Test status
Simulation time 774513071 ps
CPU time 13.74 seconds
Started Mar 26 03:07:05 PM PDT 24
Finished Mar 26 03:07:19 PM PDT 24
Peak memory 229920 kb
Host smart-958ee86c-f4d1-4388-9042-1a0b4543f14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221564596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.1221564596
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.42569224
Short name T645
Test name
Test status
Simulation time 10890391868 ps
CPU time 18.34 seconds
Started Mar 26 03:07:09 PM PDT 24
Finished Mar 26 03:07:28 PM PDT 24
Peak memory 224960 kb
Host smart-f5900859-6a0c-4df6-889f-6bc795571221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42569224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap.42569224
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.3788452757
Short name T517
Test name
Test status
Simulation time 6555222159 ps
CPU time 12.39 seconds
Started Mar 26 03:07:06 PM PDT 24
Finished Mar 26 03:07:18 PM PDT 24
Peak memory 224476 kb
Host smart-f25e2fcb-40cc-4eea-9365-1e81ed2d213f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788452757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.3788452757
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.3014114111
Short name T835
Test name
Test status
Simulation time 881114916 ps
CPU time 4.53 seconds
Started Mar 26 03:07:14 PM PDT 24
Finished Mar 26 03:07:19 PM PDT 24
Peak memory 219724 kb
Host smart-94c80478-86ec-4cc8-b804-b1caeb23e583
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3014114111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.3014114111
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.2489379521
Short name T506
Test name
Test status
Simulation time 17207476426 ps
CPU time 167.48 seconds
Started Mar 26 03:07:13 PM PDT 24
Finished Mar 26 03:10:01 PM PDT 24
Peak memory 253476 kb
Host smart-39558b45-7f55-4fe8-a687-6348c4319cad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489379521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.2489379521
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.3994191257
Short name T844
Test name
Test status
Simulation time 27591176635 ps
CPU time 17.35 seconds
Started Mar 26 03:07:06 PM PDT 24
Finished Mar 26 03:07:23 PM PDT 24
Peak memory 216752 kb
Host smart-c55c4b81-1fe9-4c0c-b5ce-6bfab0cf9fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994191257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.3994191257
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.4068688739
Short name T943
Test name
Test status
Simulation time 1567520377 ps
CPU time 7.19 seconds
Started Mar 26 03:07:03 PM PDT 24
Finished Mar 26 03:07:12 PM PDT 24
Peak memory 216616 kb
Host smart-a379e8de-4532-4703-bb3c-1cce5ac9e123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068688739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.4068688739
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.2747790117
Short name T560
Test name
Test status
Simulation time 340574316 ps
CPU time 4.36 seconds
Started Mar 26 03:07:04 PM PDT 24
Finished Mar 26 03:07:09 PM PDT 24
Peak memory 216508 kb
Host smart-19c28971-80f5-4d64-a017-82d1e58e143d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747790117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.2747790117
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.1825925781
Short name T593
Test name
Test status
Simulation time 103441384 ps
CPU time 1.07 seconds
Started Mar 26 03:07:03 PM PDT 24
Finished Mar 26 03:07:06 PM PDT 24
Peak memory 206688 kb
Host smart-046e20fa-3927-40ce-a700-c7545c03410b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825925781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.1825925781
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.3666549061
Short name T807
Test name
Test status
Simulation time 22850995719 ps
CPU time 15.23 seconds
Started Mar 26 03:07:04 PM PDT 24
Finished Mar 26 03:07:20 PM PDT 24
Peak memory 238716 kb
Host smart-369edaa2-5ffd-4fe5-ae13-db446f0afdfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666549061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.3666549061
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.129009303
Short name T863
Test name
Test status
Simulation time 14708263 ps
CPU time 0.72 seconds
Started Mar 26 03:07:16 PM PDT 24
Finished Mar 26 03:07:17 PM PDT 24
Peak memory 206152 kb
Host smart-f7b8c635-9910-4212-bfec-a99ca43b2902
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129009303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.129009303
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.2260072222
Short name T545
Test name
Test status
Simulation time 83934400 ps
CPU time 3.12 seconds
Started Mar 26 03:07:14 PM PDT 24
Finished Mar 26 03:07:17 PM PDT 24
Peak memory 235732 kb
Host smart-8d3427b6-2db5-4595-a427-f019d1abc55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260072222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.2260072222
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.2892481799
Short name T279
Test name
Test status
Simulation time 49962035 ps
CPU time 0.76 seconds
Started Mar 26 03:07:14 PM PDT 24
Finished Mar 26 03:07:15 PM PDT 24
Peak memory 207380 kb
Host smart-15a9a28a-9b10-40d8-b577-aa035aedaf2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892481799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2892481799
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.3634490327
Short name T592
Test name
Test status
Simulation time 13360460676 ps
CPU time 51.73 seconds
Started Mar 26 03:07:14 PM PDT 24
Finished Mar 26 03:08:06 PM PDT 24
Peak memory 257724 kb
Host smart-b150f668-4146-497d-acec-451fdf2e7c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634490327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.3634490327
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.3471165766
Short name T26
Test name
Test status
Simulation time 15063643925 ps
CPU time 70.21 seconds
Started Mar 26 03:07:15 PM PDT 24
Finished Mar 26 03:08:26 PM PDT 24
Peak memory 257144 kb
Host smart-639365e0-8c20-4825-a876-50fcf32fa965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471165766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.3471165766
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.2587705239
Short name T425
Test name
Test status
Simulation time 17422284265 ps
CPU time 91.8 seconds
Started Mar 26 03:07:13 PM PDT 24
Finished Mar 26 03:08:44 PM PDT 24
Peak memory 255764 kb
Host smart-8b177e14-6648-42d2-8b3d-b9d757a67c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587705239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.2587705239
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.66934653
Short name T123
Test name
Test status
Simulation time 1281790723 ps
CPU time 16.96 seconds
Started Mar 26 03:07:13 PM PDT 24
Finished Mar 26 03:07:30 PM PDT 24
Peak memory 247936 kb
Host smart-bfa474a4-e0eb-4b2a-bd0f-56942c6b4931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66934653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.66934653
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.3179743671
Short name T620
Test name
Test status
Simulation time 8658704229 ps
CPU time 8.43 seconds
Started Mar 26 03:07:11 PM PDT 24
Finished Mar 26 03:07:20 PM PDT 24
Peak memory 234752 kb
Host smart-7e9212af-7045-4ca9-8f9e-48ab278eafb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179743671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.3179743671
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.4253089565
Short name T868
Test name
Test status
Simulation time 8799389385 ps
CPU time 12.29 seconds
Started Mar 26 03:07:15 PM PDT 24
Finished Mar 26 03:07:28 PM PDT 24
Peak memory 249592 kb
Host smart-4f4f3a94-5211-4d08-8cb9-bafd96f2caa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253089565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.4253089565
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.2089499836
Short name T639
Test name
Test status
Simulation time 7972030777 ps
CPU time 12.35 seconds
Started Mar 26 03:07:16 PM PDT 24
Finished Mar 26 03:07:29 PM PDT 24
Peak memory 219332 kb
Host smart-47927de3-864f-406f-b976-c58a1d4550ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089499836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.2089499836
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.293844442
Short name T215
Test name
Test status
Simulation time 12324779185 ps
CPU time 7.56 seconds
Started Mar 26 03:07:15 PM PDT 24
Finished Mar 26 03:07:24 PM PDT 24
Peak memory 219236 kb
Host smart-b44dccb9-ac3b-4537-869d-4769eda707c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293844442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.293844442
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.3421215775
Short name T325
Test name
Test status
Simulation time 632334547 ps
CPU time 4.99 seconds
Started Mar 26 03:07:13 PM PDT 24
Finished Mar 26 03:07:19 PM PDT 24
Peak memory 222268 kb
Host smart-3f75cee8-f56c-4281-9334-00586e951197
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3421215775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.3421215775
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.2906093413
Short name T138
Test name
Test status
Simulation time 9741482858 ps
CPU time 60.94 seconds
Started Mar 26 03:07:15 PM PDT 24
Finished Mar 26 03:08:17 PM PDT 24
Peak memory 253920 kb
Host smart-c7a5fec4-061e-47b7-9cd5-7134646bf41b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906093413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.2906093413
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.210828859
Short name T145
Test name
Test status
Simulation time 1919361514 ps
CPU time 8.28 seconds
Started Mar 26 03:07:16 PM PDT 24
Finished Mar 26 03:07:24 PM PDT 24
Peak memory 216832 kb
Host smart-c5ac3c50-d9fa-4d17-8c96-31b29e8f89b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210828859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.210828859
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.3241421865
Short name T366
Test name
Test status
Simulation time 1172086623 ps
CPU time 7.38 seconds
Started Mar 26 03:07:14 PM PDT 24
Finished Mar 26 03:07:22 PM PDT 24
Peak memory 216508 kb
Host smart-583cd784-bafd-460c-ac9b-26f8d7798f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241421865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3241421865
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.1931584379
Short name T436
Test name
Test status
Simulation time 660807240 ps
CPU time 6.42 seconds
Started Mar 26 03:07:13 PM PDT 24
Finished Mar 26 03:07:20 PM PDT 24
Peak memory 216596 kb
Host smart-e8f243e1-d496-4158-a955-a9cfe460843e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931584379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.1931584379
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.2621638169
Short name T491
Test name
Test status
Simulation time 34571919 ps
CPU time 0.76 seconds
Started Mar 26 03:07:15 PM PDT 24
Finished Mar 26 03:07:17 PM PDT 24
Peak memory 206064 kb
Host smart-a17458d2-9b39-4309-aec1-6f9bb2c786c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621638169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.2621638169
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.1044429543
Short name T907
Test name
Test status
Simulation time 766870711 ps
CPU time 9.54 seconds
Started Mar 26 03:07:17 PM PDT 24
Finished Mar 26 03:07:27 PM PDT 24
Peak memory 248820 kb
Host smart-23d69544-72ef-42dc-bbf2-f37db1dc46ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044429543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.1044429543
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.2860412381
Short name T836
Test name
Test status
Simulation time 15230604 ps
CPU time 0.72 seconds
Started Mar 26 03:07:14 PM PDT 24
Finished Mar 26 03:07:15 PM PDT 24
Peak memory 205840 kb
Host smart-e6536673-739a-49ac-871a-4de3a265a578
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860412381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
2860412381
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.3216509419
Short name T330
Test name
Test status
Simulation time 325492152 ps
CPU time 4 seconds
Started Mar 26 03:07:14 PM PDT 24
Finished Mar 26 03:07:18 PM PDT 24
Peak memory 234236 kb
Host smart-5bd535ae-f425-457e-b5fd-101c7f93b0cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216509419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.3216509419
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.3021888971
Short name T284
Test name
Test status
Simulation time 52462684 ps
CPU time 0.76 seconds
Started Mar 26 03:07:14 PM PDT 24
Finished Mar 26 03:07:15 PM PDT 24
Peak memory 205968 kb
Host smart-0e1eff6c-fc3f-44c7-b3c9-ab99a61630da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021888971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.3021888971
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.2372705224
Short name T586
Test name
Test status
Simulation time 172543879305 ps
CPU time 176.25 seconds
Started Mar 26 03:07:12 PM PDT 24
Finished Mar 26 03:10:09 PM PDT 24
Peak memory 258916 kb
Host smart-0077e296-e2e4-4f27-9d16-16db4f70d1dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372705224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.2372705224
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.2996332848
Short name T516
Test name
Test status
Simulation time 64460431697 ps
CPU time 53.68 seconds
Started Mar 26 03:07:16 PM PDT 24
Finished Mar 26 03:08:10 PM PDT 24
Peak memory 238284 kb
Host smart-8998141e-6e23-4151-ba69-aec81220079f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996332848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.2996332848
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.3513641876
Short name T241
Test name
Test status
Simulation time 29818571318 ps
CPU time 147.49 seconds
Started Mar 26 03:07:16 PM PDT 24
Finished Mar 26 03:09:44 PM PDT 24
Peak memory 273636 kb
Host smart-8414dcae-88fc-47bc-a5a2-db757ee95b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513641876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.3513641876
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.1195109197
Short name T121
Test name
Test status
Simulation time 166288573 ps
CPU time 4.8 seconds
Started Mar 26 03:07:17 PM PDT 24
Finished Mar 26 03:07:21 PM PDT 24
Peak memory 224856 kb
Host smart-34dfc1b7-0d42-4416-b807-1cf780486717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195109197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.1195109197
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.435981558
Short name T797
Test name
Test status
Simulation time 3118731285 ps
CPU time 11.93 seconds
Started Mar 26 03:07:15 PM PDT 24
Finished Mar 26 03:07:28 PM PDT 24
Peak memory 220064 kb
Host smart-ad08eaa8-8c17-4af5-857d-547fd35bc6e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435981558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.435981558
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.4210942271
Short name T201
Test name
Test status
Simulation time 31773462452 ps
CPU time 46.15 seconds
Started Mar 26 03:07:16 PM PDT 24
Finished Mar 26 03:08:02 PM PDT 24
Peak memory 233796 kb
Host smart-92ff45cc-05d0-4c5c-81f9-ec84e135264f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210942271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.4210942271
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.871662994
Short name T682
Test name
Test status
Simulation time 22111541114 ps
CPU time 13.18 seconds
Started Mar 26 03:07:13 PM PDT 24
Finished Mar 26 03:07:27 PM PDT 24
Peak memory 235632 kb
Host smart-fae49490-6e71-4412-a652-fe42268991f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871662994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap
.871662994
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.3622474470
Short name T235
Test name
Test status
Simulation time 24253889820 ps
CPU time 18.26 seconds
Started Mar 26 03:07:17 PM PDT 24
Finished Mar 26 03:07:35 PM PDT 24
Peak memory 239696 kb
Host smart-c5a3c872-1dd2-497f-9b12-5cb971da6349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622474470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.3622474470
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.1073967258
Short name T827
Test name
Test status
Simulation time 406996114 ps
CPU time 3.7 seconds
Started Mar 26 03:07:13 PM PDT 24
Finished Mar 26 03:07:18 PM PDT 24
Peak memory 220564 kb
Host smart-c7cdec8b-9589-4e54-b08f-4139f6004c4f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1073967258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.1073967258
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.3836521639
Short name T14
Test name
Test status
Simulation time 59255104406 ps
CPU time 147.73 seconds
Started Mar 26 03:07:16 PM PDT 24
Finished Mar 26 03:09:44 PM PDT 24
Peak memory 271516 kb
Host smart-3af26bce-bdeb-4a29-b440-acaaba2656b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836521639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.3836521639
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.2504577325
Short name T667
Test name
Test status
Simulation time 29899883480 ps
CPU time 37.11 seconds
Started Mar 26 03:07:15 PM PDT 24
Finished Mar 26 03:07:53 PM PDT 24
Peak memory 216776 kb
Host smart-ade75ecf-2d95-4b8a-ad79-5c46f1e14aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504577325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.2504577325
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.4102787471
Short name T722
Test name
Test status
Simulation time 2128855783 ps
CPU time 5.97 seconds
Started Mar 26 03:07:13 PM PDT 24
Finished Mar 26 03:07:19 PM PDT 24
Peak memory 216540 kb
Host smart-311a098b-d6b0-4d1c-a4c9-80823df8013b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102787471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.4102787471
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.251879774
Short name T777
Test name
Test status
Simulation time 160095661 ps
CPU time 1.01 seconds
Started Mar 26 03:07:16 PM PDT 24
Finished Mar 26 03:07:17 PM PDT 24
Peak memory 207696 kb
Host smart-d0639182-e9f8-4cf4-b231-c1e8bff69bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251879774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.251879774
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.3056127755
Short name T465
Test name
Test status
Simulation time 17621598 ps
CPU time 0.74 seconds
Started Mar 26 03:07:14 PM PDT 24
Finished Mar 26 03:07:15 PM PDT 24
Peak memory 206092 kb
Host smart-0cff3525-19a7-450e-8b07-91c0af9090e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056127755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.3056127755
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.564697412
Short name T929
Test name
Test status
Simulation time 15377449835 ps
CPU time 19.13 seconds
Started Mar 26 03:07:15 PM PDT 24
Finished Mar 26 03:07:35 PM PDT 24
Peak memory 244580 kb
Host smart-6b36c3c8-6802-4a23-9e19-e22799e8bcab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564697412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.564697412
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.2627948190
Short name T293
Test name
Test status
Simulation time 31108067 ps
CPU time 0.71 seconds
Started Mar 26 03:07:21 PM PDT 24
Finished Mar 26 03:07:22 PM PDT 24
Peak memory 206108 kb
Host smart-65f74c3c-d5ea-4e4e-ba1e-9c4dd40bd9b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627948190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
2627948190
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.935407520
Short name T946
Test name
Test status
Simulation time 112494260 ps
CPU time 2.34 seconds
Started Mar 26 03:07:23 PM PDT 24
Finished Mar 26 03:07:25 PM PDT 24
Peak memory 219228 kb
Host smart-84580385-a41e-43eb-b38a-88ff2d910029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935407520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.935407520
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.1869872129
Short name T343
Test name
Test status
Simulation time 38426849 ps
CPU time 0.76 seconds
Started Mar 26 03:07:24 PM PDT 24
Finished Mar 26 03:07:25 PM PDT 24
Peak memory 207020 kb
Host smart-0b29d4b6-7da1-434c-a38e-9561a5b1c6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869872129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.1869872129
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.442675950
Short name T665
Test name
Test status
Simulation time 1430135666 ps
CPU time 7.39 seconds
Started Mar 26 03:07:22 PM PDT 24
Finished Mar 26 03:07:29 PM PDT 24
Peak memory 234192 kb
Host smart-ea881221-99f2-4db5-a0b9-7397279ab296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442675950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.442675950
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.2651915184
Short name T302
Test name
Test status
Simulation time 1244502814 ps
CPU time 2.84 seconds
Started Mar 26 03:07:22 PM PDT 24
Finished Mar 26 03:07:24 PM PDT 24
Peak memory 218936 kb
Host smart-57ad5896-909d-493a-a6dc-0aedcf35b8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651915184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.2651915184
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.2644763552
Short name T527
Test name
Test status
Simulation time 7673437138 ps
CPU time 23.51 seconds
Started Mar 26 03:07:23 PM PDT 24
Finished Mar 26 03:07:47 PM PDT 24
Peak memory 235620 kb
Host smart-58a06227-a01d-464f-b206-3c073b9b8ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644763552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.2644763552
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.698774148
Short name T255
Test name
Test status
Simulation time 1757222058 ps
CPU time 10.78 seconds
Started Mar 26 03:07:25 PM PDT 24
Finished Mar 26 03:07:36 PM PDT 24
Peak memory 241236 kb
Host smart-232e4e9b-abee-4385-9d28-5d6750f30065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698774148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap
.698774148
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.4268157414
Short name T374
Test name
Test status
Simulation time 1271641708 ps
CPU time 10.41 seconds
Started Mar 26 03:07:26 PM PDT 24
Finished Mar 26 03:07:37 PM PDT 24
Peak memory 250872 kb
Host smart-cb7f857b-f3f4-48f7-8928-b8e60a32400b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268157414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.4268157414
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.4134746461
Short name T38
Test name
Test status
Simulation time 1507084043 ps
CPU time 6.11 seconds
Started Mar 26 03:07:24 PM PDT 24
Finished Mar 26 03:07:31 PM PDT 24
Peak memory 222548 kb
Host smart-75da6264-1757-42f8-aa80-e264544f8751
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4134746461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.4134746461
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.1396249078
Short name T760
Test name
Test status
Simulation time 43975131190 ps
CPU time 23.81 seconds
Started Mar 26 03:07:26 PM PDT 24
Finished Mar 26 03:07:51 PM PDT 24
Peak memory 216952 kb
Host smart-50784bc3-3579-419c-8771-025500423d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396249078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.1396249078
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.3980402317
Short name T658
Test name
Test status
Simulation time 5002549340 ps
CPU time 7.7 seconds
Started Mar 26 03:07:22 PM PDT 24
Finished Mar 26 03:07:30 PM PDT 24
Peak memory 216796 kb
Host smart-d4d8bd97-d014-48d8-8632-68014541094b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980402317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.3980402317
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.1134152806
Short name T637
Test name
Test status
Simulation time 80938956 ps
CPU time 0.85 seconds
Started Mar 26 03:07:24 PM PDT 24
Finished Mar 26 03:07:25 PM PDT 24
Peak memory 206084 kb
Host smart-ed272ff6-6a06-4ebe-a95c-3351692bb9af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134152806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.1134152806
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.2273175571
Short name T685
Test name
Test status
Simulation time 171646832 ps
CPU time 0.93 seconds
Started Mar 26 03:07:24 PM PDT 24
Finished Mar 26 03:07:25 PM PDT 24
Peak memory 206052 kb
Host smart-13ffdedf-95a2-4d0f-a9b6-d11f5f0ca7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273175571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.2273175571
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.1808603041
Short name T200
Test name
Test status
Simulation time 627808670 ps
CPU time 8.8 seconds
Started Mar 26 03:07:23 PM PDT 24
Finished Mar 26 03:07:32 PM PDT 24
Peak memory 233548 kb
Host smart-e7bed322-4229-40de-ae4e-fc2d9dd86389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808603041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.1808603041
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.1401431280
Short name T57
Test name
Test status
Simulation time 44067661 ps
CPU time 0.72 seconds
Started Mar 26 03:07:27 PM PDT 24
Finished Mar 26 03:07:28 PM PDT 24
Peak memory 205812 kb
Host smart-d2c850ab-5fbf-4633-adcb-22c60141f4ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401431280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
1401431280
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.730723138
Short name T90
Test name
Test status
Simulation time 346710237 ps
CPU time 4.53 seconds
Started Mar 26 03:07:24 PM PDT 24
Finished Mar 26 03:07:28 PM PDT 24
Peak memory 224744 kb
Host smart-6c7e21c1-9224-458d-8cc8-0b6cdc1bfa39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730723138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.730723138
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.2687742255
Short name T17
Test name
Test status
Simulation time 24239084 ps
CPU time 0.81 seconds
Started Mar 26 03:07:23 PM PDT 24
Finished Mar 26 03:07:24 PM PDT 24
Peak memory 207020 kb
Host smart-8aa5ec40-d796-4046-93f3-87f42d0827a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687742255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.2687742255
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.90190565
Short name T248
Test name
Test status
Simulation time 38812427442 ps
CPU time 77.61 seconds
Started Mar 26 03:07:24 PM PDT 24
Finished Mar 26 03:08:42 PM PDT 24
Peak memory 251204 kb
Host smart-fe69494e-4d38-4a22-8286-cbc35333ea33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90190565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.90190565
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.2677407976
Short name T507
Test name
Test status
Simulation time 49314031906 ps
CPU time 340.47 seconds
Started Mar 26 03:07:22 PM PDT 24
Finished Mar 26 03:13:03 PM PDT 24
Peak memory 267848 kb
Host smart-3b8ee447-b992-4f43-b4b5-442e1a976b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677407976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.2677407976
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.562077856
Short name T204
Test name
Test status
Simulation time 714008116 ps
CPU time 8.23 seconds
Started Mar 26 03:07:25 PM PDT 24
Finished Mar 26 03:07:34 PM PDT 24
Peak memory 232156 kb
Host smart-77b9d1fe-e76f-482f-8218-6ac5b60cd227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562077856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.562077856
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.2155908725
Short name T794
Test name
Test status
Simulation time 2443850768 ps
CPU time 10.18 seconds
Started Mar 26 03:07:26 PM PDT 24
Finished Mar 26 03:07:36 PM PDT 24
Peak memory 220132 kb
Host smart-c7fe5d46-0fb7-487f-b226-3fe2c8083b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155908725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.2155908725
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.2343975533
Short name T327
Test name
Test status
Simulation time 1334634061 ps
CPU time 6.35 seconds
Started Mar 26 03:07:24 PM PDT 24
Finished Mar 26 03:07:31 PM PDT 24
Peak memory 240736 kb
Host smart-fac13661-9d8c-4a91-ac83-cbe15f8a9095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343975533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.2343975533
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.3536522092
Short name T12
Test name
Test status
Simulation time 960406097 ps
CPU time 8.31 seconds
Started Mar 26 03:07:25 PM PDT 24
Finished Mar 26 03:07:34 PM PDT 24
Peak memory 220484 kb
Host smart-f6944691-7506-4211-864d-934ebb05244a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536522092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.3536522092
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.1536166431
Short name T618
Test name
Test status
Simulation time 1386800887 ps
CPU time 10.09 seconds
Started Mar 26 03:07:24 PM PDT 24
Finished Mar 26 03:07:35 PM PDT 24
Peak memory 232068 kb
Host smart-71fc7a13-4781-4af4-939b-db85f44f804d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536166431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.1536166431
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.993677753
Short name T861
Test name
Test status
Simulation time 2905075509 ps
CPU time 4.86 seconds
Started Mar 26 03:07:22 PM PDT 24
Finished Mar 26 03:07:27 PM PDT 24
Peak memory 220508 kb
Host smart-6c0f8635-c4ec-4670-b734-7b3d88e51361
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=993677753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dire
ct.993677753
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.2335500610
Short name T142
Test name
Test status
Simulation time 685986470577 ps
CPU time 274.56 seconds
Started Mar 26 03:07:24 PM PDT 24
Finished Mar 26 03:11:59 PM PDT 24
Peak memory 266824 kb
Host smart-b219f004-d0ee-4e61-a311-4f44bb130447
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335500610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.2335500610
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.3576033165
Short name T274
Test name
Test status
Simulation time 3416340283 ps
CPU time 32.38 seconds
Started Mar 26 03:07:22 PM PDT 24
Finished Mar 26 03:07:55 PM PDT 24
Peak memory 221216 kb
Host smart-4d266559-0f53-4fa9-93cd-443af79ffc65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576033165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3576033165
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.2197038501
Short name T396
Test name
Test status
Simulation time 35902914482 ps
CPU time 19.57 seconds
Started Mar 26 03:07:25 PM PDT 24
Finished Mar 26 03:07:45 PM PDT 24
Peak memory 216748 kb
Host smart-6ccf1c81-5cd9-47b3-a1fa-dd091f52412f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197038501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.2197038501
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.2962261405
Short name T316
Test name
Test status
Simulation time 598640393 ps
CPU time 6.46 seconds
Started Mar 26 03:07:22 PM PDT 24
Finished Mar 26 03:07:28 PM PDT 24
Peak memory 216800 kb
Host smart-9d26e0b9-5a50-43e7-8710-e92db35a1365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962261405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.2962261405
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.1571739951
Short name T752
Test name
Test status
Simulation time 147800147 ps
CPU time 1.2 seconds
Started Mar 26 03:07:24 PM PDT 24
Finished Mar 26 03:07:26 PM PDT 24
Peak memory 207252 kb
Host smart-7ab34adc-b121-4b01-8c7e-359c1828bc6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571739951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.1571739951
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.1410168165
Short name T40
Test name
Test status
Simulation time 360651954 ps
CPU time 2.82 seconds
Started Mar 26 03:07:22 PM PDT 24
Finished Mar 26 03:07:25 PM PDT 24
Peak memory 233824 kb
Host smart-ed33c2b2-0df8-48ac-a3f7-12a30dcf123c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410168165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.1410168165
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.623473822
Short name T295
Test name
Test status
Simulation time 27865097 ps
CPU time 0.73 seconds
Started Mar 26 03:07:34 PM PDT 24
Finished Mar 26 03:07:36 PM PDT 24
Peak memory 205080 kb
Host smart-7d3378c5-dd72-457d-a72e-7a527283fca1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623473822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.623473822
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.1001559179
Short name T449
Test name
Test status
Simulation time 8330271625 ps
CPU time 8.1 seconds
Started Mar 26 03:07:25 PM PDT 24
Finished Mar 26 03:07:33 PM PDT 24
Peak memory 220636 kb
Host smart-1010def6-8427-4ae3-829f-4f4a41e19ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001559179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.1001559179
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.159229630
Short name T775
Test name
Test status
Simulation time 18293177 ps
CPU time 0.77 seconds
Started Mar 26 03:07:25 PM PDT 24
Finished Mar 26 03:07:26 PM PDT 24
Peak memory 205908 kb
Host smart-e58c0da3-2f31-4fdc-8603-c855935823ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159229630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.159229630
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.336993749
Short name T714
Test name
Test status
Simulation time 4148891150 ps
CPU time 55.41 seconds
Started Mar 26 03:07:26 PM PDT 24
Finished Mar 26 03:08:21 PM PDT 24
Peak memory 261504 kb
Host smart-78831ef5-8ec5-4c5e-90be-405170f6d286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336993749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.336993749
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.3163493589
Short name T262
Test name
Test status
Simulation time 15492631834 ps
CPU time 133.14 seconds
Started Mar 26 03:07:25 PM PDT 24
Finished Mar 26 03:09:39 PM PDT 24
Peak memory 249608 kb
Host smart-f4c4be0b-926a-40ee-9912-230c3a8df799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163493589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.3163493589
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.881781980
Short name T629
Test name
Test status
Simulation time 2600015243 ps
CPU time 19.23 seconds
Started Mar 26 03:07:23 PM PDT 24
Finished Mar 26 03:07:43 PM PDT 24
Peak memory 235168 kb
Host smart-18743b54-a601-4fa5-baba-a6407f28e978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881781980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.881781980
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.3674778766
Short name T298
Test name
Test status
Simulation time 542538169 ps
CPU time 3.69 seconds
Started Mar 26 03:07:22 PM PDT 24
Finished Mar 26 03:07:26 PM PDT 24
Peak memory 235300 kb
Host smart-9d28aff2-1f9c-487c-b584-4948ba24c0b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674778766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.3674778766
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.314957886
Short name T744
Test name
Test status
Simulation time 284636901 ps
CPU time 5.39 seconds
Started Mar 26 03:07:25 PM PDT 24
Finished Mar 26 03:07:31 PM PDT 24
Peak memory 235424 kb
Host smart-b218df68-2041-4d07-b3dc-62111172a364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314957886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.314957886
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.1150233525
Short name T782
Test name
Test status
Simulation time 3481947452 ps
CPU time 9.72 seconds
Started Mar 26 03:07:24 PM PDT 24
Finished Mar 26 03:07:34 PM PDT 24
Peak memory 231332 kb
Host smart-8a1d1bee-bd6b-46f8-a852-0d15a8348f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150233525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.1150233525
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.1912708409
Short name T746
Test name
Test status
Simulation time 1962696873 ps
CPU time 4.58 seconds
Started Mar 26 03:07:24 PM PDT 24
Finished Mar 26 03:07:29 PM PDT 24
Peak memory 219008 kb
Host smart-37fb900d-24f8-40f0-b621-7d46acdfc216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912708409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.1912708409
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.4128842181
Short name T799
Test name
Test status
Simulation time 292150342 ps
CPU time 3.74 seconds
Started Mar 26 03:07:25 PM PDT 24
Finished Mar 26 03:07:29 PM PDT 24
Peak memory 222972 kb
Host smart-09ff2dcb-7c48-44a5-826f-f3be216ffd40
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4128842181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.4128842181
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.2931080572
Short name T321
Test name
Test status
Simulation time 6173999816 ps
CPU time 9.07 seconds
Started Mar 26 03:07:25 PM PDT 24
Finished Mar 26 03:07:34 PM PDT 24
Peak memory 216772 kb
Host smart-0fdfe0e3-b5f6-4aa5-963b-08110dcd6bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931080572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.2931080572
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.3456971650
Short name T689
Test name
Test status
Simulation time 15456847796 ps
CPU time 25.67 seconds
Started Mar 26 03:07:23 PM PDT 24
Finished Mar 26 03:07:49 PM PDT 24
Peak memory 216780 kb
Host smart-d8cf4244-b1d4-4b17-ad0a-4ef72d9fa404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456971650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.3456971650
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.3120907517
Short name T317
Test name
Test status
Simulation time 289266213 ps
CPU time 9.88 seconds
Started Mar 26 03:07:24 PM PDT 24
Finished Mar 26 03:07:35 PM PDT 24
Peak memory 216864 kb
Host smart-c969726b-bb99-4315-8201-58ada559bf2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120907517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.3120907517
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.851974409
Short name T678
Test name
Test status
Simulation time 86939947 ps
CPU time 0.78 seconds
Started Mar 26 03:07:22 PM PDT 24
Finished Mar 26 03:07:23 PM PDT 24
Peak memory 206172 kb
Host smart-eb4f9ae9-6b5d-40bd-b1b1-9abdc1decac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851974409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.851974409
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.2552183498
Short name T288
Test name
Test status
Simulation time 13021227174 ps
CPU time 11.65 seconds
Started Mar 26 03:07:21 PM PDT 24
Finished Mar 26 03:07:33 PM PDT 24
Peak memory 235520 kb
Host smart-d5f70c71-f81c-413c-90f9-a0319daa6759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552183498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.2552183498
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.1167394868
Short name T825
Test name
Test status
Simulation time 21519504 ps
CPU time 0.79 seconds
Started Mar 26 03:07:33 PM PDT 24
Finished Mar 26 03:07:36 PM PDT 24
Peak memory 205208 kb
Host smart-8ba577a8-073f-4361-b3e9-49ff93a87fdb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167394868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
1167394868
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.2233584406
Short name T5
Test name
Test status
Simulation time 2764542907 ps
CPU time 9.7 seconds
Started Mar 26 03:07:33 PM PDT 24
Finished Mar 26 03:07:45 PM PDT 24
Peak memory 234236 kb
Host smart-f8071e09-59c0-4328-bab0-9b3ece205c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233584406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.2233584406
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.875316244
Short name T278
Test name
Test status
Simulation time 13183150 ps
CPU time 0.76 seconds
Started Mar 26 03:07:34 PM PDT 24
Finished Mar 26 03:07:36 PM PDT 24
Peak memory 206796 kb
Host smart-56b22510-4b40-4b34-8fe0-419db9ad2f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875316244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.875316244
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.872480333
Short name T196
Test name
Test status
Simulation time 49512135109 ps
CPU time 137.07 seconds
Started Mar 26 03:07:32 PM PDT 24
Finished Mar 26 03:09:49 PM PDT 24
Peak memory 257056 kb
Host smart-ec8ec343-eb13-4ef0-a3a7-dbf924c67e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872480333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.872480333
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.1141538347
Short name T785
Test name
Test status
Simulation time 16423299284 ps
CPU time 131.29 seconds
Started Mar 26 03:07:39 PM PDT 24
Finished Mar 26 03:09:51 PM PDT 24
Peak memory 254300 kb
Host smart-32e0caf2-e10c-4682-8e6e-cfa4d16b245e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141538347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.1141538347
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.2050243103
Short name T43
Test name
Test status
Simulation time 28845048585 ps
CPU time 148.82 seconds
Started Mar 26 03:07:34 PM PDT 24
Finished Mar 26 03:10:04 PM PDT 24
Peak memory 249720 kb
Host smart-af9d71e7-7cf5-45d5-bece-269095a82748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050243103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.2050243103
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.2593565806
Short name T816
Test name
Test status
Simulation time 45406268725 ps
CPU time 20.52 seconds
Started Mar 26 03:07:35 PM PDT 24
Finished Mar 26 03:07:56 PM PDT 24
Peak memory 234888 kb
Host smart-6a7e4fec-cc2c-4799-beaa-2f576c116088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593565806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.2593565806
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.1325053116
Short name T922
Test name
Test status
Simulation time 3028240284 ps
CPU time 10.77 seconds
Started Mar 26 03:07:31 PM PDT 24
Finished Mar 26 03:07:42 PM PDT 24
Peak memory 220444 kb
Host smart-8cbc53eb-649f-4cd4-abe4-f0dc2b525fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325053116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.1325053116
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.2063928667
Short name T701
Test name
Test status
Simulation time 15546629631 ps
CPU time 12.23 seconds
Started Mar 26 03:07:34 PM PDT 24
Finished Mar 26 03:07:48 PM PDT 24
Peak memory 231832 kb
Host smart-f7e8e6c6-ea32-415a-aead-822451a6215e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063928667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.2063928667
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.181038585
Short name T464
Test name
Test status
Simulation time 7547507263 ps
CPU time 22.87 seconds
Started Mar 26 03:07:35 PM PDT 24
Finished Mar 26 03:07:58 PM PDT 24
Peak memory 233940 kb
Host smart-2877cd1e-8821-4c53-81b3-3c0d871e3b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181038585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap
.181038585
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.4062062185
Short name T792
Test name
Test status
Simulation time 692018066 ps
CPU time 6.4 seconds
Started Mar 26 03:07:33 PM PDT 24
Finished Mar 26 03:07:42 PM PDT 24
Peak memory 233868 kb
Host smart-bb7d24fd-7c41-48e9-9aaf-c9e2d4585816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062062185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.4062062185
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.302559573
Short name T899
Test name
Test status
Simulation time 251250764 ps
CPU time 3.3 seconds
Started Mar 26 03:07:34 PM PDT 24
Finished Mar 26 03:07:39 PM PDT 24
Peak memory 220748 kb
Host smart-5d6ff35f-b944-4a76-a5a1-dc030a9b2652
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=302559573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dire
ct.302559573
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.2968970719
Short name T135
Test name
Test status
Simulation time 8997990985 ps
CPU time 36.64 seconds
Started Mar 26 03:07:33 PM PDT 24
Finished Mar 26 03:08:12 PM PDT 24
Peak memory 235620 kb
Host smart-0ef7ad89-2f3e-4d07-aae7-a2614bd40d24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968970719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.2968970719
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.980202058
Short name T276
Test name
Test status
Simulation time 21654032724 ps
CPU time 31.33 seconds
Started Mar 26 03:07:34 PM PDT 24
Finished Mar 26 03:08:07 PM PDT 24
Peak memory 216732 kb
Host smart-4c60ded0-9df9-415a-bad4-9977ddd5fc11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980202058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.980202058
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.2602743496
Short name T296
Test name
Test status
Simulation time 307033754 ps
CPU time 2.64 seconds
Started Mar 26 03:07:35 PM PDT 24
Finished Mar 26 03:07:38 PM PDT 24
Peak memory 216700 kb
Host smart-097e405b-ca6d-4240-aa8d-8044963ce284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602743496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.2602743496
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.3535203371
Short name T324
Test name
Test status
Simulation time 46586516 ps
CPU time 0.79 seconds
Started Mar 26 03:07:31 PM PDT 24
Finished Mar 26 03:07:32 PM PDT 24
Peak memory 206128 kb
Host smart-061cf65f-b0fa-49c2-8c6a-22df3e449365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535203371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.3535203371
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.927414521
Short name T375
Test name
Test status
Simulation time 172832364 ps
CPU time 0.89 seconds
Started Mar 26 03:07:34 PM PDT 24
Finished Mar 26 03:07:36 PM PDT 24
Peak memory 206128 kb
Host smart-e4880fb2-f1a8-4503-abfd-bcc2c8cd96f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927414521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.927414521
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.1269391952
Short name T202
Test name
Test status
Simulation time 2951836939 ps
CPU time 14.32 seconds
Started Mar 26 03:07:35 PM PDT 24
Finished Mar 26 03:07:50 PM PDT 24
Peak memory 241164 kb
Host smart-cbbff0f4-7ee8-45ff-8759-272204f3702f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269391952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.1269391952
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.3236145143
Short name T56
Test name
Test status
Simulation time 41240542 ps
CPU time 0.73 seconds
Started Mar 26 03:07:36 PM PDT 24
Finished Mar 26 03:07:36 PM PDT 24
Peak memory 205860 kb
Host smart-daed70dd-bdd3-478d-a6f2-da4bd7f56515
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236145143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
3236145143
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.3867197888
Short name T428
Test name
Test status
Simulation time 154895423 ps
CPU time 3.07 seconds
Started Mar 26 03:07:38 PM PDT 24
Finished Mar 26 03:07:42 PM PDT 24
Peak memory 234020 kb
Host smart-4ae71f92-5c05-47dd-a1c5-a4a7212d4c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867197888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.3867197888
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.1964370044
Short name T447
Test name
Test status
Simulation time 20145695 ps
CPU time 0.8 seconds
Started Mar 26 03:07:39 PM PDT 24
Finished Mar 26 03:07:40 PM PDT 24
Peak memory 207296 kb
Host smart-1081f024-55b2-4c63-9d40-5d5931932d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964370044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.1964370044
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.2885054224
Short name T758
Test name
Test status
Simulation time 67496847095 ps
CPU time 91.77 seconds
Started Mar 26 03:07:34 PM PDT 24
Finished Mar 26 03:09:07 PM PDT 24
Peak memory 241444 kb
Host smart-b3ead5bd-2e7c-4a29-abf0-16b2805ef56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885054224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.2885054224
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.449306265
Short name T41
Test name
Test status
Simulation time 9355286521 ps
CPU time 58.35 seconds
Started Mar 26 03:07:34 PM PDT 24
Finished Mar 26 03:08:34 PM PDT 24
Peak memory 233268 kb
Host smart-74121824-8465-4e1e-83d8-ef5986539ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449306265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idle
.449306265
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.2021266745
Short name T650
Test name
Test status
Simulation time 208192770 ps
CPU time 6.32 seconds
Started Mar 26 03:07:37 PM PDT 24
Finished Mar 26 03:07:43 PM PDT 24
Peak memory 235360 kb
Host smart-0769d238-1287-4403-9b31-2f735a39a12f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021266745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.2021266745
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.2380584053
Short name T878
Test name
Test status
Simulation time 2050135963 ps
CPU time 3.25 seconds
Started Mar 26 03:07:34 PM PDT 24
Finished Mar 26 03:07:39 PM PDT 24
Peak memory 219180 kb
Host smart-daed1af9-ec25-4678-b5ad-e69fbb9eede2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380584053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.2380584053
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.1563837232
Short name T648
Test name
Test status
Simulation time 5441692777 ps
CPU time 5.96 seconds
Started Mar 26 03:07:32 PM PDT 24
Finished Mar 26 03:07:38 PM PDT 24
Peak memory 219280 kb
Host smart-2512edca-e8c9-46db-b5b3-1a6c1dd04429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563837232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.1563837232
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.3576594989
Short name T225
Test name
Test status
Simulation time 13477089069 ps
CPU time 12.55 seconds
Started Mar 26 03:07:35 PM PDT 24
Finished Mar 26 03:07:48 PM PDT 24
Peak memory 219756 kb
Host smart-c93da68e-f8e5-4e2d-a9ca-7d8cf985cd7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576594989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.3576594989
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.679597942
Short name T845
Test name
Test status
Simulation time 379650568 ps
CPU time 3.58 seconds
Started Mar 26 03:07:32 PM PDT 24
Finished Mar 26 03:07:36 PM PDT 24
Peak memory 234744 kb
Host smart-d8a17f55-7e65-469c-8441-7740e4e9933e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679597942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.679597942
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.2780794881
Short name T730
Test name
Test status
Simulation time 2882505815 ps
CPU time 6.4 seconds
Started Mar 26 03:07:32 PM PDT 24
Finished Mar 26 03:07:39 PM PDT 24
Peak memory 220832 kb
Host smart-46223ce6-d4cf-423b-b184-65720d8a5f94
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2780794881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.2780794881
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.2876217278
Short name T48
Test name
Test status
Simulation time 42729995662 ps
CPU time 346.06 seconds
Started Mar 26 03:07:33 PM PDT 24
Finished Mar 26 03:13:22 PM PDT 24
Peak memory 273616 kb
Host smart-1bc0fedf-722e-411c-8b13-f63fd04a5585
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876217278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.2876217278
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.306254710
Short name T789
Test name
Test status
Simulation time 5171458223 ps
CPU time 37 seconds
Started Mar 26 03:07:33 PM PDT 24
Finished Mar 26 03:08:13 PM PDT 24
Peak memory 216872 kb
Host smart-5bf42225-7050-4019-a0db-1187abedff50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306254710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.306254710
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.465263058
Short name T601
Test name
Test status
Simulation time 249698929 ps
CPU time 1.16 seconds
Started Mar 26 03:07:34 PM PDT 24
Finished Mar 26 03:07:37 PM PDT 24
Peak memory 207168 kb
Host smart-3bbd4412-8925-4678-842d-20cb40970fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465263058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.465263058
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.1375791157
Short name T681
Test name
Test status
Simulation time 177626975 ps
CPU time 2.12 seconds
Started Mar 26 03:07:35 PM PDT 24
Finished Mar 26 03:07:38 PM PDT 24
Peak memory 216644 kb
Host smart-59755c66-22a7-44d6-98ac-a810cf34ec40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375791157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.1375791157
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.3071881959
Short name T546
Test name
Test status
Simulation time 282581660 ps
CPU time 0.94 seconds
Started Mar 26 03:07:32 PM PDT 24
Finished Mar 26 03:07:33 PM PDT 24
Peak memory 206212 kb
Host smart-b4803f8e-6d49-4f8d-9db1-29034e70226b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071881959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.3071881959
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.1166734561
Short name T686
Test name
Test status
Simulation time 27644775483 ps
CPU time 49.17 seconds
Started Mar 26 03:07:34 PM PDT 24
Finished Mar 26 03:08:25 PM PDT 24
Peak memory 249416 kb
Host smart-ade474a4-8992-4777-aba7-1398ca9214f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166734561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.1166734561
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.4192624313
Short name T54
Test name
Test status
Simulation time 49662322 ps
CPU time 0.7 seconds
Started Mar 26 03:07:42 PM PDT 24
Finished Mar 26 03:07:43 PM PDT 24
Peak memory 205804 kb
Host smart-21ebd884-5ac0-4f82-9039-bf52230739cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192624313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
4192624313
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.1352092633
Short name T698
Test name
Test status
Simulation time 122297468 ps
CPU time 2.39 seconds
Started Mar 26 03:07:34 PM PDT 24
Finished Mar 26 03:07:38 PM PDT 24
Peak memory 218836 kb
Host smart-668a03f2-869d-4908-b7d6-936fbb3d67d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352092633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.1352092633
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.50786437
Short name T397
Test name
Test status
Simulation time 20336753 ps
CPU time 0.77 seconds
Started Mar 26 03:07:34 PM PDT 24
Finished Mar 26 03:07:36 PM PDT 24
Peak memory 206152 kb
Host smart-debca54b-50b0-4f15-8456-fcf3f46b4701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50786437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.50786437
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.1977703959
Short name T258
Test name
Test status
Simulation time 5413871978 ps
CPU time 46.49 seconds
Started Mar 26 03:07:43 PM PDT 24
Finished Mar 26 03:08:30 PM PDT 24
Peak memory 257360 kb
Host smart-22bc7476-a498-44a0-858f-9e4226a45db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977703959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.1977703959
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.806141918
Short name T189
Test name
Test status
Simulation time 13696989872 ps
CPU time 58.6 seconds
Started Mar 26 03:07:43 PM PDT 24
Finished Mar 26 03:08:42 PM PDT 24
Peak memory 250952 kb
Host smart-6ce627eb-7561-4fb4-b5f2-3ce98d9b3c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806141918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.806141918
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.2869167881
Short name T259
Test name
Test status
Simulation time 64839476082 ps
CPU time 511.4 seconds
Started Mar 26 03:07:40 PM PDT 24
Finished Mar 26 03:16:12 PM PDT 24
Peak memory 249624 kb
Host smart-b0c7a9a3-9e52-4ba9-942f-621276bdaeab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869167881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.2869167881
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.2041953460
Short name T919
Test name
Test status
Simulation time 24488755898 ps
CPU time 22.7 seconds
Started Mar 26 03:07:41 PM PDT 24
Finished Mar 26 03:08:03 PM PDT 24
Peak memory 250840 kb
Host smart-8a9a5db6-83a8-4ef0-b541-bd3ca39608a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041953460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.2041953460
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.4028267251
Short name T783
Test name
Test status
Simulation time 248697329 ps
CPU time 4.54 seconds
Started Mar 26 03:07:33 PM PDT 24
Finished Mar 26 03:07:40 PM PDT 24
Peak memory 233840 kb
Host smart-d7962f9b-5687-4151-9415-c4bf72a1ee62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028267251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.4028267251
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.12283044
Short name T370
Test name
Test status
Simulation time 9523721354 ps
CPU time 9.54 seconds
Started Mar 26 03:07:32 PM PDT 24
Finished Mar 26 03:07:41 PM PDT 24
Peak memory 223656 kb
Host smart-ec77ccb0-1f68-4c00-819d-f6c586440aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12283044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.12283044
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.958031421
Short name T657
Test name
Test status
Simulation time 450201571 ps
CPU time 6.25 seconds
Started Mar 26 03:07:32 PM PDT 24
Finished Mar 26 03:07:38 PM PDT 24
Peak memory 234152 kb
Host smart-f457e474-12d5-45d1-8f3f-ba125498235a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958031421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap
.958031421
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.2704223562
Short name T294
Test name
Test status
Simulation time 6715459484 ps
CPU time 12.19 seconds
Started Mar 26 03:07:34 PM PDT 24
Finished Mar 26 03:07:48 PM PDT 24
Peak memory 233100 kb
Host smart-af980a68-5d86-43f5-bd65-dd06777ff1a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704223562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.2704223562
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.3184095630
Short name T581
Test name
Test status
Simulation time 359314428 ps
CPU time 4.2 seconds
Started Mar 26 03:07:41 PM PDT 24
Finished Mar 26 03:07:45 PM PDT 24
Peak memory 223492 kb
Host smart-b1dfe5e9-b28b-40d9-8602-94158dbc5b6a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3184095630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.3184095630
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.2270142658
Short name T257
Test name
Test status
Simulation time 7895744338 ps
CPU time 149.63 seconds
Started Mar 26 03:07:42 PM PDT 24
Finished Mar 26 03:10:12 PM PDT 24
Peak memory 257292 kb
Host smart-150cb8c3-60b8-4a48-b101-e27790e1dfa1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270142658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.2270142658
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.2475138100
Short name T635
Test name
Test status
Simulation time 10300016840 ps
CPU time 27.84 seconds
Started Mar 26 03:07:38 PM PDT 24
Finished Mar 26 03:08:06 PM PDT 24
Peak memory 216772 kb
Host smart-39572bd5-7612-4a1b-b601-8da7f56885d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475138100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.2475138100
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.1146657166
Short name T572
Test name
Test status
Simulation time 16890054410 ps
CPU time 20.88 seconds
Started Mar 26 03:07:35 PM PDT 24
Finished Mar 26 03:07:56 PM PDT 24
Peak memory 216836 kb
Host smart-17490c18-b900-4315-af9a-3f7b1804c086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146657166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.1146657166
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.102312757
Short name T371
Test name
Test status
Simulation time 73305794 ps
CPU time 1.31 seconds
Started Mar 26 03:07:34 PM PDT 24
Finished Mar 26 03:07:37 PM PDT 24
Peak memory 216420 kb
Host smart-a152acca-20e7-4e59-ace1-837ba47278a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102312757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.102312757
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.865330856
Short name T490
Test name
Test status
Simulation time 593075476 ps
CPU time 1.06 seconds
Started Mar 26 03:07:35 PM PDT 24
Finished Mar 26 03:07:37 PM PDT 24
Peak memory 207168 kb
Host smart-189bd668-5fb3-4acc-b07f-123fabe5345d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865330856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.865330856
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.3484175918
Short name T444
Test name
Test status
Simulation time 602995890 ps
CPU time 6.79 seconds
Started Mar 26 03:07:33 PM PDT 24
Finished Mar 26 03:07:42 PM PDT 24
Peak memory 218888 kb
Host smart-f1fbfea7-4cee-49e3-8565-ab52d21ea801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484175918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.3484175918
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.3993061030
Short name T315
Test name
Test status
Simulation time 19493209 ps
CPU time 0.7 seconds
Started Mar 26 03:04:55 PM PDT 24
Finished Mar 26 03:04:56 PM PDT 24
Peak memory 205232 kb
Host smart-f4b2b09a-c2ef-4e18-b923-51ed8b913b9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993061030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.3
993061030
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.611011477
Short name T565
Test name
Test status
Simulation time 1840447695 ps
CPU time 5.97 seconds
Started Mar 26 03:04:51 PM PDT 24
Finished Mar 26 03:04:58 PM PDT 24
Peak memory 220824 kb
Host smart-953268d6-9d29-4d68-8895-7c26d12c3fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611011477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.611011477
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.883654861
Short name T354
Test name
Test status
Simulation time 26744940 ps
CPU time 0.75 seconds
Started Mar 26 03:04:51 PM PDT 24
Finished Mar 26 03:04:52 PM PDT 24
Peak memory 205776 kb
Host smart-e3aa9b1d-d898-4da0-b4dd-38ce02ddc069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883654861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.883654861
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.2783885201
Short name T562
Test name
Test status
Simulation time 33364533660 ps
CPU time 159.45 seconds
Started Mar 26 03:04:52 PM PDT 24
Finished Mar 26 03:07:31 PM PDT 24
Peak memory 257796 kb
Host smart-81408dfa-980f-4888-9ba3-70cc4cedc3df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783885201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.2783885201
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.2590586580
Short name T184
Test name
Test status
Simulation time 52350583934 ps
CPU time 77.61 seconds
Started Mar 26 03:04:52 PM PDT 24
Finished Mar 26 03:06:10 PM PDT 24
Peak memory 252508 kb
Host smart-41143c78-2b9e-48b6-b065-0abd5e487dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590586580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.2590586580
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.2648888133
Short name T801
Test name
Test status
Simulation time 23125973997 ps
CPU time 46.17 seconds
Started Mar 26 03:04:56 PM PDT 24
Finished Mar 26 03:05:42 PM PDT 24
Peak memory 222636 kb
Host smart-3ee608d3-3fe5-40bd-bccc-bac03786cc0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648888133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.2648888133
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.2476654357
Short name T873
Test name
Test status
Simulation time 8674551444 ps
CPU time 47.29 seconds
Started Mar 26 03:04:53 PM PDT 24
Finished Mar 26 03:05:41 PM PDT 24
Peak memory 239136 kb
Host smart-342cfbd2-c415-431e-a4f9-b65c228fb092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476654357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.2476654357
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.585192562
Short name T535
Test name
Test status
Simulation time 665917187 ps
CPU time 3.77 seconds
Started Mar 26 03:04:50 PM PDT 24
Finished Mar 26 03:04:54 PM PDT 24
Peak memory 235576 kb
Host smart-80fe8b78-2024-4753-969b-c0f6fe8e8b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585192562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.585192562
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.321644417
Short name T965
Test name
Test status
Simulation time 742939832 ps
CPU time 11.87 seconds
Started Mar 26 03:04:56 PM PDT 24
Finished Mar 26 03:05:08 PM PDT 24
Peak memory 251320 kb
Host smart-9f47d6de-7245-4c67-8599-6696cf109157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321644417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.321644417
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.4261754202
Short name T612
Test name
Test status
Simulation time 15188437000 ps
CPU time 24.24 seconds
Started Mar 26 03:04:53 PM PDT 24
Finished Mar 26 03:05:19 PM PDT 24
Peak memory 237192 kb
Host smart-e3d16783-0a13-41ef-9a08-71d27b81a221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261754202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.4261754202
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.3961317820
Short name T539
Test name
Test status
Simulation time 1792397161 ps
CPU time 8.44 seconds
Started Mar 26 03:04:51 PM PDT 24
Finished Mar 26 03:05:00 PM PDT 24
Peak memory 220256 kb
Host smart-71a66b8c-0266-4e18-8185-63126f6110b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961317820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.3961317820
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_ram_cfg.53476819
Short name T925
Test name
Test status
Simulation time 21649171 ps
CPU time 0.76 seconds
Started Mar 26 03:04:50 PM PDT 24
Finished Mar 26 03:04:51 PM PDT 24
Peak memory 216472 kb
Host smart-f5d4f803-646c-4be1-aa8c-4f106d09cd50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53476819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_ram_cfg.53476819
Directory /workspace/5.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.2362039736
Short name T437
Test name
Test status
Simulation time 2836269278 ps
CPU time 4.98 seconds
Started Mar 26 03:04:57 PM PDT 24
Finished Mar 26 03:05:03 PM PDT 24
Peak memory 220004 kb
Host smart-3978d19f-de86-4300-8cc7-49fdb6aaa2ed
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2362039736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.2362039736
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.2590044860
Short name T605
Test name
Test status
Simulation time 5109808449 ps
CPU time 17.08 seconds
Started Mar 26 03:04:55 PM PDT 24
Finished Mar 26 03:05:13 PM PDT 24
Peak memory 216880 kb
Host smart-5299816b-91ff-49ca-b01d-d04872a7dd39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590044860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.2590044860
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.3817626433
Short name T342
Test name
Test status
Simulation time 4234093125 ps
CPU time 14.04 seconds
Started Mar 26 03:04:52 PM PDT 24
Finished Mar 26 03:05:06 PM PDT 24
Peak memory 216672 kb
Host smart-ffcb593a-4ebe-4a8f-8386-732f140e66da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817626433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.3817626433
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.3115640994
Short name T928
Test name
Test status
Simulation time 199370490 ps
CPU time 1.33 seconds
Started Mar 26 03:04:54 PM PDT 24
Finished Mar 26 03:04:56 PM PDT 24
Peak memory 208268 kb
Host smart-dbcf15da-9ca3-469a-aaa9-b73fce389b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115640994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.3115640994
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.3918521105
Short name T489
Test name
Test status
Simulation time 29757701 ps
CPU time 0.79 seconds
Started Mar 26 03:04:51 PM PDT 24
Finished Mar 26 03:04:53 PM PDT 24
Peak memory 206180 kb
Host smart-a671413c-3349-4f1f-8e65-d0651043004f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918521105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.3918521105
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.2322403557
Short name T735
Test name
Test status
Simulation time 2857341718 ps
CPU time 10.34 seconds
Started Mar 26 03:04:53 PM PDT 24
Finished Mar 26 03:05:05 PM PDT 24
Peak memory 239728 kb
Host smart-77731ff5-2b5e-4e64-afa3-29e8ab0ca3a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322403557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.2322403557
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.113432947
Short name T653
Test name
Test status
Simulation time 31532698 ps
CPU time 0.67 seconds
Started Mar 26 03:05:07 PM PDT 24
Finished Mar 26 03:05:08 PM PDT 24
Peak memory 205160 kb
Host smart-476780fd-8b06-4ed1-8882-a548d2ae6eb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113432947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.113432947
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.656232529
Short name T636
Test name
Test status
Simulation time 2005981299 ps
CPU time 3.53 seconds
Started Mar 26 03:05:07 PM PDT 24
Finished Mar 26 03:05:11 PM PDT 24
Peak memory 224836 kb
Host smart-e01c968c-fd0c-4ce9-b484-6cd7ceb34f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656232529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.656232529
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.2979346213
Short name T814
Test name
Test status
Simulation time 22606167 ps
CPU time 0.83 seconds
Started Mar 26 03:04:58 PM PDT 24
Finished Mar 26 03:04:58 PM PDT 24
Peak memory 207164 kb
Host smart-8886b776-f23b-432c-9aca-28b665a40223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979346213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.2979346213
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.1980488604
Short name T893
Test name
Test status
Simulation time 1885347348 ps
CPU time 34.41 seconds
Started Mar 26 03:05:07 PM PDT 24
Finished Mar 26 03:05:41 PM PDT 24
Peak memory 249412 kb
Host smart-e48f12e6-6afa-486c-86c3-3b3a75b12776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980488604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.1980488604
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.2429389495
Short name T80
Test name
Test status
Simulation time 6167253220 ps
CPU time 69.78 seconds
Started Mar 26 03:05:06 PM PDT 24
Finished Mar 26 03:06:16 PM PDT 24
Peak memory 249844 kb
Host smart-a0aaa210-8513-457d-a086-bc2bc13aca55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429389495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.2429389495
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.1864666303
Short name T187
Test name
Test status
Simulation time 32759401682 ps
CPU time 122.08 seconds
Started Mar 26 03:05:07 PM PDT 24
Finished Mar 26 03:07:09 PM PDT 24
Peak memory 249632 kb
Host smart-05ede8be-7e6c-4293-baae-0441b38c920e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864666303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.1864666303
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.3638075476
Short name T625
Test name
Test status
Simulation time 12289453990 ps
CPU time 63.33 seconds
Started Mar 26 03:05:04 PM PDT 24
Finished Mar 26 03:06:08 PM PDT 24
Peak memory 248716 kb
Host smart-7cfd2ded-b6f3-4b39-a6ed-e6b197acd58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638075476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.3638075476
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.2498995780
Short name T887
Test name
Test status
Simulation time 10726904945 ps
CPU time 11.02 seconds
Started Mar 26 03:04:56 PM PDT 24
Finished Mar 26 03:05:07 PM PDT 24
Peak memory 224936 kb
Host smart-8060da8f-88bf-4908-84cd-4734ae577c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498995780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.2498995780
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.2321335306
Short name T194
Test name
Test status
Simulation time 6046625850 ps
CPU time 13.34 seconds
Started Mar 26 03:04:54 PM PDT 24
Finished Mar 26 03:05:08 PM PDT 24
Peak memory 219052 kb
Host smart-4135d40c-54da-409c-9859-6b2555344a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321335306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.2321335306
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.809302711
Short name T231
Test name
Test status
Simulation time 2254811060 ps
CPU time 5.38 seconds
Started Mar 26 03:04:51 PM PDT 24
Finished Mar 26 03:04:56 PM PDT 24
Peak memory 222836 kb
Host smart-87b7414a-81e3-4adf-935f-68b83175d134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809302711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.
809302711
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.830710165
Short name T576
Test name
Test status
Simulation time 22701459930 ps
CPU time 8.83 seconds
Started Mar 26 03:04:52 PM PDT 24
Finished Mar 26 03:05:01 PM PDT 24
Peak memory 233684 kb
Host smart-2e62689f-35ce-4407-839f-ce18d05dda9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830710165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.830710165
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_ram_cfg.1811479407
Short name T890
Test name
Test status
Simulation time 50159244 ps
CPU time 0.74 seconds
Started Mar 26 03:04:53 PM PDT 24
Finished Mar 26 03:04:55 PM PDT 24
Peak memory 216508 kb
Host smart-3b9134cf-5efb-41f6-b73d-aaf49602e73a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811479407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_ram_cfg.1811479407
Directory /workspace/6.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.1042725397
Short name T559
Test name
Test status
Simulation time 516493326 ps
CPU time 4.61 seconds
Started Mar 26 03:05:09 PM PDT 24
Finished Mar 26 03:05:14 PM PDT 24
Peak memory 223448 kb
Host smart-d537a697-f662-4cae-83b3-0e08fb83986a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1042725397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.1042725397
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.36061022
Short name T51
Test name
Test status
Simulation time 10532664998 ps
CPU time 106.3 seconds
Started Mar 26 03:05:05 PM PDT 24
Finished Mar 26 03:06:52 PM PDT 24
Peak memory 262696 kb
Host smart-e1caa268-4fa5-4ba8-a897-da5cc9dca31c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36061022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress_
all.36061022
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.1252128011
Short name T430
Test name
Test status
Simulation time 51289172595 ps
CPU time 62.5 seconds
Started Mar 26 03:04:54 PM PDT 24
Finished Mar 26 03:05:57 PM PDT 24
Peak memory 216768 kb
Host smart-9a804855-5591-4b0c-aa49-b8aef40b486e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252128011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.1252128011
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.2286542094
Short name T292
Test name
Test status
Simulation time 13848764172 ps
CPU time 24.68 seconds
Started Mar 26 03:04:52 PM PDT 24
Finished Mar 26 03:05:17 PM PDT 24
Peak memory 216840 kb
Host smart-2e9c001d-42b3-4eb3-9c42-40301a23ae12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286542094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.2286542094
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.2237429050
Short name T940
Test name
Test status
Simulation time 45415313 ps
CPU time 0.81 seconds
Started Mar 26 03:04:51 PM PDT 24
Finished Mar 26 03:04:53 PM PDT 24
Peak memory 206192 kb
Host smart-9f9dba77-c850-404c-a0cf-54fc6a14827b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237429050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.2237429050
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.604003446
Short name T552
Test name
Test status
Simulation time 36145374 ps
CPU time 0.8 seconds
Started Mar 26 03:04:56 PM PDT 24
Finished Mar 26 03:04:57 PM PDT 24
Peak memory 206124 kb
Host smart-adf605f6-56e8-495d-87fc-ff383d04640b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604003446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.604003446
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.1033867438
Short name T903
Test name
Test status
Simulation time 3786293857 ps
CPU time 8.89 seconds
Started Mar 26 03:05:07 PM PDT 24
Finished Mar 26 03:05:16 PM PDT 24
Peak memory 218520 kb
Host smart-3e20fb08-d533-45bd-9b5a-4a3c13a5d6bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033867438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.1033867438
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.2073911342
Short name T942
Test name
Test status
Simulation time 41809386 ps
CPU time 0.68 seconds
Started Mar 26 03:05:05 PM PDT 24
Finished Mar 26 03:05:06 PM PDT 24
Peak memory 205240 kb
Host smart-fe89ef4c-ba31-4ff4-9143-49b27f6c168b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073911342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.2
073911342
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.779262083
Short name T387
Test name
Test status
Simulation time 1089485387 ps
CPU time 4.57 seconds
Started Mar 26 03:05:07 PM PDT 24
Finished Mar 26 03:05:11 PM PDT 24
Peak memory 219916 kb
Host smart-67442f8c-d46f-44e5-bd90-1b66729f23c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779262083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.779262083
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.2294033158
Short name T734
Test name
Test status
Simulation time 25239653 ps
CPU time 0.75 seconds
Started Mar 26 03:05:09 PM PDT 24
Finished Mar 26 03:05:10 PM PDT 24
Peak memory 206232 kb
Host smart-15f60fc0-a97c-429b-a78a-d1758714c76d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294033158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.2294033158
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.496578915
Short name T538
Test name
Test status
Simulation time 7006836619 ps
CPU time 27.27 seconds
Started Mar 26 03:05:10 PM PDT 24
Finished Mar 26 03:05:37 PM PDT 24
Peak memory 255628 kb
Host smart-9ff9d5b8-f277-44d3-b465-64bcfb75ef53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496578915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.496578915
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.452818137
Short name T466
Test name
Test status
Simulation time 9438313291 ps
CPU time 83.07 seconds
Started Mar 26 03:05:10 PM PDT 24
Finished Mar 26 03:06:34 PM PDT 24
Peak memory 249780 kb
Host smart-cb277fcb-66bf-40c4-b675-cb8fefc3e7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452818137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.452818137
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.1008110808
Short name T663
Test name
Test status
Simulation time 13049496617 ps
CPU time 71.56 seconds
Started Mar 26 03:05:10 PM PDT 24
Finished Mar 26 03:06:21 PM PDT 24
Peak memory 254328 kb
Host smart-b53a8c00-9103-4854-8bb4-14f259928fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008110808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.1008110808
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.3059199166
Short name T268
Test name
Test status
Simulation time 8345190783 ps
CPU time 19.7 seconds
Started Mar 26 03:05:05 PM PDT 24
Finished Mar 26 03:05:25 PM PDT 24
Peak memory 236956 kb
Host smart-1e0a0eb5-f237-4c14-8892-24cf48884d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059199166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.3059199166
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.2832129321
Short name T220
Test name
Test status
Simulation time 335952231 ps
CPU time 4.18 seconds
Started Mar 26 03:05:08 PM PDT 24
Finished Mar 26 03:05:12 PM PDT 24
Peak memory 219796 kb
Host smart-956bbae7-cd66-4d63-8260-590f0e2dd5fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832129321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.2832129321
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.430473088
Short name T340
Test name
Test status
Simulation time 2885032144 ps
CPU time 10.76 seconds
Started Mar 26 03:05:08 PM PDT 24
Finished Mar 26 03:05:19 PM PDT 24
Peak memory 235916 kb
Host smart-fd1ddc3e-dfc4-45b7-88ac-b94e6d03a00c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430473088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.430473088
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.2067050010
Short name T885
Test name
Test status
Simulation time 4514326187 ps
CPU time 7.34 seconds
Started Mar 26 03:05:06 PM PDT 24
Finished Mar 26 03:05:14 PM PDT 24
Peak memory 233924 kb
Host smart-01c6b43a-ea6e-4829-9c60-4676fdc3d55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067050010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.2067050010
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.3911983667
Short name T853
Test name
Test status
Simulation time 40848679211 ps
CPU time 25.43 seconds
Started Mar 26 03:05:09 PM PDT 24
Finished Mar 26 03:05:35 PM PDT 24
Peak memory 233724 kb
Host smart-4d2d485e-53a7-4627-bb58-1518856d77fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911983667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.3911983667
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_ram_cfg.1072734134
Short name T688
Test name
Test status
Simulation time 37346106 ps
CPU time 0.75 seconds
Started Mar 26 03:05:07 PM PDT 24
Finished Mar 26 03:05:08 PM PDT 24
Peak memory 216520 kb
Host smart-7298b651-12ce-4b45-946f-708501c32099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072734134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_ram_cfg.1072734134
Directory /workspace/7.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.891413063
Short name T543
Test name
Test status
Simulation time 1412360163 ps
CPU time 3.74 seconds
Started Mar 26 03:05:09 PM PDT 24
Finished Mar 26 03:05:13 PM PDT 24
Peak memory 223268 kb
Host smart-dfeb2728-ecb2-402f-9359-d99c34a1383b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=891413063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direc
t.891413063
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.3221194123
Short name T21
Test name
Test status
Simulation time 85240477715 ps
CPU time 266.73 seconds
Started Mar 26 03:05:06 PM PDT 24
Finished Mar 26 03:09:33 PM PDT 24
Peak memory 290612 kb
Host smart-c1f52e48-7923-4335-ba1c-5c75c44f2da1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221194123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.3221194123
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.2765420713
Short name T741
Test name
Test status
Simulation time 31647876309 ps
CPU time 48.31 seconds
Started Mar 26 03:05:09 PM PDT 24
Finished Mar 26 03:05:58 PM PDT 24
Peak memory 216740 kb
Host smart-3b9498c8-5807-4086-b4ca-9b8fed317178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765420713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.2765420713
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.132980399
Short name T859
Test name
Test status
Simulation time 4690058889 ps
CPU time 18.16 seconds
Started Mar 26 03:05:06 PM PDT 24
Finished Mar 26 03:05:24 PM PDT 24
Peak memory 216800 kb
Host smart-4d167f94-e380-4367-8b36-793e3f834c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132980399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.132980399
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.3898677663
Short name T415
Test name
Test status
Simulation time 129473479 ps
CPU time 1.58 seconds
Started Mar 26 03:05:07 PM PDT 24
Finished Mar 26 03:05:09 PM PDT 24
Peak memory 216604 kb
Host smart-fad6e835-37d3-4161-9b4a-d055d56dc5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898677663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.3898677663
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.2341030711
Short name T368
Test name
Test status
Simulation time 18858785 ps
CPU time 0.76 seconds
Started Mar 26 03:05:05 PM PDT 24
Finished Mar 26 03:05:06 PM PDT 24
Peak memory 206200 kb
Host smart-ec69be45-f8bf-490a-8232-e88427d6bbb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341030711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.2341030711
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.505112533
Short name T945
Test name
Test status
Simulation time 9674903812 ps
CPU time 18.64 seconds
Started Mar 26 03:05:08 PM PDT 24
Finished Mar 26 03:05:27 PM PDT 24
Peak memory 234660 kb
Host smart-c548b833-a68b-4768-83d9-f8b036bef2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505112533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.505112533
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.1889185614
Short name T957
Test name
Test status
Simulation time 20776610 ps
CPU time 0.68 seconds
Started Mar 26 03:05:18 PM PDT 24
Finished Mar 26 03:05:18 PM PDT 24
Peak memory 206196 kb
Host smart-b2af05cf-d3cd-4678-ab44-38e96f9d8e35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889185614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.1
889185614
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.3571174508
Short name T540
Test name
Test status
Simulation time 3569240626 ps
CPU time 4.89 seconds
Started Mar 26 03:05:08 PM PDT 24
Finished Mar 26 03:05:13 PM PDT 24
Peak memory 234008 kb
Host smart-d5549d57-70fc-4bb9-a861-e53fc768cc6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571174508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.3571174508
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.3871109625
Short name T544
Test name
Test status
Simulation time 56608021 ps
CPU time 0.75 seconds
Started Mar 26 03:05:07 PM PDT 24
Finished Mar 26 03:05:08 PM PDT 24
Peak memory 207004 kb
Host smart-a1ce41e0-b7bf-425b-8c1f-88e4a7be6869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871109625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.3871109625
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.1738580282
Short name T608
Test name
Test status
Simulation time 13888246709 ps
CPU time 100.95 seconds
Started Mar 26 03:05:17 PM PDT 24
Finished Mar 26 03:06:59 PM PDT 24
Peak memory 257168 kb
Host smart-77383dd4-4d29-4cb2-a7fd-ff5094882488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738580282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.1738580282
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.283378764
Short name T260
Test name
Test status
Simulation time 27678782065 ps
CPU time 178.57 seconds
Started Mar 26 03:05:17 PM PDT 24
Finished Mar 26 03:08:16 PM PDT 24
Peak memory 237716 kb
Host smart-2a707590-d46a-499b-8760-a066ab22174a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283378764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.283378764
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.642568141
Short name T42
Test name
Test status
Simulation time 28502016202 ps
CPU time 33.02 seconds
Started Mar 26 03:05:17 PM PDT 24
Finished Mar 26 03:05:51 PM PDT 24
Peak memory 237920 kb
Host smart-dbc72f90-fc38-43ca-af59-670f194fb1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642568141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle.
642568141
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.3504616961
Short name T269
Test name
Test status
Simulation time 1293774366 ps
CPU time 10.36 seconds
Started Mar 26 03:05:08 PM PDT 24
Finished Mar 26 03:05:18 PM PDT 24
Peak memory 239264 kb
Host smart-7783d75d-9dc4-4ac4-8275-5a642aefab1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504616961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.3504616961
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.3576345496
Short name T677
Test name
Test status
Simulation time 1830645381 ps
CPU time 6.3 seconds
Started Mar 26 03:05:08 PM PDT 24
Finished Mar 26 03:05:15 PM PDT 24
Peak memory 234284 kb
Host smart-b39f7351-3150-471f-91d8-bb0773214ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576345496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.3576345496
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.795336312
Short name T346
Test name
Test status
Simulation time 355546388 ps
CPU time 3.33 seconds
Started Mar 26 03:05:06 PM PDT 24
Finished Mar 26 03:05:09 PM PDT 24
Peak memory 235056 kb
Host smart-efc81658-7f72-4f77-8337-98b38fc3080f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795336312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.795336312
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.3206788268
Short name T474
Test name
Test status
Simulation time 389407316 ps
CPU time 2.96 seconds
Started Mar 26 03:05:08 PM PDT 24
Finished Mar 26 03:05:11 PM PDT 24
Peak memory 218716 kb
Host smart-1af36171-ec71-4323-8b9c-7650b10366f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206788268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.3206788268
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.3544712128
Short name T372
Test name
Test status
Simulation time 624845671 ps
CPU time 5.4 seconds
Started Mar 26 03:05:08 PM PDT 24
Finished Mar 26 03:05:13 PM PDT 24
Peak memory 229584 kb
Host smart-5fbd4d07-caae-4d9a-a9e3-d7c7f07c2aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544712128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.3544712128
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_ram_cfg.3645210987
Short name T736
Test name
Test status
Simulation time 17232886 ps
CPU time 0.78 seconds
Started Mar 26 03:05:10 PM PDT 24
Finished Mar 26 03:05:11 PM PDT 24
Peak memory 216480 kb
Host smart-7b7908d8-dc90-4958-a876-46af8b027e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645210987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_ram_cfg.3645210987
Directory /workspace/8.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.1284822551
Short name T384
Test name
Test status
Simulation time 4144648258 ps
CPU time 4.82 seconds
Started Mar 26 03:05:16 PM PDT 24
Finished Mar 26 03:05:21 PM PDT 24
Peak memory 219748 kb
Host smart-282c1957-ddc1-40e6-8998-550bf53ba1ac
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1284822551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.1284822551
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.3049759156
Short name T830
Test name
Test status
Simulation time 75892211 ps
CPU time 0.94 seconds
Started Mar 26 03:05:18 PM PDT 24
Finished Mar 26 03:05:19 PM PDT 24
Peak memory 205908 kb
Host smart-a500b078-2dec-4e64-a43d-273e60f89a07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049759156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.3049759156
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.970744831
Short name T804
Test name
Test status
Simulation time 12848533518 ps
CPU time 67.21 seconds
Started Mar 26 03:05:10 PM PDT 24
Finished Mar 26 03:06:17 PM PDT 24
Peak memory 216672 kb
Host smart-9ce67fcf-90f7-473c-a9e0-06189b5c5849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970744831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.970744831
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.364884854
Short name T331
Test name
Test status
Simulation time 1973997917 ps
CPU time 9.86 seconds
Started Mar 26 03:05:09 PM PDT 24
Finished Mar 26 03:05:19 PM PDT 24
Peak memory 216496 kb
Host smart-f0f06c6c-fdb2-490c-a702-e7ea19fde75c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364884854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.364884854
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.3399150150
Short name T740
Test name
Test status
Simulation time 35465315 ps
CPU time 1.18 seconds
Started Mar 26 03:05:06 PM PDT 24
Finished Mar 26 03:05:07 PM PDT 24
Peak memory 216664 kb
Host smart-648a0138-f663-4c81-b32d-33cd4c1f74f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399150150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.3399150150
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.1071044270
Short name T470
Test name
Test status
Simulation time 59066230 ps
CPU time 0.99 seconds
Started Mar 26 03:05:07 PM PDT 24
Finished Mar 26 03:05:08 PM PDT 24
Peak memory 207228 kb
Host smart-33e2f8ba-f985-4877-a990-c656fefe6ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071044270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.1071044270
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.3415330261
Short name T519
Test name
Test status
Simulation time 13631968201 ps
CPU time 21.93 seconds
Started Mar 26 03:05:06 PM PDT 24
Finished Mar 26 03:05:28 PM PDT 24
Peak memory 233340 kb
Host smart-87588a58-3fe5-4ba6-a0cf-ad898f931568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415330261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.3415330261
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.2444033631
Short name T318
Test name
Test status
Simulation time 12007593 ps
CPU time 0.71 seconds
Started Mar 26 03:05:17 PM PDT 24
Finished Mar 26 03:05:18 PM PDT 24
Peak memory 205744 kb
Host smart-d58fb27a-a02d-48af-8f11-97e6c316f1db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444033631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.2
444033631
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.420197325
Short name T313
Test name
Test status
Simulation time 308755291 ps
CPU time 3.06 seconds
Started Mar 26 03:05:22 PM PDT 24
Finished Mar 26 03:05:26 PM PDT 24
Peak memory 219216 kb
Host smart-d925bab7-c30f-4d0c-a52c-5c0fbc17b3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420197325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.420197325
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.252695272
Short name T886
Test name
Test status
Simulation time 25407249 ps
CPU time 0.75 seconds
Started Mar 26 03:05:16 PM PDT 24
Finished Mar 26 03:05:17 PM PDT 24
Peak memory 206284 kb
Host smart-40125d2e-de9a-48e8-8f2e-479885b297ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252695272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.252695272
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.105093289
Short name T568
Test name
Test status
Simulation time 7183850496 ps
CPU time 24.86 seconds
Started Mar 26 03:05:20 PM PDT 24
Finished Mar 26 03:05:45 PM PDT 24
Peak memory 241432 kb
Host smart-16d392c9-8442-4679-8f47-f6c3eb98ec96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105093289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.105093289
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.4201922822
Short name T488
Test name
Test status
Simulation time 11334985281 ps
CPU time 66.36 seconds
Started Mar 26 03:05:24 PM PDT 24
Finished Mar 26 03:06:31 PM PDT 24
Peak memory 249628 kb
Host smart-7cd488f5-8de8-4ecd-8d2d-ed3c3733b5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201922822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.4201922822
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.116962198
Short name T649
Test name
Test status
Simulation time 35967763244 ps
CPU time 112.82 seconds
Started Mar 26 03:05:18 PM PDT 24
Finished Mar 26 03:07:11 PM PDT 24
Peak memory 255940 kb
Host smart-610f0d13-de77-412e-9e7c-89431f3ee4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116962198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.
116962198
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.2606286063
Short name T410
Test name
Test status
Simulation time 51236803009 ps
CPU time 49.99 seconds
Started Mar 26 03:05:16 PM PDT 24
Finished Mar 26 03:06:06 PM PDT 24
Peak memory 249452 kb
Host smart-433da3ca-d018-4550-b5a2-e2dcb0dc1d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606286063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.2606286063
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.3947693272
Short name T603
Test name
Test status
Simulation time 654722465 ps
CPU time 4.58 seconds
Started Mar 26 03:05:20 PM PDT 24
Finished Mar 26 03:05:25 PM PDT 24
Peak memory 233664 kb
Host smart-af89e5ee-771b-4629-a762-a8fb1894f777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947693272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.3947693272
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.2837297969
Short name T575
Test name
Test status
Simulation time 18852456436 ps
CPU time 22.9 seconds
Started Mar 26 03:05:24 PM PDT 24
Finished Mar 26 03:05:47 PM PDT 24
Peak memory 235848 kb
Host smart-c84a5b3a-92c2-4cd3-9aa0-e3c1526c856f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837297969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.2837297969
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.2288823790
Short name T591
Test name
Test status
Simulation time 1948606903 ps
CPU time 13.63 seconds
Started Mar 26 03:05:19 PM PDT 24
Finished Mar 26 03:05:33 PM PDT 24
Peak memory 233940 kb
Host smart-5ddcdafa-98a6-4738-832c-656d69aee839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288823790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.2288823790
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.3979092914
Short name T472
Test name
Test status
Simulation time 866528354 ps
CPU time 2.81 seconds
Started Mar 26 03:05:20 PM PDT 24
Finished Mar 26 03:05:23 PM PDT 24
Peak memory 224840 kb
Host smart-f99a9e0e-f69e-4f55-b443-9c99a789e1b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979092914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.3979092914
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_ram_cfg.4127000496
Short name T64
Test name
Test status
Simulation time 16731993 ps
CPU time 0.74 seconds
Started Mar 26 03:05:18 PM PDT 24
Finished Mar 26 03:05:19 PM PDT 24
Peak memory 216504 kb
Host smart-ec2b82f0-1d5b-4c54-902e-218d8ec668df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127000496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_ram_cfg.4127000496
Directory /workspace/9.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.799338463
Short name T939
Test name
Test status
Simulation time 4200667081 ps
CPU time 4.65 seconds
Started Mar 26 03:05:22 PM PDT 24
Finished Mar 26 03:05:27 PM PDT 24
Peak memory 223064 kb
Host smart-be385449-ab5f-4a41-9778-0c84a780dd27
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=799338463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direc
t.799338463
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.2387947266
Short name T738
Test name
Test status
Simulation time 111482088 ps
CPU time 1.2 seconds
Started Mar 26 03:05:24 PM PDT 24
Finished Mar 26 03:05:26 PM PDT 24
Peak memory 207568 kb
Host smart-57beceaa-ccb4-44c6-a972-b84ca0851209
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387947266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.2387947266
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.4002247299
Short name T440
Test name
Test status
Simulation time 3218111754 ps
CPU time 15.42 seconds
Started Mar 26 03:05:18 PM PDT 24
Finished Mar 26 03:05:33 PM PDT 24
Peak memory 216760 kb
Host smart-609bd942-9641-48e2-b93b-a3f2785e3b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002247299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.4002247299
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.3499581702
Short name T870
Test name
Test status
Simulation time 846068671 ps
CPU time 2.47 seconds
Started Mar 26 03:05:19 PM PDT 24
Finished Mar 26 03:05:22 PM PDT 24
Peak memory 216444 kb
Host smart-b698ee46-2be7-4331-9757-ab87de94c64f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499581702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.3499581702
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.3237316977
Short name T438
Test name
Test status
Simulation time 883445507 ps
CPU time 6.12 seconds
Started Mar 26 03:05:19 PM PDT 24
Finished Mar 26 03:05:25 PM PDT 24
Peak memory 216668 kb
Host smart-745cf08d-2018-46f8-aec9-ac86f55a70a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237316977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.3237316977
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.3191916157
Short name T344
Test name
Test status
Simulation time 57380233 ps
CPU time 0.91 seconds
Started Mar 26 03:05:19 PM PDT 24
Finished Mar 26 03:05:20 PM PDT 24
Peak memory 206172 kb
Host smart-84c3f94f-2c44-4075-ac4e-dda080fb8a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191916157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.3191916157
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.2894258111
Short name T614
Test name
Test status
Simulation time 5428101014 ps
CPU time 18.97 seconds
Started Mar 26 03:05:23 PM PDT 24
Finished Mar 26 03:05:42 PM PDT 24
Peak memory 241376 kb
Host smart-1970e7fb-ce02-436f-b25d-aac8adcb4575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894258111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.2894258111
Directory /workspace/9.spi_device_upload/latest
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