Group : tl_agent_pkg::pending_req_on_rst_cg
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Group : tl_agent_pkg::pending_req_on_rst_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
50.00 50.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_pending_req_on_rst_cg 50.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_pending_req_on_rst_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_pending_req_on_rst_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 1 1 50.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_pending_req_on_rst_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_pending 2 1 1 50.00 100 1 1 0


Summary for Variable cp_req_pending

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 1 1 50.00


User Defined Bins for cp_req_pending

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
values[0x1] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x0] 603 1 T2 2 T9 1 T12 2

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%