Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5941967	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

6217774

1

T1

1

T2

11969

T3

912

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	7823761	1			T1	75		T2	11265		T3	16
values[0x0]	2167490	1			T2	5095		T3	456		T4	2140
values[0x1]	2168490	1			T2	4907		T3	451		T4	2107

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4298087	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

7861654

1

T1

27

T2

14703

T3

912

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	51904	1			T2	85		T3	2		T5	43
valid_sources[0x01]	46074	1			T2	53		T3	4		T5	39
valid_sources[0x02]	45350	1			T2	102		T3	4		T4	810
valid_sources[0x03]	44486	1			T2	72		T3	3		T5	36
valid_sources[0x04]	51863	1			T2	91		T3	8		T5	51
valid_sources[0x05]	48441	1			T2	86		T3	3		T5	48
valid_sources[0x06]	46439	1			T2	93		T3	1		T5	26
valid_sources[0x07]	46690	1			T2	81		T3	11		T5	33
valid_sources[0x08]	41976	1			T2	98		T3	3		T4	1
valid_sources[0x09]	48078	1			T2	88		T3	6		T5	37
valid_sources[0x0a]	48671	1			T2	64		T3	2		T5	57
valid_sources[0x0b]	50700	1			T2	53		T3	6		T5	44
valid_sources[0x0c]	46396	1			T2	64		T3	2		T5	55
valid_sources[0x0d]	49904	1			T2	65		T3	2		T5	39
valid_sources[0x0e]	48629	1			T2	93		T3	3		T4	2
valid_sources[0x0f]	44598	1			T2	84		T3	4		T5	37
valid_sources[0x10]	43235	1			T2	91		T3	2		T5	39
valid_sources[0x11]	43158	1			T2	69		T3	2		T4	1
valid_sources[0x12]	50292	1			T2	91		T3	8		T5	29
valid_sources[0x13]	45631	1			T2	87		T3	4		T5	46
valid_sources[0x14]	49570	1			T2	124		T3	1		T5	37
valid_sources[0x15]	47683	1			T2	88		T3	3		T5	46
valid_sources[0x16]	45566	1			T2	92		T3	3		T4	1
valid_sources[0x17]	46191	1			T2	66		T3	3		T4	1
valid_sources[0x18]	46884	1			T2	64		T3	4		T5	52
valid_sources[0x19]	44013	1			T2	73		T3	5		T4	1
valid_sources[0x1a]	46140	1			T2	50		T3	3		T5	53
valid_sources[0x1b]	47518	1			T2	73		T3	6		T5	43
valid_sources[0x1c]	50303	1			T2	104		T3	2		T4	1
valid_sources[0x1d]	46518	1			T2	58		T3	1		T5	41
valid_sources[0x1e]	46857	1			T2	93		T3	3		T5	37
valid_sources[0x1f]	48650	1			T2	65		T3	2		T5	23
valid_sources[0x20]	52711	1			T2	117		T3	6		T5	37
valid_sources[0x21]	45169	1			T2	78		T3	7		T5	33
valid_sources[0x22]	48130	1			T2	92		T3	2		T4	1
valid_sources[0x23]	46276	1			T2	106		T3	2		T5	48
valid_sources[0x24]	42994	1			T2	100		T3	3		T5	49
valid_sources[0x25]	44914	1			T2	101		T3	4		T5	46
valid_sources[0x26]	47701	1			T2	85		T3	4		T5	32
valid_sources[0x27]	49309	1			T2	98		T3	3		T4	42
valid_sources[0x28]	52861	1			T2	98		T3	3		T5	47
valid_sources[0x29]	51549	1			T2	71		T3	5		T4	1
valid_sources[0x2a]	45683	1			T2	100		T3	4		T5	27
valid_sources[0x2b]	48291	1			T2	73		T3	1		T5	46
valid_sources[0x2c]	48510	1			T1	75		T2	72		T3	5
valid_sources[0x2d]	47159	1			T2	80		T3	8		T4	1
valid_sources[0x2e]	51263	1			T2	99		T3	7		T5	46
valid_sources[0x2f]	43850	1			T2	86		T5	36		T6	994
valid_sources[0x30]	47537	1			T2	93		T3	1		T5	49
valid_sources[0x31]	46283	1			T2	77		T3	2		T4	1
valid_sources[0x32]	46923	1			T2	74		T3	3		T5	49
valid_sources[0x33]	51092	1			T2	77		T4	1		T5	45
valid_sources[0x34]	47213	1			T2	79		T3	5		T5	36
valid_sources[0x35]	45083	1			T2	74		T3	3		T4	1
valid_sources[0x36]	47141	1			T2	114		T3	4		T4	823
valid_sources[0x37]	46197	1			T2	94		T3	5		T4	1
valid_sources[0x38]	45266	1			T2	78		T3	5		T4	1
valid_sources[0x39]	46940	1			T2	74		T3	3		T4	1
valid_sources[0x3a]	43720	1			T2	65		T3	4		T5	48
valid_sources[0x3b]	45494	1			T2	84		T3	1		T4	169
valid_sources[0x3c]	47570	1			T2	78		T3	4		T5	29
valid_sources[0x3d]	48775	1			T2	65		T3	3		T5	35
valid_sources[0x3e]	47523	1			T2	109		T3	5		T5	46
valid_sources[0x3f]	48791	1			T2	85		T3	6		T5	41
valid_sources[0x40]	48739	1			T2	109		T3	2		T4	1
valid_sources[0x41]	46727	1			T2	67		T3	3		T4	524
valid_sources[0x42]	46713	1			T2	100		T3	5		T4	1
valid_sources[0x43]	50658	1			T2	61		T3	2		T5	41
valid_sources[0x44]	50339	1			T2	82		T3	1		T4	1
valid_sources[0x45]	47277	1			T2	75		T3	9		T4	1
valid_sources[0x46]	45042	1			T2	65		T3	3		T4	728
valid_sources[0x47]	47834	1			T2	73		T3	2		T5	41
valid_sources[0x48]	52202	1			T2	78		T3	4		T4	304
valid_sources[0x49]	46639	1			T2	80		T3	3		T5	38
valid_sources[0x4a]	46938	1			T2	64		T3	3		T5	40
valid_sources[0x4b]	57173	1			T2	81		T3	4		T4	1
valid_sources[0x4c]	49451	1			T2	68		T3	5		T5	45
valid_sources[0x4d]	46405	1			T2	83		T3	4		T4	1
valid_sources[0x4e]	45612	1			T2	71		T3	3		T5	47
valid_sources[0x4f]	46414	1			T2	88		T3	6		T5	39
valid_sources[0x50]	43960	1			T2	63		T3	2		T5	53
valid_sources[0x51]	45533	1			T2	87		T3	3		T5	45
valid_sources[0x52]	51749	1			T2	113		T3	2		T5	47
valid_sources[0x53]	47531	1			T2	103		T3	5		T5	56
valid_sources[0x54]	51557	1			T2	91		T3	1		T4	824
valid_sources[0x55]	53715	1			T2	90		T3	3		T5	45
valid_sources[0x56]	53039	1			T2	79		T3	4		T5	47
valid_sources[0x57]	48565	1			T2	85		T3	2		T5	50
valid_sources[0x58]	49366	1			T2	74		T3	2		T5	28
valid_sources[0x59]	47652	1			T2	73		T3	3		T4	1
valid_sources[0x5a]	48821	1			T2	81		T3	4		T4	336
valid_sources[0x5b]	49742	1			T2	68		T3	3		T4	2
valid_sources[0x5c]	51016	1			T2	84		T3	2		T5	42
valid_sources[0x5d]	44557	1			T2	97		T3	2		T4	1
valid_sources[0x5e]	48180	1			T2	80		T3	4		T5	45
valid_sources[0x5f]	48586	1			T2	81		T3	6		T5	41
valid_sources[0x60]	45127	1			T2	108		T3	5		T4	1
valid_sources[0x61]	45001	1			T2	72		T3	4		T5	32
valid_sources[0x62]	42312	1			T2	85		T3	5		T4	1
valid_sources[0x63]	44321	1			T2	107		T3	1		T4	2
valid_sources[0x64]	44804	1			T2	74		T3	2		T4	193
valid_sources[0x65]	53505	1			T2	97		T3	1		T5	47
valid_sources[0x66]	45062	1			T2	82		T3	3		T5	45
valid_sources[0x67]	45313	1			T2	92		T3	4		T4	1
valid_sources[0x68]	44358	1			T2	91		T3	2		T4	2
valid_sources[0x69]	51363	1			T2	73		T3	8		T5	41
valid_sources[0x6a]	47594	1			T2	90		T3	6		T5	44
valid_sources[0x6b]	44309	1			T2	106		T3	6		T5	57
valid_sources[0x6c]	48723	1			T2	117		T3	2		T4	167
valid_sources[0x6d]	45345	1			T2	82		T3	3		T4	831
valid_sources[0x6e]	48604	1			T2	86		T3	1		T4	1
valid_sources[0x6f]	43785	1			T2	86		T3	6		T4	27
valid_sources[0x70]	49516	1			T2	50		T3	3		T5	34
valid_sources[0x71]	44887	1			T2	81		T3	7		T4	1
valid_sources[0x72]	44532	1			T2	88		T3	5		T5	41
valid_sources[0x73]	52958	1			T2	77		T3	1		T4	2
valid_sources[0x74]	45164	1			T2	109		T3	6		T5	38
valid_sources[0x75]	49968	1			T2	72		T3	1		T5	35
valid_sources[0x76]	46226	1			T2	93		T3	4		T5	37
valid_sources[0x77]	48435	1			T2	92		T3	3		T4	1
valid_sources[0x78]	47138	1			T2	77		T3	5		T4	2
valid_sources[0x79]	48417	1			T2	109		T3	3		T5	36
valid_sources[0x7a]	48229	1			T2	79		T3	5		T5	44
valid_sources[0x7b]	48420	1			T2	75		T3	5		T5	34
valid_sources[0x7c]	49328	1			T2	66		T3	3		T5	29
valid_sources[0x7d]	46631	1			T2	67		T3	2		T5	46
valid_sources[0x7e]	51116	1			T2	92		T3	4		T4	1
valid_sources[0x7f]	48938	1			T2	54		T3	2		T5	39
valid_sources[0x80]	47517	1			T2	96		T3	3		T5	39

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

2345089

1

T1

1

T2

3288

T3

8

values[0x0]

all_enables

biggest_size

1951913

1

T2

4479

T3

455

T4

2129

values[0x1]

all_enables

biggest_size

1920772

1

T2

4202

T3

449

T4

2089