Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

5961965

1

T1

74

T2

9298

T3

11

full_word

6218909

1

T1

1

T2

11969

T3

912

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	12180534	1			T1	75		T2	21267		T3	923
auto[TlIntgErrCmd]	103	1			T49	3		T80	5		T83	1
auto[TlIntgErrData]	118	1			T49	9		T80	9		T83	3
auto[TlIntgErrBoth]	119	1			T49	8		T80	6		T83	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7826834

1

T1

75

T2

11265

T3

16

auto[1]

4354040

1

T2

10002

T3

907

T4

4247

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	5481337	1			T1	74		T2	7977		T3	8
auto[TlIntgErrNone]	partial	auto[1]	480309	1			T2	1321		T3	3		T4	29
auto[TlIntgErrNone]	full_word	auto[0]	2345345	1			T1	1		T2	3288		T3	8
auto[TlIntgErrNone]	full_word	auto[1]	3873543	1			T2	8681		T3	904		T4	4218
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T49	2		T80	2		T141	3
auto[TlIntgErrCmd]	partial	auto[1]	54	1			T49	1		T80	2		T83	1
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T143	1		T144	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T80	1		T138	1		T145	1
auto[TlIntgErrData]	partial	auto[0]	54	1			T49	3		T80	4		T83	3
auto[TlIntgErrData]	partial	auto[1]	54	1			T49	4		T80	5		T124	3
auto[TlIntgErrData]	full_word	auto[0]	7	1			T49	2		T125	1		T139	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T125	1		T90	1		T146	1
auto[TlIntgErrBoth]	partial	auto[0]	43	1			T49	1		T80	3		T83	2
auto[TlIntgErrBoth]	partial	auto[1]	71	1			T49	7		T80	3		T83	4
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T141	1		T147	2		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T138	1		T144	1		-	-