Unified Coverage Report :: Module :: prim_generic_ram_1r1w

Module : prim_generic_ram_1r1w

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_ram_1r1w

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	724878271	3565443	0	0
gen_wmask[1].MaskCheckPortA_A	724878271	3565443	0	0
gen_wmask[2].MaskCheckPortA_A	724878271	3565443	0	0
gen_wmask[3].MaskCheckPortA_A	724878271	3565443	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724878271	3565443	0	0
T2	1101627	9383	0	0
T3	532082	832	0	0
T4	240603	4160	0	0
T5	1090564	2880	0	0
T6	1115604	32601	0	0
T7	316565	832	0	0
T8	147649	1344	0	0
T9	5429	0	0	0
T10	49292	832	0	0
T11	335852	832	0	0
T12	169415	36373	0	0
T13	0	221	0	0
T14	0	3176	0	0
T16	0	132	0	0
T21	0	2688	0	0
T22	0	235	0	0
T23	0	9855	0	0
T24	0	427	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724878271	3565443	0	0
T2	1101627	9383	0	0
T3	532082	832	0	0
T4	240603	4160	0	0
T5	1090564	2880	0	0
T6	1115604	32601	0	0
T7	316565	832	0	0
T8	147649	1344	0	0
T9	5429	0	0	0
T10	49292	832	0	0
T11	335852	832	0	0
T12	169415	36373	0	0
T13	0	221	0	0
T14	0	3176	0	0
T16	0	132	0	0
T21	0	2688	0	0
T22	0	235	0	0
T23	0	9855	0	0
T24	0	427	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724878271	3565443	0	0
T2	1101627	9383	0	0
T3	532082	832	0	0
T4	240603	4160	0	0
T5	1090564	2880	0	0
T6	1115604	32601	0	0
T7	316565	832	0	0
T8	147649	1344	0	0
T9	5429	0	0	0
T10	49292	832	0	0
T11	335852	832	0	0
T12	169415	36373	0	0
T13	0	221	0	0
T14	0	3176	0	0
T16	0	132	0	0
T21	0	2688	0	0
T22	0	235	0	0
T23	0	9855	0	0
T24	0	427	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724878271	3565443	0	0
T2	1101627	9383	0	0
T3	532082	832	0	0
T4	240603	4160	0	0
T5	1090564	2880	0	0
T6	1115604	32601	0	0
T7	316565	832	0	0
T8	147649	1344	0	0
T9	5429	0	0	0
T10	49292	832	0	0
T11	335852	832	0	0
T12	169415	36373	0	0
T13	0	221	0	0
T14	0	3176	0	0
T16	0	132	0	0
T21	0	2688	0	0
T22	0	235	0	0
T23	0	9855	0	0
T24	0	427	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			==> MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T2,T3,T4

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	546387782	2361629	0	0
gen_wmask[1].MaskCheckPortA_A	546387782	2361629	0	0
gen_wmask[2].MaskCheckPortA_A	546387782	2361629	0	0
gen_wmask[3].MaskCheckPortA_A	546387782	2361629	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546387782	2361629	0	0
T2	563524	5770	0	0
T3	268026	832	0	0
T4	107577	4160	0	0
T5	909689	2880	0	0
T6	976342	17772	0	0
T7	264469	832	0	0
T8	34767	1344	0	0
T9	5429	0	0	0
T10	27701	832	0	0
T11	116306	832	0	0
T12	0	21871	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546387782	2361629	0	0
T2	563524	5770	0	0
T3	268026	832	0	0
T4	107577	4160	0	0
T5	909689	2880	0	0
T6	976342	17772	0	0
T7	264469	832	0	0
T8	34767	1344	0	0
T9	5429	0	0	0
T10	27701	832	0	0
T11	116306	832	0	0
T12	0	21871	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546387782	2361629	0	0
T2	563524	5770	0	0
T3	268026	832	0	0
T4	107577	4160	0	0
T5	909689	2880	0	0
T6	976342	17772	0	0
T7	264469	832	0	0
T8	34767	1344	0	0
T9	5429	0	0	0
T10	27701	832	0	0
T11	116306	832	0	0
T12	0	21871	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546387782	2361629	0	0
T2	563524	5770	0	0
T3	268026	832	0	0
T4	107577	4160	0	0
T5	909689	2880	0	0
T6	976342	17772	0	0
T7	264469	832	0	0
T8	34767	1344	0	0
T9	5429	0	0	0
T10	27701	832	0	0
T11	116306	832	0	0
T12	0	21871	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T12
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T12
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	178490489	1203814	0	0
gen_wmask[1].MaskCheckPortA_A	178490489	1203814	0	0
gen_wmask[2].MaskCheckPortA_A	178490489	1203814	0	0
gen_wmask[3].MaskCheckPortA_A	178490489	1203814	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178490489	1203814	0	0
T2	538103	3613	0	0
T3	264056	0	0	0
T4	133026	0	0	0
T5	180875	0	0	0
T6	139262	14829	0	0
T7	52096	0	0	0
T8	112882	0	0	0
T10	21591	0	0	0
T11	219546	0	0	0
T12	169415	14502	0	0
T13	0	221	0	0
T14	0	3176	0	0
T16	0	132	0	0
T21	0	2688	0	0
T22	0	235	0	0
T23	0	9855	0	0
T24	0	427	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178490489	1203814	0	0
T2	538103	3613	0	0
T3	264056	0	0	0
T4	133026	0	0	0
T5	180875	0	0	0
T6	139262	14829	0	0
T7	52096	0	0	0
T8	112882	0	0	0
T10	21591	0	0	0
T11	219546	0	0	0
T12	169415	14502	0	0
T13	0	221	0	0
T14	0	3176	0	0
T16	0	132	0	0
T21	0	2688	0	0
T22	0	235	0	0
T23	0	9855	0	0
T24	0	427	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178490489	1203814	0	0
T2	538103	3613	0	0
T3	264056	0	0	0
T4	133026	0	0	0
T5	180875	0	0	0
T6	139262	14829	0	0
T7	52096	0	0	0
T8	112882	0	0	0
T10	21591	0	0	0
T11	219546	0	0	0
T12	169415	14502	0	0
T13	0	221	0	0
T14	0	3176	0	0
T16	0	132	0	0
T21	0	2688	0	0
T22	0	235	0	0
T23	0	9855	0	0
T24	0	427	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178490489	1203814	0	0
T2	538103	3613	0	0
T3	264056	0	0	0
T4	133026	0	0	0
T5	180875	0	0	0
T6	139262	14829	0	0
T7	52096	0	0	0
T8	112882	0	0	0
T10	21591	0	0	0
T11	219546	0	0	0
T12	169415	14502	0	0
T13	0	221	0	0
T14	0	3176	0	0
T16	0	132	0	0
T21	0	2688	0	0
T22	0	235	0	0
T23	0	9855	0	0
T24	0	427	0	0