Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T6,T12
1	0	Covered	T2,T6,T12

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T12
1	0	Unreachable
1	1	Covered	T2,T6,T12

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T12

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T6,T12
1	0	Covered	T2,T6,T12

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Unreachable
1	1	Covered	T2,T6,T12

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T12

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T6,T12
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	903368760	722946890	0	0
CheckNGreaterZero_A	2763	2763	0	0
GntImpliesReady_A	903368760	4082378	0	0
GntImpliesValid_A	903368760	4082378	0	0
GrantKnown_A	903368760	722946890	0	0
IdxKnown_A	903368760	722946890	0	0
IndexIsCorrect_A	903368760	4082378	0	0
LockArbDecision_A	903368760	0	0	0
NoReadyValidNoGrant_A	903368760	0	0	0
ReadyAndValidImplyGrant_A	903368760	4082378	0	0
ReqAndReadyImplyGrant_A	903368760	4082378	0	0
ReqImpliesValid_A	903368760	4082378	0	0
ReqStaysHighUntilGranted0_M	903368760	0	0	0
RoundRobin_A	903368760	6	0	921
ValidKnown_A	903368760	722946890	0	0
gen_data_port_assertion.DataFlow_A	903368760	4082378	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	903368760	722946890	0	0
T1	1396	1310	0	0
T2	1639730	1094148	0	0
T3	796138	531744	0	0
T4	373629	240228	0	0
T5	1271439	1090384	0	0
T6	1254866	1239299	0	0
T7	368661	316485	0	0
T8	260531	146705	0	0
T9	5429	5294	0	0
T10	70883	48778	0	0
T11	439092	219182	0	0
T12	338830	462682	0	0
T13	0	9152	0	0
T14	0	77880	0	0
T15	0	66232	0	0
T16	0	2512	0	0
T17	0	84896	0	0
T21	0	107432	0	0
T22	0	3128	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2763	2763	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	903368760	4082378	0	0
T2	1639730	12081	0	0
T3	796138	832	0	0
T4	373629	4160	0	0
T5	1271439	2880	0	0
T6	1254866	36585	0	0
T7	368661	832	0	0
T8	260531	1344	0	0
T9	5429	0	0	0
T10	70883	832	0	0
T11	555398	832	0	0
T12	338830	40310	0	0
T13	0	329	0	0
T14	0	4193	0	0
T16	0	166	0	0
T18	0	1677	0	0
T21	0	4173	0	0
T22	0	258	0	0
T23	0	12756	0	0
T24	0	458	0	0
T26	0	2559	0	0
T27	0	1739	0	0
T33	0	780	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	903368760	4082378	0	0
T2	1639730	12081	0	0
T3	796138	832	0	0
T4	373629	4160	0	0
T5	1271439	2880	0	0
T6	1254866	36585	0	0
T7	368661	832	0	0
T8	260531	1344	0	0
T9	5429	0	0	0
T10	70883	832	0	0
T11	555398	832	0	0
T12	338830	40310	0	0
T13	0	329	0	0
T14	0	4193	0	0
T16	0	166	0	0
T18	0	1677	0	0
T21	0	4173	0	0
T22	0	258	0	0
T23	0	12756	0	0
T24	0	458	0	0
T26	0	2559	0	0
T27	0	1739	0	0
T33	0	780	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	903368760	722946890	0	0
T1	1396	1310	0	0
T2	1639730	1094148	0	0
T3	796138	531744	0	0
T4	373629	240228	0	0
T5	1271439	1090384	0	0
T6	1254866	1239299	0	0
T7	368661	316485	0	0
T8	260531	146705	0	0
T9	5429	5294	0	0
T10	70883	48778	0	0
T11	439092	219182	0	0
T12	338830	462682	0	0
T13	0	9152	0	0
T14	0	77880	0	0
T15	0	66232	0	0
T16	0	2512	0	0
T17	0	84896	0	0
T21	0	107432	0	0
T22	0	3128	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	903368760	722946890	0	0
T1	1396	1310	0	0
T2	1639730	1094148	0	0
T3	796138	531744	0	0
T4	373629	240228	0	0
T5	1271439	1090384	0	0
T6	1254866	1239299	0	0
T7	368661	316485	0	0
T8	260531	146705	0	0
T9	5429	5294	0	0
T10	70883	48778	0	0
T11	439092	219182	0	0
T12	338830	462682	0	0
T13	0	9152	0	0
T14	0	77880	0	0
T15	0	66232	0	0
T16	0	2512	0	0
T17	0	84896	0	0
T21	0	107432	0	0
T22	0	3128	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	903368760	4082378	0	0
T2	1639730	12081	0	0
T3	796138	832	0	0
T4	373629	4160	0	0
T5	1271439	2880	0	0
T6	1254866	36585	0	0
T7	368661	832	0	0
T8	260531	1344	0	0
T9	5429	0	0	0
T10	70883	832	0	0
T11	555398	832	0	0
T12	338830	40310	0	0
T13	0	329	0	0
T14	0	4193	0	0
T16	0	166	0	0
T18	0	1677	0	0
T21	0	4173	0	0
T22	0	258	0	0
T23	0	12756	0	0
T24	0	458	0	0
T26	0	2559	0	0
T27	0	1739	0	0
T33	0	780	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	903368760	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	903368760	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	903368760	4082378	0	0
T2	1639730	12081	0	0
T3	796138	832	0	0
T4	373629	4160	0	0
T5	1271439	2880	0	0
T6	1254866	36585	0	0
T7	368661	832	0	0
T8	260531	1344	0	0
T9	5429	0	0	0
T10	70883	832	0	0
T11	555398	832	0	0
T12	338830	40310	0	0
T13	0	329	0	0
T14	0	4193	0	0
T16	0	166	0	0
T18	0	1677	0	0
T21	0	4173	0	0
T22	0	258	0	0
T23	0	12756	0	0
T24	0	458	0	0
T26	0	2559	0	0
T27	0	1739	0	0
T33	0	780	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	903368760	4082378	0	0
T2	1639730	12081	0	0
T3	796138	832	0	0
T4	373629	4160	0	0
T5	1271439	2880	0	0
T6	1254866	36585	0	0
T7	368661	832	0	0
T8	260531	1344	0	0
T9	5429	0	0	0
T10	70883	832	0	0
T11	555398	832	0	0
T12	338830	40310	0	0
T13	0	329	0	0
T14	0	4193	0	0
T16	0	166	0	0
T18	0	1677	0	0
T21	0	4173	0	0
T22	0	258	0	0
T23	0	12756	0	0
T24	0	458	0	0
T26	0	2559	0	0
T27	0	1739	0	0
T33	0	780	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	903368760	4082378	0	0
T2	1639730	12081	0	0
T3	796138	832	0	0
T4	373629	4160	0	0
T5	1271439	2880	0	0
T6	1254866	36585	0	0
T7	368661	832	0	0
T8	260531	1344	0	0
T9	5429	0	0	0
T10	70883	832	0	0
T11	555398	832	0	0
T12	338830	40310	0	0
T13	0	329	0	0
T14	0	4193	0	0
T16	0	166	0	0
T18	0	1677	0	0
T21	0	4173	0	0
T22	0	258	0	0
T23	0	12756	0	0
T24	0	458	0	0
T26	0	2559	0	0
T27	0	1739	0	0
T33	0	780	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	903368760	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	903368760	6	0	921
T18	302003	1	0	1
T27	928068	0	0	1
T31	0	1	0	0
T34	588168	0	0	1
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	11002	0	0	1
T40	9369	0	0	1
T41	77814	0	0	1
T42	902	0	0	1
T43	919916	0	0	1
T44	396401	0	0	1
T45	16234	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	903368760	722946890	0	0
T1	1396	1310	0	0
T2	1639730	1094148	0	0
T3	796138	531744	0	0
T4	373629	240228	0	0
T5	1271439	1090384	0	0
T6	1254866	1239299	0	0
T7	368661	316485	0	0
T8	260531	146705	0	0
T9	5429	5294	0	0
T10	70883	48778	0	0
T11	439092	219182	0	0
T12	338830	462682	0	0
T13	0	9152	0	0
T14	0	77880	0	0
T15	0	66232	0	0
T16	0	2512	0	0
T17	0	84896	0	0
T21	0	107432	0	0
T22	0	3128	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	903368760	4082378	0	0
T2	1639730	12081	0	0
T3	796138	832	0	0
T4	373629	4160	0	0
T5	1271439	2880	0	0
T6	1254866	36585	0	0
T7	368661	832	0	0
T8	260531	1344	0	0
T9	5429	0	0	0
T10	70883	832	0	0
T11	555398	832	0	0
T12	338830	40310	0	0
T13	0	329	0	0
T14	0	4193	0	0
T16	0	166	0	0
T18	0	1677	0	0
T21	0	4173	0	0
T22	0	258	0	0
T23	0	12756	0	0
T24	0	458	0	0
T26	0	2559	0	0
T27	0	1739	0	0
T33	0	780	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T6,T12
1	0	Covered	T2,T6,T12

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T12
1	0	Unreachable
1	1	Covered	T2,T6,T12

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T6,T12
0	0	1	Unreachable
0	0	0	Covered	T2,T6,T12

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T12
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	178490489	41113805	0	0
CheckNGreaterZero_A	921	921	0	0
GntImpliesReady_A	178490489	924777	0	0
GntImpliesValid_A	178490489	924777	0	0
GrantKnown_A	178490489	41113805	0	0
IdxKnown_A	178490489	41113805	0	0
IndexIsCorrect_A	178490489	924777	0	0
LockArbDecision_A	178490489	0	0	0
NoReadyValidNoGrant_A	178490489	0	0	0
ReadyAndValidImplyGrant_A	178490489	924777	0	0
ReqAndReadyImplyGrant_A	178490489	924777	0	0
ReqImpliesValid_A	178490489	924777	0	0
ReqStaysHighUntilGranted0_M	178490489	0	0	0
RoundRobin_A	178490489	0	0	0
ValidKnown_A	178490489	41113805	0	0
gen_data_port_assertion.DataFlow_A	178490489	924777	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178490489	41113805	0	0
T2	538103	217760	0	0
T3	264056	0	0	0
T4	133026	0	0	0
T5	180875	0	0	0
T6	139262	138712	0	0
T7	52096	0	0	0
T8	112882	0	0	0
T10	21591	0	0	0
T11	219546	0	0	0
T12	169415	327792	0	0
T13	0	9152	0	0
T14	0	77880	0	0
T15	0	66232	0	0
T16	0	2512	0	0
T17	0	84896	0	0
T21	0	107432	0	0
T22	0	3128	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	921	921	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178490489	924777	0	0
T2	538103	5236	0	0
T3	264056	0	0	0
T4	133026	0	0	0
T5	180875	0	0	0
T6	139262	6508	0	0
T7	52096	0	0	0
T8	112882	0	0	0
T10	21591	0	0	0
T11	219546	0	0	0
T12	169415	6058	0	0
T13	0	329	0	0
T14	0	3143	0	0
T16	0	166	0	0
T21	0	4173	0	0
T22	0	258	0	0
T23	0	8497	0	0
T24	0	458	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178490489	924777	0	0
T2	538103	5236	0	0
T3	264056	0	0	0
T4	133026	0	0	0
T5	180875	0	0	0
T6	139262	6508	0	0
T7	52096	0	0	0
T8	112882	0	0	0
T10	21591	0	0	0
T11	219546	0	0	0
T12	169415	6058	0	0
T13	0	329	0	0
T14	0	3143	0	0
T16	0	166	0	0
T21	0	4173	0	0
T22	0	258	0	0
T23	0	8497	0	0
T24	0	458	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178490489	41113805	0	0
T2	538103	217760	0	0
T3	264056	0	0	0
T4	133026	0	0	0
T5	180875	0	0	0
T6	139262	138712	0	0
T7	52096	0	0	0
T8	112882	0	0	0
T10	21591	0	0	0
T11	219546	0	0	0
T12	169415	327792	0	0
T13	0	9152	0	0
T14	0	77880	0	0
T15	0	66232	0	0
T16	0	2512	0	0
T17	0	84896	0	0
T21	0	107432	0	0
T22	0	3128	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178490489	41113805	0	0
T2	538103	217760	0	0
T3	264056	0	0	0
T4	133026	0	0	0
T5	180875	0	0	0
T6	139262	138712	0	0
T7	52096	0	0	0
T8	112882	0	0	0
T10	21591	0	0	0
T11	219546	0	0	0
T12	169415	327792	0	0
T13	0	9152	0	0
T14	0	77880	0	0
T15	0	66232	0	0
T16	0	2512	0	0
T17	0	84896	0	0
T21	0	107432	0	0
T22	0	3128	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178490489	924777	0	0
T2	538103	5236	0	0
T3	264056	0	0	0
T4	133026	0	0	0
T5	180875	0	0	0
T6	139262	6508	0	0
T7	52096	0	0	0
T8	112882	0	0	0
T10	21591	0	0	0
T11	219546	0	0	0
T12	169415	6058	0	0
T13	0	329	0	0
T14	0	3143	0	0
T16	0	166	0	0
T21	0	4173	0	0
T22	0	258	0	0
T23	0	8497	0	0
T24	0	458	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178490489	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178490489	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178490489	924777	0	0
T2	538103	5236	0	0
T3	264056	0	0	0
T4	133026	0	0	0
T5	180875	0	0	0
T6	139262	6508	0	0
T7	52096	0	0	0
T8	112882	0	0	0
T10	21591	0	0	0
T11	219546	0	0	0
T12	169415	6058	0	0
T13	0	329	0	0
T14	0	3143	0	0
T16	0	166	0	0
T21	0	4173	0	0
T22	0	258	0	0
T23	0	8497	0	0
T24	0	458	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178490489	924777	0	0
T2	538103	5236	0	0
T3	264056	0	0	0
T4	133026	0	0	0
T5	180875	0	0	0
T6	139262	6508	0	0
T7	52096	0	0	0
T8	112882	0	0	0
T10	21591	0	0	0
T11	219546	0	0	0
T12	169415	6058	0	0
T13	0	329	0	0
T14	0	3143	0	0
T16	0	166	0	0
T21	0	4173	0	0
T22	0	258	0	0
T23	0	8497	0	0
T24	0	458	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178490489	924777	0	0
T2	538103	5236	0	0
T3	264056	0	0	0
T4	133026	0	0	0
T5	180875	0	0	0
T6	139262	6508	0	0
T7	52096	0	0	0
T8	112882	0	0	0
T10	21591	0	0	0
T11	219546	0	0	0
T12	169415	6058	0	0
T13	0	329	0	0
T14	0	3143	0	0
T16	0	166	0	0
T21	0	4173	0	0
T22	0	258	0	0
T23	0	8497	0	0
T24	0	458	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	178490489	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178490489	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178490489	41113805	0	0
T2	538103	217760	0	0
T3	264056	0	0	0
T4	133026	0	0	0
T5	180875	0	0	0
T6	139262	138712	0	0
T7	52096	0	0	0
T8	112882	0	0	0
T10	21591	0	0	0
T11	219546	0	0	0
T12	169415	327792	0	0
T13	0	9152	0	0
T14	0	77880	0	0
T15	0	66232	0	0
T16	0	2512	0	0
T17	0	84896	0	0
T21	0	107432	0	0
T22	0	3128	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178490489	924777	0	0
T2	538103	5236	0	0
T3	264056	0	0	0
T4	133026	0	0	0
T5	180875	0	0	0
T6	139262	6508	0	0
T7	52096	0	0	0
T8	112882	0	0	0
T10	21591	0	0	0
T11	219546	0	0	0
T12	169415	6058	0	0
T13	0	329	0	0
T14	0	3143	0	0
T16	0	166	0	0
T21	0	4173	0	0
T22	0	258	0	0
T23	0	8497	0	0
T24	0	458	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T12

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T6,T12
1	0	Covered	T2,T6,T12

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Unreachable
1	1	Covered	T2,T6,T12

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T6,T12
0	0	1	Unreachable
0	0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T12
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	178490489	135530114	0	0
CheckNGreaterZero_A	921	921	0	0
GntImpliesReady_A	178490489	583185	0	0
GntImpliesValid_A	178490489	583185	0	0
GrantKnown_A	178490489	135530114	0	0
IdxKnown_A	178490489	135530114	0	0
IndexIsCorrect_A	178490489	583185	0	0
LockArbDecision_A	178490489	0	0	0
NoReadyValidNoGrant_A	178490489	0	0	0
ReadyAndValidImplyGrant_A	178490489	583185	0	0
ReqAndReadyImplyGrant_A	178490489	583185	0	0
ReqImpliesValid_A	178490489	583185	0	0
ReqStaysHighUntilGranted0_M	178490489	0	0	0
RoundRobin_A	178490489	0	0	0
ValidKnown_A	178490489	135530114	0	0
gen_data_port_assertion.DataFlow_A	178490489	583185	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178490489	135530114	0	0
T2	538103	313070	0	0
T3	264056	263790	0	0
T4	133026	132658	0	0
T5	180875	180770	0	0
T6	139262	124254	0	0
T7	52096	52096	0	0
T8	112882	112025	0	0
T10	21591	21168	0	0
T11	219546	219182	0	0
T12	169415	134890	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	921	921	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178490489	583185	0	0
T2	538103	143	0	0
T3	264056	0	0	0
T4	133026	0	0	0
T5	180875	0	0	0
T6	139262	10476	0	0
T7	52096	0	0	0
T8	112882	0	0	0
T10	21591	0	0	0
T11	219546	0	0	0
T12	169415	10535	0	0
T14	0	1050	0	0
T18	0	1677	0	0
T23	0	4259	0	0
T26	0	2559	0	0
T27	0	1739	0	0
T33	0	780	0	0
T34	0	7016	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178490489	583185	0	0
T2	538103	143	0	0
T3	264056	0	0	0
T4	133026	0	0	0
T5	180875	0	0	0
T6	139262	10476	0	0
T7	52096	0	0	0
T8	112882	0	0	0
T10	21591	0	0	0
T11	219546	0	0	0
T12	169415	10535	0	0
T14	0	1050	0	0
T18	0	1677	0	0
T23	0	4259	0	0
T26	0	2559	0	0
T27	0	1739	0	0
T33	0	780	0	0
T34	0	7016	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178490489	135530114	0	0
T2	538103	313070	0	0
T3	264056	263790	0	0
T4	133026	132658	0	0
T5	180875	180770	0	0
T6	139262	124254	0	0
T7	52096	52096	0	0
T8	112882	112025	0	0
T10	21591	21168	0	0
T11	219546	219182	0	0
T12	169415	134890	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178490489	135530114	0	0
T2	538103	313070	0	0
T3	264056	263790	0	0
T4	133026	132658	0	0
T5	180875	180770	0	0
T6	139262	124254	0	0
T7	52096	52096	0	0
T8	112882	112025	0	0
T10	21591	21168	0	0
T11	219546	219182	0	0
T12	169415	134890	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178490489	583185	0	0
T2	538103	143	0	0
T3	264056	0	0	0
T4	133026	0	0	0
T5	180875	0	0	0
T6	139262	10476	0	0
T7	52096	0	0	0
T8	112882	0	0	0
T10	21591	0	0	0
T11	219546	0	0	0
T12	169415	10535	0	0
T14	0	1050	0	0
T18	0	1677	0	0
T23	0	4259	0	0
T26	0	2559	0	0
T27	0	1739	0	0
T33	0	780	0	0
T34	0	7016	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178490489	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178490489	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178490489	583185	0	0
T2	538103	143	0	0
T3	264056	0	0	0
T4	133026	0	0	0
T5	180875	0	0	0
T6	139262	10476	0	0
T7	52096	0	0	0
T8	112882	0	0	0
T10	21591	0	0	0
T11	219546	0	0	0
T12	169415	10535	0	0
T14	0	1050	0	0
T18	0	1677	0	0
T23	0	4259	0	0
T26	0	2559	0	0
T27	0	1739	0	0
T33	0	780	0	0
T34	0	7016	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178490489	583185	0	0
T2	538103	143	0	0
T3	264056	0	0	0
T4	133026	0	0	0
T5	180875	0	0	0
T6	139262	10476	0	0
T7	52096	0	0	0
T8	112882	0	0	0
T10	21591	0	0	0
T11	219546	0	0	0
T12	169415	10535	0	0
T14	0	1050	0	0
T18	0	1677	0	0
T23	0	4259	0	0
T26	0	2559	0	0
T27	0	1739	0	0
T33	0	780	0	0
T34	0	7016	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178490489	583185	0	0
T2	538103	143	0	0
T3	264056	0	0	0
T4	133026	0	0	0
T5	180875	0	0	0
T6	139262	10476	0	0
T7	52096	0	0	0
T8	112882	0	0	0
T10	21591	0	0	0
T11	219546	0	0	0
T12	169415	10535	0	0
T14	0	1050	0	0
T18	0	1677	0	0
T23	0	4259	0	0
T26	0	2559	0	0
T27	0	1739	0	0
T33	0	780	0	0
T34	0	7016	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	178490489	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178490489	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178490489	135530114	0	0
T2	538103	313070	0	0
T3	264056	263790	0	0
T4	133026	132658	0	0
T5	180875	180770	0	0
T6	139262	124254	0	0
T7	52096	52096	0	0
T8	112882	112025	0	0
T10	21591	21168	0	0
T11	219546	219182	0	0
T12	169415	134890	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178490489	583185	0	0
T2	538103	143	0	0
T3	264056	0	0	0
T4	133026	0	0	0
T5	180875	0	0	0
T6	139262	10476	0	0
T7	52096	0	0	0
T8	112882	0	0	0
T10	21591	0	0	0
T11	219546	0	0	0
T12	169415	10535	0	0
T14	0	1050	0	0
T18	0	1677	0	0
T23	0	4259	0	0
T26	0	2559	0	0
T27	0	1739	0	0
T33	0	780	0	0
T34	0	7016	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T12

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T6,T12
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	546387782	546302971	0	0
CheckNGreaterZero_A	921	921	0	0
GntImpliesReady_A	546387782	2574416	0	0
GntImpliesValid_A	546387782	2574416	0	0
GrantKnown_A	546387782	546302971	0	0
IdxKnown_A	546387782	546302971	0	0
IndexIsCorrect_A	546387782	2574416	0	0
LockArbDecision_A	546387782	0	0	0
NoReadyValidNoGrant_A	546387782	0	0	0
ReadyAndValidImplyGrant_A	546387782	2574416	0	0
ReqAndReadyImplyGrant_A	546387782	2574416	0	0
ReqImpliesValid_A	546387782	2574416	0	0
ReqStaysHighUntilGranted0_M	546387782	0	0	0
RoundRobin_A	546387782	6	0	921
ValidKnown_A	546387782	546302971	0	0
gen_data_port_assertion.DataFlow_A	546387782	2574416	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546387782	546302971	0	0
T1	1396	1310	0	0
T2	563524	563318	0	0
T3	268026	267954	0	0
T4	107577	107570	0	0
T5	909689	909614	0	0
T6	976342	976333	0	0
T7	264469	264389	0	0
T8	34767	34680	0	0
T9	5429	5294	0	0
T10	27701	27610	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	921	921	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546387782	2574416	0	0
T2	563524	6702	0	0
T3	268026	832	0	0
T4	107577	4160	0	0
T5	909689	2880	0	0
T6	976342	19601	0	0
T7	264469	832	0	0
T8	34767	1344	0	0
T9	5429	0	0	0
T10	27701	832	0	0
T11	116306	832	0	0
T12	0	23717	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546387782	2574416	0	0
T2	563524	6702	0	0
T3	268026	832	0	0
T4	107577	4160	0	0
T5	909689	2880	0	0
T6	976342	19601	0	0
T7	264469	832	0	0
T8	34767	1344	0	0
T9	5429	0	0	0
T10	27701	832	0	0
T11	116306	832	0	0
T12	0	23717	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546387782	546302971	0	0
T1	1396	1310	0	0
T2	563524	563318	0	0
T3	268026	267954	0	0
T4	107577	107570	0	0
T5	909689	909614	0	0
T6	976342	976333	0	0
T7	264469	264389	0	0
T8	34767	34680	0	0
T9	5429	5294	0	0
T10	27701	27610	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546387782	546302971	0	0
T1	1396	1310	0	0
T2	563524	563318	0	0
T3	268026	267954	0	0
T4	107577	107570	0	0
T5	909689	909614	0	0
T6	976342	976333	0	0
T7	264469	264389	0	0
T8	34767	34680	0	0
T9	5429	5294	0	0
T10	27701	27610	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546387782	2574416	0	0
T2	563524	6702	0	0
T3	268026	832	0	0
T4	107577	4160	0	0
T5	909689	2880	0	0
T6	976342	19601	0	0
T7	264469	832	0	0
T8	34767	1344	0	0
T9	5429	0	0	0
T10	27701	832	0	0
T11	116306	832	0	0
T12	0	23717	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546387782	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546387782	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546387782	2574416	0	0
T2	563524	6702	0	0
T3	268026	832	0	0
T4	107577	4160	0	0
T5	909689	2880	0	0
T6	976342	19601	0	0
T7	264469	832	0	0
T8	34767	1344	0	0
T9	5429	0	0	0
T10	27701	832	0	0
T11	116306	832	0	0
T12	0	23717	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546387782	2574416	0	0
T2	563524	6702	0	0
T3	268026	832	0	0
T4	107577	4160	0	0
T5	909689	2880	0	0
T6	976342	19601	0	0
T7	264469	832	0	0
T8	34767	1344	0	0
T9	5429	0	0	0
T10	27701	832	0	0
T11	116306	832	0	0
T12	0	23717	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546387782	2574416	0	0
T2	563524	6702	0	0
T3	268026	832	0	0
T4	107577	4160	0	0
T5	909689	2880	0	0
T6	976342	19601	0	0
T7	264469	832	0	0
T8	34767	1344	0	0
T9	5429	0	0	0
T10	27701	832	0	0
T11	116306	832	0	0
T12	0	23717	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	546387782	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546387782	6	0	921
T18	302003	1	0	1
T27	928068	0	0	1
T31	0	1	0	0
T34	588168	0	0	1
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	11002	0	0	1
T40	9369	0	0	1
T41	77814	0	0	1
T42	902	0	0	1
T43	919916	0	0	1
T44	396401	0	0	1
T45	16234	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546387782	546302971	0	0
T1	1396	1310	0	0
T2	563524	563318	0	0
T3	268026	267954	0	0
T4	107577	107570	0	0
T5	909689	909614	0	0
T6	976342	976333	0	0
T7	264469	264389	0	0
T8	34767	34680	0	0
T9	5429	5294	0	0
T10	27701	27610	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546387782	2574416	0	0
T2	563524	6702	0	0
T3	268026	832	0	0
T4	107577	4160	0	0
T5	909689	2880	0	0
T6	976342	19601	0	0
T7	264469	832	0	0
T8	34767	1344	0	0
T9	5429	0	0	0
T10	27701	832	0	0
T11	116306	832	0	0
T12	0	23717	0	0