Unified Coverage Report :: Module :: spi_device_csr_assert_fpv

Module : spi_device_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_spi_device_csr_assert_0/spi_device_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.spi_device_csr_assert	100.00						100.00

---

Module Instance : tb.dut.spi_device_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.69	94.25	84.31	96.94		87.50	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : spi_device_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	58	58	100.00	58	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	58	58	100.00	58	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	548850392	3313	0	0
addr_swap_data_rd_A	548850392	1274	0	0
addr_swap_mask_rd_A	548850392	1344	0	0
cfg_rd_A	548850392	1684	0	0
cmd_filter_0_rd_A	548850392	8307	0	0
cmd_filter_1_rd_A	548850392	8070	0	0
cmd_filter_2_rd_A	548850392	8315	0	0
cmd_filter_3_rd_A	548850392	6841	0	0
cmd_filter_4_rd_A	548850392	7757	0	0
cmd_filter_5_rd_A	548850392	8395	0	0
cmd_filter_6_rd_A	548850392	7536	0	0
cmd_filter_7_rd_A	548850392	7857	0	0
cmd_info_0_rd_A	548850392	3984	0	0
cmd_info_10_rd_A	548850392	3733	0	0
cmd_info_11_rd_A	548850392	3956	0	0
cmd_info_12_rd_A	548850392	3689	0	0
cmd_info_13_rd_A	548850392	4163	0	0
cmd_info_14_rd_A	548850392	3962	0	0
cmd_info_15_rd_A	548850392	3446	0	0
cmd_info_16_rd_A	548850392	3454	0	0
cmd_info_17_rd_A	548850392	3914	0	0
cmd_info_18_rd_A	548850392	4042	0	0
cmd_info_19_rd_A	548850392	3734	0	0
cmd_info_1_rd_A	548850392	3792	0	0
cmd_info_20_rd_A	548850392	3845	0	0
cmd_info_21_rd_A	548850392	3931	0	0
cmd_info_22_rd_A	548850392	3597	0	0
cmd_info_23_rd_A	548850392	3923	0	0
cmd_info_2_rd_A	548850392	4137	0	0
cmd_info_3_rd_A	548850392	3418	0	0
cmd_info_4_rd_A	548850392	3497	0	0
cmd_info_5_rd_A	548850392	3640	0	0
cmd_info_6_rd_A	548850392	4083	0	0
cmd_info_7_rd_A	548850392	3829	0	0
cmd_info_8_rd_A	548850392	3510	0	0
cmd_info_9_rd_A	548850392	3499	0	0
cmd_info_en4b_rd_A	548850392	1648	0	0
cmd_info_ex4b_rd_A	548850392	1593	0	0
cmd_info_wrdi_rd_A	548850392	1499	0	0
cmd_info_wren_rd_A	548850392	1412	0	0
intercept_en_rd_A	548850392	2219	0	0
intr_enable_rd_A	548850392	3556	0	0
jedec_cc_rd_A	548850392	1530	0	0
jedec_id_rd_A	548850392	1434	0	0
mailbox_addr_rd_A	548850392	1317	0	0
payload_swap_data_rd_A	548850392	1308	0	0
payload_swap_mask_rd_A	548850392	1158	0	0
read_threshold_rd_A	548850392	1187	0	0
tpm_access_0_rd_A	548850392	2140	0	0
tpm_access_1_rd_A	548850392	1388	0	0
tpm_cfg_rd_A	548850392	2071	0	0
tpm_did_vid_rd_A	548850392	1486	0	0
tpm_int_enable_rd_A	548850392	1319	0	0
tpm_int_status_rd_A	548850392	1202	0	0
tpm_int_vector_rd_A	548850392	1370	0	0
tpm_intf_capability_rd_A	548850392	1327	0	0
tpm_rid_rd_A	548850392	1227	0	0
tpm_sts_rd_A	548850392	1351	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548850392	3313	0	0
T48	15581	4	0	0
T49	19213	5	0	0
T50	14589	3	0	0
T79	2700	7	0	0
T80	53627	2	0	0
T81	4897	1	0	0
T82	14283	145	0	0
T84	8196	4	0	0
T96	4028	1	0	0
T97	11117	4	0	0

addr_swap_data_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548850392	1274	0	0
T48	15581	30	0	0
T50	14589	24	0	0
T70	3559	5	0	0
T83	31480	15	0	0
T97	11117	12	0	0
T105	157249	299	0	0
T122	19413	21	0	0
T123	6103	13	0	0
T124	31917	14	0	0
T125	36758	39	0	0

addr_swap_mask_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548850392	1344	0	0
T48	15581	19	0	0
T50	14589	21	0	0
T70	3559	8	0	0
T83	31480	13	0	0
T97	11117	17	0	0
T105	157249	321	0	0
T122	19413	30	0	0
T123	6103	2	0	0
T124	31917	21	0	0
T125	36758	27	0	0

cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548850392	1684	0	0
T48	15581	28	0	0
T50	14589	23	0	0
T70	3559	6	0	0
T83	31480	50	0	0
T97	11117	28	0	0
T105	157249	297	0	0
T122	19413	47	0	0
T123	6103	25	0	0
T124	31917	48	0	0
T125	36758	60	0	0

cmd_filter_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548850392	8307	0	0
T48	15581	235	0	0
T50	14589	15	0	0
T70	3559	9	0	0
T83	31480	456	0	0
T97	11117	130	0	0
T105	157249	292	0	0
T122	19413	33	0	0
T123	6103	244	0	0
T124	31917	390	0	0
T125	36758	507	0	0

cmd_filter_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548850392	8070	0	0
T48	15581	117	0	0
T50	14589	250	0	0
T70	3559	12	0	0
T83	31480	235	0	0
T97	11117	9	0	0
T105	157249	287	0	0
T122	19413	39	0	0
T123	6103	6	0	0
T124	31917	425	0	0
T125	36758	563	0	0

cmd_filter_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548850392	8315	0	0
T48	15581	263	0	0
T50	14589	139	0	0
T70	3559	1	0	0
T83	31480	203	0	0
T97	11117	20	0	0
T105	157249	316	0	0
T122	19413	55	0	0
T123	6103	10	0	0
T124	31917	308	0	0
T125	36758	850	0	0

cmd_filter_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548850392	6841	0	0
T48	15581	264	0	0
T50	14589	373	0	0
T70	3559	6	0	0
T83	31480	351	0	0
T97	11117	226	0	0
T105	157249	285	0	0
T122	19413	40	0	0
T123	6103	12	0	0
T124	31917	307	0	0
T125	36758	378	0	0

cmd_filter_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548850392	7757	0	0
T48	15581	264	0	0
T50	14589	215	0	0
T70	3559	3	0	0
T83	31480	375	0	0
T97	11117	142	0	0
T105	157249	311	0	0
T122	19413	60	0	0
T123	6103	140	0	0
T124	31917	384	0	0
T125	36758	662	0	0

cmd_filter_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548850392	8395	0	0
T48	15581	258	0	0
T50	14589	245	0	0
T70	3559	14	0	0
T83	31480	310	0	0
T97	11117	128	0	0
T105	157249	270	0	0
T122	19413	13	0	0
T123	6103	176	0	0
T124	31917	420	0	0
T125	36758	599	0	0

cmd_filter_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548850392	7536	0	0
T48	15581	118	0	0
T50	14589	289	0	0
T70	3559	9	0	0
T83	31480	314	0	0
T97	11117	160	0	0
T105	157249	253	0	0
T122	19413	12	0	0
T123	6103	5	0	0
T124	31917	307	0	0
T125	36758	659	0	0

cmd_filter_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548850392	7857	0	0
T48	15581	217	0	0
T50	14589	274	0	0
T70	3559	17	0	0
T83	31480	346	0	0
T97	11117	167	0	0
T105	157249	229	0	0
T122	19413	53	0	0
T123	6103	6	0	0
T124	31917	280	0	0
T125	36758	746	0	0

cmd_info_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548850392	3984	0	0
T48	15581	13	0	0
T50	14589	52	0	0
T70	3559	9	0	0
T83	31480	123	0	0
T97	11117	109	0	0
T105	157249	347	0	0
T122	19413	46	0	0
T123	6103	40	0	0
T124	31917	236	0	0
T125	36758	272	0	0

cmd_info_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548850392	3733	0	0
T48	15581	127	0	0
T50	14589	101	0	0
T70	3559	4	0	0
T83	31480	102	0	0
T97	11117	13	0	0
T105	157249	240	0	0
T122	19413	42	0	0
T123	6103	8	0	0
T124	31917	126	0	0
T125	36758	186	0	0

cmd_info_11_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548850392	3956	0	0
T48	15581	85	0	0
T50	14589	159	0	0
T70	3559	6	0	0
T83	31480	264	0	0
T97	11117	88	0	0
T105	157249	265	0	0
T122	19413	61	0	0
T123	6103	102	0	0
T124	31917	166	0	0
T125	36758	225	0	0

cmd_info_12_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548850392	3689	0	0
T48	15581	108	0	0
T50	14589	125	0	0
T70	3559	1	0	0
T83	31480	102	0	0
T97	11117	92	0	0
T105	157249	318	0	0
T122	19413	28	0	0
T123	6103	68	0	0
T124	31917	137	0	0
T125	36758	281	0	0

cmd_info_13_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548850392	4163	0	0
T48	15581	111	0	0
T50	14589	78	0	0
T70	3559	4	0	0
T83	31480	202	0	0
T97	11117	124	0	0
T105	157249	275	0	0
T122	19413	17	0	0
T123	6103	81	0	0
T124	31917	203	0	0
T125	36758	278	0	0

cmd_info_14_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548850392	3962	0	0
T48	15581	19	0	0
T50	14589	58	0	0
T70	3559	6	0	0
T83	31480	165	0	0
T87	15164	5	0	0
T97	11117	118	0	0
T105	157249	287	0	0
T122	19413	23	0	0
T123	6103	59	0	0
T124	31917	82	0	0

cmd_info_15_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548850392	3446	0	0
T48	15581	19	0	0
T50	14589	49	0	0
T70	3559	8	0	0
T83	31480	142	0	0
T97	11117	37	0	0
T105	157249	340	0	0
T122	19413	26	0	0
T123	6103	53	0	0
T124	31917	201	0	0
T125	36758	255	0	0

cmd_info_16_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548850392	3454	0	0
T48	15581	138	0	0
T50	14589	28	0	0
T70	3559	8	0	0
T83	31480	138	0	0
T97	11117	60	0	0
T105	157249	277	0	0
T122	19413	39	0	0
T123	6103	74	0	0
T124	31917	147	0	0
T125	36758	252	0	0

cmd_info_17_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548850392	3914	0	0
T48	15581	14	0	0
T50	14589	17	0	0
T70	3559	6	0	0
T83	31480	194	0	0
T97	11117	38	0	0
T105	157249	255	0	0
T122	19413	56	0	0
T123	6103	6	0	0
T124	31917	75	0	0
T125	36758	384	0	0

cmd_info_18_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548850392	4042	0	0
T48	15581	69	0	0
T50	14589	148	0	0
T70	3559	7	0	0
T83	31480	195	0	0
T97	11117	62	0	0
T105	157249	257	0	0
T122	19413	13	0	0
T123	6103	56	0	0
T124	31917	176	0	0
T125	36758	383	0	0

cmd_info_19_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548850392	3734	0	0
T48	15581	113	0	0
T50	14589	75	0	0
T70	3559	2	0	0
T83	31480	158	0	0
T97	11117	22	0	0
T105	157249	316	0	0
T122	19413	69	0	0
T123	6103	15	0	0
T124	31917	71	0	0
T125	36758	241	0	0

cmd_info_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548850392	3792	0	0
T48	15581	137	0	0
T50	14589	34	0	0
T70	3559	3	0	0
T83	31480	143	0	0
T97	11117	39	0	0
T105	157249	301	0	0
T122	19413	26	0	0
T123	6103	58	0	0
T124	31917	137	0	0
T125	36758	321	0	0

cmd_info_20_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548850392	3845	0	0
T48	15581	18	0	0
T50	14589	80	0	0
T70	3559	9	0	0
T83	31480	148	0	0
T97	11117	12	0	0
T105	157249	233	0	0
T122	19413	46	0	0
T123	6103	9	0	0
T124	31917	207	0	0
T125	36758	482	0	0

cmd_info_21_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548850392	3931	0	0
T48	15581	91	0	0
T50	14589	47	0	0
T71	2162	6	0	0
T83	31480	216	0	0
T97	11117	54	0	0
T105	157249	264	0	0
T122	19413	17	0	0
T123	6103	51	0	0
T124	31917	160	0	0
T125	36758	398	0	0

cmd_info_22_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548850392	3597	0	0
T48	15581	88	0	0
T50	14589	143	0	0
T70	3559	3	0	0
T83	31480	123	0	0
T97	11117	124	0	0
T105	157249	235	0	0
T122	19413	39	0	0
T123	6103	66	0	0
T124	31917	123	0	0
T125	36758	251	0	0

cmd_info_23_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548850392	3923	0	0
T48	15581	78	0	0
T50	14589	104	0	0
T70	3559	8	0	0
T83	31480	141	0	0
T97	11117	77	0	0
T105	157249	313	0	0
T122	19413	38	0	0
T123	6103	46	0	0
T124	31917	193	0	0
T125	36758	281	0	0

cmd_info_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548850392	4137	0	0
T48	15581	68	0	0
T50	14589	98	0	0
T70	3559	8	0	0
T83	31480	234	0	0
T97	11117	113	0	0
T105	157249	293	0	0
T122	19413	47	0	0
T123	6103	58	0	0
T124	31917	168	0	0
T125	36758	351	0	0

cmd_info_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548850392	3418	0	0
T48	15581	146	0	0
T50	14589	57	0	0
T70	3559	2	0	0
T83	31480	125	0	0
T97	11117	66	0	0
T105	157249	219	0	0
T122	19413	35	0	0
T123	6103	74	0	0
T124	31917	190	0	0
T125	36758	374	0	0

cmd_info_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548850392	3497	0	0
T48	15581	103	0	0
T50	14589	87	0	0
T70	3559	5	0	0
T83	31480	118	0	0
T97	11117	40	0	0
T105	157249	262	0	0
T122	19413	48	0	0
T123	6103	43	0	0
T124	31917	150	0	0
T125	36758	171	0	0

cmd_info_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548850392	3640	0	0
T48	15581	164	0	0
T50	14589	116	0	0
T70	3559	10	0	0
T83	31480	151	0	0
T87	15164	1	0	0
T97	11117	56	0	0
T105	157249	281	0	0
T122	19413	42	0	0
T123	6103	67	0	0
T124	31917	106	0	0

cmd_info_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548850392	4083	0	0
T48	15581	110	0	0
T50	14589	139	0	0
T70	3559	10	0	0
T83	31480	156	0	0
T97	11117	20	0	0
T105	157249	310	0	0
T122	19413	53	0	0
T123	6103	46	0	0
T124	31917	125	0	0
T125	36758	348	0	0

cmd_info_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548850392	3829	0	0
T48	15581	21	0	0
T50	14589	112	0	0
T70	3559	12	0	0
T83	31480	128	0	0
T97	11117	48	0	0
T105	157249	251	0	0
T122	19413	76	0	0
T123	6103	59	0	0
T124	31917	175	0	0
T125	36758	183	0	0

cmd_info_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548850392	3510	0	0
T48	15581	62	0	0
T50	14589	26	0	0
T70	3559	7	0	0
T83	31480	64	0	0
T97	11117	19	0	0
T105	157249	269	0	0
T122	19413	71	0	0
T123	6103	14	0	0
T124	31917	173	0	0
T125	36758	258	0	0

cmd_info_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548850392	3499	0	0
T48	15581	29	0	0
T50	14589	33	0	0
T70	3559	8	0	0
T83	31480	116	0	0
T97	11117	100	0	0
T105	157249	268	0	0
T122	19413	71	0	0
T123	6103	78	0	0
T124	31917	178	0	0
T125	36758	242	0	0

cmd_info_en4b_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548850392	1648	0	0
T48	15581	29	0	0
T50	14589	21	0	0
T70	3559	2	0	0
T82	14283	4	0	0
T83	31480	12	0	0
T97	11117	20	0	0
T105	157249	280	0	0
T122	19413	70	0	0
T123	6103	27	0	0
T124	31917	14	0	0

cmd_info_ex4b_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548850392	1593	0	0
T48	15581	18	0	0
T50	14589	31	0	0
T70	3559	12	0	0
T83	31480	20	0	0
T97	11117	14	0	0
T105	157249	288	0	0
T122	19413	14	0	0
T123	6103	6	0	0
T124	31917	31	0	0
T125	36758	69	0	0

cmd_info_wrdi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548850392	1499	0	0
T48	15581	27	0	0
T50	14589	21	0	0
T70	3559	2	0	0
T83	31480	46	0	0
T97	11117	11	0	0
T105	157249	249	0	0
T122	19413	18	0	0
T123	6103	15	0	0
T124	31917	33	0	0
T125	36758	42	0	0

cmd_info_wren_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548850392	1412	0	0
T48	15581	36	0	0
T50	14589	36	0	0
T70	3559	5	0	0
T83	31480	31	0	0
T97	11117	12	0	0
T105	157249	233	0	0
T122	19413	21	0	0
T123	6103	12	0	0
T124	31917	15	0	0
T125	36758	60	0	0

intercept_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548850392	2219	0	0
T48	15581	64	0	0
T50	14589	45	0	0
T70	3559	3	0	0
T83	31480	46	0	0
T97	11117	45	0	0
T105	157249	247	0	0
T122	19413	52	0	0
T123	6103	19	0	0
T124	31917	95	0	0
T125	36758	158	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548850392	3556	0	0
T2	563524	35	0	0
T3	268026	0	0	0
T4	107577	0	0	0
T5	909689	0	0	0
T6	976342	0	0	0
T7	264469	0	0	0
T8	34767	0	0	0
T9	5429	0	0	0
T10	27701	0	0	0
T11	116306	0	0	0
T28	0	21	0	0
T66	0	25	0	0
T114	0	43	0	0
T126	0	39	0	0
T127	0	17	0	0
T128	0	50	0	0
T129	0	21	0	0
T130	0	49	0	0
T131	0	53	0	0

jedec_cc_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548850392	1530	0	0
T48	15581	22	0	0
T50	14589	43	0	0
T70	3559	12	0	0
T83	31480	47	0	0
T97	11117	17	0	0
T105	157249	275	0	0
T122	19413	14	0	0
T123	6103	16	0	0
T124	31917	25	0	0
T125	36758	66	0	0

jedec_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548850392	1434	0	0
T48	15581	23	0	0
T50	14589	42	0	0
T70	3559	7	0	0
T83	31480	25	0	0
T97	11117	13	0	0
T105	157249	199	0	0
T122	19413	17	0	0
T123	6103	12	0	0
T124	31917	26	0	0
T125	36758	28	0	0

mailbox_addr_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548850392	1317	0	0
T48	15581	19	0	0
T50	14589	17	0	0
T70	3559	13	0	0
T83	31480	4	0	0
T97	11117	28	0	0
T105	157249	256	0	0
T122	19413	67	0	0
T123	6103	9	0	0
T124	31917	18	0	0
T125	36758	46	0	0

payload_swap_data_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548850392	1308	0	0
T48	15581	13	0	0
T50	14589	19	0	0
T70	3559	11	0	0
T83	31480	26	0	0
T97	11117	19	0	0
T105	157249	247	0	0
T122	19413	45	0	0
T123	6103	7	0	0
T124	31917	23	0	0
T125	36758	38	0	0

payload_swap_mask_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548850392	1158	0	0
T48	15581	9	0	0
T50	14589	21	0	0
T70	3559	6	0	0
T83	31480	24	0	0
T97	11117	20	0	0
T105	157249	213	0	0
T122	19413	53	0	0
T123	6103	5	0	0
T124	31917	11	0	0
T125	36758	20	0	0

read_threshold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548850392	1187	0	0
T48	15581	19	0	0
T50	14589	27	0	0
T70	3559	8	0	0
T83	31480	20	0	0
T97	11117	15	0	0
T105	157249	219	0	0
T122	19413	37	0	0
T123	6103	11	0	0
T124	31917	15	0	0
T125	36758	32	0	0

tpm_access_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548850392	2140	0	0
T48	15581	53	0	0
T50	14589	36	0	0
T70	3559	11	0	0
T83	31480	130	0	0
T97	11117	17	0	0
T105	157249	253	0	0
T122	19413	29	0	0
T123	6103	42	0	0
T124	31917	32	0	0
T125	36758	80	0	0

tpm_access_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548850392	1388	0	0
T48	15581	25	0	0
T50	14589	14	0	0
T70	3559	8	0	0
T83	31480	6	0	0
T97	11117	16	0	0
T105	157249	284	0	0
T122	19413	82	0	0
T123	6103	8	0	0
T124	31917	26	0	0
T125	36758	40	0	0

tpm_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548850392	2071	0	0
T48	15581	69	0	0
T50	14589	17	0	0
T70	3559	6	0	0
T83	31480	33	0	0
T97	11117	53	0	0
T105	157249	293	0	0
T122	19413	65	0	0
T123	6103	9	0	0
T124	31917	38	0	0
T125	36758	90	0	0

tpm_did_vid_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548850392	1486	0	0
T48	15581	27	0	0
T50	14589	28	0	0
T70	3559	10	0	0
T83	31480	21	0	0
T97	11117	18	0	0
T105	157249	294	0	0
T122	19413	54	0	0
T123	6103	19	0	0
T124	31917	21	0	0
T125	36758	39	0	0

tpm_int_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548850392	1319	0	0
T48	15581	12	0	0
T50	14589	27	0	0
T70	3559	10	0	0
T83	31480	14	0	0
T97	11117	14	0	0
T105	157249	296	0	0
T122	19413	42	0	0
T123	6103	13	0	0
T124	31917	24	0	0
T125	36758	37	0	0

tpm_int_status_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548850392	1202	0	0
T48	15581	11	0	0
T50	14589	23	0	0
T70	3559	8	0	0
T83	31480	25	0	0
T97	11117	19	0	0
T105	157249	275	0	0
T122	19413	24	0	0
T123	6103	12	0	0
T124	31917	33	0	0
T125	36758	34	0	0

tpm_int_vector_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548850392	1370	0	0
T48	15581	24	0	0
T50	14589	12	0	0
T70	3559	15	0	0
T83	31480	31	0	0
T97	11117	8	0	0
T105	157249	227	0	0
T122	19413	33	0	0
T123	6103	11	0	0
T124	31917	46	0	0
T125	36758	29	0	0

tpm_intf_capability_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548850392	1327	0	0
T48	15581	14	0	0
T50	14589	28	0	0
T70	3559	9	0	0
T83	31480	23	0	0
T97	11117	11	0	0
T105	157249	248	0	0
T122	19413	16	0	0
T123	6103	5	0	0
T124	31917	19	0	0
T125	36758	34	0	0

tpm_rid_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548850392	1227	0	0
T48	15581	15	0	0
T50	14589	24	0	0
T70	3559	7	0	0
T83	31480	16	0	0
T87	15164	2	0	0
T97	11117	7	0	0
T105	157249	311	0	0
T122	19413	27	0	0
T123	6103	9	0	0
T124	31917	9	0	0

tpm_sts_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548850392	1351	0	0
T48	15581	25	0	0
T50	14589	21	0	0
T70	3559	7	0	0
T83	31480	4	0	0
T97	11117	18	0	0
T105	157249	254	0	0
T122	19413	61	0	0
T123	6103	8	0	0
T124	31917	7	0	0
T125	36758	29	0	0