| T809 |
/workspace/coverage/default/46.spi_device_intercept.682804309 |
|
|
Mar 28 03:24:44 PM PDT 24 |
Mar 28 03:24:48 PM PDT 24 |
478301058 ps |
| T810 |
/workspace/coverage/default/19.spi_device_mailbox.3846466281 |
|
|
Mar 28 03:22:32 PM PDT 24 |
Mar 28 03:23:20 PM PDT 24 |
99388043390 ps |
| T811 |
/workspace/coverage/default/19.spi_device_cfg_cmd.327852865 |
|
|
Mar 28 03:22:32 PM PDT 24 |
Mar 28 03:22:35 PM PDT 24 |
468536562 ps |
| T812 |
/workspace/coverage/default/38.spi_device_flash_all.1502404066 |
|
|
Mar 28 03:24:09 PM PDT 24 |
Mar 28 03:25:00 PM PDT 24 |
58088598370 ps |
| T813 |
/workspace/coverage/default/44.spi_device_tpm_rw.2363086067 |
|
|
Mar 28 03:24:31 PM PDT 24 |
Mar 28 03:24:32 PM PDT 24 |
76898519 ps |
| T814 |
/workspace/coverage/default/20.spi_device_tpm_read_hw_reg.121946416 |
|
|
Mar 28 03:22:37 PM PDT 24 |
Mar 28 03:22:43 PM PDT 24 |
6369178476 ps |
| T815 |
/workspace/coverage/default/8.spi_device_intercept.2244900362 |
|
|
Mar 28 03:21:50 PM PDT 24 |
Mar 28 03:21:53 PM PDT 24 |
201336106 ps |
| T816 |
/workspace/coverage/default/37.spi_device_flash_all.1048803737 |
|
|
Mar 28 03:23:51 PM PDT 24 |
Mar 28 03:23:57 PM PDT 24 |
228484998 ps |
| T817 |
/workspace/coverage/default/6.spi_device_tpm_sts_read.2837568803 |
|
|
Mar 28 03:21:44 PM PDT 24 |
Mar 28 03:21:46 PM PDT 24 |
354191341 ps |
| T818 |
/workspace/coverage/default/35.spi_device_pass_addr_payload_swap.3965015279 |
|
|
Mar 28 03:23:50 PM PDT 24 |
Mar 28 03:23:57 PM PDT 24 |
5243213373 ps |
| T819 |
/workspace/coverage/default/9.spi_device_alert_test.3738304049 |
|
|
Mar 28 03:21:53 PM PDT 24 |
Mar 28 03:21:54 PM PDT 24 |
14590262 ps |
| T820 |
/workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.2550854226 |
|
|
Mar 28 03:21:24 PM PDT 24 |
Mar 28 03:22:43 PM PDT 24 |
4210694086 ps |
| T821 |
/workspace/coverage/default/40.spi_device_flash_mode.3289335982 |
|
|
Mar 28 03:24:02 PM PDT 24 |
Mar 28 03:24:19 PM PDT 24 |
398525171 ps |
| T822 |
/workspace/coverage/default/10.spi_device_tpm_read_hw_reg.943748412 |
|
|
Mar 28 03:21:46 PM PDT 24 |
Mar 28 03:21:58 PM PDT 24 |
6457217435 ps |
| T823 |
/workspace/coverage/default/14.spi_device_flash_and_tpm.2172778952 |
|
|
Mar 28 03:22:28 PM PDT 24 |
Mar 28 03:22:50 PM PDT 24 |
10470124692 ps |
| T824 |
/workspace/coverage/default/19.spi_device_tpm_all.2445863273 |
|
|
Mar 28 03:22:31 PM PDT 24 |
Mar 28 03:22:58 PM PDT 24 |
1873395578 ps |
| T255 |
/workspace/coverage/default/27.spi_device_flash_all.3766424607 |
|
|
Mar 28 03:23:18 PM PDT 24 |
Mar 28 03:26:14 PM PDT 24 |
126706803010 ps |
| T825 |
/workspace/coverage/default/26.spi_device_pass_cmd_filtering.496262115 |
|
|
Mar 28 03:23:11 PM PDT 24 |
Mar 28 03:23:24 PM PDT 24 |
3559623233 ps |
| T826 |
/workspace/coverage/default/34.spi_device_read_buffer_direct.3838299141 |
|
|
Mar 28 03:23:45 PM PDT 24 |
Mar 28 03:23:50 PM PDT 24 |
8964601401 ps |
| T827 |
/workspace/coverage/default/26.spi_device_stress_all.3357339740 |
|
|
Mar 28 03:23:18 PM PDT 24 |
Mar 28 03:24:34 PM PDT 24 |
14389694646 ps |
| T828 |
/workspace/coverage/default/43.spi_device_pass_addr_payload_swap.3773573834 |
|
|
Mar 28 03:24:29 PM PDT 24 |
Mar 28 03:25:12 PM PDT 24 |
57360604818 ps |
| T829 |
/workspace/coverage/default/21.spi_device_read_buffer_direct.23055162 |
|
|
Mar 28 03:22:51 PM PDT 24 |
Mar 28 03:22:57 PM PDT 24 |
5737382976 ps |
| T830 |
/workspace/coverage/default/9.spi_device_upload.733146404 |
|
|
Mar 28 03:21:44 PM PDT 24 |
Mar 28 03:21:58 PM PDT 24 |
2503011883 ps |
| T831 |
/workspace/coverage/default/2.spi_device_alert_test.720801278 |
|
|
Mar 28 03:21:24 PM PDT 24 |
Mar 28 03:21:25 PM PDT 24 |
13489422 ps |
| T832 |
/workspace/coverage/default/43.spi_device_tpm_read_hw_reg.452319778 |
|
|
Mar 28 03:24:34 PM PDT 24 |
Mar 28 03:24:47 PM PDT 24 |
18848541832 ps |
| T833 |
/workspace/coverage/default/25.spi_device_stress_all.3632445617 |
|
|
Mar 28 03:23:09 PM PDT 24 |
Mar 28 03:37:47 PM PDT 24 |
250388897974 ps |
| T834 |
/workspace/coverage/default/1.spi_device_ram_cfg.1211991827 |
|
|
Mar 28 03:21:08 PM PDT 24 |
Mar 28 03:21:09 PM PDT 24 |
29336942 ps |
| T835 |
/workspace/coverage/default/40.spi_device_csb_read.3099790133 |
|
|
Mar 28 03:24:06 PM PDT 24 |
Mar 28 03:24:07 PM PDT 24 |
18670540 ps |
| T836 |
/workspace/coverage/default/31.spi_device_intercept.1437793183 |
|
|
Mar 28 03:23:28 PM PDT 24 |
Mar 28 03:23:41 PM PDT 24 |
13657499109 ps |
| T251 |
/workspace/coverage/default/41.spi_device_flash_and_tpm.1849810626 |
|
|
Mar 28 03:24:28 PM PDT 24 |
Mar 28 03:26:10 PM PDT 24 |
43679641178 ps |
| T837 |
/workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.98539123 |
|
|
Mar 28 03:21:53 PM PDT 24 |
Mar 28 03:23:41 PM PDT 24 |
16847255455 ps |
| T838 |
/workspace/coverage/default/18.spi_device_mailbox.3784322412 |
|
|
Mar 28 03:22:29 PM PDT 24 |
Mar 28 03:22:44 PM PDT 24 |
5562243766 ps |
| T839 |
/workspace/coverage/default/49.spi_device_tpm_sts_read.1895278786 |
|
|
Mar 28 03:24:49 PM PDT 24 |
Mar 28 03:24:50 PM PDT 24 |
163823286 ps |
| T840 |
/workspace/coverage/default/27.spi_device_tpm_all.1255138758 |
|
|
Mar 28 03:23:17 PM PDT 24 |
Mar 28 03:23:32 PM PDT 24 |
4133170723 ps |
| T841 |
/workspace/coverage/default/19.spi_device_tpm_read_hw_reg.2890460388 |
|
|
Mar 28 03:22:34 PM PDT 24 |
Mar 28 03:22:41 PM PDT 24 |
1736688365 ps |
| T842 |
/workspace/coverage/default/40.spi_device_pass_addr_payload_swap.197319314 |
|
|
Mar 28 03:24:02 PM PDT 24 |
Mar 28 03:24:37 PM PDT 24 |
61240749137 ps |
| T843 |
/workspace/coverage/default/36.spi_device_alert_test.459190851 |
|
|
Mar 28 03:23:51 PM PDT 24 |
Mar 28 03:23:53 PM PDT 24 |
16342420 ps |
| T844 |
/workspace/coverage/default/9.spi_device_csb_read.2828752846 |
|
|
Mar 28 03:21:42 PM PDT 24 |
Mar 28 03:21:43 PM PDT 24 |
16175675 ps |
| T845 |
/workspace/coverage/default/17.spi_device_pass_cmd_filtering.1983455865 |
|
|
Mar 28 03:22:28 PM PDT 24 |
Mar 28 03:22:43 PM PDT 24 |
10676030124 ps |
| T846 |
/workspace/coverage/default/19.spi_device_tpm_rw.2990587997 |
|
|
Mar 28 03:22:31 PM PDT 24 |
Mar 28 03:22:33 PM PDT 24 |
75274639 ps |
| T847 |
/workspace/coverage/default/37.spi_device_tpm_read_hw_reg.2353830789 |
|
|
Mar 28 03:23:51 PM PDT 24 |
Mar 28 03:24:18 PM PDT 24 |
8861836191 ps |
| T848 |
/workspace/coverage/default/26.spi_device_flash_mode.3668544993 |
|
|
Mar 28 03:23:10 PM PDT 24 |
Mar 28 03:23:24 PM PDT 24 |
8118948161 ps |
| T849 |
/workspace/coverage/default/10.spi_device_upload.2190570704 |
|
|
Mar 28 03:22:11 PM PDT 24 |
Mar 28 03:22:47 PM PDT 24 |
10296793248 ps |
| T850 |
/workspace/coverage/default/35.spi_device_csb_read.2450240076 |
|
|
Mar 28 03:23:47 PM PDT 24 |
Mar 28 03:23:48 PM PDT 24 |
46449894 ps |
| T851 |
/workspace/coverage/default/6.spi_device_tpm_all.730395120 |
|
|
Mar 28 03:21:40 PM PDT 24 |
Mar 28 03:22:18 PM PDT 24 |
4910734806 ps |
| T38 |
/workspace/coverage/default/16.spi_device_stress_all.571018667 |
|
|
Mar 28 03:22:33 PM PDT 24 |
Mar 28 03:31:10 PM PDT 24 |
99297689035 ps |
| T852 |
/workspace/coverage/default/11.spi_device_read_buffer_direct.370076744 |
|
|
Mar 28 03:22:05 PM PDT 24 |
Mar 28 03:22:12 PM PDT 24 |
2066669182 ps |
| T853 |
/workspace/coverage/default/12.spi_device_upload.2658590319 |
|
|
Mar 28 03:22:09 PM PDT 24 |
Mar 28 03:22:22 PM PDT 24 |
4707990312 ps |
| T243 |
/workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.3043731199 |
|
|
Mar 28 03:22:33 PM PDT 24 |
Mar 28 03:28:23 PM PDT 24 |
81345187892 ps |
| T854 |
/workspace/coverage/default/7.spi_device_alert_test.1985530576 |
|
|
Mar 28 03:21:47 PM PDT 24 |
Mar 28 03:21:49 PM PDT 24 |
14389368 ps |
| T855 |
/workspace/coverage/default/10.spi_device_alert_test.715134082 |
|
|
Mar 28 03:22:04 PM PDT 24 |
Mar 28 03:22:05 PM PDT 24 |
10996244 ps |
| T856 |
/workspace/coverage/default/18.spi_device_tpm_rw.4268194656 |
|
|
Mar 28 03:22:29 PM PDT 24 |
Mar 28 03:22:32 PM PDT 24 |
526457047 ps |
| T857 |
/workspace/coverage/default/10.spi_device_tpm_sts_read.1345838172 |
|
|
Mar 28 03:21:45 PM PDT 24 |
Mar 28 03:21:48 PM PDT 24 |
25029060 ps |
| T858 |
/workspace/coverage/default/25.spi_device_alert_test.4293439230 |
|
|
Mar 28 03:23:12 PM PDT 24 |
Mar 28 03:23:13 PM PDT 24 |
73254666 ps |
| T859 |
/workspace/coverage/default/35.spi_device_flash_all.2512879624 |
|
|
Mar 28 03:23:48 PM PDT 24 |
Mar 28 03:24:32 PM PDT 24 |
26751695193 ps |
| T860 |
/workspace/coverage/default/13.spi_device_tpm_rw.118401665 |
|
|
Mar 28 03:22:27 PM PDT 24 |
Mar 28 03:22:28 PM PDT 24 |
81273538 ps |
| T861 |
/workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.2201421210 |
|
|
Mar 28 03:22:29 PM PDT 24 |
Mar 28 03:24:18 PM PDT 24 |
106349631373 ps |
| T862 |
/workspace/coverage/default/16.spi_device_tpm_rw.1072771510 |
|
|
Mar 28 03:22:32 PM PDT 24 |
Mar 28 03:22:34 PM PDT 24 |
46074810 ps |
| T863 |
/workspace/coverage/default/32.spi_device_stress_all.3918004310 |
|
|
Mar 28 03:23:30 PM PDT 24 |
Mar 28 03:23:31 PM PDT 24 |
747717095 ps |
| T864 |
/workspace/coverage/default/38.spi_device_tpm_rw.1447607768 |
|
|
Mar 28 03:23:59 PM PDT 24 |
Mar 28 03:24:02 PM PDT 24 |
381832013 ps |
| T865 |
/workspace/coverage/default/44.spi_device_read_buffer_direct.1538854038 |
|
|
Mar 28 03:24:31 PM PDT 24 |
Mar 28 03:24:35 PM PDT 24 |
227522122 ps |
| T866 |
/workspace/coverage/default/35.spi_device_flash_and_tpm.3997825430 |
|
|
Mar 28 03:23:45 PM PDT 24 |
Mar 28 03:26:27 PM PDT 24 |
16452615444 ps |
| T867 |
/workspace/coverage/default/16.spi_device_alert_test.1565421453 |
|
|
Mar 28 03:22:31 PM PDT 24 |
Mar 28 03:22:32 PM PDT 24 |
14374009 ps |
| T868 |
/workspace/coverage/default/30.spi_device_tpm_read_hw_reg.509559289 |
|
|
Mar 28 03:23:27 PM PDT 24 |
Mar 28 03:23:30 PM PDT 24 |
477101849 ps |
| T869 |
/workspace/coverage/default/1.spi_device_upload.1321041501 |
|
|
Mar 28 03:21:17 PM PDT 24 |
Mar 28 03:21:38 PM PDT 24 |
27495299826 ps |
| T870 |
/workspace/coverage/default/29.spi_device_pass_addr_payload_swap.2479083826 |
|
|
Mar 28 03:23:26 PM PDT 24 |
Mar 28 03:23:40 PM PDT 24 |
98749662760 ps |
| T871 |
/workspace/coverage/default/25.spi_device_pass_cmd_filtering.4062640479 |
|
|
Mar 28 03:22:52 PM PDT 24 |
Mar 28 03:23:03 PM PDT 24 |
11107577068 ps |
| T872 |
/workspace/coverage/default/8.spi_device_cfg_cmd.2079426528 |
|
|
Mar 28 03:21:44 PM PDT 24 |
Mar 28 03:21:48 PM PDT 24 |
85696434 ps |
| T873 |
/workspace/coverage/default/39.spi_device_pass_addr_payload_swap.2187756673 |
|
|
Mar 28 03:24:00 PM PDT 24 |
Mar 28 03:24:26 PM PDT 24 |
17500660864 ps |
| T874 |
/workspace/coverage/default/5.spi_device_read_buffer_direct.2764978552 |
|
|
Mar 28 03:21:40 PM PDT 24 |
Mar 28 03:21:44 PM PDT 24 |
235416313 ps |
| T875 |
/workspace/coverage/default/13.spi_device_alert_test.3558111594 |
|
|
Mar 28 03:22:30 PM PDT 24 |
Mar 28 03:22:31 PM PDT 24 |
73963817 ps |
| T876 |
/workspace/coverage/default/26.spi_device_tpm_all.3222378420 |
|
|
Mar 28 03:23:17 PM PDT 24 |
Mar 28 03:24:20 PM PDT 24 |
14100015317 ps |
| T877 |
/workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.192491 |
|
|
Mar 28 03:24:46 PM PDT 24 |
Mar 28 03:28:24 PM PDT 24 |
25201105170 ps |
| T878 |
/workspace/coverage/default/14.spi_device_read_buffer_direct.3015489299 |
|
|
Mar 28 03:22:30 PM PDT 24 |
Mar 28 03:22:34 PM PDT 24 |
245129852 ps |
| T879 |
/workspace/coverage/default/17.spi_device_tpm_rw.1212748270 |
|
|
Mar 28 03:22:32 PM PDT 24 |
Mar 28 03:22:33 PM PDT 24 |
20470592 ps |
| T880 |
/workspace/coverage/default/13.spi_device_flash_and_tpm.1936723690 |
|
|
Mar 28 03:22:31 PM PDT 24 |
Mar 28 03:26:18 PM PDT 24 |
30750152667 ps |
| T881 |
/workspace/coverage/default/46.spi_device_csb_read.1075832030 |
|
|
Mar 28 03:24:29 PM PDT 24 |
Mar 28 03:24:30 PM PDT 24 |
177086522 ps |
| T882 |
/workspace/coverage/default/8.spi_device_alert_test.2273266488 |
|
|
Mar 28 03:21:46 PM PDT 24 |
Mar 28 03:21:48 PM PDT 24 |
11159238 ps |
| T883 |
/workspace/coverage/default/12.spi_device_cfg_cmd.2094993890 |
|
|
Mar 28 03:22:08 PM PDT 24 |
Mar 28 03:22:13 PM PDT 24 |
3191858601 ps |
| T884 |
/workspace/coverage/default/30.spi_device_stress_all.1029418839 |
|
|
Mar 28 03:23:29 PM PDT 24 |
Mar 28 03:23:30 PM PDT 24 |
229599001 ps |
| T885 |
/workspace/coverage/default/28.spi_device_intercept.3330622049 |
|
|
Mar 28 03:23:13 PM PDT 24 |
Mar 28 03:23:26 PM PDT 24 |
3238267828 ps |
| T886 |
/workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.2790631554 |
|
|
Mar 28 03:22:33 PM PDT 24 |
Mar 28 03:28:33 PM PDT 24 |
53502870529 ps |
| T887 |
/workspace/coverage/default/22.spi_device_intercept.1345993386 |
|
|
Mar 28 03:22:47 PM PDT 24 |
Mar 28 03:22:50 PM PDT 24 |
481098686 ps |
| T888 |
/workspace/coverage/default/45.spi_device_upload.1968999446 |
|
|
Mar 28 03:24:30 PM PDT 24 |
Mar 28 03:24:35 PM PDT 24 |
512882207 ps |
| T889 |
/workspace/coverage/default/11.spi_device_ram_cfg.582097009 |
|
|
Mar 28 03:22:10 PM PDT 24 |
Mar 28 03:22:12 PM PDT 24 |
36792901 ps |
| T890 |
/workspace/coverage/default/6.spi_device_cfg_cmd.3842819334 |
|
|
Mar 28 03:21:51 PM PDT 24 |
Mar 28 03:21:55 PM PDT 24 |
467834846 ps |
| T891 |
/workspace/coverage/default/17.spi_device_csb_read.3190854256 |
|
|
Mar 28 03:22:34 PM PDT 24 |
Mar 28 03:22:35 PM PDT 24 |
14487970 ps |
| T892 |
/workspace/coverage/default/40.spi_device_pass_cmd_filtering.1979193434 |
|
|
Mar 28 03:24:01 PM PDT 24 |
Mar 28 03:24:08 PM PDT 24 |
1320796776 ps |
| T893 |
/workspace/coverage/default/49.spi_device_tpm_read_hw_reg.46455337 |
|
|
Mar 28 03:24:51 PM PDT 24 |
Mar 28 03:24:57 PM PDT 24 |
678337496 ps |
| T894 |
/workspace/coverage/default/35.spi_device_upload.2045870618 |
|
|
Mar 28 03:23:48 PM PDT 24 |
Mar 28 03:24:09 PM PDT 24 |
6044269838 ps |
| T895 |
/workspace/coverage/default/28.spi_device_pass_addr_payload_swap.3431358768 |
|
|
Mar 28 03:23:20 PM PDT 24 |
Mar 28 03:23:26 PM PDT 24 |
2360056475 ps |
| T896 |
/workspace/coverage/default/2.spi_device_pass_cmd_filtering.1918537497 |
|
|
Mar 28 03:21:32 PM PDT 24 |
Mar 28 03:21:40 PM PDT 24 |
710234273 ps |
| T897 |
/workspace/coverage/default/34.spi_device_upload.1763174220 |
|
|
Mar 28 03:23:48 PM PDT 24 |
Mar 28 03:24:09 PM PDT 24 |
5863350247 ps |
| T898 |
/workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.1302950198 |
|
|
Mar 28 03:22:30 PM PDT 24 |
Mar 28 03:31:01 PM PDT 24 |
74321078185 ps |
| T899 |
/workspace/coverage/default/22.spi_device_tpm_sts_read.3057101847 |
|
|
Mar 28 03:22:54 PM PDT 24 |
Mar 28 03:22:55 PM PDT 24 |
40811284 ps |
| T900 |
/workspace/coverage/default/4.spi_device_flash_all.1496228594 |
|
|
Mar 28 03:21:31 PM PDT 24 |
Mar 28 03:24:57 PM PDT 24 |
173309539658 ps |
| T901 |
/workspace/coverage/default/41.spi_device_flash_mode.2647717593 |
|
|
Mar 28 03:24:06 PM PDT 24 |
Mar 28 03:24:28 PM PDT 24 |
3374839856 ps |
| T902 |
/workspace/coverage/default/30.spi_device_tpm_all.2052974188 |
|
|
Mar 28 03:23:28 PM PDT 24 |
Mar 28 03:24:05 PM PDT 24 |
16802230769 ps |
| T903 |
/workspace/coverage/default/27.spi_device_upload.793000769 |
|
|
Mar 28 03:23:12 PM PDT 24 |
Mar 28 03:24:05 PM PDT 24 |
16562380313 ps |
| T904 |
/workspace/coverage/default/32.spi_device_upload.911177095 |
|
|
Mar 28 03:23:27 PM PDT 24 |
Mar 28 03:23:40 PM PDT 24 |
6346342194 ps |
| T905 |
/workspace/coverage/default/26.spi_device_cfg_cmd.1926238136 |
|
|
Mar 28 03:23:10 PM PDT 24 |
Mar 28 03:23:20 PM PDT 24 |
3941514334 ps |
| T906 |
/workspace/coverage/default/15.spi_device_tpm_all.2440852142 |
|
|
Mar 28 03:22:29 PM PDT 24 |
Mar 28 03:23:08 PM PDT 24 |
28163960303 ps |
| T907 |
/workspace/coverage/default/12.spi_device_alert_test.4233493654 |
|
|
Mar 28 03:22:11 PM PDT 24 |
Mar 28 03:22:12 PM PDT 24 |
32096276 ps |
| T908 |
/workspace/coverage/default/28.spi_device_tpm_all.1623696314 |
|
|
Mar 28 03:23:18 PM PDT 24 |
Mar 28 03:23:52 PM PDT 24 |
21981486969 ps |
| T909 |
/workspace/coverage/default/17.spi_device_read_buffer_direct.3893645575 |
|
|
Mar 28 03:22:32 PM PDT 24 |
Mar 28 03:22:38 PM PDT 24 |
3323833730 ps |
| T910 |
/workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.3440736785 |
|
|
Mar 28 03:23:44 PM PDT 24 |
Mar 28 03:26:31 PM PDT 24 |
94599179276 ps |
| T911 |
/workspace/coverage/default/34.spi_device_tpm_rw.3757609311 |
|
|
Mar 28 03:23:47 PM PDT 24 |
Mar 28 03:23:48 PM PDT 24 |
146167720 ps |
| T912 |
/workspace/coverage/default/28.spi_device_pass_cmd_filtering.3264120810 |
|
|
Mar 28 03:23:18 PM PDT 24 |
Mar 28 03:23:24 PM PDT 24 |
417805610 ps |
| T913 |
/workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.3115669553 |
|
|
Mar 28 03:23:25 PM PDT 24 |
Mar 28 03:24:59 PM PDT 24 |
71009133851 ps |
| T914 |
/workspace/coverage/default/39.spi_device_tpm_read_hw_reg.3680782393 |
|
|
Mar 28 03:24:07 PM PDT 24 |
Mar 28 03:24:10 PM PDT 24 |
750772930 ps |
| T915 |
/workspace/coverage/default/20.spi_device_flash_all.92026101 |
|
|
Mar 28 03:22:47 PM PDT 24 |
Mar 28 03:25:35 PM PDT 24 |
35625391238 ps |
| T916 |
/workspace/coverage/default/24.spi_device_mailbox.2897398414 |
|
|
Mar 28 03:22:47 PM PDT 24 |
Mar 28 03:22:56 PM PDT 24 |
623524098 ps |
| T917 |
/workspace/coverage/default/28.spi_device_stress_all.930964757 |
|
|
Mar 28 03:23:26 PM PDT 24 |
Mar 28 03:23:27 PM PDT 24 |
354388689 ps |
| T918 |
/workspace/coverage/default/36.spi_device_tpm_read_hw_reg.625460445 |
|
|
Mar 28 03:23:47 PM PDT 24 |
Mar 28 03:23:53 PM PDT 24 |
5448284858 ps |
| T919 |
/workspace/coverage/default/30.spi_device_pass_cmd_filtering.21364662 |
|
|
Mar 28 03:23:27 PM PDT 24 |
Mar 28 03:23:33 PM PDT 24 |
1147988764 ps |
| T920 |
/workspace/coverage/default/11.spi_device_stress_all.796558715 |
|
|
Mar 28 03:22:08 PM PDT 24 |
Mar 28 03:26:27 PM PDT 24 |
75970395641 ps |
| T921 |
/workspace/coverage/default/20.spi_device_cfg_cmd.4096480796 |
|
|
Mar 28 03:22:50 PM PDT 24 |
Mar 28 03:22:55 PM PDT 24 |
2767749325 ps |
| T922 |
/workspace/coverage/default/22.spi_device_csb_read.3923658051 |
|
|
Mar 28 03:22:52 PM PDT 24 |
Mar 28 03:22:53 PM PDT 24 |
28588069 ps |
| T923 |
/workspace/coverage/default/16.spi_device_ram_cfg.1964676834 |
|
|
Mar 28 03:22:29 PM PDT 24 |
Mar 28 03:22:31 PM PDT 24 |
22584479 ps |
| T924 |
/workspace/coverage/default/36.spi_device_read_buffer_direct.3423928017 |
|
|
Mar 28 03:23:48 PM PDT 24 |
Mar 28 03:23:52 PM PDT 24 |
1458389256 ps |
| T925 |
/workspace/coverage/default/44.spi_device_mailbox.2264440496 |
|
|
Mar 28 03:24:30 PM PDT 24 |
Mar 28 03:24:45 PM PDT 24 |
24112882304 ps |
| T926 |
/workspace/coverage/default/43.spi_device_tpm_sts_read.2575795373 |
|
|
Mar 28 03:24:30 PM PDT 24 |
Mar 28 03:24:31 PM PDT 24 |
246025779 ps |
| T927 |
/workspace/coverage/default/0.spi_device_tpm_all.2854216500 |
|
|
Mar 28 03:21:10 PM PDT 24 |
Mar 28 03:21:20 PM PDT 24 |
1585025427 ps |
| T928 |
/workspace/coverage/default/18.spi_device_ram_cfg.2360207914 |
|
|
Mar 28 03:22:28 PM PDT 24 |
Mar 28 03:22:29 PM PDT 24 |
16424774 ps |
| T929 |
/workspace/coverage/default/40.spi_device_flash_all.3148850867 |
|
|
Mar 28 03:24:01 PM PDT 24 |
Mar 28 03:24:14 PM PDT 24 |
5199245315 ps |
| T930 |
/workspace/coverage/default/26.spi_device_tpm_sts_read.2470403135 |
|
|
Mar 28 03:23:18 PM PDT 24 |
Mar 28 03:23:20 PM PDT 24 |
24762239 ps |
| T931 |
/workspace/coverage/default/41.spi_device_tpm_read_hw_reg.3058205223 |
|
|
Mar 28 03:24:07 PM PDT 24 |
Mar 28 03:24:20 PM PDT 24 |
6624721446 ps |
| T58 |
/workspace/coverage/default/4.spi_device_sec_cm.3954612748 |
|
|
Mar 28 03:21:31 PM PDT 24 |
Mar 28 03:21:33 PM PDT 24 |
171894004 ps |
| T932 |
/workspace/coverage/default/48.spi_device_csb_read.1858754151 |
|
|
Mar 28 03:24:47 PM PDT 24 |
Mar 28 03:24:48 PM PDT 24 |
28255192 ps |
| T933 |
/workspace/coverage/default/42.spi_device_cfg_cmd.2374133317 |
|
|
Mar 28 03:24:32 PM PDT 24 |
Mar 28 03:24:36 PM PDT 24 |
844196882 ps |
| T934 |
/workspace/coverage/default/43.spi_device_flash_and_tpm.3103732758 |
|
|
Mar 28 03:24:32 PM PDT 24 |
Mar 28 03:25:06 PM PDT 24 |
10374518159 ps |
| T935 |
/workspace/coverage/default/26.spi_device_tpm_rw.426986731 |
|
|
Mar 28 03:23:18 PM PDT 24 |
Mar 28 03:23:22 PM PDT 24 |
1490547698 ps |
| T936 |
/workspace/coverage/default/12.spi_device_tpm_read_hw_reg.1931168382 |
|
|
Mar 28 03:22:07 PM PDT 24 |
Mar 28 03:22:37 PM PDT 24 |
9671369608 ps |
| T937 |
/workspace/coverage/default/6.spi_device_stress_all.2107720181 |
|
|
Mar 28 03:21:43 PM PDT 24 |
Mar 28 03:22:59 PM PDT 24 |
103952405546 ps |
| T938 |
/workspace/coverage/default/5.spi_device_tpm_sts_read.2434832400 |
|
|
Mar 28 03:21:29 PM PDT 24 |
Mar 28 03:21:30 PM PDT 24 |
67882132 ps |
| T939 |
/workspace/coverage/default/8.spi_device_tpm_read_hw_reg.2637106962 |
|
|
Mar 28 03:21:56 PM PDT 24 |
Mar 28 03:22:02 PM PDT 24 |
6012518862 ps |
| T940 |
/workspace/coverage/default/7.spi_device_csb_read.453505392 |
|
|
Mar 28 03:21:43 PM PDT 24 |
Mar 28 03:21:45 PM PDT 24 |
49601476 ps |
| T941 |
/workspace/coverage/default/32.spi_device_tpm_rw.1112977013 |
|
|
Mar 28 03:23:38 PM PDT 24 |
Mar 28 03:23:41 PM PDT 24 |
213029096 ps |
| T942 |
/workspace/coverage/default/48.spi_device_tpm_read_hw_reg.1738345474 |
|
|
Mar 28 03:24:50 PM PDT 24 |
Mar 28 03:24:52 PM PDT 24 |
901304289 ps |
| T943 |
/workspace/coverage/default/8.spi_device_mailbox.3694447684 |
|
|
Mar 28 03:21:41 PM PDT 24 |
Mar 28 03:21:49 PM PDT 24 |
717196832 ps |
| T944 |
/workspace/coverage/default/0.spi_device_read_buffer_direct.2702343626 |
|
|
Mar 28 03:21:13 PM PDT 24 |
Mar 28 03:21:18 PM PDT 24 |
9876763435 ps |
| T945 |
/workspace/coverage/default/0.spi_device_flash_mode.1868298043 |
|
|
Mar 28 03:21:13 PM PDT 24 |
Mar 28 03:21:23 PM PDT 24 |
4739924972 ps |
| T946 |
/workspace/coverage/default/4.spi_device_alert_test.3053088844 |
|
|
Mar 28 03:21:32 PM PDT 24 |
Mar 28 03:21:32 PM PDT 24 |
10832801 ps |
| T947 |
/workspace/coverage/default/32.spi_device_pass_cmd_filtering.4240021847 |
|
|
Mar 28 03:23:32 PM PDT 24 |
Mar 28 03:24:16 PM PDT 24 |
32868252035 ps |
| T241 |
/workspace/coverage/default/48.spi_device_flash_all.3764160423 |
|
|
Mar 28 03:24:47 PM PDT 24 |
Mar 28 03:25:54 PM PDT 24 |
7464938494 ps |
| T948 |
/workspace/coverage/default/47.spi_device_tpm_all.1811362454 |
|
|
Mar 28 03:24:47 PM PDT 24 |
Mar 28 03:24:59 PM PDT 24 |
27160951757 ps |
| T949 |
/workspace/coverage/default/39.spi_device_pass_cmd_filtering.514823830 |
|
|
Mar 28 03:23:59 PM PDT 24 |
Mar 28 03:24:22 PM PDT 24 |
19634481286 ps |
| T950 |
/workspace/coverage/default/43.spi_device_csb_read.2146854165 |
|
|
Mar 28 03:24:34 PM PDT 24 |
Mar 28 03:24:35 PM PDT 24 |
47967755 ps |
| T951 |
/workspace/coverage/default/18.spi_device_upload.2762436007 |
|
|
Mar 28 03:22:29 PM PDT 24 |
Mar 28 03:22:34 PM PDT 24 |
839123987 ps |
| T952 |
/workspace/coverage/default/20.spi_device_pass_addr_payload_swap.1678209334 |
|
|
Mar 28 03:22:37 PM PDT 24 |
Mar 28 03:22:49 PM PDT 24 |
12819346271 ps |
| T953 |
/workspace/coverage/default/2.spi_device_flash_mode.1235824191 |
|
|
Mar 28 03:21:24 PM PDT 24 |
Mar 28 03:21:48 PM PDT 24 |
4510899934 ps |
| T954 |
/workspace/coverage/default/18.spi_device_flash_and_tpm.4049173994 |
|
|
Mar 28 03:22:28 PM PDT 24 |
Mar 28 03:23:19 PM PDT 24 |
12344581130 ps |
| T955 |
/workspace/coverage/default/49.spi_device_read_buffer_direct.3701107955 |
|
|
Mar 28 03:24:52 PM PDT 24 |
Mar 28 03:24:58 PM PDT 24 |
1530269901 ps |
| T956 |
/workspace/coverage/default/42.spi_device_pass_addr_payload_swap.413609711 |
|
|
Mar 28 03:24:28 PM PDT 24 |
Mar 28 03:24:41 PM PDT 24 |
18216028146 ps |
| T957 |
/workspace/coverage/default/45.spi_device_stress_all.1147094713 |
|
|
Mar 28 03:24:26 PM PDT 24 |
Mar 28 03:27:47 PM PDT 24 |
24785935391 ps |
| T958 |
/workspace/coverage/default/14.spi_device_intercept.2746421819 |
|
|
Mar 28 03:22:29 PM PDT 24 |
Mar 28 03:22:33 PM PDT 24 |
265815354 ps |
| T959 |
/workspace/coverage/default/13.spi_device_stress_all.2500562975 |
|
|
Mar 28 03:22:27 PM PDT 24 |
Mar 28 03:23:18 PM PDT 24 |
6239847195 ps |
| T960 |
/workspace/coverage/default/49.spi_device_tpm_all.3108241053 |
|
|
Mar 28 03:24:49 PM PDT 24 |
Mar 28 03:25:02 PM PDT 24 |
1724074234 ps |
| T961 |
/workspace/coverage/default/0.spi_device_flash_and_tpm.2590806507 |
|
|
Mar 28 03:21:12 PM PDT 24 |
Mar 28 03:23:49 PM PDT 24 |
87095062237 ps |
| T962 |
/workspace/coverage/default/5.spi_device_upload.3168497968 |
|
|
Mar 28 03:21:27 PM PDT 24 |
Mar 28 03:21:52 PM PDT 24 |
6482126622 ps |
| T963 |
/workspace/coverage/default/34.spi_device_flash_mode.2511440002 |
|
|
Mar 28 03:23:45 PM PDT 24 |
Mar 28 03:23:53 PM PDT 24 |
868333189 ps |
| T964 |
/workspace/coverage/default/35.spi_device_tpm_sts_read.2087534530 |
|
|
Mar 28 03:23:46 PM PDT 24 |
Mar 28 03:23:47 PM PDT 24 |
27762639 ps |
| T965 |
/workspace/coverage/default/16.spi_device_read_buffer_direct.3190429669 |
|
|
Mar 28 03:22:36 PM PDT 24 |
Mar 28 03:22:40 PM PDT 24 |
95415663 ps |
| T966 |
/workspace/coverage/default/8.spi_device_tpm_rw.3144355959 |
|
|
Mar 28 03:21:42 PM PDT 24 |
Mar 28 03:21:45 PM PDT 24 |
114819031 ps |
| T967 |
/workspace/coverage/default/0.spi_device_csb_read.1516814553 |
|
|
Mar 28 03:21:16 PM PDT 24 |
Mar 28 03:21:16 PM PDT 24 |
13624261 ps |
| T968 |
/workspace/coverage/default/30.spi_device_intercept.4211750567 |
|
|
Mar 28 03:23:26 PM PDT 24 |
Mar 28 03:23:35 PM PDT 24 |
2357332857 ps |
| T969 |
/workspace/coverage/default/4.spi_device_read_buffer_direct.2647735463 |
|
|
Mar 28 03:21:31 PM PDT 24 |
Mar 28 03:21:35 PM PDT 24 |
1128364140 ps |
| T970 |
/workspace/coverage/default/44.spi_device_stress_all.166597369 |
|
|
Mar 28 03:24:32 PM PDT 24 |
Mar 28 03:25:31 PM PDT 24 |
9437631290 ps |
| T971 |
/workspace/coverage/default/37.spi_device_flash_and_tpm.1700625181 |
|
|
Mar 28 03:23:51 PM PDT 24 |
Mar 28 03:24:50 PM PDT 24 |
28597090987 ps |
| T972 |
/workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.3291467060 |
|
|
Mar 28 03:21:13 PM PDT 24 |
Mar 28 03:22:23 PM PDT 24 |
13361137181 ps |
| T973 |
/workspace/coverage/default/35.spi_device_alert_test.3016857385 |
|
|
Mar 28 03:23:45 PM PDT 24 |
Mar 28 03:23:46 PM PDT 24 |
35435847 ps |
| T974 |
/workspace/coverage/cover_reg_top/6.spi_device_intr_test.1165390053 |
|
|
Mar 28 12:57:15 PM PDT 24 |
Mar 28 12:57:16 PM PDT 24 |
36819815 ps |
| T975 |
/workspace/coverage/cover_reg_top/47.spi_device_intr_test.4049316905 |
|
|
Mar 28 12:57:21 PM PDT 24 |
Mar 28 12:57:22 PM PDT 24 |
42793760 ps |
| T976 |
/workspace/coverage/cover_reg_top/40.spi_device_intr_test.1316138700 |
|
|
Mar 28 12:57:29 PM PDT 24 |
Mar 28 12:57:30 PM PDT 24 |
15002563 ps |
| T48 |
/workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1078502837 |
|
|
Mar 28 12:57:27 PM PDT 24 |
Mar 28 12:57:31 PM PDT 24 |
649283212 ps |
| T49 |
/workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3334844876 |
|
|
Mar 28 12:57:14 PM PDT 24 |
Mar 28 12:57:26 PM PDT 24 |
768621351 ps |
| T122 |
/workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1010987916 |
|
|
Mar 28 12:57:11 PM PDT 24 |
Mar 28 12:57:16 PM PDT 24 |
388291596 ps |
| T977 |
/workspace/coverage/cover_reg_top/27.spi_device_intr_test.2203634963 |
|
|
Mar 28 12:57:25 PM PDT 24 |
Mar 28 12:57:26 PM PDT 24 |
56981316 ps |
| T50 |
/workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3546418338 |
|
|
Mar 28 12:57:06 PM PDT 24 |
Mar 28 12:57:11 PM PDT 24 |
972728898 ps |
| T100 |
/workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3722479582 |
|
|
Mar 28 12:57:16 PM PDT 24 |
Mar 28 12:57:31 PM PDT 24 |
836526994 ps |
| T101 |
/workspace/coverage/cover_reg_top/2.spi_device_csr_rw.495505123 |
|
|
Mar 28 12:57:15 PM PDT 24 |
Mar 28 12:57:17 PM PDT 24 |
30921731 ps |
| T978 |
/workspace/coverage/cover_reg_top/20.spi_device_intr_test.1263693568 |
|
|
Mar 28 12:57:22 PM PDT 24 |
Mar 28 12:57:23 PM PDT 24 |
45651201 ps |
| T979 |
/workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1529805814 |
|
|
Mar 28 12:57:11 PM PDT 24 |
Mar 28 12:57:15 PM PDT 24 |
162823974 ps |
| T980 |
/workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2915606548 |
|
|
Mar 28 12:57:09 PM PDT 24 |
Mar 28 12:57:10 PM PDT 24 |
13718185 ps |
| T79 |
/workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2264156824 |
|
|
Mar 28 12:57:09 PM PDT 24 |
Mar 28 12:57:12 PM PDT 24 |
34198693 ps |
| T96 |
/workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.3340104966 |
|
|
Mar 28 12:57:18 PM PDT 24 |
Mar 28 12:57:20 PM PDT 24 |
447652549 ps |
| T82 |
/workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2989196545 |
|
|
Mar 28 12:57:08 PM PDT 24 |
Mar 28 12:57:13 PM PDT 24 |
144296838 ps |
| T80 |
/workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3262714185 |
|
|
Mar 28 12:57:08 PM PDT 24 |
Mar 28 12:57:23 PM PDT 24 |
552863206 ps |
| T107 |
/workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3605019497 |
|
|
Mar 28 12:57:11 PM PDT 24 |
Mar 28 12:57:14 PM PDT 24 |
85052864 ps |
| T981 |
/workspace/coverage/cover_reg_top/38.spi_device_intr_test.1407538787 |
|
|
Mar 28 12:57:26 PM PDT 24 |
Mar 28 12:57:26 PM PDT 24 |
87014081 ps |
| T102 |
/workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3828024005 |
|
|
Mar 28 12:57:08 PM PDT 24 |
Mar 28 12:57:10 PM PDT 24 |
21070073 ps |
| T982 |
/workspace/coverage/cover_reg_top/34.spi_device_intr_test.2119323659 |
|
|
Mar 28 12:57:22 PM PDT 24 |
Mar 28 12:57:23 PM PDT 24 |
16138201 ps |
| T103 |
/workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3279444831 |
|
|
Mar 28 12:57:11 PM PDT 24 |
Mar 28 12:57:14 PM PDT 24 |
30402701 ps |
| T69 |
/workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3766717631 |
|
|
Mar 28 12:57:08 PM PDT 24 |
Mar 28 12:57:11 PM PDT 24 |
24929331 ps |
| T81 |
/workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3270456691 |
|
|
Mar 28 12:57:11 PM PDT 24 |
Mar 28 12:57:14 PM PDT 24 |
50500181 ps |
| T104 |
/workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1780437342 |
|
|
Mar 28 12:57:11 PM PDT 24 |
Mar 28 12:57:14 PM PDT 24 |
32367824 ps |
| T84 |
/workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1824482664 |
|
|
Mar 28 12:57:14 PM PDT 24 |
Mar 28 12:57:17 PM PDT 24 |
341600200 ps |
| T983 |
/workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1106335478 |
|
|
Mar 28 12:57:11 PM PDT 24 |
Mar 28 12:57:14 PM PDT 24 |
222725344 ps |
| T97 |
/workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.301888193 |
|
|
Mar 28 12:57:09 PM PDT 24 |
Mar 28 12:57:13 PM PDT 24 |
463330169 ps |
| T984 |
/workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1222069505 |
|
|
Mar 28 12:57:12 PM PDT 24 |
Mar 28 12:57:15 PM PDT 24 |
42953044 ps |
| T985 |
/workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.85558410 |
|
|
Mar 28 12:57:19 PM PDT 24 |
Mar 28 12:57:21 PM PDT 24 |
188170287 ps |
| T83 |
/workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1045542212 |
|
|
Mar 28 12:57:10 PM PDT 24 |
Mar 28 12:57:19 PM PDT 24 |
314833135 ps |
| T123 |
/workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3746725367 |
|
|
Mar 28 12:57:14 PM PDT 24 |
Mar 28 12:57:16 PM PDT 24 |
124577401 ps |
| T986 |
/workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3694567221 |
|
|
Mar 28 12:57:13 PM PDT 24 |
Mar 28 12:57:17 PM PDT 24 |
41447906 ps |
| T124 |
/workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2402006218 |
|
|
Mar 28 12:57:08 PM PDT 24 |
Mar 28 12:57:17 PM PDT 24 |
431365502 ps |
| T987 |
/workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3980922313 |
|
|
Mar 28 12:57:13 PM PDT 24 |
Mar 28 12:57:30 PM PDT 24 |
613592357 ps |
| T988 |
/workspace/coverage/cover_reg_top/7.spi_device_intr_test.2893401241 |
|
|
Mar 28 12:57:18 PM PDT 24 |
Mar 28 12:57:18 PM PDT 24 |
28563794 ps |
| T70 |
/workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.420651685 |
|
|
Mar 28 12:57:13 PM PDT 24 |
Mar 28 12:57:16 PM PDT 24 |
37101883 ps |
| T85 |
/workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2475896063 |
|
|
Mar 28 12:57:18 PM PDT 24 |
Mar 28 12:57:22 PM PDT 24 |
166720836 ps |
| T105 |
/workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1844050430 |
|
|
Mar 28 12:57:07 PM PDT 24 |
Mar 28 12:57:32 PM PDT 24 |
5824035621 ps |
| T87 |
/workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3481461660 |
|
|
Mar 28 12:57:11 PM PDT 24 |
Mar 28 12:57:16 PM PDT 24 |
151672362 ps |
| T141 |
/workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.174482897 |
|
|
Mar 28 12:57:13 PM PDT 24 |
Mar 28 12:57:21 PM PDT 24 |
207909363 ps |
| T86 |
/workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2705073463 |
|
|
Mar 28 12:57:28 PM PDT 24 |
Mar 28 12:57:31 PM PDT 24 |
203691649 ps |
| T125 |
/workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1151792706 |
|
|
Mar 28 12:57:42 PM PDT 24 |
Mar 28 12:57:52 PM PDT 24 |
1470377667 ps |
| T989 |
/workspace/coverage/cover_reg_top/28.spi_device_intr_test.2046053987 |
|
|
Mar 28 12:57:22 PM PDT 24 |
Mar 28 12:57:22 PM PDT 24 |
16070853 ps |
| T95 |
/workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3808551904 |
|
|
Mar 28 12:57:24 PM PDT 24 |
Mar 28 12:57:27 PM PDT 24 |
40744747 ps |
| T990 |
/workspace/coverage/cover_reg_top/23.spi_device_intr_test.1055319399 |
|
|
Mar 28 12:57:28 PM PDT 24 |
Mar 28 12:57:29 PM PDT 24 |
57842886 ps |
| T991 |
/workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1460019482 |
|
|
Mar 28 12:57:11 PM PDT 24 |
Mar 28 12:57:15 PM PDT 24 |
43066633 ps |
| T71 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.4127969180 |
|
|
Mar 28 12:57:08 PM PDT 24 |
Mar 28 12:57:10 PM PDT 24 |
113871973 ps |
| T992 |
/workspace/coverage/cover_reg_top/17.spi_device_intr_test.1210923878 |
|
|
Mar 28 12:57:22 PM PDT 24 |
Mar 28 12:57:24 PM PDT 24 |
17925614 ps |
| T138 |
/workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.762573073 |
|
|
Mar 28 12:57:09 PM PDT 24 |
Mar 28 12:57:21 PM PDT 24 |
802989756 ps |
| T993 |
/workspace/coverage/cover_reg_top/48.spi_device_intr_test.3213837185 |
|
|
Mar 28 12:57:26 PM PDT 24 |
Mar 28 12:57:27 PM PDT 24 |
48454334 ps |
| T994 |
/workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1830146669 |
|
|
Mar 28 12:57:19 PM PDT 24 |
Mar 28 12:57:54 PM PDT 24 |
3555476354 ps |
| T106 |
/workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3256440890 |
|
|
Mar 28 12:57:19 PM PDT 24 |
Mar 28 12:57:21 PM PDT 24 |
20587162 ps |
| T995 |
/workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3525922584 |
|
|
Mar 28 12:57:18 PM PDT 24 |
Mar 28 12:57:20 PM PDT 24 |
29281878 ps |
| T89 |
/workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3741094718 |
|
|
Mar 28 12:57:20 PM PDT 24 |
Mar 28 12:57:22 PM PDT 24 |
129992261 ps |
| T88 |
/workspace/coverage/cover_reg_top/6.spi_device_tl_errors.314235300 |
|
|
Mar 28 12:57:14 PM PDT 24 |
Mar 28 12:57:16 PM PDT 24 |
23941505 ps |
| T108 |
/workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3176968333 |
|
|
Mar 28 12:57:22 PM PDT 24 |
Mar 28 12:57:24 PM PDT 24 |
47046509 ps |
| T91 |
/workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1409518927 |
|
|
Mar 28 12:57:05 PM PDT 24 |
Mar 28 12:57:09 PM PDT 24 |
214172124 ps |
| T996 |
/workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.531437933 |
|
|
Mar 28 12:57:27 PM PDT 24 |
Mar 28 12:57:31 PM PDT 24 |
194982660 ps |
| T92 |
/workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2068176737 |
|
|
Mar 28 12:57:09 PM PDT 24 |
Mar 28 12:57:13 PM PDT 24 |
653552309 ps |
| T997 |
/workspace/coverage/cover_reg_top/11.spi_device_intr_test.4281591304 |
|
|
Mar 28 12:57:10 PM PDT 24 |
Mar 28 12:57:11 PM PDT 24 |
44684083 ps |
| T109 |
/workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1369891858 |
|
|
Mar 28 12:57:13 PM PDT 24 |
Mar 28 12:57:16 PM PDT 24 |
72129399 ps |
| T998 |
/workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.4243087336 |
|
|
Mar 28 12:57:29 PM PDT 24 |
Mar 28 12:57:33 PM PDT 24 |
677822381 ps |
| T999 |
/workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2339909511 |
|
|
Mar 28 12:57:09 PM PDT 24 |
Mar 28 12:57:13 PM PDT 24 |
230493084 ps |
| T93 |
/workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1699594776 |
|
|
Mar 28 12:57:21 PM PDT 24 |
Mar 28 12:57:27 PM PDT 24 |
485800202 ps |
| T1000 |
/workspace/coverage/cover_reg_top/25.spi_device_intr_test.3854993452 |
|
|
Mar 28 12:57:21 PM PDT 24 |
Mar 28 12:57:22 PM PDT 24 |
58431596 ps |
| T1001 |
/workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2740980016 |
|
|
Mar 28 12:57:08 PM PDT 24 |
Mar 28 12:57:11 PM PDT 24 |
26788761 ps |
| T1002 |
/workspace/coverage/cover_reg_top/32.spi_device_intr_test.4145613124 |
|
|
Mar 28 12:57:27 PM PDT 24 |
Mar 28 12:57:28 PM PDT 24 |
35193765 ps |
| T1003 |
/workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.4196954918 |
|
|
Mar 28 12:57:09 PM PDT 24 |
Mar 28 12:57:36 PM PDT 24 |
30020237744 ps |
| T1004 |
/workspace/coverage/cover_reg_top/29.spi_device_intr_test.172827310 |
|
|
Mar 28 12:57:27 PM PDT 24 |
Mar 28 12:57:28 PM PDT 24 |
47947146 ps |
| T72 |
/workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.472164480 |
|
|
Mar 28 12:57:07 PM PDT 24 |
Mar 28 12:57:09 PM PDT 24 |
24350953 ps |
| T1005 |
/workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1789426876 |
|
|
Mar 28 12:57:10 PM PDT 24 |
Mar 28 12:57:13 PM PDT 24 |
24230918 ps |
| T1006 |
/workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.209280647 |
|
|
Mar 28 12:57:27 PM PDT 24 |
Mar 28 12:57:30 PM PDT 24 |
42722057 ps |
| T1007 |
/workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1747668639 |
|
|
Mar 28 12:57:14 PM PDT 24 |
Mar 28 12:57:19 PM PDT 24 |
200927909 ps |
| T1008 |
/workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2290608300 |
|
|
Mar 28 12:57:10 PM PDT 24 |
Mar 28 12:57:23 PM PDT 24 |
262628358 ps |
| T110 |
/workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2185095679 |
|
|
Mar 28 12:57:24 PM PDT 24 |
Mar 28 12:57:26 PM PDT 24 |
207623338 ps |
| T111 |
/workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2406905862 |
|
|
Mar 28 12:57:09 PM PDT 24 |
Mar 28 12:57:12 PM PDT 24 |
159607143 ps |
| T1009 |
/workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.4071392976 |
|
|
Mar 28 12:57:18 PM PDT 24 |
Mar 28 12:57:21 PM PDT 24 |
58847920 ps |
| T145 |
/workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3037047344 |
|
|
Mar 28 12:57:10 PM PDT 24 |
Mar 28 12:57:19 PM PDT 24 |
724695984 ps |