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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.92 98.30 94.08 98.61 89.36 97.00 95.84 98.22


Total test records in report: 1096
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T1010 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2160567026 Mar 28 12:57:29 PM PDT 24 Mar 28 12:57:33 PM PDT 24 64297859 ps
T1011 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2653404992 Mar 28 12:57:26 PM PDT 24 Mar 28 12:57:27 PM PDT 24 31820058 ps
T1012 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.4166692512 Mar 28 12:57:08 PM PDT 24 Mar 28 12:57:10 PM PDT 24 12736179 ps
T1013 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3653146695 Mar 28 12:57:11 PM PDT 24 Mar 28 12:57:13 PM PDT 24 79731663 ps
T139 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.933302891 Mar 28 12:57:27 PM PDT 24 Mar 28 12:57:39 PM PDT 24 782428211 ps
T94 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3097357090 Mar 28 12:57:10 PM PDT 24 Mar 28 12:57:15 PM PDT 24 699537066 ps
T1014 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.169740174 Mar 28 12:57:12 PM PDT 24 Mar 28 12:57:46 PM PDT 24 3008814917 ps
T1015 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3000973910 Mar 28 12:57:14 PM PDT 24 Mar 28 12:57:15 PM PDT 24 13710676 ps
T1016 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1733050794 Mar 28 12:57:42 PM PDT 24 Mar 28 12:57:44 PM PDT 24 25907486 ps
T1017 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2590005847 Mar 28 12:57:15 PM PDT 24 Mar 28 12:57:23 PM PDT 24 603278929 ps
T1018 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.553061149 Mar 28 12:57:14 PM PDT 24 Mar 28 12:57:16 PM PDT 24 51960503 ps
T1019 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2452866692 Mar 28 12:57:27 PM PDT 24 Mar 28 12:57:28 PM PDT 24 17680989 ps
T1020 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1006354064 Mar 28 12:57:28 PM PDT 24 Mar 28 12:57:28 PM PDT 24 22653994 ps
T1021 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1448032349 Mar 28 12:57:32 PM PDT 24 Mar 28 12:57:33 PM PDT 24 11554641 ps
T1022 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3338397125 Mar 28 12:57:10 PM PDT 24 Mar 28 12:57:12 PM PDT 24 21179658 ps
T147 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2859700283 Mar 28 12:57:21 PM PDT 24 Mar 28 12:57:44 PM PDT 24 1032267807 ps
T1023 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.4058930157 Mar 28 12:57:13 PM PDT 24 Mar 28 12:57:16 PM PDT 24 19346879 ps
T1024 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1517002081 Mar 28 12:57:09 PM PDT 24 Mar 28 12:57:12 PM PDT 24 255529341 ps
T1025 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3955638373 Mar 28 12:57:17 PM PDT 24 Mar 28 12:57:18 PM PDT 24 17322117 ps
T1026 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2442384341 Mar 28 12:57:09 PM PDT 24 Mar 28 12:57:13 PM PDT 24 125430584 ps
T1027 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2576954427 Mar 28 12:57:28 PM PDT 24 Mar 28 12:57:31 PM PDT 24 372626355 ps
T1028 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2736015486 Mar 28 12:57:12 PM PDT 24 Mar 28 12:57:13 PM PDT 24 49849407 ps
T1029 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1453555794 Mar 28 12:57:22 PM PDT 24 Mar 28 12:57:23 PM PDT 24 28869353 ps
T1030 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.113584179 Mar 28 12:57:15 PM PDT 24 Mar 28 12:57:17 PM PDT 24 76213791 ps
T1031 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2732595596 Mar 28 12:57:11 PM PDT 24 Mar 28 12:57:13 PM PDT 24 16443309 ps
T1032 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.4291425845 Mar 28 12:57:14 PM PDT 24 Mar 28 12:57:16 PM PDT 24 98711213 ps
T1033 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.4105680487 Mar 28 12:57:09 PM PDT 24 Mar 28 12:57:11 PM PDT 24 33613249 ps
T142 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.51546941 Mar 28 12:57:13 PM PDT 24 Mar 28 12:57:35 PM PDT 24 1209750796 ps
T1034 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2737756110 Mar 28 12:57:21 PM PDT 24 Mar 28 12:57:22 PM PDT 24 34243371 ps
T1035 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.344918295 Mar 28 12:57:15 PM PDT 24 Mar 28 12:57:17 PM PDT 24 233712536 ps
T1036 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2533289761 Mar 28 12:57:19 PM PDT 24 Mar 28 12:57:20 PM PDT 24 12542600 ps
T143 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2434329785 Mar 28 12:57:07 PM PDT 24 Mar 28 12:57:21 PM PDT 24 208766091 ps
T1037 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.37755765 Mar 28 12:57:09 PM PDT 24 Mar 28 12:57:12 PM PDT 24 69467374 ps
T1038 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3007689707 Mar 28 12:57:12 PM PDT 24 Mar 28 12:57:38 PM PDT 24 930404831 ps
T1039 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1752215410 Mar 28 12:57:18 PM PDT 24 Mar 28 12:57:20 PM PDT 24 213911928 ps
T1040 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3691264014 Mar 28 12:57:18 PM PDT 24 Mar 28 12:57:20 PM PDT 24 153279048 ps
T1041 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.862594640 Mar 28 12:57:27 PM PDT 24 Mar 28 12:57:31 PM PDT 24 457537427 ps
T1042 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2212841861 Mar 28 12:57:15 PM PDT 24 Mar 28 12:57:19 PM PDT 24 265781109 ps
T1043 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.962086607 Mar 28 12:57:09 PM PDT 24 Mar 28 12:57:12 PM PDT 24 74626040 ps
T1044 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3534510762 Mar 28 12:57:14 PM PDT 24 Mar 28 12:57:17 PM PDT 24 416433330 ps
T1045 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1478770481 Mar 28 12:57:10 PM PDT 24 Mar 28 12:57:14 PM PDT 24 39405896 ps
T1046 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2508815282 Mar 28 12:57:08 PM PDT 24 Mar 28 12:57:12 PM PDT 24 61234804 ps
T1047 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.693309639 Mar 28 12:57:10 PM PDT 24 Mar 28 12:57:11 PM PDT 24 26805760 ps
T1048 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.116738574 Mar 28 12:57:11 PM PDT 24 Mar 28 12:57:13 PM PDT 24 16944966 ps
T1049 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.3922411885 Mar 28 12:57:40 PM PDT 24 Mar 28 12:57:41 PM PDT 24 52466538 ps
T1050 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.511391294 Mar 28 12:57:13 PM PDT 24 Mar 28 12:57:15 PM PDT 24 11426234 ps
T1051 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1514066080 Mar 28 12:57:40 PM PDT 24 Mar 28 12:57:40 PM PDT 24 38568018 ps
T1052 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1913262367 Mar 28 12:57:05 PM PDT 24 Mar 28 12:57:09 PM PDT 24 1231357119 ps
T1053 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2018132445 Mar 28 12:57:11 PM PDT 24 Mar 28 12:57:19 PM PDT 24 191674763 ps
T1054 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3868276349 Mar 28 12:57:16 PM PDT 24 Mar 28 12:57:19 PM PDT 24 184208639 ps
T1055 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3129686681 Mar 28 12:57:27 PM PDT 24 Mar 28 12:57:28 PM PDT 24 48094352 ps
T1056 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3500936652 Mar 28 12:57:14 PM PDT 24 Mar 28 12:57:16 PM PDT 24 35989315 ps
T90 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2511698598 Mar 28 12:57:20 PM PDT 24 Mar 28 12:57:34 PM PDT 24 2405939360 ps
T1057 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2993850565 Mar 28 12:57:12 PM PDT 24 Mar 28 12:57:21 PM PDT 24 105094024 ps
T1058 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1597603199 Mar 28 12:57:08 PM PDT 24 Mar 28 12:57:10 PM PDT 24 67456184 ps
T1059 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1058448822 Mar 28 12:57:19 PM PDT 24 Mar 28 12:57:20 PM PDT 24 37804266 ps
T1060 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2106975638 Mar 28 12:57:09 PM PDT 24 Mar 28 12:57:12 PM PDT 24 68950154 ps
T1061 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3627656109 Mar 28 12:57:09 PM PDT 24 Mar 28 12:57:12 PM PDT 24 28106632 ps
T1062 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.659075748 Mar 28 12:57:10 PM PDT 24 Mar 28 12:57:15 PM PDT 24 280721474 ps
T1063 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2834028306 Mar 28 12:57:12 PM PDT 24 Mar 28 12:57:17 PM PDT 24 163869769 ps
T1064 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.4010248409 Mar 28 12:57:25 PM PDT 24 Mar 28 12:57:26 PM PDT 24 13175947 ps
T146 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2867234715 Mar 28 12:57:11 PM PDT 24 Mar 28 12:57:20 PM PDT 24 298221572 ps
T1065 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3847235004 Mar 28 12:57:11 PM PDT 24 Mar 28 12:57:12 PM PDT 24 19155660 ps
T1066 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.3408078759 Mar 28 12:57:40 PM PDT 24 Mar 28 12:57:40 PM PDT 24 16950819 ps
T1067 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1885883877 Mar 28 12:57:05 PM PDT 24 Mar 28 12:57:06 PM PDT 24 25240511 ps
T1068 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3177614231 Mar 28 12:57:08 PM PDT 24 Mar 28 12:57:11 PM PDT 24 284612165 ps
T1069 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1311810981 Mar 28 12:57:08 PM PDT 24 Mar 28 12:57:48 PM PDT 24 3674774901 ps
T1070 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1174982546 Mar 28 12:57:19 PM PDT 24 Mar 28 12:57:21 PM PDT 24 244028220 ps
T140 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.492162438 Mar 28 12:57:14 PM PDT 24 Mar 28 12:57:31 PM PDT 24 2650712211 ps
T1071 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2099537071 Mar 28 12:57:13 PM PDT 24 Mar 28 12:57:17 PM PDT 24 37033671 ps
T1072 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2400426634 Mar 28 12:57:09 PM PDT 24 Mar 28 12:57:11 PM PDT 24 58992140 ps
T1073 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3049391566 Mar 28 12:57:27 PM PDT 24 Mar 28 12:57:29 PM PDT 24 57620493 ps
T1074 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2839835394 Mar 28 12:57:08 PM PDT 24 Mar 28 12:57:10 PM PDT 24 30990711 ps
T1075 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1400139571 Mar 28 12:57:27 PM PDT 24 Mar 28 12:57:29 PM PDT 24 33713184 ps
T1076 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.755021336 Mar 28 12:57:11 PM PDT 24 Mar 28 12:57:13 PM PDT 24 239614945 ps
T144 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3457271338 Mar 28 12:57:19 PM PDT 24 Mar 28 12:57:33 PM PDT 24 814990242 ps
T1077 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1050574999 Mar 28 12:57:12 PM PDT 24 Mar 28 12:57:15 PM PDT 24 55313777 ps
T1078 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1439519162 Mar 28 12:57:09 PM PDT 24 Mar 28 12:57:11 PM PDT 24 35518637 ps
T1079 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2137231494 Mar 28 12:57:05 PM PDT 24 Mar 28 12:57:06 PM PDT 24 17075746 ps
T1080 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3957708956 Mar 28 12:57:12 PM PDT 24 Mar 28 12:57:29 PM PDT 24 1236621807 ps
T1081 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1923797199 Mar 28 12:57:23 PM PDT 24 Mar 28 12:57:27 PM PDT 24 110459943 ps
T1082 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.303601509 Mar 28 12:57:26 PM PDT 24 Mar 28 12:57:28 PM PDT 24 134298251 ps
T1083 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2305032939 Mar 28 12:57:13 PM PDT 24 Mar 28 12:57:16 PM PDT 24 146113006 ps
T1084 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2734403773 Mar 28 12:57:08 PM PDT 24 Mar 28 12:57:10 PM PDT 24 12045000 ps
T1085 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3759685832 Mar 28 12:57:09 PM PDT 24 Mar 28 12:57:12 PM PDT 24 108116664 ps
T1086 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.824503387 Mar 28 12:57:09 PM PDT 24 Mar 28 12:57:10 PM PDT 24 21850268 ps
T1087 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1563806482 Mar 28 12:57:28 PM PDT 24 Mar 28 12:57:29 PM PDT 24 14924502 ps
T1088 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2445983652 Mar 28 12:57:26 PM PDT 24 Mar 28 12:57:27 PM PDT 24 46591230 ps
T1089 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1000037687 Mar 28 12:57:16 PM PDT 24 Mar 28 12:57:17 PM PDT 24 31538265 ps
T1090 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3674782940 Mar 28 12:57:19 PM PDT 24 Mar 28 12:57:19 PM PDT 24 19466093 ps
T1091 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1406012819 Mar 28 12:57:19 PM PDT 24 Mar 28 12:57:20 PM PDT 24 29031080 ps
T1092 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1484697716 Mar 28 12:57:27 PM PDT 24 Mar 28 12:57:28 PM PDT 24 36034699 ps
T1093 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1480441505 Mar 28 12:57:29 PM PDT 24 Mar 28 12:57:29 PM PDT 24 22482237 ps
T1094 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3624423145 Mar 28 12:57:05 PM PDT 24 Mar 28 12:57:28 PM PDT 24 2943120466 ps
T1095 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1720721353 Mar 28 12:57:15 PM PDT 24 Mar 28 12:57:16 PM PDT 24 82006343 ps
T1096 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.296178924 Mar 28 12:57:22 PM PDT 24 Mar 28 12:57:24 PM PDT 24 18227936 ps

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.2151011162
Short name T6
Test name
Test status
Simulation time 135604283152 ps
CPU time 729.57 seconds
Started Mar 28 03:22:28 PM PDT 24
Finished Mar 28 03:34:39 PM PDT 24
Peak memory 266856 kb
Host smart-17ea605e-863e-441d-86d3-71cb96a37088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151011162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.2151011162
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.1157518176
Short name T12
Test name
Test status
Simulation time 104799625085 ps
CPU time 233.88 seconds
Started Mar 28 03:21:47 PM PDT 24
Finished Mar 28 03:25:42 PM PDT 24
Peak memory 267040 kb
Host smart-baf04d48-2b1a-4764-8d08-8439f667d570
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157518176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.1157518176
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.3297539375
Short name T26
Test name
Test status
Simulation time 150244124882 ps
CPU time 308.72 seconds
Started Mar 28 03:24:03 PM PDT 24
Finished Mar 28 03:29:12 PM PDT 24
Peak memory 267396 kb
Host smart-7500114b-03cb-48c9-8a10-2fb67ac0e29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297539375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.3297539375
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.301888193
Short name T97
Test name
Test status
Simulation time 463330169 ps
CPU time 2.94 seconds
Started Mar 28 12:57:09 PM PDT 24
Finished Mar 28 12:57:13 PM PDT 24
Peak memory 216852 kb
Host smart-378caee3-975f-44e2-88f3-80242c05c033
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301888193 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.301888193
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.4115126650
Short name T33
Test name
Test status
Simulation time 7299096501 ps
CPU time 77.83 seconds
Started Mar 28 03:24:01 PM PDT 24
Finished Mar 28 03:25:19 PM PDT 24
Peak memory 249616 kb
Host smart-ed97ed10-1bb5-46d5-9993-969c11113890
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115126650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.4115126650
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_ram_cfg.1685779382
Short name T53
Test name
Test status
Simulation time 39147056 ps
CPU time 0.76 seconds
Started Mar 28 03:22:06 PM PDT 24
Finished Mar 28 03:22:07 PM PDT 24
Peak memory 216568 kb
Host smart-806fd437-070e-4dcf-b753-2287238ced3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685779382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_ram_cfg.1685779382
Directory /workspace/12.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.1076929878
Short name T114
Test name
Test status
Simulation time 94854925783 ps
CPU time 645.2 seconds
Started Mar 28 03:23:45 PM PDT 24
Finished Mar 28 03:34:30 PM PDT 24
Peak memory 282224 kb
Host smart-9ec440f7-6301-406f-8f8c-8f7c7afb3a00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076929878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.1076929878
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.3280183952
Short name T182
Test name
Test status
Simulation time 70266484523 ps
CPU time 122.26 seconds
Started Mar 28 03:21:32 PM PDT 24
Finished Mar 28 03:23:34 PM PDT 24
Peak memory 266008 kb
Host smart-4db9e65c-771b-4c80-a957-256bd12eb9a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280183952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.3280183952
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.4046732604
Short name T4
Test name
Test status
Simulation time 16550885838 ps
CPU time 57.06 seconds
Started Mar 28 03:21:45 PM PDT 24
Finished Mar 28 03:22:42 PM PDT 24
Peak memory 233168 kb
Host smart-721de48f-2b59-4f4e-a808-4ae3989f4542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046732604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.4046732604
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3262714185
Short name T80
Test name
Test status
Simulation time 552863206 ps
CPU time 14.23 seconds
Started Mar 28 12:57:08 PM PDT 24
Finished Mar 28 12:57:23 PM PDT 24
Peak memory 215496 kb
Host smart-d24ccc6a-8680-4c7b-9803-194bb95ee347
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262714185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.3262714185
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.945426896
Short name T148
Test name
Test status
Simulation time 18464533769 ps
CPU time 216.16 seconds
Started Mar 28 03:22:08 PM PDT 24
Finished Mar 28 03:25:45 PM PDT 24
Peak memory 266980 kb
Host smart-2d7db5ab-69f3-4221-bd6e-e611eab13457
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945426896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stres
s_all.945426896
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.3592568733
Short name T46
Test name
Test status
Simulation time 11286803 ps
CPU time 0.71 seconds
Started Mar 28 03:21:12 PM PDT 24
Finished Mar 28 03:21:13 PM PDT 24
Peak memory 205884 kb
Host smart-035baff9-38c0-436c-b4d9-795783e01efd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592568733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.3
592568733
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.1909746561
Short name T20
Test name
Test status
Simulation time 137725409260 ps
CPU time 531.89 seconds
Started Mar 28 03:24:25 PM PDT 24
Finished Mar 28 03:33:17 PM PDT 24
Peak memory 267088 kb
Host smart-bb5fecef-df37-43a9-a3c7-f7236969f766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909746561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.1909746561
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3279444831
Short name T103
Test name
Test status
Simulation time 30402701 ps
CPU time 2.14 seconds
Started Mar 28 12:57:11 PM PDT 24
Finished Mar 28 12:57:14 PM PDT 24
Peak memory 215424 kb
Host smart-5f017361-4068-4737-88cb-a297472f6c06
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279444831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
3279444831
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2068176737
Short name T92
Test name
Test status
Simulation time 653552309 ps
CPU time 3.33 seconds
Started Mar 28 12:57:09 PM PDT 24
Finished Mar 28 12:57:13 PM PDT 24
Peak memory 215388 kb
Host smart-a893e1bb-7040-4453-879f-68c07872335f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068176737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
2068176737
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.779391055
Short name T18
Test name
Test status
Simulation time 58078403112 ps
CPU time 234.01 seconds
Started Mar 28 03:24:45 PM PDT 24
Finished Mar 28 03:28:39 PM PDT 24
Peak memory 249484 kb
Host smart-ee6b2617-55ed-4412-b748-b4b9f776837e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779391055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stres
s_all.779391055
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.1577911334
Short name T193
Test name
Test status
Simulation time 50337501904 ps
CPU time 354.86 seconds
Started Mar 28 03:21:25 PM PDT 24
Finished Mar 28 03:27:20 PM PDT 24
Peak memory 253420 kb
Host smart-484b4c9c-e0f5-4928-a855-9e02fea02122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577911334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.1577911334
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.542805406
Short name T249
Test name
Test status
Simulation time 5869300264 ps
CPU time 126.49 seconds
Started Mar 28 03:23:19 PM PDT 24
Finished Mar 28 03:25:26 PM PDT 24
Peak memory 262540 kb
Host smart-6ca4a2c6-3358-48bf-b577-923335f8c2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542805406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.542805406
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.2795077198
Short name T60
Test name
Test status
Simulation time 165630446823 ps
CPU time 602.41 seconds
Started Mar 28 03:22:34 PM PDT 24
Finished Mar 28 03:32:37 PM PDT 24
Peak memory 281672 kb
Host smart-a40ed7ad-5b80-4b65-9d36-41e1540986d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795077198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.2795077198
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.983872811
Short name T57
Test name
Test status
Simulation time 36850181 ps
CPU time 0.98 seconds
Started Mar 28 03:21:17 PM PDT 24
Finished Mar 28 03:21:18 PM PDT 24
Peak memory 235616 kb
Host smart-009e82c6-f935-4ad0-8b52-f0c1c343ad98
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983872811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.983872811
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.3932929490
Short name T29
Test name
Test status
Simulation time 155452022159 ps
CPU time 260.02 seconds
Started Mar 28 03:21:17 PM PDT 24
Finished Mar 28 03:25:37 PM PDT 24
Peak memory 241452 kb
Host smart-c4e05ab6-0ffa-47f1-b296-5b59c3e87dc9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932929490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.3932929490
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.3994734105
Short name T134
Test name
Test status
Simulation time 21449705845 ps
CPU time 152.36 seconds
Started Mar 28 03:22:30 PM PDT 24
Finished Mar 28 03:25:02 PM PDT 24
Peak memory 263764 kb
Host smart-4456c16e-e249-4d14-a144-c74bfb306345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994734105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.3994734105
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.2772390734
Short name T235
Test name
Test status
Simulation time 59402567405 ps
CPU time 136.33 seconds
Started Mar 28 03:21:43 PM PDT 24
Finished Mar 28 03:24:00 PM PDT 24
Peak memory 272416 kb
Host smart-4406d0f4-81d7-465e-a22d-a4fa7e1e666e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772390734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.2772390734
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.1499794484
Short name T2
Test name
Test status
Simulation time 20125713671 ps
CPU time 66.13 seconds
Started Mar 28 03:21:15 PM PDT 24
Finished Mar 28 03:22:21 PM PDT 24
Peak memory 251736 kb
Host smart-f91788cd-b38e-4d85-8791-0daa125fcae1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499794484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.1499794484
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.2422446628
Short name T240
Test name
Test status
Simulation time 566576453342 ps
CPU time 599.79 seconds
Started Mar 28 03:21:07 PM PDT 24
Finished Mar 28 03:31:07 PM PDT 24
Peak memory 273964 kb
Host smart-e63342f0-5fa9-4dfa-a763-b5d100834817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422446628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.2422446628
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.1798664826
Short name T230
Test name
Test status
Simulation time 12653845477 ps
CPU time 106.7 seconds
Started Mar 28 03:22:46 PM PDT 24
Finished Mar 28 03:24:33 PM PDT 24
Peak memory 264292 kb
Host smart-13f9ca30-9be4-4d7f-abfc-7073603c0233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798664826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.1798664826
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2475896063
Short name T85
Test name
Test status
Simulation time 166720836 ps
CPU time 3.41 seconds
Started Mar 28 12:57:18 PM PDT 24
Finished Mar 28 12:57:22 PM PDT 24
Peak memory 215536 kb
Host smart-51ba3689-58e7-4b26-b593-d0d616483235
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475896063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.2
475896063
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2511698598
Short name T90
Test name
Test status
Simulation time 2405939360 ps
CPU time 13.6 seconds
Started Mar 28 12:57:20 PM PDT 24
Finished Mar 28 12:57:34 PM PDT 24
Peak memory 215544 kb
Host smart-96061050-58fd-4ce0-a563-a97900cd7990
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511698598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.2511698598
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.3050572582
Short name T113
Test name
Test status
Simulation time 20848563874 ps
CPU time 109.66 seconds
Started Mar 28 03:21:46 PM PDT 24
Finished Mar 28 03:23:36 PM PDT 24
Peak memory 249624 kb
Host smart-ba7dd4f7-8053-4d07-91a7-8c373f24e6b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050572582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.3050572582
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3457271338
Short name T144
Test name
Test status
Simulation time 814990242 ps
CPU time 13.57 seconds
Started Mar 28 12:57:19 PM PDT 24
Finished Mar 28 12:57:33 PM PDT 24
Peak memory 215316 kb
Host smart-232040f5-87fe-4794-9030-57822e9515b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457271338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.3457271338
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.2726486588
Short name T454
Test name
Test status
Simulation time 1160402695 ps
CPU time 10.91 seconds
Started Mar 28 03:22:09 PM PDT 24
Finished Mar 28 03:22:21 PM PDT 24
Peak memory 238972 kb
Host smart-ea85c00e-1dfb-4482-b750-22201b1477b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726486588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.2726486588
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.1825238221
Short name T181
Test name
Test status
Simulation time 25508357258 ps
CPU time 112.67 seconds
Started Mar 28 03:22:33 PM PDT 24
Finished Mar 28 03:24:26 PM PDT 24
Peak memory 253628 kb
Host smart-ec015358-6694-4209-8fb0-c5eb6d8f1c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825238221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.1825238221
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.1438788343
Short name T156
Test name
Test status
Simulation time 153738723243 ps
CPU time 252.63 seconds
Started Mar 28 03:22:48 PM PDT 24
Finished Mar 28 03:27:01 PM PDT 24
Peak memory 251796 kb
Host smart-acc44056-6790-469e-a433-a36c377965f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438788343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.1438788343
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.1001683701
Short name T162
Test name
Test status
Simulation time 5486873570 ps
CPU time 102.23 seconds
Started Mar 28 03:23:29 PM PDT 24
Finished Mar 28 03:25:12 PM PDT 24
Peak memory 262084 kb
Host smart-bc0f4165-4865-4eca-8404-0eec6973f471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001683701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.1001683701
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.3499536200
Short name T250
Test name
Test status
Simulation time 68526748358 ps
CPU time 81.41 seconds
Started Mar 28 03:24:47 PM PDT 24
Finished Mar 28 03:26:08 PM PDT 24
Peak memory 269488 kb
Host smart-29d7412a-d891-4587-82d2-0205d53842b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499536200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.3499536200
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.879778595
Short name T3
Test name
Test status
Simulation time 5583815316 ps
CPU time 15.42 seconds
Started Mar 28 03:22:30 PM PDT 24
Finished Mar 28 03:22:46 PM PDT 24
Peak memory 233212 kb
Host smart-9425f428-1d84-456b-9789-aaee20767f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879778595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap
.879778595
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.1778697376
Short name T74
Test name
Test status
Simulation time 1947232392 ps
CPU time 12.17 seconds
Started Mar 28 03:23:29 PM PDT 24
Finished Mar 28 03:23:41 PM PDT 24
Peak memory 216632 kb
Host smart-087bcdfa-1037-4fad-a760-1bfdff4bcf71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778697376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.1778697376
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2859700283
Short name T147
Test name
Test status
Simulation time 1032267807 ps
CPU time 22.84 seconds
Started Mar 28 12:57:21 PM PDT 24
Finished Mar 28 12:57:44 PM PDT 24
Peak memory 215312 kb
Host smart-8362fb0f-48a7-4456-9bdc-6234ba994772
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859700283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.2859700283
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.51546941
Short name T142
Test name
Test status
Simulation time 1209750796 ps
CPU time 21.27 seconds
Started Mar 28 12:57:13 PM PDT 24
Finished Mar 28 12:57:35 PM PDT 24
Peak memory 219088 kb
Host smart-bee29019-117e-4cd3-904b-53503446cdec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51546941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_t
l_intg_err.51546941
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.229871438
Short name T239
Test name
Test status
Simulation time 228298534034 ps
CPU time 347.63 seconds
Started Mar 28 03:22:13 PM PDT 24
Finished Mar 28 03:28:02 PM PDT 24
Peak memory 257776 kb
Host smart-dd396694-9d4f-4699-86ed-93ce74c86d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229871438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.229871438
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.1592520781
Short name T614
Test name
Test status
Simulation time 293756418 ps
CPU time 8.86 seconds
Started Mar 28 03:22:09 PM PDT 24
Finished Mar 28 03:22:18 PM PDT 24
Peak memory 237048 kb
Host smart-22def93d-c8c0-49e8-83a2-62a8a4907658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592520781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.1592520781
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.2500562975
Short name T959
Test name
Test status
Simulation time 6239847195 ps
CPU time 51.09 seconds
Started Mar 28 03:22:27 PM PDT 24
Finished Mar 28 03:23:18 PM PDT 24
Peak memory 266008 kb
Host smart-ffbc2477-f53b-492f-80e9-202d365e7666
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500562975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.2500562975
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.3043731199
Short name T243
Test name
Test status
Simulation time 81345187892 ps
CPU time 349.68 seconds
Started Mar 28 03:22:33 PM PDT 24
Finished Mar 28 03:28:23 PM PDT 24
Peak memory 268324 kb
Host smart-25740aaf-6e81-4f84-a8ab-deb83c2f554a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043731199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.3043731199
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.1967387525
Short name T161
Test name
Test status
Simulation time 47854025876 ps
CPU time 175.1 seconds
Started Mar 28 03:22:44 PM PDT 24
Finished Mar 28 03:25:39 PM PDT 24
Peak memory 250272 kb
Host smart-7a449928-ce6b-43da-b101-88e1a9510b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967387525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.1967387525
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.3766424607
Short name T255
Test name
Test status
Simulation time 126706803010 ps
CPU time 176.1 seconds
Started Mar 28 03:23:18 PM PDT 24
Finished Mar 28 03:26:14 PM PDT 24
Peak memory 257552 kb
Host smart-a2dc4a95-fabf-48f1-9ac7-5afe129c0815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766424607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.3766424607
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.1147094713
Short name T957
Test name
Test status
Simulation time 24785935391 ps
CPU time 200.59 seconds
Started Mar 28 03:24:26 PM PDT 24
Finished Mar 28 03:27:47 PM PDT 24
Peak memory 285704 kb
Host smart-597d80f9-2726-4a57-8bba-4b4df54da36f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147094713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.1147094713
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.420651685
Short name T70
Test name
Test status
Simulation time 37101883 ps
CPU time 1.26 seconds
Started Mar 28 12:57:13 PM PDT 24
Finished Mar 28 12:57:16 PM PDT 24
Peak memory 206732 kb
Host smart-62416951-18bc-4cdd-a635-2263153fe502
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420651685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_hw_reset.420651685
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3097357090
Short name T94
Test name
Test status
Simulation time 699537066 ps
CPU time 3.98 seconds
Started Mar 28 12:57:10 PM PDT 24
Finished Mar 28 12:57:15 PM PDT 24
Peak memory 215708 kb
Host smart-3b34205f-8631-4ad4-b372-1f01a12c096e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097357090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
3097357090
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2993850565
Short name T1057
Test name
Test status
Simulation time 105094024 ps
CPU time 7.63 seconds
Started Mar 28 12:57:12 PM PDT 24
Finished Mar 28 12:57:21 PM PDT 24
Peak memory 206756 kb
Host smart-de63b030-34d7-46f2-9995-2d5fe45644e1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993850565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.2993850565
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.169740174
Short name T1014
Test name
Test status
Simulation time 3008814917 ps
CPU time 33.1 seconds
Started Mar 28 12:57:12 PM PDT 24
Finished Mar 28 12:57:46 PM PDT 24
Peak memory 207196 kb
Host smart-4c1dcbb8-f033-4a2e-9a66-9f7ab3482041
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169740174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_bit_bash.169740174
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.4127969180
Short name T71
Test name
Test status
Simulation time 113871973 ps
CPU time 0.99 seconds
Started Mar 28 12:57:08 PM PDT 24
Finished Mar 28 12:57:10 PM PDT 24
Peak memory 207012 kb
Host smart-b9ccf3c9-0834-49e4-b8e8-383a39e59ebd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127969180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.4127969180
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2099537071
Short name T1071
Test name
Test status
Simulation time 37033671 ps
CPU time 2.35 seconds
Started Mar 28 12:57:13 PM PDT 24
Finished Mar 28 12:57:17 PM PDT 24
Peak memory 216528 kb
Host smart-a1d315ce-20de-4fdf-b530-f5f32b2a8e42
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099537071 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.2099537071
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1478770481
Short name T1045
Test name
Test status
Simulation time 39405896 ps
CPU time 2.56 seconds
Started Mar 28 12:57:10 PM PDT 24
Finished Mar 28 12:57:14 PM PDT 24
Peak memory 207228 kb
Host smart-7c6753fa-0cae-4759-ab1b-760edb3704b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478770481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.1
478770481
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.4166692512
Short name T1012
Test name
Test status
Simulation time 12736179 ps
CPU time 0.7 seconds
Started Mar 28 12:57:08 PM PDT 24
Finished Mar 28 12:57:10 PM PDT 24
Peak memory 203476 kb
Host smart-a85bdafe-5621-4b18-a0c3-58ec80328dab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166692512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.4
166692512
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.4105680487
Short name T1033
Test name
Test status
Simulation time 33613249 ps
CPU time 1.36 seconds
Started Mar 28 12:57:09 PM PDT 24
Finished Mar 28 12:57:11 PM PDT 24
Peak memory 215404 kb
Host smart-19a7cae5-a43f-4439-9cb1-6b5492a5beeb
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105680487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.4105680487
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3338397125
Short name T1022
Test name
Test status
Simulation time 21179658 ps
CPU time 0.65 seconds
Started Mar 28 12:57:10 PM PDT 24
Finished Mar 28 12:57:12 PM PDT 24
Peak memory 203460 kb
Host smart-1a5d1ef3-d095-4370-90d1-180203ba9ed5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338397125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.3338397125
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1106335478
Short name T983
Test name
Test status
Simulation time 222725344 ps
CPU time 1.74 seconds
Started Mar 28 12:57:11 PM PDT 24
Finished Mar 28 12:57:14 PM PDT 24
Peak memory 207192 kb
Host smart-9293b794-5bff-4e2d-b38a-da77584a2a8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106335478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.1106335478
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2106975638
Short name T1060
Test name
Test status
Simulation time 68950154 ps
CPU time 2.04 seconds
Started Mar 28 12:57:09 PM PDT 24
Finished Mar 28 12:57:12 PM PDT 24
Peak memory 215436 kb
Host smart-629b5f42-05aa-4e54-ba61-d5366e705807
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106975638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.2
106975638
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3980922313
Short name T987
Test name
Test status
Simulation time 613592357 ps
CPU time 15.28 seconds
Started Mar 28 12:57:13 PM PDT 24
Finished Mar 28 12:57:30 PM PDT 24
Peak memory 207160 kb
Host smart-4947187e-2fb7-4e87-b103-edba20feb9d4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980922313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.3980922313
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1830146669
Short name T994
Test name
Test status
Simulation time 3555476354 ps
CPU time 35.81 seconds
Started Mar 28 12:57:19 PM PDT 24
Finished Mar 28 12:57:54 PM PDT 24
Peak memory 207440 kb
Host smart-9e1a5cc9-9a28-43a0-9a72-0fcc480e72eb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830146669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.1830146669
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1824482664
Short name T84
Test name
Test status
Simulation time 341600200 ps
CPU time 2.53 seconds
Started Mar 28 12:57:14 PM PDT 24
Finished Mar 28 12:57:17 PM PDT 24
Peak memory 216620 kb
Host smart-3582bab5-3d48-488a-9142-85e5f5ea4b92
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824482664 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.1824482664
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.4058930157
Short name T1023
Test name
Test status
Simulation time 19346879 ps
CPU time 1.28 seconds
Started Mar 28 12:57:13 PM PDT 24
Finished Mar 28 12:57:16 PM PDT 24
Peak memory 207032 kb
Host smart-dd0dd127-8fa7-4cf5-a52f-c3a05a191720
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058930157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.4
058930157
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1720721353
Short name T1095
Test name
Test status
Simulation time 82006343 ps
CPU time 0.7 seconds
Started Mar 28 12:57:15 PM PDT 24
Finished Mar 28 12:57:16 PM PDT 24
Peak memory 203604 kb
Host smart-2df7d6d3-9c7c-43de-809a-e74b66e20c1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720721353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.1
720721353
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.4071392976
Short name T1009
Test name
Test status
Simulation time 58847920 ps
CPU time 2.28 seconds
Started Mar 28 12:57:18 PM PDT 24
Finished Mar 28 12:57:21 PM PDT 24
Peak memory 215392 kb
Host smart-eb099947-b4f6-4691-9f7d-33bc0a9b261a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071392976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.4071392976
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.511391294
Short name T1050
Test name
Test status
Simulation time 11426234 ps
CPU time 0.67 seconds
Started Mar 28 12:57:13 PM PDT 24
Finished Mar 28 12:57:15 PM PDT 24
Peak memory 203444 kb
Host smart-4db042c6-348b-4f88-a0fe-2b13c59b5673
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511391294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem
_walk.511391294
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1010987916
Short name T122
Test name
Test status
Simulation time 388291596 ps
CPU time 4.49 seconds
Started Mar 28 12:57:11 PM PDT 24
Finished Mar 28 12:57:16 PM PDT 24
Peak memory 215460 kb
Host smart-97cb75d0-7414-4934-9369-a5b384fdd9bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010987916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.1010987916
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1409518927
Short name T91
Test name
Test status
Simulation time 214172124 ps
CPU time 3.36 seconds
Started Mar 28 12:57:05 PM PDT 24
Finished Mar 28 12:57:09 PM PDT 24
Peak memory 216520 kb
Host smart-919468fc-3b6b-4c7e-a773-0384635df103
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409518927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.1
409518927
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2867234715
Short name T146
Test name
Test status
Simulation time 298221572 ps
CPU time 7.55 seconds
Started Mar 28 12:57:11 PM PDT 24
Finished Mar 28 12:57:20 PM PDT 24
Peak memory 215432 kb
Host smart-a1306ef3-bb27-46cb-bcc1-b53c28515bce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867234715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.2867234715
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1597603199
Short name T1058
Test name
Test status
Simulation time 67456184 ps
CPU time 1.19 seconds
Started Mar 28 12:57:08 PM PDT 24
Finished Mar 28 12:57:10 PM PDT 24
Peak memory 207152 kb
Host smart-6f4dee70-3a2b-48e1-aa9e-b681a57cd29c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597603199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
1597603199
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2839835394
Short name T1074
Test name
Test status
Simulation time 30990711 ps
CPU time 0.74 seconds
Started Mar 28 12:57:08 PM PDT 24
Finished Mar 28 12:57:10 PM PDT 24
Peak memory 203444 kb
Host smart-7482d100-f775-4894-894b-f29c9046f81f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839835394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
2839835394
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1913262367
Short name T1052
Test name
Test status
Simulation time 1231357119 ps
CPU time 3.19 seconds
Started Mar 28 12:57:05 PM PDT 24
Finished Mar 28 12:57:09 PM PDT 24
Peak memory 215476 kb
Host smart-78ff1ba0-20c4-4ad3-a180-92890f06890e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913262367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.1913262367
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1045542212
Short name T83
Test name
Test status
Simulation time 314833135 ps
CPU time 7.67 seconds
Started Mar 28 12:57:10 PM PDT 24
Finished Mar 28 12:57:19 PM PDT 24
Peak memory 215584 kb
Host smart-048f70a6-ef56-4cf5-bbe9-3d891b24653f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045542212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.1045542212
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3177614231
Short name T1068
Test name
Test status
Simulation time 284612165 ps
CPU time 1.56 seconds
Started Mar 28 12:57:08 PM PDT 24
Finished Mar 28 12:57:11 PM PDT 24
Peak memory 215448 kb
Host smart-149bab14-03bf-4fe7-ac48-2c11fb942f41
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177614231 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.3177614231
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.4281591304
Short name T997
Test name
Test status
Simulation time 44684083 ps
CPU time 0.73 seconds
Started Mar 28 12:57:10 PM PDT 24
Finished Mar 28 12:57:11 PM PDT 24
Peak memory 203464 kb
Host smart-3e69076b-76af-4f97-8932-840a8b1a1f91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281591304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
4281591304
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3627656109
Short name T1061
Test name
Test status
Simulation time 28106632 ps
CPU time 1.9 seconds
Started Mar 28 12:57:09 PM PDT 24
Finished Mar 28 12:57:12 PM PDT 24
Peak memory 215284 kb
Host smart-df46fce9-65db-4440-90d4-d2f051314075
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627656109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.3627656109
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3037047344
Short name T145
Test name
Test status
Simulation time 724695984 ps
CPU time 8.8 seconds
Started Mar 28 12:57:10 PM PDT 24
Finished Mar 28 12:57:19 PM PDT 24
Peak memory 215500 kb
Host smart-7831685e-f7e1-4604-b79c-1860198801b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037047344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.3037047344
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3691264014
Short name T1040
Test name
Test status
Simulation time 153279048 ps
CPU time 1.74 seconds
Started Mar 28 12:57:18 PM PDT 24
Finished Mar 28 12:57:20 PM PDT 24
Peak memory 215480 kb
Host smart-433a911a-7edf-4ad2-8ce2-2a32812eff18
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691264014 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3691264014
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2508815282
Short name T1046
Test name
Test status
Simulation time 61234804 ps
CPU time 1.97 seconds
Started Mar 28 12:57:08 PM PDT 24
Finished Mar 28 12:57:12 PM PDT 24
Peak memory 215336 kb
Host smart-60949f78-c23e-487a-b2b6-ebfc7bed1b0d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508815282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
2508815282
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.116738574
Short name T1048
Test name
Test status
Simulation time 16944966 ps
CPU time 0.75 seconds
Started Mar 28 12:57:11 PM PDT 24
Finished Mar 28 12:57:13 PM PDT 24
Peak memory 203588 kb
Host smart-dd4b0862-46e8-4f42-8069-e362b6db138f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116738574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.116738574
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2339909511
Short name T999
Test name
Test status
Simulation time 230493084 ps
CPU time 3.09 seconds
Started Mar 28 12:57:09 PM PDT 24
Finished Mar 28 12:57:13 PM PDT 24
Peak memory 215444 kb
Host smart-a357335e-9b59-4a1a-adbb-7737101e340b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339909511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.2339909511
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3653146695
Short name T1013
Test name
Test status
Simulation time 79731663 ps
CPU time 1.51 seconds
Started Mar 28 12:57:11 PM PDT 24
Finished Mar 28 12:57:13 PM PDT 24
Peak memory 206840 kb
Host smart-26a19231-2361-49c2-a3df-caf4b13d7cdd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653146695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
3653146695
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2018132445
Short name T1053
Test name
Test status
Simulation time 191674763 ps
CPU time 6.8 seconds
Started Mar 28 12:57:11 PM PDT 24
Finished Mar 28 12:57:19 PM PDT 24
Peak memory 215816 kb
Host smart-fa511647-317e-4844-98e0-5fb2bc55fe4d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018132445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.2018132445
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.3340104966
Short name T96
Test name
Test status
Simulation time 447652549 ps
CPU time 1.7 seconds
Started Mar 28 12:57:18 PM PDT 24
Finished Mar 28 12:57:20 PM PDT 24
Peak memory 215448 kb
Host smart-41a0b61e-7fce-4427-be51-a0d2791aa62e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340104966 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.3340104966
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3605019497
Short name T107
Test name
Test status
Simulation time 85052864 ps
CPU time 2.33 seconds
Started Mar 28 12:57:11 PM PDT 24
Finished Mar 28 12:57:14 PM PDT 24
Peak memory 215428 kb
Host smart-a25a3d7b-e234-4e4b-b0dc-1b56caf2a2bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605019497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
3605019497
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2732595596
Short name T1031
Test name
Test status
Simulation time 16443309 ps
CPU time 0.71 seconds
Started Mar 28 12:57:11 PM PDT 24
Finished Mar 28 12:57:13 PM PDT 24
Peak memory 203576 kb
Host smart-e4f4f015-80a0-4f02-946b-0ec55b9aede3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732595596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
2732595596
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1460019482
Short name T991
Test name
Test status
Simulation time 43066633 ps
CPU time 2.87 seconds
Started Mar 28 12:57:11 PM PDT 24
Finished Mar 28 12:57:15 PM PDT 24
Peak memory 215408 kb
Host smart-cba191b6-3640-4947-bfb9-2233e9cfd417
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460019482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.1460019482
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.659075748
Short name T1062
Test name
Test status
Simulation time 280721474 ps
CPU time 4.26 seconds
Started Mar 28 12:57:10 PM PDT 24
Finished Mar 28 12:57:15 PM PDT 24
Peak memory 215668 kb
Host smart-e887fb2e-5edb-49d7-9171-6b77b1b2f08e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659075748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.659075748
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2290608300
Short name T1008
Test name
Test status
Simulation time 262628358 ps
CPU time 12.3 seconds
Started Mar 28 12:57:10 PM PDT 24
Finished Mar 28 12:57:23 PM PDT 24
Peak memory 215560 kb
Host smart-1c472c2f-d690-4ad2-a838-120ad9fa6d06
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290608300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.2290608300
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2737756110
Short name T1034
Test name
Test status
Simulation time 34243371 ps
CPU time 1.72 seconds
Started Mar 28 12:57:21 PM PDT 24
Finished Mar 28 12:57:22 PM PDT 24
Peak memory 215524 kb
Host smart-87933160-533f-4998-8f04-64c032a81a6f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737756110 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.2737756110
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3746725367
Short name T123
Test name
Test status
Simulation time 124577401 ps
CPU time 1.83 seconds
Started Mar 28 12:57:14 PM PDT 24
Finished Mar 28 12:57:16 PM PDT 24
Peak memory 207372 kb
Host smart-3a60f1c1-23aa-4d60-af45-52a0cd0d7de4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746725367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
3746725367
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.693309639
Short name T1047
Test name
Test status
Simulation time 26805760 ps
CPU time 0.7 seconds
Started Mar 28 12:57:10 PM PDT 24
Finished Mar 28 12:57:11 PM PDT 24
Peak memory 203584 kb
Host smart-4b640628-1f87-4cb7-9548-6022041685f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693309639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.693309639
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.344918295
Short name T1035
Test name
Test status
Simulation time 233712536 ps
CPU time 1.67 seconds
Started Mar 28 12:57:15 PM PDT 24
Finished Mar 28 12:57:17 PM PDT 24
Peak memory 215448 kb
Host smart-6766c9c2-b272-423f-93eb-643fefb8dd5b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344918295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.s
pi_device_same_csr_outstanding.344918295
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2989196545
Short name T82
Test name
Test status
Simulation time 144296838 ps
CPU time 3.69 seconds
Started Mar 28 12:57:08 PM PDT 24
Finished Mar 28 12:57:13 PM PDT 24
Peak memory 215576 kb
Host smart-edb0ffdf-4f4a-4551-896b-4505264f9ae4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989196545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
2989196545
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3957708956
Short name T1080
Test name
Test status
Simulation time 1236621807 ps
CPU time 15.06 seconds
Started Mar 28 12:57:12 PM PDT 24
Finished Mar 28 12:57:29 PM PDT 24
Peak memory 215736 kb
Host smart-e1f159d3-1cc2-401d-9f1b-ad018937bd26
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957708956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.3957708956
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1078502837
Short name T48
Test name
Test status
Simulation time 649283212 ps
CPU time 3.73 seconds
Started Mar 28 12:57:27 PM PDT 24
Finished Mar 28 12:57:31 PM PDT 24
Peak memory 217208 kb
Host smart-0e6021b0-75f3-4a92-a2e8-56fe23ca4052
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078502837 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.1078502837
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2185095679
Short name T110
Test name
Test status
Simulation time 207623338 ps
CPU time 2.52 seconds
Started Mar 28 12:57:24 PM PDT 24
Finished Mar 28 12:57:26 PM PDT 24
Peak memory 215444 kb
Host smart-326ff81b-6ef6-4da2-884d-a00d23d87a68
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185095679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
2185095679
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3674782940
Short name T1090
Test name
Test status
Simulation time 19466093 ps
CPU time 0.74 seconds
Started Mar 28 12:57:19 PM PDT 24
Finished Mar 28 12:57:19 PM PDT 24
Peak memory 203608 kb
Host smart-a93c242e-f4f5-4d17-a4c4-9470435e8677
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674782940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
3674782940
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.85558410
Short name T985
Test name
Test status
Simulation time 188170287 ps
CPU time 1.65 seconds
Started Mar 28 12:57:19 PM PDT 24
Finished Mar 28 12:57:21 PM PDT 24
Peak memory 207248 kb
Host smart-d85bb075-f8ab-4460-9bc9-813c8e1e5d81
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85558410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sp
i_device_same_csr_outstanding.85558410
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1923797199
Short name T1081
Test name
Test status
Simulation time 110459943 ps
CPU time 4.05 seconds
Started Mar 28 12:57:23 PM PDT 24
Finished Mar 28 12:57:27 PM PDT 24
Peak memory 216616 kb
Host smart-fb0dbee8-bdbc-4a5f-9aeb-d81e9cb99ab0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923797199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
1923797199
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1733050794
Short name T1016
Test name
Test status
Simulation time 25907486 ps
CPU time 1.82 seconds
Started Mar 28 12:57:42 PM PDT 24
Finished Mar 28 12:57:44 PM PDT 24
Peak memory 215548 kb
Host smart-bd775809-f803-403b-bc1b-b1def468ca0c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733050794 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.1733050794
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1752215410
Short name T1039
Test name
Test status
Simulation time 213911928 ps
CPU time 1.78 seconds
Started Mar 28 12:57:18 PM PDT 24
Finished Mar 28 12:57:20 PM PDT 24
Peak memory 215424 kb
Host smart-3ba00bbc-4284-4d89-ba3b-5a6986aec703
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752215410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
1752215410
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3955638373
Short name T1025
Test name
Test status
Simulation time 17322117 ps
CPU time 0.77 seconds
Started Mar 28 12:57:17 PM PDT 24
Finished Mar 28 12:57:18 PM PDT 24
Peak memory 203588 kb
Host smart-fec3bd42-935e-4f03-9a7d-1e13ab928209
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955638373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
3955638373
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2160567026
Short name T1010
Test name
Test status
Simulation time 64297859 ps
CPU time 3.78 seconds
Started Mar 28 12:57:29 PM PDT 24
Finished Mar 28 12:57:33 PM PDT 24
Peak memory 215416 kb
Host smart-3c384fda-3965-4a2d-8db9-7a8a140a58cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160567026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.2160567026
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3741094718
Short name T89
Test name
Test status
Simulation time 129992261 ps
CPU time 2.13 seconds
Started Mar 28 12:57:20 PM PDT 24
Finished Mar 28 12:57:22 PM PDT 24
Peak memory 215512 kb
Host smart-0e100f88-d6ac-4f49-abe2-8f842b1821a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741094718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
3741094718
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1151792706
Short name T125
Test name
Test status
Simulation time 1470377667 ps
CPU time 9.3 seconds
Started Mar 28 12:57:42 PM PDT 24
Finished Mar 28 12:57:52 PM PDT 24
Peak memory 215824 kb
Host smart-9dcc2a04-9520-43a0-b66a-ab9d7b55c7ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151792706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.1151792706
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.209280647
Short name T1006
Test name
Test status
Simulation time 42722057 ps
CPU time 2.85 seconds
Started Mar 28 12:57:27 PM PDT 24
Finished Mar 28 12:57:30 PM PDT 24
Peak memory 216976 kb
Host smart-9ee001a9-0c2a-488c-83b5-3664ac39677c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209280647 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.209280647
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3256440890
Short name T106
Test name
Test status
Simulation time 20587162 ps
CPU time 1.35 seconds
Started Mar 28 12:57:19 PM PDT 24
Finished Mar 28 12:57:21 PM PDT 24
Peak memory 215340 kb
Host smart-1a670757-ed27-46b8-87b0-fde770024ffa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256440890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
3256440890
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1210923878
Short name T992
Test name
Test status
Simulation time 17925614 ps
CPU time 0.7 seconds
Started Mar 28 12:57:22 PM PDT 24
Finished Mar 28 12:57:24 PM PDT 24
Peak memory 203468 kb
Host smart-ab177069-22b4-4b1a-8414-2de3d034cb24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210923878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
1210923878
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2576954427
Short name T1027
Test name
Test status
Simulation time 372626355 ps
CPU time 3.7 seconds
Started Mar 28 12:57:28 PM PDT 24
Finished Mar 28 12:57:31 PM PDT 24
Peak memory 215472 kb
Host smart-41f86726-f0d2-494f-b0b2-018c88899346
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576954427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.2576954427
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.862594640
Short name T1041
Test name
Test status
Simulation time 457537427 ps
CPU time 3.76 seconds
Started Mar 28 12:57:27 PM PDT 24
Finished Mar 28 12:57:31 PM PDT 24
Peak memory 215312 kb
Host smart-f29aab94-6e0e-4c93-aea0-87bf321bc8b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862594640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.862594640
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.4243087336
Short name T998
Test name
Test status
Simulation time 677822381 ps
CPU time 3.72 seconds
Started Mar 28 12:57:29 PM PDT 24
Finished Mar 28 12:57:33 PM PDT 24
Peak memory 217328 kb
Host smart-721e4957-bd90-4805-86ee-80da09686cba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243087336 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.4243087336
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3176968333
Short name T108
Test name
Test status
Simulation time 47046509 ps
CPU time 1.57 seconds
Started Mar 28 12:57:22 PM PDT 24
Finished Mar 28 12:57:24 PM PDT 24
Peak memory 214840 kb
Host smart-bc45745a-49f7-4a90-8c7a-28ffa23ee5fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176968333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
3176968333
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1514066080
Short name T1051
Test name
Test status
Simulation time 38568018 ps
CPU time 0.71 seconds
Started Mar 28 12:57:40 PM PDT 24
Finished Mar 28 12:57:40 PM PDT 24
Peak memory 203600 kb
Host smart-b9657020-7c12-47a2-ab79-8e4d7e0c5a97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514066080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
1514066080
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3049391566
Short name T1073
Test name
Test status
Simulation time 57620493 ps
CPU time 1.74 seconds
Started Mar 28 12:57:27 PM PDT 24
Finished Mar 28 12:57:29 PM PDT 24
Peak memory 215444 kb
Host smart-907ec52c-30f2-474c-a7e6-378dab442bdb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049391566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.3049391566
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2705073463
Short name T86
Test name
Test status
Simulation time 203691649 ps
CPU time 3.6 seconds
Started Mar 28 12:57:28 PM PDT 24
Finished Mar 28 12:57:31 PM PDT 24
Peak memory 215584 kb
Host smart-1d850046-2c6b-4f9f-9e76-ab4e040cab26
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705073463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
2705073463
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3808551904
Short name T95
Test name
Test status
Simulation time 40744747 ps
CPU time 2.64 seconds
Started Mar 28 12:57:24 PM PDT 24
Finished Mar 28 12:57:27 PM PDT 24
Peak memory 217084 kb
Host smart-6d5d64e1-5144-481c-ab6f-370fce8aba2e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808551904 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.3808551904
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1400139571
Short name T1075
Test name
Test status
Simulation time 33713184 ps
CPU time 2.14 seconds
Started Mar 28 12:57:27 PM PDT 24
Finished Mar 28 12:57:29 PM PDT 24
Peak memory 207184 kb
Host smart-610bef31-2d28-4c0d-8358-e215e94dbd27
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400139571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
1400139571
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.3922411885
Short name T1049
Test name
Test status
Simulation time 52466538 ps
CPU time 0.76 seconds
Started Mar 28 12:57:40 PM PDT 24
Finished Mar 28 12:57:41 PM PDT 24
Peak memory 203608 kb
Host smart-57f594b5-783c-41bb-aef1-e48a7e0e32ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922411885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
3922411885
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.531437933
Short name T996
Test name
Test status
Simulation time 194982660 ps
CPU time 3.38 seconds
Started Mar 28 12:57:27 PM PDT 24
Finished Mar 28 12:57:31 PM PDT 24
Peak memory 215476 kb
Host smart-a88e19ae-5a3f-4be6-9a2b-e2a15d0d0631
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531437933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.s
pi_device_same_csr_outstanding.531437933
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1699594776
Short name T93
Test name
Test status
Simulation time 485800202 ps
CPU time 5.25 seconds
Started Mar 28 12:57:21 PM PDT 24
Finished Mar 28 12:57:27 PM PDT 24
Peak memory 215436 kb
Host smart-c0b057cc-d8fd-43cc-89b5-c5872790c096
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699594776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
1699594776
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.933302891
Short name T139
Test name
Test status
Simulation time 782428211 ps
CPU time 12.25 seconds
Started Mar 28 12:57:27 PM PDT 24
Finished Mar 28 12:57:39 PM PDT 24
Peak memory 215564 kb
Host smart-e13f7480-fda4-434f-a7f2-d255f8ab5520
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933302891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device
_tl_intg_err.933302891
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3722479582
Short name T100
Test name
Test status
Simulation time 836526994 ps
CPU time 14.46 seconds
Started Mar 28 12:57:16 PM PDT 24
Finished Mar 28 12:57:31 PM PDT 24
Peak memory 215260 kb
Host smart-802e9d91-f051-4f8c-916a-67ffba60d90b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722479582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.3722479582
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1844050430
Short name T105
Test name
Test status
Simulation time 5824035621 ps
CPU time 24.21 seconds
Started Mar 28 12:57:07 PM PDT 24
Finished Mar 28 12:57:32 PM PDT 24
Peak memory 207300 kb
Host smart-e6c3a4cb-274c-4e38-a554-9f9e5dc55427
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844050430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.1844050430
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1000037687
Short name T1089
Test name
Test status
Simulation time 31538265 ps
CPU time 0.95 seconds
Started Mar 28 12:57:16 PM PDT 24
Finished Mar 28 12:57:17 PM PDT 24
Peak memory 206548 kb
Host smart-380fe905-af27-4873-ad3f-4adf77505514
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000037687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.1000037687
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1789426876
Short name T1005
Test name
Test status
Simulation time 24230918 ps
CPU time 1.57 seconds
Started Mar 28 12:57:10 PM PDT 24
Finished Mar 28 12:57:13 PM PDT 24
Peak memory 215576 kb
Host smart-26e5f4a1-cb3a-4f06-801f-bc5746552331
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789426876 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.1789426876
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.495505123
Short name T101
Test name
Test status
Simulation time 30921731 ps
CPU time 1.83 seconds
Started Mar 28 12:57:15 PM PDT 24
Finished Mar 28 12:57:17 PM PDT 24
Peak memory 215256 kb
Host smart-bab6ae0c-0488-4e78-96d8-d326f3025f87
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495505123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.495505123
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1439519162
Short name T1078
Test name
Test status
Simulation time 35518637 ps
CPU time 0.76 seconds
Started Mar 28 12:57:09 PM PDT 24
Finished Mar 28 12:57:11 PM PDT 24
Peak memory 203460 kb
Host smart-fcde2b86-0c2e-4ad4-aad4-a41d5b5d69bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439519162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.1
439519162
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2406905862
Short name T111
Test name
Test status
Simulation time 159607143 ps
CPU time 1.78 seconds
Started Mar 28 12:57:09 PM PDT 24
Finished Mar 28 12:57:12 PM PDT 24
Peak memory 215352 kb
Host smart-a8b3c2a2-c83b-4262-81d3-59d867189e1c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406905862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.2406905862
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3000973910
Short name T1015
Test name
Test status
Simulation time 13710676 ps
CPU time 0.68 seconds
Started Mar 28 12:57:14 PM PDT 24
Finished Mar 28 12:57:15 PM PDT 24
Peak memory 203324 kb
Host smart-1c562022-260f-46ee-9225-ee6d82f5a5ef
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000973910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.3000973910
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3868276349
Short name T1054
Test name
Test status
Simulation time 184208639 ps
CPU time 2.69 seconds
Started Mar 28 12:57:16 PM PDT 24
Finished Mar 28 12:57:19 PM PDT 24
Peak memory 215296 kb
Host smart-f35c9e2c-2a7d-4ef1-a1de-279a6c03623b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868276349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.3868276349
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3500936652
Short name T1056
Test name
Test status
Simulation time 35989315 ps
CPU time 1.39 seconds
Started Mar 28 12:57:14 PM PDT 24
Finished Mar 28 12:57:16 PM PDT 24
Peak memory 207048 kb
Host smart-33ae6dc4-338f-43b1-8249-2efccbfca23e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500936652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.3
500936652
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.174482897
Short name T141
Test name
Test status
Simulation time 207909363 ps
CPU time 6.96 seconds
Started Mar 28 12:57:13 PM PDT 24
Finished Mar 28 12:57:21 PM PDT 24
Peak memory 215348 kb
Host smart-26fab325-bca0-4c7f-98ca-396ee5c9e80d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174482897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_
tl_intg_err.174482897
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1263693568
Short name T978
Test name
Test status
Simulation time 45651201 ps
CPU time 0.73 seconds
Started Mar 28 12:57:22 PM PDT 24
Finished Mar 28 12:57:23 PM PDT 24
Peak memory 203172 kb
Host smart-29ed53a0-0bb9-4ee5-8398-92f56f76f55c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263693568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
1263693568
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.303601509
Short name T1082
Test name
Test status
Simulation time 134298251 ps
CPU time 0.7 seconds
Started Mar 28 12:57:26 PM PDT 24
Finished Mar 28 12:57:28 PM PDT 24
Peak memory 203572 kb
Host smart-dfac5cdf-6c70-418c-b1dc-44c2b4843438
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303601509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.303601509
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1453555794
Short name T1029
Test name
Test status
Simulation time 28869353 ps
CPU time 0.68 seconds
Started Mar 28 12:57:22 PM PDT 24
Finished Mar 28 12:57:23 PM PDT 24
Peak memory 203608 kb
Host smart-b924d7c9-03fb-4d52-926a-2179365bf657
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453555794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
1453555794
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1055319399
Short name T990
Test name
Test status
Simulation time 57842886 ps
CPU time 0.78 seconds
Started Mar 28 12:57:28 PM PDT 24
Finished Mar 28 12:57:29 PM PDT 24
Peak memory 203548 kb
Host smart-88dbb4c6-8732-43d1-ba1a-7140d45e81b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055319399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
1055319399
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.296178924
Short name T1096
Test name
Test status
Simulation time 18227936 ps
CPU time 0.75 seconds
Started Mar 28 12:57:22 PM PDT 24
Finished Mar 28 12:57:24 PM PDT 24
Peak memory 203588 kb
Host smart-0adb7ab7-9662-4819-948c-76f991ca1a4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296178924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.296178924
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3854993452
Short name T1000
Test name
Test status
Simulation time 58431596 ps
CPU time 0.69 seconds
Started Mar 28 12:57:21 PM PDT 24
Finished Mar 28 12:57:22 PM PDT 24
Peak memory 203568 kb
Host smart-58d1466b-094b-46d4-81e8-11fbe016ada1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854993452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
3854993452
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1174982546
Short name T1070
Test name
Test status
Simulation time 244028220 ps
CPU time 0.72 seconds
Started Mar 28 12:57:19 PM PDT 24
Finished Mar 28 12:57:21 PM PDT 24
Peak memory 203560 kb
Host smart-567cd238-d617-48ec-b821-2971b9e4a833
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174982546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
1174982546
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2203634963
Short name T977
Test name
Test status
Simulation time 56981316 ps
CPU time 0.72 seconds
Started Mar 28 12:57:25 PM PDT 24
Finished Mar 28 12:57:26 PM PDT 24
Peak memory 203596 kb
Host smart-1dabef36-5491-42d5-ae8c-58b310eea77f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203634963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
2203634963
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2046053987
Short name T989
Test name
Test status
Simulation time 16070853 ps
CPU time 0.7 seconds
Started Mar 28 12:57:22 PM PDT 24
Finished Mar 28 12:57:22 PM PDT 24
Peak memory 203608 kb
Host smart-95d2e6a7-233b-47c8-9707-84cd18d3016e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046053987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
2046053987
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.172827310
Short name T1004
Test name
Test status
Simulation time 47947146 ps
CPU time 0.77 seconds
Started Mar 28 12:57:27 PM PDT 24
Finished Mar 28 12:57:28 PM PDT 24
Peak memory 203668 kb
Host smart-77ea8bce-25d7-4297-8a5c-f3bdeb560baf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172827310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.172827310
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3624423145
Short name T1094
Test name
Test status
Simulation time 2943120466 ps
CPU time 21.96 seconds
Started Mar 28 12:57:05 PM PDT 24
Finished Mar 28 12:57:28 PM PDT 24
Peak memory 207164 kb
Host smart-906c90e0-1d5f-48e7-bf8d-4dc39bb2932a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624423145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.3624423145
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1311810981
Short name T1069
Test name
Test status
Simulation time 3674774901 ps
CPU time 38.1 seconds
Started Mar 28 12:57:08 PM PDT 24
Finished Mar 28 12:57:48 PM PDT 24
Peak memory 207292 kb
Host smart-9251723e-f20b-419c-9b6b-ed979b81dd09
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311810981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.1311810981
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.472164480
Short name T72
Test name
Test status
Simulation time 24350953 ps
CPU time 1.36 seconds
Started Mar 28 12:57:07 PM PDT 24
Finished Mar 28 12:57:09 PM PDT 24
Peak memory 207052 kb
Host smart-da8f47c3-e11c-4bc5-bf21-26781a998ae4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472164480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_hw_reset.472164480
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3546418338
Short name T50
Test name
Test status
Simulation time 972728898 ps
CPU time 3.48 seconds
Started Mar 28 12:57:06 PM PDT 24
Finished Mar 28 12:57:11 PM PDT 24
Peak memory 217024 kb
Host smart-7ce39e15-ee69-4b58-b5ea-a2ce22e35319
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546418338 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.3546418338
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1517002081
Short name T1024
Test name
Test status
Simulation time 255529341 ps
CPU time 2.27 seconds
Started Mar 28 12:57:09 PM PDT 24
Finished Mar 28 12:57:12 PM PDT 24
Peak memory 207176 kb
Host smart-f622a130-0cdb-4abf-a6b9-27742a17cea3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517002081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.1
517002081
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.824503387
Short name T1086
Test name
Test status
Simulation time 21850268 ps
CPU time 0.71 seconds
Started Mar 28 12:57:09 PM PDT 24
Finished Mar 28 12:57:10 PM PDT 24
Peak memory 203528 kb
Host smart-5ec3d010-a346-46c4-b888-51d0df661196
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824503387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.824503387
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.962086607
Short name T1043
Test name
Test status
Simulation time 74626040 ps
CPU time 1.29 seconds
Started Mar 28 12:57:09 PM PDT 24
Finished Mar 28 12:57:12 PM PDT 24
Peak memory 215384 kb
Host smart-a817e594-6efc-4621-8f3b-d64e6289dbb7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962086607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_
device_mem_partial_access.962086607
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2137231494
Short name T1079
Test name
Test status
Simulation time 17075746 ps
CPU time 0.72 seconds
Started Mar 28 12:57:05 PM PDT 24
Finished Mar 28 12:57:06 PM PDT 24
Peak memory 203448 kb
Host smart-08432bc6-4b28-4cf6-b860-420672686ea7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137231494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.2137231494
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2740980016
Short name T1001
Test name
Test status
Simulation time 26788761 ps
CPU time 1.7 seconds
Started Mar 28 12:57:08 PM PDT 24
Finished Mar 28 12:57:11 PM PDT 24
Peak memory 215440 kb
Host smart-64dfe9bf-6ea9-4149-8ff4-4c7ec8a45171
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740980016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.2740980016
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2442384341
Short name T1026
Test name
Test status
Simulation time 125430584 ps
CPU time 3.24 seconds
Started Mar 28 12:57:09 PM PDT 24
Finished Mar 28 12:57:13 PM PDT 24
Peak memory 215508 kb
Host smart-9c007b8b-29ae-41e4-b0c9-fa1addb8a630
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442384341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.2
442384341
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.762573073
Short name T138
Test name
Test status
Simulation time 802989756 ps
CPU time 11.55 seconds
Started Mar 28 12:57:09 PM PDT 24
Finished Mar 28 12:57:21 PM PDT 24
Peak memory 215284 kb
Host smart-414298d1-8ac9-4edc-a92d-4a31ce0d15f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762573073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_
tl_intg_err.762573073
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1563806482
Short name T1087
Test name
Test status
Simulation time 14924502 ps
CPU time 0.73 seconds
Started Mar 28 12:57:28 PM PDT 24
Finished Mar 28 12:57:29 PM PDT 24
Peak memory 203616 kb
Host smart-ac359ddf-162b-4f9c-8ac7-ef9ab98786e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563806482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
1563806482
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1406012819
Short name T1091
Test name
Test status
Simulation time 29031080 ps
CPU time 0.76 seconds
Started Mar 28 12:57:19 PM PDT 24
Finished Mar 28 12:57:20 PM PDT 24
Peak memory 203528 kb
Host smart-97ca9705-0142-4f44-b8c8-e37dc6b9746f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406012819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
1406012819
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.4145613124
Short name T1002
Test name
Test status
Simulation time 35193765 ps
CPU time 0.73 seconds
Started Mar 28 12:57:27 PM PDT 24
Finished Mar 28 12:57:28 PM PDT 24
Peak memory 203424 kb
Host smart-ee9c9519-e7a3-4533-af42-19f6010c7cec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145613124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
4145613124
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1058448822
Short name T1059
Test name
Test status
Simulation time 37804266 ps
CPU time 0.79 seconds
Started Mar 28 12:57:19 PM PDT 24
Finished Mar 28 12:57:20 PM PDT 24
Peak memory 203564 kb
Host smart-9d003532-0978-4d77-be19-05ff5174ecb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058448822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
1058448822
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2119323659
Short name T982
Test name
Test status
Simulation time 16138201 ps
CPU time 0.74 seconds
Started Mar 28 12:57:22 PM PDT 24
Finished Mar 28 12:57:23 PM PDT 24
Peak memory 203604 kb
Host smart-53b1a8dd-2450-4901-83ef-509dcc9a2cb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119323659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
2119323659
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2653404992
Short name T1011
Test name
Test status
Simulation time 31820058 ps
CPU time 0.75 seconds
Started Mar 28 12:57:26 PM PDT 24
Finished Mar 28 12:57:27 PM PDT 24
Peak memory 203580 kb
Host smart-ea66f5c2-bf4d-4c09-bf09-d7b412832631
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653404992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
2653404992
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.4010248409
Short name T1064
Test name
Test status
Simulation time 13175947 ps
CPU time 0.7 seconds
Started Mar 28 12:57:25 PM PDT 24
Finished Mar 28 12:57:26 PM PDT 24
Peak memory 203592 kb
Host smart-39593754-55a9-4298-b579-e508d4ff1b2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010248409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
4010248409
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.3408078759
Short name T1066
Test name
Test status
Simulation time 16950819 ps
CPU time 0.7 seconds
Started Mar 28 12:57:40 PM PDT 24
Finished Mar 28 12:57:40 PM PDT 24
Peak memory 203600 kb
Host smart-72d2a56c-67ca-42ac-9ee9-232f91e19554
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408078759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
3408078759
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.1407538787
Short name T981
Test name
Test status
Simulation time 87014081 ps
CPU time 0.7 seconds
Started Mar 28 12:57:26 PM PDT 24
Finished Mar 28 12:57:26 PM PDT 24
Peak memory 203452 kb
Host smart-3bbb1770-e069-4918-881d-1efb471a6be9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407538787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
1407538787
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2445983652
Short name T1088
Test name
Test status
Simulation time 46591230 ps
CPU time 0.71 seconds
Started Mar 28 12:57:26 PM PDT 24
Finished Mar 28 12:57:27 PM PDT 24
Peak memory 203580 kb
Host smart-5fc2deb0-ebea-41e2-9c9d-e70dcbe28e82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445983652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
2445983652
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3007689707
Short name T1038
Test name
Test status
Simulation time 930404831 ps
CPU time 23.73 seconds
Started Mar 28 12:57:12 PM PDT 24
Finished Mar 28 12:57:38 PM PDT 24
Peak memory 215340 kb
Host smart-74856e74-f5f8-40d2-b8ba-099a346574e9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007689707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.3007689707
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.4196954918
Short name T1003
Test name
Test status
Simulation time 30020237744 ps
CPU time 26.7 seconds
Started Mar 28 12:57:09 PM PDT 24
Finished Mar 28 12:57:36 PM PDT 24
Peak memory 207164 kb
Host smart-75f9a344-f005-4d34-aea4-c30bc213c467
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196954918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.4196954918
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3766717631
Short name T69
Test name
Test status
Simulation time 24929331 ps
CPU time 1.35 seconds
Started Mar 28 12:57:08 PM PDT 24
Finished Mar 28 12:57:11 PM PDT 24
Peak memory 216392 kb
Host smart-b4cd46ad-dd56-429e-8816-98424d6494d8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766717631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.3766717631
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1050574999
Short name T1077
Test name
Test status
Simulation time 55313777 ps
CPU time 1.6 seconds
Started Mar 28 12:57:12 PM PDT 24
Finished Mar 28 12:57:15 PM PDT 24
Peak memory 215232 kb
Host smart-3db2287c-b5ad-406b-a6b4-717858d0a47a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050574999 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.1050574999
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1369891858
Short name T109
Test name
Test status
Simulation time 72129399 ps
CPU time 2.39 seconds
Started Mar 28 12:57:13 PM PDT 24
Finished Mar 28 12:57:16 PM PDT 24
Peak memory 215408 kb
Host smart-6c6efe6a-2cae-4418-a75d-4ba664116c45
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369891858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.1
369891858
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2734403773
Short name T1084
Test name
Test status
Simulation time 12045000 ps
CPU time 0.74 seconds
Started Mar 28 12:57:08 PM PDT 24
Finished Mar 28 12:57:10 PM PDT 24
Peak memory 203648 kb
Host smart-93b7a368-2672-4a6b-a4ee-ae18d0624424
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734403773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.2
734403773
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3828024005
Short name T102
Test name
Test status
Simulation time 21070073 ps
CPU time 1.21 seconds
Started Mar 28 12:57:08 PM PDT 24
Finished Mar 28 12:57:10 PM PDT 24
Peak memory 215448 kb
Host smart-8d5f49c3-13bd-4fe1-a37f-9ce193b86b67
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828024005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.3828024005
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2915606548
Short name T980
Test name
Test status
Simulation time 13718185 ps
CPU time 0.68 seconds
Started Mar 28 12:57:09 PM PDT 24
Finished Mar 28 12:57:10 PM PDT 24
Peak memory 203352 kb
Host smart-63d86496-1d08-45cd-8663-2e2722a9c27c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915606548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.2915606548
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1222069505
Short name T984
Test name
Test status
Simulation time 42953044 ps
CPU time 2.6 seconds
Started Mar 28 12:57:12 PM PDT 24
Finished Mar 28 12:57:15 PM PDT 24
Peak memory 215384 kb
Host smart-f2519de7-abb9-4f18-9fe2-ccc0ea27b961
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222069505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.1222069505
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.37755765
Short name T1037
Test name
Test status
Simulation time 69467374 ps
CPU time 2 seconds
Started Mar 28 12:57:09 PM PDT 24
Finished Mar 28 12:57:12 PM PDT 24
Peak memory 215700 kb
Host smart-7ed86c85-7665-4c6b-9bca-e4265ea49c0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37755765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.37755765
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2434329785
Short name T143
Test name
Test status
Simulation time 208766091 ps
CPU time 12.84 seconds
Started Mar 28 12:57:07 PM PDT 24
Finished Mar 28 12:57:21 PM PDT 24
Peak memory 215492 kb
Host smart-26610d25-d3a8-46f1-a338-18c32b5e5aed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434329785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.2434329785
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1316138700
Short name T976
Test name
Test status
Simulation time 15002563 ps
CPU time 0.72 seconds
Started Mar 28 12:57:29 PM PDT 24
Finished Mar 28 12:57:30 PM PDT 24
Peak memory 203600 kb
Host smart-5dec0603-851f-4472-bece-2a9e0b54fc33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316138700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
1316138700
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1484697716
Short name T1092
Test name
Test status
Simulation time 36034699 ps
CPU time 0.73 seconds
Started Mar 28 12:57:27 PM PDT 24
Finished Mar 28 12:57:28 PM PDT 24
Peak memory 203576 kb
Host smart-58cb1fd5-e575-49da-9884-cd5810e49081
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484697716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
1484697716
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3129686681
Short name T1055
Test name
Test status
Simulation time 48094352 ps
CPU time 0.71 seconds
Started Mar 28 12:57:27 PM PDT 24
Finished Mar 28 12:57:28 PM PDT 24
Peak memory 203576 kb
Host smart-89b11839-8602-4a93-bb38-fa0513a1e7b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129686681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
3129686681
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2452866692
Short name T1019
Test name
Test status
Simulation time 17680989 ps
CPU time 0.72 seconds
Started Mar 28 12:57:27 PM PDT 24
Finished Mar 28 12:57:28 PM PDT 24
Peak memory 202996 kb
Host smart-3a7bd1f1-dbcf-446b-a631-5ff7635dcab9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452866692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
2452866692
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1448032349
Short name T1021
Test name
Test status
Simulation time 11554641 ps
CPU time 0.68 seconds
Started Mar 28 12:57:32 PM PDT 24
Finished Mar 28 12:57:33 PM PDT 24
Peak memory 203576 kb
Host smart-234db666-1f0c-45a6-9ca4-db628cc6484d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448032349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
1448032349
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2533289761
Short name T1036
Test name
Test status
Simulation time 12542600 ps
CPU time 0.77 seconds
Started Mar 28 12:57:19 PM PDT 24
Finished Mar 28 12:57:20 PM PDT 24
Peak memory 203436 kb
Host smart-b2d6ff02-cfe8-4616-b70e-e3b2aefaf441
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533289761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
2533289761
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1006354064
Short name T1020
Test name
Test status
Simulation time 22653994 ps
CPU time 0.71 seconds
Started Mar 28 12:57:28 PM PDT 24
Finished Mar 28 12:57:28 PM PDT 24
Peak memory 203600 kb
Host smart-8ddacf44-f4b6-4cdb-ae4b-da3a08597939
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006354064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
1006354064
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.4049316905
Short name T975
Test name
Test status
Simulation time 42793760 ps
CPU time 0.67 seconds
Started Mar 28 12:57:21 PM PDT 24
Finished Mar 28 12:57:22 PM PDT 24
Peak memory 203576 kb
Host smart-764642c1-d802-4828-9284-b440403cc461
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049316905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
4049316905
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3213837185
Short name T993
Test name
Test status
Simulation time 48454334 ps
CPU time 0.76 seconds
Started Mar 28 12:57:26 PM PDT 24
Finished Mar 28 12:57:27 PM PDT 24
Peak memory 203584 kb
Host smart-5255a6e5-d8a8-4d46-a8aa-e5dcee9cfe91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213837185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
3213837185
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1480441505
Short name T1093
Test name
Test status
Simulation time 22482237 ps
CPU time 0.69 seconds
Started Mar 28 12:57:29 PM PDT 24
Finished Mar 28 12:57:29 PM PDT 24
Peak memory 203608 kb
Host smart-c0179350-b7a3-4496-adcd-20e4c2846703
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480441505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
1480441505
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2834028306
Short name T1063
Test name
Test status
Simulation time 163869769 ps
CPU time 3.82 seconds
Started Mar 28 12:57:12 PM PDT 24
Finished Mar 28 12:57:17 PM PDT 24
Peak memory 217792 kb
Host smart-29257893-01c0-406e-8702-54f4165594a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834028306 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.2834028306
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1780437342
Short name T104
Test name
Test status
Simulation time 32367824 ps
CPU time 1.95 seconds
Started Mar 28 12:57:11 PM PDT 24
Finished Mar 28 12:57:14 PM PDT 24
Peak memory 215420 kb
Host smart-4bbd2ace-8c59-4989-9007-0f4d8c2f79ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780437342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.1
780437342
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2736015486
Short name T1028
Test name
Test status
Simulation time 49849407 ps
CPU time 0.66 seconds
Started Mar 28 12:57:12 PM PDT 24
Finished Mar 28 12:57:13 PM PDT 24
Peak memory 203488 kb
Host smart-41866568-e5a8-4b9b-a5c7-21ee4d8718f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736015486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.2
736015486
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3694567221
Short name T986
Test name
Test status
Simulation time 41447906 ps
CPU time 2.71 seconds
Started Mar 28 12:57:13 PM PDT 24
Finished Mar 28 12:57:17 PM PDT 24
Peak memory 215492 kb
Host smart-6ac27315-9a53-44f0-9e68-9c88fdcac96c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694567221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.3694567221
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2305032939
Short name T1083
Test name
Test status
Simulation time 146113006 ps
CPU time 2.44 seconds
Started Mar 28 12:57:13 PM PDT 24
Finished Mar 28 12:57:16 PM PDT 24
Peak memory 215468 kb
Host smart-5ec90cf9-511b-4478-93a0-1cb03e207af6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305032939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.2
305032939
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3525922584
Short name T995
Test name
Test status
Simulation time 29281878 ps
CPU time 2.21 seconds
Started Mar 28 12:57:18 PM PDT 24
Finished Mar 28 12:57:20 PM PDT 24
Peak memory 216484 kb
Host smart-7fb908e0-33f8-43a6-9c91-bc8b0d04b974
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525922584 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.3525922584
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.4291425845
Short name T1032
Test name
Test status
Simulation time 98711213 ps
CPU time 1.78 seconds
Started Mar 28 12:57:14 PM PDT 24
Finished Mar 28 12:57:16 PM PDT 24
Peak memory 215468 kb
Host smart-5cf72518-f443-4c3d-bce2-99be05dae92b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291425845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.4
291425845
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1165390053
Short name T974
Test name
Test status
Simulation time 36819815 ps
CPU time 0.69 seconds
Started Mar 28 12:57:15 PM PDT 24
Finished Mar 28 12:57:16 PM PDT 24
Peak memory 203612 kb
Host smart-396b03d3-9fdc-4fe9-9945-18aec6fd4ff7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165390053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.1
165390053
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1747668639
Short name T1007
Test name
Test status
Simulation time 200927909 ps
CPU time 4.2 seconds
Started Mar 28 12:57:14 PM PDT 24
Finished Mar 28 12:57:19 PM PDT 24
Peak memory 215396 kb
Host smart-e7f3bd04-982b-484c-a984-7f8c4fca91e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747668639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.1747668639
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.314235300
Short name T88
Test name
Test status
Simulation time 23941505 ps
CPU time 1.71 seconds
Started Mar 28 12:57:14 PM PDT 24
Finished Mar 28 12:57:16 PM PDT 24
Peak memory 216500 kb
Host smart-15b3086d-f928-450f-be5b-55bb7d445e1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314235300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.314235300
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3334844876
Short name T49
Test name
Test status
Simulation time 768621351 ps
CPU time 11.9 seconds
Started Mar 28 12:57:14 PM PDT 24
Finished Mar 28 12:57:26 PM PDT 24
Peak memory 215736 kb
Host smart-f294add2-9b1b-4224-938f-1e48ee676593
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334844876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.3334844876
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2212841861
Short name T1042
Test name
Test status
Simulation time 265781109 ps
CPU time 3.65 seconds
Started Mar 28 12:57:15 PM PDT 24
Finished Mar 28 12:57:19 PM PDT 24
Peak memory 216640 kb
Host smart-9c685a59-f9ff-46fe-b088-ab7b9b664ee1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212841861 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.2212841861
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.553061149
Short name T1018
Test name
Test status
Simulation time 51960503 ps
CPU time 1.35 seconds
Started Mar 28 12:57:14 PM PDT 24
Finished Mar 28 12:57:16 PM PDT 24
Peak memory 215396 kb
Host smart-857ae39c-782b-41d0-87b5-098bceecccc1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553061149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.553061149
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2893401241
Short name T988
Test name
Test status
Simulation time 28563794 ps
CPU time 0.79 seconds
Started Mar 28 12:57:18 PM PDT 24
Finished Mar 28 12:57:18 PM PDT 24
Peak memory 203540 kb
Host smart-c4754c01-95cc-4b1a-b13a-102c43a543b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893401241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.2
893401241
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1529805814
Short name T979
Test name
Test status
Simulation time 162823974 ps
CPU time 2.92 seconds
Started Mar 28 12:57:11 PM PDT 24
Finished Mar 28 12:57:15 PM PDT 24
Peak memory 215516 kb
Host smart-2bab500d-232a-45e2-b047-f2e752702f2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529805814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.1529805814
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2590005847
Short name T1017
Test name
Test status
Simulation time 603278929 ps
CPU time 7.23 seconds
Started Mar 28 12:57:15 PM PDT 24
Finished Mar 28 12:57:23 PM PDT 24
Peak memory 215512 kb
Host smart-71ca8569-e916-4165-804b-31d3229845f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590005847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.2590005847
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3270456691
Short name T81
Test name
Test status
Simulation time 50500181 ps
CPU time 1.98 seconds
Started Mar 28 12:57:11 PM PDT 24
Finished Mar 28 12:57:14 PM PDT 24
Peak memory 215468 kb
Host smart-60fb8471-4ecf-4cd7-9ab8-9a80242039b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270456691 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.3270456691
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.113584179
Short name T1030
Test name
Test status
Simulation time 76213791 ps
CPU time 1.2 seconds
Started Mar 28 12:57:15 PM PDT 24
Finished Mar 28 12:57:17 PM PDT 24
Peak memory 207008 kb
Host smart-38419076-f66a-4c28-921e-816582fef799
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113584179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.113584179
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3847235004
Short name T1065
Test name
Test status
Simulation time 19155660 ps
CPU time 0.68 seconds
Started Mar 28 12:57:11 PM PDT 24
Finished Mar 28 12:57:12 PM PDT 24
Peak memory 203600 kb
Host smart-d6189240-e6eb-4dba-811e-a6262997d9ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847235004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.3
847235004
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3759685832
Short name T1085
Test name
Test status
Simulation time 108116664 ps
CPU time 2.63 seconds
Started Mar 28 12:57:09 PM PDT 24
Finished Mar 28 12:57:12 PM PDT 24
Peak memory 215292 kb
Host smart-d7feadac-7401-4b7a-9b59-63cf91963212
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759685832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.3759685832
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3534510762
Short name T1044
Test name
Test status
Simulation time 416433330 ps
CPU time 2.06 seconds
Started Mar 28 12:57:14 PM PDT 24
Finished Mar 28 12:57:17 PM PDT 24
Peak memory 215392 kb
Host smart-9c874e23-5e76-49e0-b508-a9447b5f6c43
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534510762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.3
534510762
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.492162438
Short name T140
Test name
Test status
Simulation time 2650712211 ps
CPU time 16.43 seconds
Started Mar 28 12:57:14 PM PDT 24
Finished Mar 28 12:57:31 PM PDT 24
Peak memory 215440 kb
Host smart-01b7fc6a-8997-4b48-b5dd-2788ddb266a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492162438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_
tl_intg_err.492162438
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2264156824
Short name T79
Test name
Test status
Simulation time 34198693 ps
CPU time 2 seconds
Started Mar 28 12:57:09 PM PDT 24
Finished Mar 28 12:57:12 PM PDT 24
Peak memory 216588 kb
Host smart-217d9223-3c6a-4661-9820-fc7df0adb34e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264156824 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.2264156824
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2400426634
Short name T1072
Test name
Test status
Simulation time 58992140 ps
CPU time 1.47 seconds
Started Mar 28 12:57:09 PM PDT 24
Finished Mar 28 12:57:11 PM PDT 24
Peak memory 207036 kb
Host smart-811607b7-1f1d-4217-bdfe-217c02f9ab92
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400426634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.2
400426634
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1885883877
Short name T1067
Test name
Test status
Simulation time 25240511 ps
CPU time 0.71 seconds
Started Mar 28 12:57:05 PM PDT 24
Finished Mar 28 12:57:06 PM PDT 24
Peak memory 203596 kb
Host smart-75b32836-10b9-466b-b2da-151820b88c1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885883877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.1
885883877
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.755021336
Short name T1076
Test name
Test status
Simulation time 239614945 ps
CPU time 1.82 seconds
Started Mar 28 12:57:11 PM PDT 24
Finished Mar 28 12:57:13 PM PDT 24
Peak memory 215396 kb
Host smart-18802ac6-7534-41d9-a567-e067210b98ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755021336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sp
i_device_same_csr_outstanding.755021336
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3481461660
Short name T87
Test name
Test status
Simulation time 151672362 ps
CPU time 3.92 seconds
Started Mar 28 12:57:11 PM PDT 24
Finished Mar 28 12:57:16 PM PDT 24
Peak memory 215772 kb
Host smart-8b5bc6db-ea9e-49b4-9428-cd964f8e3ba2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481461660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.3
481461660
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2402006218
Short name T124
Test name
Test status
Simulation time 431365502 ps
CPU time 7.3 seconds
Started Mar 28 12:57:08 PM PDT 24
Finished Mar 28 12:57:17 PM PDT 24
Peak memory 216132 kb
Host smart-953d9fea-cb23-43d2-ad4f-307d083765a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402006218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.2402006218
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.2019278538
Short name T7
Test name
Test status
Simulation time 5509693263 ps
CPU time 11.25 seconds
Started Mar 28 03:21:14 PM PDT 24
Finished Mar 28 03:21:26 PM PDT 24
Peak memory 235096 kb
Host smart-1d05082d-f5b0-4a75-ab23-bc2d54494efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019278538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.2019278538
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.1516814553
Short name T967
Test name
Test status
Simulation time 13624261 ps
CPU time 0.79 seconds
Started Mar 28 03:21:16 PM PDT 24
Finished Mar 28 03:21:16 PM PDT 24
Peak memory 207008 kb
Host smart-cf3b562a-d079-40d4-b60e-0eeee4bc09bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516814553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.1516814553
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.3076315689
Short name T402
Test name
Test status
Simulation time 9987923567 ps
CPU time 29.15 seconds
Started Mar 28 03:21:12 PM PDT 24
Finished Mar 28 03:21:42 PM PDT 24
Peak memory 236324 kb
Host smart-feed23a9-69f7-4c33-8e89-799293049c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076315689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.3076315689
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.2590806507
Short name T961
Test name
Test status
Simulation time 87095062237 ps
CPU time 156.12 seconds
Started Mar 28 03:21:12 PM PDT 24
Finished Mar 28 03:23:49 PM PDT 24
Peak memory 257648 kb
Host smart-f99c9e73-bc19-4178-b699-c088ee97f9ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590806507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.2590806507
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.3291467060
Short name T972
Test name
Test status
Simulation time 13361137181 ps
CPU time 69.49 seconds
Started Mar 28 03:21:13 PM PDT 24
Finished Mar 28 03:22:23 PM PDT 24
Peak memory 256584 kb
Host smart-2f4478c5-c281-4cb9-a087-760e8924d1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291467060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.3291467060
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.1868298043
Short name T945
Test name
Test status
Simulation time 4739924972 ps
CPU time 10.27 seconds
Started Mar 28 03:21:13 PM PDT 24
Finished Mar 28 03:21:23 PM PDT 24
Peak memory 238288 kb
Host smart-cc407716-d987-4172-b888-4ad6fab5c18a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868298043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.1868298043
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.2879281286
Short name T637
Test name
Test status
Simulation time 2944595763 ps
CPU time 4.88 seconds
Started Mar 28 03:21:13 PM PDT 24
Finished Mar 28 03:21:18 PM PDT 24
Peak memory 219384 kb
Host smart-7371e960-51d1-4e46-84f8-a67241342fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879281286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.2879281286
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.3333844630
Short name T601
Test name
Test status
Simulation time 26659964840 ps
CPU time 20.16 seconds
Started Mar 28 03:21:08 PM PDT 24
Finished Mar 28 03:21:29 PM PDT 24
Peak memory 239964 kb
Host smart-2ef55a5d-60d7-47f6-ae08-b13f5e1af59a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333844630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.3333844630
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.1594856769
Short name T386
Test name
Test status
Simulation time 7026664050 ps
CPU time 8.3 seconds
Started Mar 28 03:21:13 PM PDT 24
Finished Mar 28 03:21:21 PM PDT 24
Peak memory 235876 kb
Host smart-04d8d252-03f5-4b5a-8779-4f03cefa4f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594856769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.1594856769
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.1187582171
Short name T302
Test name
Test status
Simulation time 3352877587 ps
CPU time 8.17 seconds
Started Mar 28 03:21:13 PM PDT 24
Finished Mar 28 03:21:22 PM PDT 24
Peak memory 233768 kb
Host smart-f59cd6b3-b56a-4822-9345-e10894e2475b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187582171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.1187582171
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.2856227040
Short name T541
Test name
Test status
Simulation time 52356139 ps
CPU time 0.79 seconds
Started Mar 28 03:21:12 PM PDT 24
Finished Mar 28 03:21:13 PM PDT 24
Peak memory 216572 kb
Host smart-9483f962-fbed-41e3-aeed-f6fc84791224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856227040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.2856227040
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.2702343626
Short name T944
Test name
Test status
Simulation time 9876763435 ps
CPU time 4.74 seconds
Started Mar 28 03:21:13 PM PDT 24
Finished Mar 28 03:21:18 PM PDT 24
Peak memory 219736 kb
Host smart-631a7cfb-b504-4d33-91bb-01544a0352e0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2702343626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.2702343626
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.2854216500
Short name T927
Test name
Test status
Simulation time 1585025427 ps
CPU time 9.14 seconds
Started Mar 28 03:21:10 PM PDT 24
Finished Mar 28 03:21:20 PM PDT 24
Peak memory 216736 kb
Host smart-9432c0e8-7475-422b-a5e1-a5770a6d367d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854216500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.2854216500
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.774975684
Short name T292
Test name
Test status
Simulation time 2492796599 ps
CPU time 8.5 seconds
Started Mar 28 03:21:13 PM PDT 24
Finished Mar 28 03:21:22 PM PDT 24
Peak memory 216852 kb
Host smart-5d586964-bd84-49d5-bc19-41edbb7ae233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774975684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.774975684
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.3831794771
Short name T707
Test name
Test status
Simulation time 175963446 ps
CPU time 1.43 seconds
Started Mar 28 03:21:13 PM PDT 24
Finished Mar 28 03:21:15 PM PDT 24
Peak memory 216636 kb
Host smart-7ba59212-2f7d-4cfd-93eb-31c8c363375d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831794771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.3831794771
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.1629794037
Short name T327
Test name
Test status
Simulation time 156576275 ps
CPU time 1.2 seconds
Started Mar 28 03:21:14 PM PDT 24
Finished Mar 28 03:21:16 PM PDT 24
Peak memory 207164 kb
Host smart-c71856a7-d400-4c55-a9a0-ba7802345020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629794037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1629794037
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.1706238013
Short name T204
Test name
Test status
Simulation time 6643117945 ps
CPU time 21.89 seconds
Started Mar 28 03:21:11 PM PDT 24
Finished Mar 28 03:21:33 PM PDT 24
Peak memory 236348 kb
Host smart-060b657c-a3d8-4d23-99a8-c305a4ae1133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706238013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.1706238013
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.3010638728
Short name T322
Test name
Test status
Simulation time 51124856 ps
CPU time 0.75 seconds
Started Mar 28 03:21:31 PM PDT 24
Finished Mar 28 03:21:32 PM PDT 24
Peak memory 205884 kb
Host smart-fc5b08c9-54d9-4fe1-8cac-c62715b6ff70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010638728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.3
010638728
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.994506898
Short name T569
Test name
Test status
Simulation time 63044772 ps
CPU time 2.71 seconds
Started Mar 28 03:21:18 PM PDT 24
Finished Mar 28 03:21:21 PM PDT 24
Peak memory 234608 kb
Host smart-13449358-8da5-4f6f-bfe6-8d3c1c5eeee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994506898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.994506898
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.3507922486
Short name T554
Test name
Test status
Simulation time 19695539 ps
CPU time 0.81 seconds
Started Mar 28 03:21:13 PM PDT 24
Finished Mar 28 03:21:14 PM PDT 24
Peak memory 207352 kb
Host smart-f999ece2-0730-4910-9261-11b9cb25b15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507922486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.3507922486
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.3509941070
Short name T244
Test name
Test status
Simulation time 26564013021 ps
CPU time 133.21 seconds
Started Mar 28 03:21:18 PM PDT 24
Finished Mar 28 03:23:32 PM PDT 24
Peak memory 256288 kb
Host smart-cb51503a-3f62-4a22-8bfa-24d226376863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509941070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.3509941070
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.3271600235
Short name T659
Test name
Test status
Simulation time 67378048394 ps
CPU time 109.55 seconds
Started Mar 28 03:21:18 PM PDT 24
Finished Mar 28 03:23:07 PM PDT 24
Peak memory 250548 kb
Host smart-631657da-ce64-4e77-8796-c3ec4d09b3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271600235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.3271600235
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.4167419718
Short name T487
Test name
Test status
Simulation time 5886778567 ps
CPU time 30.04 seconds
Started Mar 28 03:21:18 PM PDT 24
Finished Mar 28 03:21:49 PM PDT 24
Peak memory 247196 kb
Host smart-4486d4a6-ec6b-433c-8103-83661ef1825e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167419718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.4167419718
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.3102087210
Short name T528
Test name
Test status
Simulation time 1795685353 ps
CPU time 5.87 seconds
Started Mar 28 03:21:16 PM PDT 24
Finished Mar 28 03:21:23 PM PDT 24
Peak memory 224864 kb
Host smart-09b69bde-c858-4268-aa52-98832959bf0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102087210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.3102087210
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.3164379919
Short name T625
Test name
Test status
Simulation time 52193668737 ps
CPU time 35.72 seconds
Started Mar 28 03:21:18 PM PDT 24
Finished Mar 28 03:21:54 PM PDT 24
Peak memory 232520 kb
Host smart-18419f0d-7a4f-498e-b8cc-01b71b0b57ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164379919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3164379919
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.4154378949
Short name T234
Test name
Test status
Simulation time 2529976287 ps
CPU time 7.6 seconds
Started Mar 28 03:21:17 PM PDT 24
Finished Mar 28 03:21:25 PM PDT 24
Peak memory 229384 kb
Host smart-8e47e82c-86d2-4ba2-af96-0f791719a40d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154378949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.4154378949
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.153774916
Short name T606
Test name
Test status
Simulation time 1488223706 ps
CPU time 5.61 seconds
Started Mar 28 03:21:16 PM PDT 24
Finished Mar 28 03:21:22 PM PDT 24
Peak memory 219280 kb
Host smart-be877eeb-96ea-4365-ade7-07f8504890d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153774916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.153774916
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_ram_cfg.1211991827
Short name T834
Test name
Test status
Simulation time 29336942 ps
CPU time 0.8 seconds
Started Mar 28 03:21:08 PM PDT 24
Finished Mar 28 03:21:09 PM PDT 24
Peak memory 216548 kb
Host smart-d885f4b2-ff30-4578-985b-d52e017893cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211991827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_ram_cfg.1211991827
Directory /workspace/1.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.271500007
Short name T638
Test name
Test status
Simulation time 1299874170 ps
CPU time 5.91 seconds
Started Mar 28 03:21:13 PM PDT 24
Finished Mar 28 03:21:19 PM PDT 24
Peak memory 222820 kb
Host smart-eb0be728-5669-416c-9180-6a9c24a0bf85
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=271500007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_direc
t.271500007
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.636320956
Short name T55
Test name
Test status
Simulation time 217606931 ps
CPU time 1.06 seconds
Started Mar 28 03:21:17 PM PDT 24
Finished Mar 28 03:21:18 PM PDT 24
Peak memory 235544 kb
Host smart-5ff46e4e-c2ec-48be-9473-1ecad1ad3451
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636320956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.636320956
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.2092999503
Short name T728
Test name
Test status
Simulation time 114950123359 ps
CPU time 42.44 seconds
Started Mar 28 03:21:17 PM PDT 24
Finished Mar 28 03:21:59 PM PDT 24
Peak memory 216808 kb
Host smart-8ca384c1-f8de-4534-b9ea-7c7859acde96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092999503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.2092999503
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.988368182
Short name T507
Test name
Test status
Simulation time 9821240910 ps
CPU time 14.95 seconds
Started Mar 28 03:21:16 PM PDT 24
Finished Mar 28 03:21:31 PM PDT 24
Peak memory 216756 kb
Host smart-efe49a95-6609-41ed-a912-559005e8da39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988368182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.988368182
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.760795858
Short name T676
Test name
Test status
Simulation time 78550237 ps
CPU time 2.18 seconds
Started Mar 28 03:21:05 PM PDT 24
Finished Mar 28 03:21:07 PM PDT 24
Peak memory 216668 kb
Host smart-ae14884a-a224-4dda-90a4-98aba0d7b8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760795858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.760795858
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.2918077555
Short name T750
Test name
Test status
Simulation time 38166398 ps
CPU time 0.87 seconds
Started Mar 28 03:21:16 PM PDT 24
Finished Mar 28 03:21:17 PM PDT 24
Peak memory 206200 kb
Host smart-8973212d-cbe7-4e2c-8d78-d05646b509ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918077555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.2918077555
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.1321041501
Short name T869
Test name
Test status
Simulation time 27495299826 ps
CPU time 20.37 seconds
Started Mar 28 03:21:17 PM PDT 24
Finished Mar 28 03:21:38 PM PDT 24
Peak memory 220592 kb
Host smart-d91b9f85-6280-4d90-a489-f15a6151768b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321041501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.1321041501
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.715134082
Short name T855
Test name
Test status
Simulation time 10996244 ps
CPU time 0.74 seconds
Started Mar 28 03:22:04 PM PDT 24
Finished Mar 28 03:22:05 PM PDT 24
Peak memory 205788 kb
Host smart-eb863308-1adc-43b3-b9b4-1727e1c10107
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715134082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.715134082
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.3623803298
Short name T652
Test name
Test status
Simulation time 1236168134 ps
CPU time 3.98 seconds
Started Mar 28 03:22:05 PM PDT 24
Finished Mar 28 03:22:10 PM PDT 24
Peak memory 234704 kb
Host smart-b1217ec8-7f13-4a4b-872e-8c14b3a8ba5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623803298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.3623803298
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.2984550485
Short name T620
Test name
Test status
Simulation time 70593146 ps
CPU time 0.77 seconds
Started Mar 28 03:21:52 PM PDT 24
Finished Mar 28 03:21:53 PM PDT 24
Peak memory 206916 kb
Host smart-c6b93386-3e7b-4978-a4fc-697fd653f3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984550485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.2984550485
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.1116294250
Short name T494
Test name
Test status
Simulation time 9008990610 ps
CPU time 112.19 seconds
Started Mar 28 03:22:05 PM PDT 24
Finished Mar 28 03:23:57 PM PDT 24
Peak memory 249696 kb
Host smart-80045226-bb57-44a9-a36d-26549df40c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116294250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.1116294250
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.1233555018
Short name T708
Test name
Test status
Simulation time 15322568792 ps
CPU time 76.74 seconds
Started Mar 28 03:22:05 PM PDT 24
Finished Mar 28 03:23:22 PM PDT 24
Peak memory 252548 kb
Host smart-6ffc25b7-5191-4d53-bdc4-cf700247a32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233555018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.1233555018
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.1741240109
Short name T564
Test name
Test status
Simulation time 1369279498 ps
CPU time 18.3 seconds
Started Mar 28 03:22:08 PM PDT 24
Finished Mar 28 03:22:26 PM PDT 24
Peak memory 234500 kb
Host smart-2c96a8cd-b41d-4274-ae45-94f778a4ddae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741240109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.1741240109
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.2324627091
Short name T165
Test name
Test status
Simulation time 719246664 ps
CPU time 4 seconds
Started Mar 28 03:21:43 PM PDT 24
Finished Mar 28 03:21:48 PM PDT 24
Peak memory 224888 kb
Host smart-33c3535a-e9be-4476-a4e0-d0c7631c3f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324627091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.2324627091
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.1290772649
Short name T738
Test name
Test status
Simulation time 45503325118 ps
CPU time 28.91 seconds
Started Mar 28 03:21:52 PM PDT 24
Finished Mar 28 03:22:21 PM PDT 24
Peak memory 250396 kb
Host smart-90f07fe6-ee61-4d23-a97e-27ce768841e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290772649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.1290772649
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.2936558501
Short name T222
Test name
Test status
Simulation time 155259845 ps
CPU time 3.17 seconds
Started Mar 28 03:21:43 PM PDT 24
Finished Mar 28 03:21:47 PM PDT 24
Peak memory 233920 kb
Host smart-4790700a-9e99-467e-a6ea-08439bf9cae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936558501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.2936558501
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.1600323876
Short name T752
Test name
Test status
Simulation time 400025273 ps
CPU time 6.48 seconds
Started Mar 28 03:21:44 PM PDT 24
Finished Mar 28 03:21:51 PM PDT 24
Peak memory 223828 kb
Host smart-65fc6fc9-c91d-4471-85a3-4ea75d6dd847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600323876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.1600323876
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_ram_cfg.2210772778
Short name T692
Test name
Test status
Simulation time 42288116 ps
CPU time 0.75 seconds
Started Mar 28 03:21:47 PM PDT 24
Finished Mar 28 03:21:48 PM PDT 24
Peak memory 216552 kb
Host smart-0c4d7d2f-70f7-44ff-9422-74e6682a85d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210772778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_ram_cfg.2210772778
Directory /workspace/10.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.2088309019
Short name T727
Test name
Test status
Simulation time 192563460 ps
CPU time 3.96 seconds
Started Mar 28 03:22:03 PM PDT 24
Finished Mar 28 03:22:08 PM PDT 24
Peak memory 223472 kb
Host smart-d7cf68e4-a6bc-436c-88a2-584fa60ebbda
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2088309019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.2088309019
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.2353538215
Short name T130
Test name
Test status
Simulation time 122185860 ps
CPU time 1.23 seconds
Started Mar 28 03:22:07 PM PDT 24
Finished Mar 28 03:22:09 PM PDT 24
Peak memory 207552 kb
Host smart-50261472-afdd-485c-ae82-dafec15cc13b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353538215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.2353538215
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.1431968559
Short name T335
Test name
Test status
Simulation time 1631934177 ps
CPU time 16.66 seconds
Started Mar 28 03:21:53 PM PDT 24
Finished Mar 28 03:22:10 PM PDT 24
Peak memory 216656 kb
Host smart-77601e14-b58c-4266-9848-7b9900149d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431968559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.1431968559
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.943748412
Short name T822
Test name
Test status
Simulation time 6457217435 ps
CPU time 10.25 seconds
Started Mar 28 03:21:46 PM PDT 24
Finished Mar 28 03:21:58 PM PDT 24
Peak memory 216768 kb
Host smart-b3c90065-63b3-4754-be6c-0d30296b0308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943748412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.943748412
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.2938432463
Short name T329
Test name
Test status
Simulation time 90995755 ps
CPU time 1.43 seconds
Started Mar 28 03:21:53 PM PDT 24
Finished Mar 28 03:21:55 PM PDT 24
Peak memory 216276 kb
Host smart-8509b911-1417-4792-9555-0780a6c40baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938432463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.2938432463
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.1345838172
Short name T857
Test name
Test status
Simulation time 25029060 ps
CPU time 0.76 seconds
Started Mar 28 03:21:45 PM PDT 24
Finished Mar 28 03:21:48 PM PDT 24
Peak memory 206168 kb
Host smart-dbd2cfdc-22c1-4a4f-a979-170286efeb08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345838172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.1345838172
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.2190570704
Short name T849
Test name
Test status
Simulation time 10296793248 ps
CPU time 35.68 seconds
Started Mar 28 03:22:11 PM PDT 24
Finished Mar 28 03:22:47 PM PDT 24
Peak memory 250184 kb
Host smart-699eb16e-33af-45dc-8990-54e0d8d38e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190570704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.2190570704
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.12815963
Short name T491
Test name
Test status
Simulation time 12781710 ps
CPU time 0.73 seconds
Started Mar 28 03:22:05 PM PDT 24
Finished Mar 28 03:22:06 PM PDT 24
Peak memory 205256 kb
Host smart-04a9f6d3-5312-4f62-8163-1cbf4eb4352b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12815963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.12815963
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.1358043375
Short name T211
Test name
Test status
Simulation time 375192380 ps
CPU time 3.85 seconds
Started Mar 28 03:22:08 PM PDT 24
Finished Mar 28 03:22:12 PM PDT 24
Peak memory 234672 kb
Host smart-662aa4e6-cbab-410b-8624-5de727af9aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358043375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.1358043375
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.578967097
Short name T563
Test name
Test status
Simulation time 57204210 ps
CPU time 0.74 seconds
Started Mar 28 03:22:11 PM PDT 24
Finished Mar 28 03:22:12 PM PDT 24
Peak memory 205992 kb
Host smart-ff57409e-5796-40a6-beae-9bfe024cb030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578967097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.578967097
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.1853194688
Short name T800
Test name
Test status
Simulation time 13256422411 ps
CPU time 65.77 seconds
Started Mar 28 03:22:06 PM PDT 24
Finished Mar 28 03:23:12 PM PDT 24
Peak memory 249564 kb
Host smart-34339971-450d-4a50-825b-5321ac36d691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853194688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.1853194688
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.3712546974
Short name T265
Test name
Test status
Simulation time 105726680161 ps
CPU time 387.19 seconds
Started Mar 28 03:22:14 PM PDT 24
Finished Mar 28 03:28:41 PM PDT 24
Peak memory 261980 kb
Host smart-891c7703-0138-4e3a-bc84-97f31912b272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712546974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.3712546974
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.568695384
Short name T160
Test name
Test status
Simulation time 79159544701 ps
CPU time 557.86 seconds
Started Mar 28 03:22:08 PM PDT 24
Finished Mar 28 03:31:27 PM PDT 24
Peak memory 273772 kb
Host smart-0f6fb8f3-f5e2-4fba-b934-82bc1490df6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568695384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle
.568695384
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_intercept.1091557331
Short name T731
Test name
Test status
Simulation time 169545967 ps
CPU time 3.78 seconds
Started Mar 28 03:22:14 PM PDT 24
Finished Mar 28 03:22:18 PM PDT 24
Peak memory 234176 kb
Host smart-8a73f9f7-2ef0-4715-8c1d-24bc623f2c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091557331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.1091557331
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.1335312584
Short name T778
Test name
Test status
Simulation time 1479852143 ps
CPU time 15.02 seconds
Started Mar 28 03:22:08 PM PDT 24
Finished Mar 28 03:22:23 PM PDT 24
Peak memory 251356 kb
Host smart-c6d0f938-d892-46f2-9add-4a9ffad5bd2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335312584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.1335312584
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.16011144
Short name T766
Test name
Test status
Simulation time 17613014961 ps
CPU time 15.04 seconds
Started Mar 28 03:22:06 PM PDT 24
Finished Mar 28 03:22:21 PM PDT 24
Peak memory 218200 kb
Host smart-5c907281-5a53-47d8-a550-e74d28c27307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16011144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap.16011144
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.346369976
Short name T755
Test name
Test status
Simulation time 3324514004 ps
CPU time 8.62 seconds
Started Mar 28 03:22:10 PM PDT 24
Finished Mar 28 03:22:20 PM PDT 24
Peak memory 224976 kb
Host smart-e46e66fd-ce45-4a6c-8700-75ac6470a189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346369976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.346369976
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_ram_cfg.582097009
Short name T889
Test name
Test status
Simulation time 36792901 ps
CPU time 0.75 seconds
Started Mar 28 03:22:10 PM PDT 24
Finished Mar 28 03:22:12 PM PDT 24
Peak memory 216544 kb
Host smart-5930307d-be7d-4ee6-9de9-c2602f3a0aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582097009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_ram_cfg.582097009
Directory /workspace/11.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.370076744
Short name T852
Test name
Test status
Simulation time 2066669182 ps
CPU time 6.51 seconds
Started Mar 28 03:22:05 PM PDT 24
Finished Mar 28 03:22:12 PM PDT 24
Peak memory 219648 kb
Host smart-96804a18-58a8-4b2f-874d-259bdd878754
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=370076744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dire
ct.370076744
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.796558715
Short name T920
Test name
Test status
Simulation time 75970395641 ps
CPU time 258.84 seconds
Started Mar 28 03:22:08 PM PDT 24
Finished Mar 28 03:26:27 PM PDT 24
Peak memory 253784 kb
Host smart-5767cb44-2bd6-44a6-8dd3-909cd0626c6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796558715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stres
s_all.796558715
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.3478011033
Short name T263
Test name
Test status
Simulation time 3222308520 ps
CPU time 18.27 seconds
Started Mar 28 03:22:04 PM PDT 24
Finished Mar 28 03:22:23 PM PDT 24
Peak memory 216720 kb
Host smart-f633b2aa-82ba-4484-afc6-347a8821a41c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478011033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.3478011033
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.2074105622
Short name T790
Test name
Test status
Simulation time 12369083057 ps
CPU time 30.47 seconds
Started Mar 28 03:22:06 PM PDT 24
Finished Mar 28 03:22:37 PM PDT 24
Peak memory 216812 kb
Host smart-08cb0657-e8a3-4290-bed8-a7052c94cfbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074105622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.2074105622
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.2880501871
Short name T599
Test name
Test status
Simulation time 139715374 ps
CPU time 1.13 seconds
Started Mar 28 03:22:08 PM PDT 24
Finished Mar 28 03:22:09 PM PDT 24
Peak memory 207680 kb
Host smart-600abc6b-1eba-407e-837f-0fb389c45039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880501871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.2880501871
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.3342831468
Short name T489
Test name
Test status
Simulation time 157485008 ps
CPU time 1.14 seconds
Started Mar 28 03:22:11 PM PDT 24
Finished Mar 28 03:22:13 PM PDT 24
Peak memory 207232 kb
Host smart-05a859f9-0741-4b66-9496-dae553949fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342831468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.3342831468
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.2230561021
Short name T225
Test name
Test status
Simulation time 18733448318 ps
CPU time 17.57 seconds
Started Mar 28 03:22:08 PM PDT 24
Finished Mar 28 03:22:26 PM PDT 24
Peak memory 248940 kb
Host smart-11eaef76-91e5-45fa-a40f-ec4407e265e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230561021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.2230561021
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.4233493654
Short name T907
Test name
Test status
Simulation time 32096276 ps
CPU time 0.7 seconds
Started Mar 28 03:22:11 PM PDT 24
Finished Mar 28 03:22:12 PM PDT 24
Peak memory 205308 kb
Host smart-c5de52e7-380c-4445-ac7e-36fe17ccd073
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233493654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
4233493654
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.2094993890
Short name T883
Test name
Test status
Simulation time 3191858601 ps
CPU time 4.25 seconds
Started Mar 28 03:22:08 PM PDT 24
Finished Mar 28 03:22:13 PM PDT 24
Peak memory 233720 kb
Host smart-ffbf74bd-3a79-4e15-acfa-f39614373b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094993890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.2094993890
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.3613109734
Short name T796
Test name
Test status
Simulation time 58544073 ps
CPU time 0.83 seconds
Started Mar 28 03:22:08 PM PDT 24
Finished Mar 28 03:22:09 PM PDT 24
Peak memory 206952 kb
Host smart-995ca447-f33d-4fe5-97f4-e429ddc9a44e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613109734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.3613109734
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.1915766934
Short name T443
Test name
Test status
Simulation time 12805266138 ps
CPU time 72.86 seconds
Started Mar 28 03:22:07 PM PDT 24
Finished Mar 28 03:23:20 PM PDT 24
Peak memory 241180 kb
Host smart-ec026aaf-dc00-4acf-8f88-ca3e09a63503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915766934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.1915766934
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.350812304
Short name T353
Test name
Test status
Simulation time 659797554 ps
CPU time 13.69 seconds
Started Mar 28 03:22:08 PM PDT 24
Finished Mar 28 03:22:22 PM PDT 24
Peak memory 233136 kb
Host smart-81e5e4d5-45ce-4f26-ad50-86870a449257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350812304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.350812304
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_intercept.2600141431
Short name T643
Test name
Test status
Simulation time 4115120786 ps
CPU time 5.73 seconds
Started Mar 28 03:22:07 PM PDT 24
Finished Mar 28 03:22:13 PM PDT 24
Peak memory 234184 kb
Host smart-ba2a6100-e8b2-4a0d-a5fa-e5fb49bf1333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600141431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.2600141431
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.2393720978
Short name T741
Test name
Test status
Simulation time 27351737999 ps
CPU time 27.86 seconds
Started Mar 28 03:22:06 PM PDT 24
Finished Mar 28 03:22:34 PM PDT 24
Peak memory 238220 kb
Host smart-2dfbbc1f-f82e-4075-b63f-67262b3d6d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393720978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.2393720978
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.2908730286
Short name T781
Test name
Test status
Simulation time 4676769054 ps
CPU time 20.72 seconds
Started Mar 28 03:22:08 PM PDT 24
Finished Mar 28 03:22:29 PM PDT 24
Peak memory 241384 kb
Host smart-177a6d0f-1d85-4320-99a7-befefdb565ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908730286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.2908730286
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.4173166850
Short name T414
Test name
Test status
Simulation time 486642969 ps
CPU time 9.87 seconds
Started Mar 28 03:22:03 PM PDT 24
Finished Mar 28 03:22:13 PM PDT 24
Peak memory 229184 kb
Host smart-298ad013-5ee6-4c09-8329-fb4a3539fc9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173166850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.4173166850
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.546632373
Short name T744
Test name
Test status
Simulation time 2600747535 ps
CPU time 6.55 seconds
Started Mar 28 03:22:13 PM PDT 24
Finished Mar 28 03:22:20 PM PDT 24
Peak memory 222788 kb
Host smart-1e63cb21-1a7c-4b26-bf8e-4b385c0720c7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=546632373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dire
ct.546632373
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.1273110392
Short name T384
Test name
Test status
Simulation time 5408586457 ps
CPU time 14.18 seconds
Started Mar 28 03:22:08 PM PDT 24
Finished Mar 28 03:22:23 PM PDT 24
Peak memory 216936 kb
Host smart-eaf7a878-dc6d-4a21-998a-ce0211854590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273110392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.1273110392
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.1931168382
Short name T936
Test name
Test status
Simulation time 9671369608 ps
CPU time 29.58 seconds
Started Mar 28 03:22:07 PM PDT 24
Finished Mar 28 03:22:37 PM PDT 24
Peak memory 216532 kb
Host smart-6bbb03ba-5b53-413d-a8c7-3c089ec01b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931168382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.1931168382
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.3361301402
Short name T589
Test name
Test status
Simulation time 212095137 ps
CPU time 9.13 seconds
Started Mar 28 03:22:06 PM PDT 24
Finished Mar 28 03:22:16 PM PDT 24
Peak memory 216720 kb
Host smart-964de064-483b-4bbc-9f30-25587398aa3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361301402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.3361301402
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.1692461958
Short name T697
Test name
Test status
Simulation time 245931558 ps
CPU time 1.18 seconds
Started Mar 28 03:22:09 PM PDT 24
Finished Mar 28 03:22:10 PM PDT 24
Peak memory 207168 kb
Host smart-86882c1a-82ae-405e-90c3-32b405773b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692461958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.1692461958
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.2658590319
Short name T853
Test name
Test status
Simulation time 4707990312 ps
CPU time 13.24 seconds
Started Mar 28 03:22:09 PM PDT 24
Finished Mar 28 03:22:22 PM PDT 24
Peak memory 237124 kb
Host smart-e8de4c16-6207-472b-9623-d5aa7a8c8298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658590319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.2658590319
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.3558111594
Short name T875
Test name
Test status
Simulation time 73963817 ps
CPU time 0.7 seconds
Started Mar 28 03:22:30 PM PDT 24
Finished Mar 28 03:22:31 PM PDT 24
Peak memory 205868 kb
Host smart-88e20ce1-0dc5-4bbd-b456-dd9c31861ef9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558111594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
3558111594
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.3458724568
Short name T798
Test name
Test status
Simulation time 108676831 ps
CPU time 2.89 seconds
Started Mar 28 03:22:25 PM PDT 24
Finished Mar 28 03:22:28 PM PDT 24
Peak memory 234460 kb
Host smart-f9a7b530-701f-42b1-9056-b55118609387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458724568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.3458724568
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.42913708
Short name T275
Test name
Test status
Simulation time 19229771 ps
CPU time 0.8 seconds
Started Mar 28 03:22:11 PM PDT 24
Finished Mar 28 03:22:12 PM PDT 24
Peak memory 206984 kb
Host smart-cf32aa4e-605d-4b68-be9c-49f3a226d22e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42913708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.42913708
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.1762241956
Short name T635
Test name
Test status
Simulation time 12898211000 ps
CPU time 74.34 seconds
Started Mar 28 03:22:28 PM PDT 24
Finished Mar 28 03:23:42 PM PDT 24
Peak memory 249664 kb
Host smart-781b8f8f-9703-419b-a1a8-6567cfa35767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762241956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.1762241956
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.1936723690
Short name T880
Test name
Test status
Simulation time 30750152667 ps
CPU time 227.52 seconds
Started Mar 28 03:22:31 PM PDT 24
Finished Mar 28 03:26:18 PM PDT 24
Peak memory 250632 kb
Host smart-22eae248-5ce4-4ec1-84e2-754c9fcde7b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936723690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.1936723690
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.2201421210
Short name T861
Test name
Test status
Simulation time 106349631373 ps
CPU time 108.75 seconds
Started Mar 28 03:22:29 PM PDT 24
Finished Mar 28 03:24:18 PM PDT 24
Peak memory 265116 kb
Host smart-6efedc86-6245-4de2-a69c-72eb0eadd3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201421210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.2201421210
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.4088073866
Short name T315
Test name
Test status
Simulation time 5771642539 ps
CPU time 31.11 seconds
Started Mar 28 03:22:27 PM PDT 24
Finished Mar 28 03:22:58 PM PDT 24
Peak memory 246780 kb
Host smart-fa121c47-3ca6-46ca-adf3-aeb079d48665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088073866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.4088073866
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.3361405908
Short name T597
Test name
Test status
Simulation time 342649583 ps
CPU time 4 seconds
Started Mar 28 03:22:27 PM PDT 24
Finished Mar 28 03:22:32 PM PDT 24
Peak memory 224804 kb
Host smart-7a09fd12-4b48-4972-a153-4c9d0a4dd8db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361405908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.3361405908
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.1844634548
Short name T762
Test name
Test status
Simulation time 18456710955 ps
CPU time 24.84 seconds
Started Mar 28 03:22:28 PM PDT 24
Finished Mar 28 03:22:53 PM PDT 24
Peak memory 226488 kb
Host smart-e6909e17-17b8-49dc-b795-be1967d28bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844634548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.1844634548
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.4127332670
Short name T773
Test name
Test status
Simulation time 2003807512 ps
CPU time 7.85 seconds
Started Mar 28 03:22:29 PM PDT 24
Finished Mar 28 03:22:38 PM PDT 24
Peak memory 233032 kb
Host smart-0f03df55-cab7-49eb-8539-4ac75ba33f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127332670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.4127332670
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_ram_cfg.560637100
Short name T537
Test name
Test status
Simulation time 46587095 ps
CPU time 0.72 seconds
Started Mar 28 03:22:26 PM PDT 24
Finished Mar 28 03:22:27 PM PDT 24
Peak memory 216564 kb
Host smart-11dc414a-6b3a-4c4c-a458-13797fe22a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560637100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_ram_cfg.560637100
Directory /workspace/13.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.2685443992
Short name T118
Test name
Test status
Simulation time 1127892696 ps
CPU time 6.06 seconds
Started Mar 28 03:22:25 PM PDT 24
Finished Mar 28 03:22:31 PM PDT 24
Peak memory 219076 kb
Host smart-1b82d3f0-5713-427b-8322-fa45f007b65d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2685443992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.2685443992
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.3713763951
Short name T558
Test name
Test status
Simulation time 10179269099 ps
CPU time 59.66 seconds
Started Mar 28 03:22:26 PM PDT 24
Finished Mar 28 03:23:26 PM PDT 24
Peak memory 216764 kb
Host smart-dc3d875c-ab0f-4327-8368-35a1a635bb97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713763951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.3713763951
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.2923456710
Short name T682
Test name
Test status
Simulation time 835766941 ps
CPU time 5.53 seconds
Started Mar 28 03:22:25 PM PDT 24
Finished Mar 28 03:22:31 PM PDT 24
Peak memory 216640 kb
Host smart-bdf269eb-6760-4a1d-aa4a-21e9a9b5f9f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923456710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.2923456710
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.118401665
Short name T860
Test name
Test status
Simulation time 81273538 ps
CPU time 1.1 seconds
Started Mar 28 03:22:27 PM PDT 24
Finished Mar 28 03:22:28 PM PDT 24
Peak memory 207436 kb
Host smart-5d48c50d-4300-4f87-9b73-fced6bbf7765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118401665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.118401665
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.1038029430
Short name T306
Test name
Test status
Simulation time 32182700 ps
CPU time 0.74 seconds
Started Mar 28 03:22:28 PM PDT 24
Finished Mar 28 03:22:29 PM PDT 24
Peak memory 206096 kb
Host smart-565cd96f-1d26-4138-a7e3-5da391b746d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038029430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.1038029430
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.3265315583
Short name T748
Test name
Test status
Simulation time 26566946098 ps
CPU time 27.52 seconds
Started Mar 28 03:22:31 PM PDT 24
Finished Mar 28 03:22:59 PM PDT 24
Peak memory 246988 kb
Host smart-6744dcd7-38bd-4224-8a42-4a880cc27c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265315583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.3265315583
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.1553226440
Short name T634
Test name
Test status
Simulation time 14021117 ps
CPU time 0.75 seconds
Started Mar 28 03:22:35 PM PDT 24
Finished Mar 28 03:22:36 PM PDT 24
Peak memory 205856 kb
Host smart-25d8a322-c4b3-46ff-9d9f-86049e9d39b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553226440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
1553226440
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.2064232425
Short name T59
Test name
Test status
Simulation time 99706382 ps
CPU time 3.18 seconds
Started Mar 28 03:22:31 PM PDT 24
Finished Mar 28 03:22:35 PM PDT 24
Peak memory 234128 kb
Host smart-089c11ff-4b55-4d57-a9e8-9985e0a5e863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064232425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.2064232425
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.798124574
Short name T595
Test name
Test status
Simulation time 21286355 ps
CPU time 0.75 seconds
Started Mar 28 03:22:27 PM PDT 24
Finished Mar 28 03:22:28 PM PDT 24
Peak memory 207268 kb
Host smart-98d13af5-3d4a-4837-ae2d-ba40afb28c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798124574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.798124574
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.161669851
Short name T135
Test name
Test status
Simulation time 78593294360 ps
CPU time 213.62 seconds
Started Mar 28 03:22:24 PM PDT 24
Finished Mar 28 03:25:58 PM PDT 24
Peak memory 251692 kb
Host smart-2dcf0dfb-76db-4168-bc97-9244612ccabc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161669851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.161669851
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.2172778952
Short name T823
Test name
Test status
Simulation time 10470124692 ps
CPU time 20.29 seconds
Started Mar 28 03:22:28 PM PDT 24
Finished Mar 28 03:22:50 PM PDT 24
Peak memory 233296 kb
Host smart-7d854304-4145-4938-9745-0990f7aa6477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172778952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.2172778952
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.1302950198
Short name T898
Test name
Test status
Simulation time 74321078185 ps
CPU time 510.24 seconds
Started Mar 28 03:22:30 PM PDT 24
Finished Mar 28 03:31:01 PM PDT 24
Peak memory 265832 kb
Host smart-ead82698-a87d-45ff-8ef6-d3c2063a20b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302950198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.1302950198
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.395466132
Short name T450
Test name
Test status
Simulation time 4665591721 ps
CPU time 27.87 seconds
Started Mar 28 03:22:25 PM PDT 24
Finished Mar 28 03:22:53 PM PDT 24
Peak memory 235096 kb
Host smart-d941d93d-a15c-444d-af8c-72c29c71edfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395466132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.395466132
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.2746421819
Short name T958
Test name
Test status
Simulation time 265815354 ps
CPU time 3.25 seconds
Started Mar 28 03:22:29 PM PDT 24
Finished Mar 28 03:22:33 PM PDT 24
Peak memory 234900 kb
Host smart-2e00c9ca-b248-4b4c-bd4b-a6abd2831a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746421819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.2746421819
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.3132644193
Short name T407
Test name
Test status
Simulation time 232076199 ps
CPU time 4.4 seconds
Started Mar 28 03:22:27 PM PDT 24
Finished Mar 28 03:22:31 PM PDT 24
Peak memory 227300 kb
Host smart-38e01997-be3b-4175-8584-a87edf09b75b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132644193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.3132644193
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.3178671290
Short name T25
Test name
Test status
Simulation time 9636692281 ps
CPU time 8.39 seconds
Started Mar 28 03:22:26 PM PDT 24
Finished Mar 28 03:22:35 PM PDT 24
Peak memory 221516 kb
Host smart-bc143626-addf-4803-a3c0-cd2f17151579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178671290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.3178671290
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.3926400615
Short name T325
Test name
Test status
Simulation time 312314836 ps
CPU time 3.74 seconds
Started Mar 28 03:22:24 PM PDT 24
Finished Mar 28 03:22:28 PM PDT 24
Peak memory 219988 kb
Host smart-8cfc0c11-30f4-4e08-a12d-600cdb4ef53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926400615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.3926400615
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_ram_cfg.1318275359
Short name T51
Test name
Test status
Simulation time 22020914 ps
CPU time 0.77 seconds
Started Mar 28 03:22:27 PM PDT 24
Finished Mar 28 03:22:28 PM PDT 24
Peak memory 216448 kb
Host smart-b9a5d6e9-3f19-4b0d-afb5-33fc5608e138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318275359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_ram_cfg.1318275359
Directory /workspace/14.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.3015489299
Short name T878
Test name
Test status
Simulation time 245129852 ps
CPU time 3.13 seconds
Started Mar 28 03:22:30 PM PDT 24
Finished Mar 28 03:22:34 PM PDT 24
Peak memory 221164 kb
Host smart-578fee5e-ef4f-429f-ba99-45b69e63f239
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3015489299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.3015489299
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.1665825926
Short name T618
Test name
Test status
Simulation time 80186756 ps
CPU time 1.05 seconds
Started Mar 28 03:22:27 PM PDT 24
Finished Mar 28 03:22:28 PM PDT 24
Peak memory 215888 kb
Host smart-f7c6aee9-71e4-4a0a-894b-91e395e20a83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665825926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.1665825926
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.842647276
Short name T400
Test name
Test status
Simulation time 13357625682 ps
CPU time 32.31 seconds
Started Mar 28 03:22:27 PM PDT 24
Finished Mar 28 03:22:59 PM PDT 24
Peak memory 220764 kb
Host smart-ea256d3f-e4d9-41ff-b759-a3a86cd95008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842647276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.842647276
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.2869789496
Short name T579
Test name
Test status
Simulation time 13855058937 ps
CPU time 11.96 seconds
Started Mar 28 03:22:28 PM PDT 24
Finished Mar 28 03:22:42 PM PDT 24
Peak memory 216580 kb
Host smart-b22810a7-3e22-4824-a926-d83f7dec22fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869789496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.2869789496
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.2215126404
Short name T290
Test name
Test status
Simulation time 706107395 ps
CPU time 6.2 seconds
Started Mar 28 03:22:29 PM PDT 24
Finished Mar 28 03:22:36 PM PDT 24
Peak memory 216616 kb
Host smart-6ce2608d-1a16-42b2-b20c-8eae73228403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215126404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.2215126404
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.3191188017
Short name T339
Test name
Test status
Simulation time 325426943 ps
CPU time 0.83 seconds
Started Mar 28 03:22:27 PM PDT 24
Finished Mar 28 03:22:28 PM PDT 24
Peak memory 206188 kb
Host smart-f8d05c86-8eb4-48df-85d8-fd3b4d2c9b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191188017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.3191188017
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.1896679140
Short name T435
Test name
Test status
Simulation time 96673084965 ps
CPU time 16.69 seconds
Started Mar 28 03:22:25 PM PDT 24
Finished Mar 28 03:22:42 PM PDT 24
Peak memory 219380 kb
Host smart-f168b6c5-4f58-4f8d-8aa9-894028d19d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896679140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.1896679140
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.3760723215
Short name T655
Test name
Test status
Simulation time 13050747 ps
CPU time 0.74 seconds
Started Mar 28 03:22:27 PM PDT 24
Finished Mar 28 03:22:28 PM PDT 24
Peak memory 205924 kb
Host smart-9bfd674e-5dc3-4874-bd35-72ba0cfc1eac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760723215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
3760723215
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.2011623099
Short name T197
Test name
Test status
Simulation time 999639262 ps
CPU time 4.61 seconds
Started Mar 28 03:22:27 PM PDT 24
Finished Mar 28 03:22:31 PM PDT 24
Peak memory 218916 kb
Host smart-05c723b9-90b2-4b4c-8748-47001988c3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011623099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.2011623099
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.3262184333
Short name T785
Test name
Test status
Simulation time 51899140 ps
CPU time 0.8 seconds
Started Mar 28 03:22:27 PM PDT 24
Finished Mar 28 03:22:28 PM PDT 24
Peak memory 206992 kb
Host smart-52987cc2-e04c-4840-8092-62e80617c17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262184333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.3262184333
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.3350056974
Short name T137
Test name
Test status
Simulation time 4122655324 ps
CPU time 16.48 seconds
Started Mar 28 03:22:33 PM PDT 24
Finished Mar 28 03:22:50 PM PDT 24
Peak memory 241404 kb
Host smart-1eda2af8-2f39-47ff-8c7f-fdd6c193c366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350056974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.3350056974
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.4241045065
Short name T317
Test name
Test status
Simulation time 7542894599 ps
CPU time 100.18 seconds
Started Mar 28 03:22:29 PM PDT 24
Finished Mar 28 03:24:10 PM PDT 24
Peak memory 249648 kb
Host smart-e2de3aa7-d1db-4b5d-8036-2f074d92d66c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241045065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.4241045065
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.2547879146
Short name T656
Test name
Test status
Simulation time 8539727085 ps
CPU time 40.56 seconds
Started Mar 28 03:22:28 PM PDT 24
Finished Mar 28 03:23:10 PM PDT 24
Peak memory 241444 kb
Host smart-0aa2365f-aa0a-4a4b-a61e-47788faafae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547879146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.2547879146
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.2751587135
Short name T177
Test name
Test status
Simulation time 745584187 ps
CPU time 4.59 seconds
Started Mar 28 03:22:28 PM PDT 24
Finished Mar 28 03:22:32 PM PDT 24
Peak memory 233648 kb
Host smart-56b5c267-0263-4276-9334-38219110f0bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751587135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.2751587135
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.528453851
Short name T557
Test name
Test status
Simulation time 36369670305 ps
CPU time 34.54 seconds
Started Mar 28 03:22:27 PM PDT 24
Finished Mar 28 03:23:02 PM PDT 24
Peak memory 250732 kb
Host smart-381d16b2-8acb-49c8-9927-92f51d8cfc1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528453851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.528453851
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.3517394442
Short name T237
Test name
Test status
Simulation time 29162657819 ps
CPU time 19.34 seconds
Started Mar 28 03:22:26 PM PDT 24
Finished Mar 28 03:22:46 PM PDT 24
Peak memory 219508 kb
Host smart-d440ef93-362b-422d-a13f-351d5325a0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517394442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.3517394442
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.642072384
Short name T212
Test name
Test status
Simulation time 4052694292 ps
CPU time 7.3 seconds
Started Mar 28 03:22:29 PM PDT 24
Finished Mar 28 03:22:37 PM PDT 24
Peak memory 219320 kb
Host smart-0e3271f2-8950-4aef-ac2f-609a37dc9153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642072384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.642072384
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_ram_cfg.1808096807
Short name T344
Test name
Test status
Simulation time 15680105 ps
CPU time 0.76 seconds
Started Mar 28 03:22:27 PM PDT 24
Finished Mar 28 03:22:28 PM PDT 24
Peak memory 216568 kb
Host smart-8a1869d1-94a1-4b90-bbe1-02a221997f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808096807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_ram_cfg.1808096807
Directory /workspace/15.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.3669077949
Short name T391
Test name
Test status
Simulation time 5113842169 ps
CPU time 6.03 seconds
Started Mar 28 03:22:32 PM PDT 24
Finished Mar 28 03:22:38 PM PDT 24
Peak memory 223192 kb
Host smart-b857134f-16c6-4b92-b8ec-bba0a78e6f07
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3669077949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.3669077949
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.4184575208
Short name T127
Test name
Test status
Simulation time 5119543021 ps
CPU time 34.33 seconds
Started Mar 28 03:22:29 PM PDT 24
Finished Mar 28 03:23:04 PM PDT 24
Peak memory 222744 kb
Host smart-b6560314-152b-444f-b2e2-5d68d9239cb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184575208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.4184575208
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.2440852142
Short name T906
Test name
Test status
Simulation time 28163960303 ps
CPU time 38.59 seconds
Started Mar 28 03:22:29 PM PDT 24
Finished Mar 28 03:23:08 PM PDT 24
Peak memory 216836 kb
Host smart-02f5607f-349b-49c1-a1aa-a65e2141df99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440852142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.2440852142
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.2975959568
Short name T310
Test name
Test status
Simulation time 10098465290 ps
CPU time 7.94 seconds
Started Mar 28 03:22:28 PM PDT 24
Finished Mar 28 03:22:36 PM PDT 24
Peak memory 216800 kb
Host smart-9809c20d-fe68-4577-94a6-ea3ed022dd24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975959568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.2975959568
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.3862750541
Short name T395
Test name
Test status
Simulation time 800526136 ps
CPU time 3.81 seconds
Started Mar 28 03:22:25 PM PDT 24
Finished Mar 28 03:22:30 PM PDT 24
Peak memory 216720 kb
Host smart-b297f531-edfa-47f3-a22d-6f886cf4aa77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862750541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.3862750541
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.1965091768
Short name T279
Test name
Test status
Simulation time 248105078 ps
CPU time 1.28 seconds
Started Mar 28 03:22:26 PM PDT 24
Finished Mar 28 03:22:27 PM PDT 24
Peak memory 207180 kb
Host smart-e25d02de-fa6c-43d7-8fce-c4e6f728193e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965091768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.1965091768
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.4220572117
Short name T451
Test name
Test status
Simulation time 3372654557 ps
CPU time 10.75 seconds
Started Mar 28 03:22:32 PM PDT 24
Finished Mar 28 03:22:43 PM PDT 24
Peak memory 227660 kb
Host smart-3b082658-29ed-48ba-be16-25115e2f0b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220572117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.4220572117
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.1565421453
Short name T867
Test name
Test status
Simulation time 14374009 ps
CPU time 0.71 seconds
Started Mar 28 03:22:31 PM PDT 24
Finished Mar 28 03:22:32 PM PDT 24
Peak memory 205276 kb
Host smart-2edb8e34-2940-4476-814e-d3c1b2150be1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565421453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
1565421453
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.800963280
Short name T543
Test name
Test status
Simulation time 1628112954 ps
CPU time 7.29 seconds
Started Mar 28 03:22:36 PM PDT 24
Finished Mar 28 03:22:43 PM PDT 24
Peak memory 220260 kb
Host smart-caeab85c-81d6-43d7-84bc-5a6f08e4780d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800963280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.800963280
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.525658629
Short name T761
Test name
Test status
Simulation time 18517387 ps
CPU time 0.79 seconds
Started Mar 28 03:22:28 PM PDT 24
Finished Mar 28 03:22:30 PM PDT 24
Peak memory 207020 kb
Host smart-5895a3be-17cb-49da-818e-50d8e1ded084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525658629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.525658629
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.2507503325
Short name T782
Test name
Test status
Simulation time 44216380690 ps
CPU time 219.38 seconds
Started Mar 28 03:22:32 PM PDT 24
Finished Mar 28 03:26:11 PM PDT 24
Peak memory 253280 kb
Host smart-a92b70ee-d032-4c2b-8533-9c39e71afb08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507503325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.2507503325
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.2194945188
Short name T115
Test name
Test status
Simulation time 28439541173 ps
CPU time 236.63 seconds
Started Mar 28 03:22:31 PM PDT 24
Finished Mar 28 03:26:29 PM PDT 24
Peak memory 256620 kb
Host smart-7bf73539-0895-4ff7-9d12-d5df1d435206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194945188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.2194945188
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.2790631554
Short name T886
Test name
Test status
Simulation time 53502870529 ps
CPU time 359.08 seconds
Started Mar 28 03:22:33 PM PDT 24
Finished Mar 28 03:28:33 PM PDT 24
Peak memory 261856 kb
Host smart-d96c8a93-3595-4b56-b6a6-736529fc005d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790631554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.2790631554
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.1030814645
Short name T806
Test name
Test status
Simulation time 26838350359 ps
CPU time 18.11 seconds
Started Mar 28 03:22:32 PM PDT 24
Finished Mar 28 03:22:50 PM PDT 24
Peak memory 244884 kb
Host smart-383265d7-7b58-4bd1-ab39-4b755c0e7250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030814645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.1030814645
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.3184924914
Short name T457
Test name
Test status
Simulation time 141757496 ps
CPU time 3.2 seconds
Started Mar 28 03:22:24 PM PDT 24
Finished Mar 28 03:22:28 PM PDT 24
Peak memory 219168 kb
Host smart-66e4dea6-3055-47b6-8194-fa9427a885b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184924914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.3184924914
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.902273090
Short name T788
Test name
Test status
Simulation time 32965823988 ps
CPU time 8.25 seconds
Started Mar 28 03:22:28 PM PDT 24
Finished Mar 28 03:22:36 PM PDT 24
Peak memory 220820 kb
Host smart-e92011c3-4639-4a72-8981-d59a7eb4b6d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902273090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.902273090
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.1488075733
Short name T622
Test name
Test status
Simulation time 66380383834 ps
CPU time 22.71 seconds
Started Mar 28 03:22:29 PM PDT 24
Finished Mar 28 03:22:52 PM PDT 24
Peak memory 234504 kb
Host smart-87d532fe-81b8-420f-bb0e-b64c2b319c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488075733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.1488075733
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.2711109978
Short name T43
Test name
Test status
Simulation time 11218392702 ps
CPU time 25.03 seconds
Started Mar 28 03:22:29 PM PDT 24
Finished Mar 28 03:22:55 PM PDT 24
Peak memory 239896 kb
Host smart-0c54d316-74e0-4369-977c-fe8ee138d6a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711109978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.2711109978
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_ram_cfg.1964676834
Short name T923
Test name
Test status
Simulation time 22584479 ps
CPU time 0.75 seconds
Started Mar 28 03:22:29 PM PDT 24
Finished Mar 28 03:22:31 PM PDT 24
Peak memory 216460 kb
Host smart-3d25e4de-b66f-47c8-8ce5-07e7ddeb928a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964676834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_ram_cfg.1964676834
Directory /workspace/16.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.3190429669
Short name T965
Test name
Test status
Simulation time 95415663 ps
CPU time 3.77 seconds
Started Mar 28 03:22:36 PM PDT 24
Finished Mar 28 03:22:40 PM PDT 24
Peak memory 223372 kb
Host smart-13af3416-0f12-4ca5-aea8-3213b1e4b450
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3190429669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.3190429669
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.571018667
Short name T38
Test name
Test status
Simulation time 99297689035 ps
CPU time 516.25 seconds
Started Mar 28 03:22:33 PM PDT 24
Finished Mar 28 03:31:10 PM PDT 24
Peak memory 284616 kb
Host smart-5ae9fc39-c0a8-49b7-8a2f-60660f8dcda8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571018667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stres
s_all.571018667
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.3381030236
Short name T540
Test name
Test status
Simulation time 14895158574 ps
CPU time 76.81 seconds
Started Mar 28 03:22:29 PM PDT 24
Finished Mar 28 03:23:47 PM PDT 24
Peak memory 216764 kb
Host smart-e958999c-d73d-4212-afb2-50ba8d0379a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381030236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.3381030236
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.1506887518
Short name T452
Test name
Test status
Simulation time 32924265964 ps
CPU time 5.8 seconds
Started Mar 28 03:22:31 PM PDT 24
Finished Mar 28 03:22:37 PM PDT 24
Peak memory 216768 kb
Host smart-263a3d8e-c2a9-44a9-8ca6-bf84943f12c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506887518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.1506887518
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.1072771510
Short name T862
Test name
Test status
Simulation time 46074810 ps
CPU time 0.75 seconds
Started Mar 28 03:22:32 PM PDT 24
Finished Mar 28 03:22:34 PM PDT 24
Peak memory 206164 kb
Host smart-cf44c5bb-8f0c-4ea7-84c8-14cb6dff138b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072771510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.1072771510
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.1807038989
Short name T469
Test name
Test status
Simulation time 116576816 ps
CPU time 0.93 seconds
Started Mar 28 03:22:28 PM PDT 24
Finished Mar 28 03:22:31 PM PDT 24
Peak memory 206096 kb
Host smart-9827b6ce-7915-498a-b437-8aeacccd39dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807038989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.1807038989
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.3085279655
Short name T633
Test name
Test status
Simulation time 62566311967 ps
CPU time 34.55 seconds
Started Mar 28 03:22:33 PM PDT 24
Finished Mar 28 03:23:08 PM PDT 24
Peak memory 228904 kb
Host smart-9c416614-7ab4-4270-af9b-1d6306f87c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085279655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.3085279655
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.4264945420
Short name T598
Test name
Test status
Simulation time 11090438 ps
CPU time 0.73 seconds
Started Mar 28 03:22:38 PM PDT 24
Finished Mar 28 03:22:39 PM PDT 24
Peak memory 205828 kb
Host smart-6ad6b09a-3c5f-4f0d-b6c3-098a100457bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264945420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
4264945420
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.2037411605
Short name T210
Test name
Test status
Simulation time 167788348 ps
CPU time 2.93 seconds
Started Mar 28 03:22:37 PM PDT 24
Finished Mar 28 03:22:40 PM PDT 24
Peak memory 219760 kb
Host smart-55f7c2da-142e-4621-b6e3-077d1e9246bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037411605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.2037411605
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.3190854256
Short name T891
Test name
Test status
Simulation time 14487970 ps
CPU time 0.75 seconds
Started Mar 28 03:22:34 PM PDT 24
Finished Mar 28 03:22:35 PM PDT 24
Peak memory 205996 kb
Host smart-5cf3c56c-d2c1-41e0-aec8-d96b2cfcbc57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190854256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.3190854256
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.1478139114
Short name T518
Test name
Test status
Simulation time 3735187183 ps
CPU time 59.74 seconds
Started Mar 28 03:22:33 PM PDT 24
Finished Mar 28 03:23:33 PM PDT 24
Peak memory 252656 kb
Host smart-0692967f-0966-42a6-8382-829a982e1eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478139114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.1478139114
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.3101440877
Short name T440
Test name
Test status
Simulation time 267554034725 ps
CPU time 454.87 seconds
Started Mar 28 03:22:33 PM PDT 24
Finished Mar 28 03:30:08 PM PDT 24
Peak memory 261604 kb
Host smart-e99c3a92-fb4a-41c4-9572-04551380ef55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101440877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.3101440877
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.2785283609
Short name T8
Test name
Test status
Simulation time 939663714 ps
CPU time 9.28 seconds
Started Mar 28 03:22:33 PM PDT 24
Finished Mar 28 03:22:43 PM PDT 24
Peak memory 241276 kb
Host smart-dd483163-a4ba-4e28-a4f1-f5239a39f499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785283609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.2785283609
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.3549530388
Short name T594
Test name
Test status
Simulation time 3576926884 ps
CPU time 7.55 seconds
Started Mar 28 03:22:31 PM PDT 24
Finished Mar 28 03:22:39 PM PDT 24
Peak memory 235368 kb
Host smart-1c884e21-3213-4e88-a6b4-414f3495e8af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549530388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.3549530388
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.1227992876
Short name T504
Test name
Test status
Simulation time 1744102026 ps
CPU time 7.8 seconds
Started Mar 28 03:22:37 PM PDT 24
Finished Mar 28 03:22:44 PM PDT 24
Peak memory 224632 kb
Host smart-b666f46e-6e35-497d-b18b-d68eefbbd771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227992876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.1227992876
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.3192461695
Short name T183
Test name
Test status
Simulation time 159443780 ps
CPU time 3.41 seconds
Started Mar 28 03:22:37 PM PDT 24
Finished Mar 28 03:22:40 PM PDT 24
Peak memory 233620 kb
Host smart-3655841d-7f92-45ef-a637-7ca5dec63ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192461695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.3192461695
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.1983455865
Short name T845
Test name
Test status
Simulation time 10676030124 ps
CPU time 14.5 seconds
Started Mar 28 03:22:28 PM PDT 24
Finished Mar 28 03:22:43 PM PDT 24
Peak memory 248680 kb
Host smart-cf5acd37-1e6f-47e3-bc16-c9ac5b44d0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983455865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.1983455865
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_ram_cfg.667227812
Short name T517
Test name
Test status
Simulation time 35474387 ps
CPU time 0.71 seconds
Started Mar 28 03:22:32 PM PDT 24
Finished Mar 28 03:22:33 PM PDT 24
Peak memory 216464 kb
Host smart-d91c83a8-3c11-4ea5-8941-c90c4099699f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667227812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_ram_cfg.667227812
Directory /workspace/17.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.3893645575
Short name T909
Test name
Test status
Simulation time 3323833730 ps
CPU time 5.68 seconds
Started Mar 28 03:22:32 PM PDT 24
Finished Mar 28 03:22:38 PM PDT 24
Peak memory 223616 kb
Host smart-4b0f6b69-9381-4e28-8ede-5796c4cbd6ee
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3893645575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.3893645575
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.245184910
Short name T775
Test name
Test status
Simulation time 5417318483 ps
CPU time 30.13 seconds
Started Mar 28 03:22:32 PM PDT 24
Finished Mar 28 03:23:02 PM PDT 24
Peak memory 216724 kb
Host smart-51240f9a-fa90-442f-981f-dc90dd64b51b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245184910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.245184910
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.412515109
Short name T514
Test name
Test status
Simulation time 10636134801 ps
CPU time 10.07 seconds
Started Mar 28 03:22:32 PM PDT 24
Finished Mar 28 03:22:43 PM PDT 24
Peak memory 216544 kb
Host smart-efc43f7a-2ad1-4ba4-9ed9-1d03ff694594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412515109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.412515109
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.1212748270
Short name T879
Test name
Test status
Simulation time 20470592 ps
CPU time 0.87 seconds
Started Mar 28 03:22:32 PM PDT 24
Finished Mar 28 03:22:33 PM PDT 24
Peak memory 206984 kb
Host smart-6545652d-0397-48fb-b93d-db4b4a7ba8b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212748270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.1212748270
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.4212019720
Short name T490
Test name
Test status
Simulation time 226001712 ps
CPU time 0.93 seconds
Started Mar 28 03:22:32 PM PDT 24
Finished Mar 28 03:22:34 PM PDT 24
Peak memory 207200 kb
Host smart-fac0026e-5933-44f1-9205-d414543af3aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212019720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.4212019720
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.4201532122
Short name T208
Test name
Test status
Simulation time 2784693441 ps
CPU time 8.44 seconds
Started Mar 28 03:22:37 PM PDT 24
Finished Mar 28 03:22:45 PM PDT 24
Peak memory 218232 kb
Host smart-c0c8f57d-e303-4f49-a143-6213ebf58459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201532122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.4201532122
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.68878822
Short name T47
Test name
Test status
Simulation time 35310116 ps
CPU time 0.72 seconds
Started Mar 28 03:22:29 PM PDT 24
Finished Mar 28 03:22:31 PM PDT 24
Peak memory 205860 kb
Host smart-bbf0f66d-c5c7-45d4-957c-854231b30af9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68878822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.68878822
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.1436635557
Short name T198
Test name
Test status
Simulation time 728714522 ps
CPU time 3.26 seconds
Started Mar 28 03:22:28 PM PDT 24
Finished Mar 28 03:22:33 PM PDT 24
Peak memory 219332 kb
Host smart-f62b819f-29c6-4e87-a72a-eb3b64969325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436635557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.1436635557
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.2412385949
Short name T627
Test name
Test status
Simulation time 60884161 ps
CPU time 0.83 seconds
Started Mar 28 03:22:35 PM PDT 24
Finished Mar 28 03:22:36 PM PDT 24
Peak memory 206000 kb
Host smart-b2d31c8f-ef64-4dcb-84e2-1f0b4c326df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412385949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2412385949
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.4049173994
Short name T954
Test name
Test status
Simulation time 12344581130 ps
CPU time 49.92 seconds
Started Mar 28 03:22:28 PM PDT 24
Finished Mar 28 03:23:19 PM PDT 24
Peak memory 249732 kb
Host smart-39fb0813-53f8-4664-a080-f48a43f621d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049173994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.4049173994
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.662680620
Short name T586
Test name
Test status
Simulation time 75867376565 ps
CPU time 137.76 seconds
Started Mar 28 03:22:27 PM PDT 24
Finished Mar 28 03:24:45 PM PDT 24
Peak memory 250492 kb
Host smart-d5427791-8e2f-45cd-a235-f60727a2091b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662680620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idle
.662680620
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.3551944679
Short name T459
Test name
Test status
Simulation time 5528936802 ps
CPU time 13.9 seconds
Started Mar 28 03:22:28 PM PDT 24
Finished Mar 28 03:22:42 PM PDT 24
Peak memory 238556 kb
Host smart-0098c126-3760-4631-9f67-119a7789f981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551944679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.3551944679
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.993164464
Short name T550
Test name
Test status
Simulation time 641891690 ps
CPU time 5.03 seconds
Started Mar 28 03:22:28 PM PDT 24
Finished Mar 28 03:22:33 PM PDT 24
Peak memory 234136 kb
Host smart-b9186fab-08af-4169-88f9-dbf781a39ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993164464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.993164464
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.3784322412
Short name T838
Test name
Test status
Simulation time 5562243766 ps
CPU time 14.52 seconds
Started Mar 28 03:22:29 PM PDT 24
Finished Mar 28 03:22:44 PM PDT 24
Peak memory 228812 kb
Host smart-b4ffd422-4a97-4682-9ff0-3571471972d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784322412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.3784322412
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.265042401
Short name T167
Test name
Test status
Simulation time 1017198216 ps
CPU time 7.47 seconds
Started Mar 28 03:22:29 PM PDT 24
Finished Mar 28 03:22:37 PM PDT 24
Peak memory 218988 kb
Host smart-807520c4-dd7f-4dc1-8424-dd7909d3b3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265042401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap
.265042401
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.3503607489
Short name T496
Test name
Test status
Simulation time 329230622 ps
CPU time 2.84 seconds
Started Mar 28 03:22:29 PM PDT 24
Finished Mar 28 03:22:33 PM PDT 24
Peak memory 218880 kb
Host smart-7b2c0f46-25ca-49d9-b5b1-3fa867306ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503607489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.3503607489
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_ram_cfg.2360207914
Short name T928
Test name
Test status
Simulation time 16424774 ps
CPU time 0.76 seconds
Started Mar 28 03:22:28 PM PDT 24
Finished Mar 28 03:22:29 PM PDT 24
Peak memory 216560 kb
Host smart-3570cd75-b023-4943-b743-56bae94afb50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360207914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_ram_cfg.2360207914
Directory /workspace/18.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.1701509967
Short name T722
Test name
Test status
Simulation time 4818353865 ps
CPU time 5.1 seconds
Started Mar 28 03:22:28 PM PDT 24
Finished Mar 28 03:22:35 PM PDT 24
Peak memory 223672 kb
Host smart-39bfe19c-eef9-49e5-8d63-54ce5a0556bb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1701509967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.1701509967
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.1592820558
Short name T131
Test name
Test status
Simulation time 815282143813 ps
CPU time 336.76 seconds
Started Mar 28 03:22:33 PM PDT 24
Finished Mar 28 03:28:11 PM PDT 24
Peak memory 268632 kb
Host smart-34276f0a-269d-43cf-9ab8-33b8366b85c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592820558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.1592820558
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.3645314581
Short name T631
Test name
Test status
Simulation time 9687437838 ps
CPU time 50.94 seconds
Started Mar 28 03:22:35 PM PDT 24
Finished Mar 28 03:23:26 PM PDT 24
Peak memory 216832 kb
Host smart-263eded3-f6ab-4f54-83af-54b2fbf74119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645314581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3645314581
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.297791559
Short name T357
Test name
Test status
Simulation time 10450223250 ps
CPU time 32.42 seconds
Started Mar 28 03:22:34 PM PDT 24
Finished Mar 28 03:23:07 PM PDT 24
Peak memory 216796 kb
Host smart-9213c5e6-3c42-4c02-8a80-07cca330fd03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297791559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.297791559
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.4268194656
Short name T856
Test name
Test status
Simulation time 526457047 ps
CPU time 1.97 seconds
Started Mar 28 03:22:29 PM PDT 24
Finished Mar 28 03:22:32 PM PDT 24
Peak memory 216700 kb
Host smart-dac98acb-06cf-42b3-893a-a9e52ec9443c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268194656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.4268194656
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.4280008823
Short name T578
Test name
Test status
Simulation time 105736963 ps
CPU time 1.1 seconds
Started Mar 28 03:22:28 PM PDT 24
Finished Mar 28 03:22:29 PM PDT 24
Peak memory 207108 kb
Host smart-cb4d70dc-2d20-44a8-ac9a-e052aab2e174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280008823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.4280008823
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.2762436007
Short name T951
Test name
Test status
Simulation time 839123987 ps
CPU time 4.54 seconds
Started Mar 28 03:22:29 PM PDT 24
Finished Mar 28 03:22:34 PM PDT 24
Peak memory 234536 kb
Host smart-59b1585d-dd8e-40d9-9576-1a5eba89add0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762436007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.2762436007
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.1475034001
Short name T515
Test name
Test status
Simulation time 13725672 ps
CPU time 0.72 seconds
Started Mar 28 03:22:33 PM PDT 24
Finished Mar 28 03:22:34 PM PDT 24
Peak memory 205264 kb
Host smart-1281b71a-5d33-427a-b4b2-52ede0f31f6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475034001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
1475034001
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.327852865
Short name T811
Test name
Test status
Simulation time 468536562 ps
CPU time 3.26 seconds
Started Mar 28 03:22:32 PM PDT 24
Finished Mar 28 03:22:35 PM PDT 24
Peak memory 235448 kb
Host smart-7c10cc2f-b43a-40d1-afb8-d7154b704857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327852865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.327852865
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.375244476
Short name T309
Test name
Test status
Simulation time 29089132 ps
CPU time 0.8 seconds
Started Mar 28 03:22:28 PM PDT 24
Finished Mar 28 03:22:31 PM PDT 24
Peak memory 206304 kb
Host smart-052ee1b7-90c1-4d47-be32-1fb81763328b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375244476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.375244476
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.2184708498
Short name T538
Test name
Test status
Simulation time 136941618491 ps
CPU time 73.03 seconds
Started Mar 28 03:22:37 PM PDT 24
Finished Mar 28 03:23:50 PM PDT 24
Peak memory 249136 kb
Host smart-b4cf663b-8270-41fd-8ee8-97a3207b3544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184708498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.2184708498
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.1616964159
Short name T503
Test name
Test status
Simulation time 2690610861 ps
CPU time 59.69 seconds
Started Mar 28 03:22:28 PM PDT 24
Finished Mar 28 03:23:29 PM PDT 24
Peak memory 257856 kb
Host smart-fe726a4f-2b4f-48a4-a7d6-c8560e362c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616964159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.1616964159
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.2616507599
Short name T405
Test name
Test status
Simulation time 9933679238 ps
CPU time 11.54 seconds
Started Mar 28 03:22:35 PM PDT 24
Finished Mar 28 03:22:47 PM PDT 24
Peak memory 231020 kb
Host smart-652fe01e-6508-483a-ac0d-e5be721d3125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616507599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.2616507599
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.2599951611
Short name T501
Test name
Test status
Simulation time 1547185563 ps
CPU time 7.45 seconds
Started Mar 28 03:22:31 PM PDT 24
Finished Mar 28 03:22:39 PM PDT 24
Peak memory 234500 kb
Host smart-e8653074-cebc-4383-990b-784c367b0756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599951611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.2599951611
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.3846466281
Short name T810
Test name
Test status
Simulation time 99388043390 ps
CPU time 47.58 seconds
Started Mar 28 03:22:32 PM PDT 24
Finished Mar 28 03:23:20 PM PDT 24
Peak memory 234624 kb
Host smart-199800b2-0fc1-41c9-a481-c8e067d4f2fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846466281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.3846466281
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.2717962015
Short name T771
Test name
Test status
Simulation time 3852115254 ps
CPU time 6.85 seconds
Started Mar 28 03:22:32 PM PDT 24
Finished Mar 28 03:22:40 PM PDT 24
Peak memory 228364 kb
Host smart-55477ad3-57a0-4e78-8d4c-7fa500df35d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717962015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.2717962015
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.2184119983
Short name T78
Test name
Test status
Simulation time 9951814988 ps
CPU time 16.17 seconds
Started Mar 28 03:22:33 PM PDT 24
Finished Mar 28 03:22:50 PM PDT 24
Peak memory 230520 kb
Host smart-5abe05a2-adb4-48ac-b2df-328e628ab377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184119983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.2184119983
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_ram_cfg.2056481662
Short name T476
Test name
Test status
Simulation time 16926352 ps
CPU time 0.74 seconds
Started Mar 28 03:22:33 PM PDT 24
Finished Mar 28 03:22:35 PM PDT 24
Peak memory 216516 kb
Host smart-14c2e74a-72ee-4c71-a694-37b9777effec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056481662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_ram_cfg.2056481662
Directory /workspace/19.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.2464146436
Short name T577
Test name
Test status
Simulation time 4190868139 ps
CPU time 4.35 seconds
Started Mar 28 03:22:33 PM PDT 24
Finished Mar 28 03:22:38 PM PDT 24
Peak memory 223768 kb
Host smart-e2fd2312-453c-4d4e-bcfc-5525a592407a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2464146436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.2464146436
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.8601995
Short name T9
Test name
Test status
Simulation time 54863103 ps
CPU time 1.13 seconds
Started Mar 28 03:22:32 PM PDT 24
Finished Mar 28 03:22:34 PM PDT 24
Peak memory 207676 kb
Host smart-46df2af6-f93a-442d-a75f-5d94bdc8380b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8601995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stress_
all.8601995
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.2445863273
Short name T824
Test name
Test status
Simulation time 1873395578 ps
CPU time 26.88 seconds
Started Mar 28 03:22:31 PM PDT 24
Finished Mar 28 03:22:58 PM PDT 24
Peak memory 216660 kb
Host smart-fd630470-9780-4ba6-8b15-f27b59dbbfb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445863273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.2445863273
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.2890460388
Short name T841
Test name
Test status
Simulation time 1736688365 ps
CPU time 6.81 seconds
Started Mar 28 03:22:34 PM PDT 24
Finished Mar 28 03:22:41 PM PDT 24
Peak memory 216656 kb
Host smart-b1acf97d-75da-4c3f-ad81-ff5aab57cc52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890460388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.2890460388
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.2990587997
Short name T846
Test name
Test status
Simulation time 75274639 ps
CPU time 1.93 seconds
Started Mar 28 03:22:31 PM PDT 24
Finished Mar 28 03:22:33 PM PDT 24
Peak memory 216688 kb
Host smart-fcf11628-cf13-479d-871d-449ef2c06a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990587997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.2990587997
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.3212076668
Short name T297
Test name
Test status
Simulation time 995565081 ps
CPU time 0.98 seconds
Started Mar 28 03:22:32 PM PDT 24
Finished Mar 28 03:22:33 PM PDT 24
Peak memory 207204 kb
Host smart-1a4d6d6a-18ad-4c13-a09c-865fc6d0b5f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212076668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.3212076668
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.3648948085
Short name T641
Test name
Test status
Simulation time 8065437111 ps
CPU time 17.31 seconds
Started Mar 28 03:22:29 PM PDT 24
Finished Mar 28 03:22:47 PM PDT 24
Peak memory 249324 kb
Host smart-702c069c-2299-45b2-ab59-2bd204f7cb5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648948085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.3648948085
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.720801278
Short name T831
Test name
Test status
Simulation time 13489422 ps
CPU time 0.73 seconds
Started Mar 28 03:21:24 PM PDT 24
Finished Mar 28 03:21:25 PM PDT 24
Peak memory 205860 kb
Host smart-fe9cb0d7-920a-4ea5-aeee-1b6fc829110e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720801278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.720801278
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.1649910945
Short name T423
Test name
Test status
Simulation time 876883457 ps
CPU time 3.73 seconds
Started Mar 28 03:21:27 PM PDT 24
Finished Mar 28 03:21:31 PM PDT 24
Peak memory 219104 kb
Host smart-226cbaaa-836f-4832-801d-903d331d32c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649910945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.1649910945
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.1237784231
Short name T703
Test name
Test status
Simulation time 38194012 ps
CPU time 0.75 seconds
Started Mar 28 03:21:24 PM PDT 24
Finished Mar 28 03:21:25 PM PDT 24
Peak memory 205952 kb
Host smart-2212ecac-c0d9-4440-970f-0f373284e5bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237784231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.1237784231
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.1411069383
Short name T584
Test name
Test status
Simulation time 22051557013 ps
CPU time 43.1 seconds
Started Mar 28 03:21:26 PM PDT 24
Finished Mar 28 03:22:10 PM PDT 24
Peak memory 241324 kb
Host smart-fd4d11c7-fe0b-428a-bd80-42b3067efeca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411069383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.1411069383
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.3449024015
Short name T699
Test name
Test status
Simulation time 21803174169 ps
CPU time 110.01 seconds
Started Mar 28 03:21:31 PM PDT 24
Finished Mar 28 03:23:22 PM PDT 24
Peak memory 257900 kb
Host smart-601b7281-d7f9-4675-81ee-4688c40b0056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449024015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.3449024015
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.2550854226
Short name T820
Test name
Test status
Simulation time 4210694086 ps
CPU time 78.57 seconds
Started Mar 28 03:21:24 PM PDT 24
Finished Mar 28 03:22:43 PM PDT 24
Peak memory 255524 kb
Host smart-72ee23e4-2372-41e8-a010-cd2c5103b1d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550854226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.2550854226
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.1235824191
Short name T953
Test name
Test status
Simulation time 4510899934 ps
CPU time 23.45 seconds
Started Mar 28 03:21:24 PM PDT 24
Finished Mar 28 03:21:48 PM PDT 24
Peak memory 240576 kb
Host smart-d3f2331d-4130-4fcd-9dd3-a98aff513f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235824191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.1235824191
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.3540050250
Short name T532
Test name
Test status
Simulation time 20827492434 ps
CPU time 9.14 seconds
Started Mar 28 03:21:24 PM PDT 24
Finished Mar 28 03:21:33 PM PDT 24
Peak memory 233964 kb
Host smart-f02d9368-0e88-40f6-8abc-b0b17f1af0a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540050250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.3540050250
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.3558515006
Short name T559
Test name
Test status
Simulation time 11097233973 ps
CPU time 36.7 seconds
Started Mar 28 03:21:23 PM PDT 24
Finished Mar 28 03:22:00 PM PDT 24
Peak memory 246188 kb
Host smart-24b58f3a-d79a-4cf4-bcc3-e43761f07087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558515006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.3558515006
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.418839309
Short name T379
Test name
Test status
Simulation time 4179599951 ps
CPU time 14.2 seconds
Started Mar 28 03:21:25 PM PDT 24
Finished Mar 28 03:21:40 PM PDT 24
Peak memory 234680 kb
Host smart-8b237c1d-0db8-409e-8614-ff7ac68cb5b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418839309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.
418839309
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.1918537497
Short name T896
Test name
Test status
Simulation time 710234273 ps
CPU time 7.65 seconds
Started Mar 28 03:21:32 PM PDT 24
Finished Mar 28 03:21:40 PM PDT 24
Peak memory 245392 kb
Host smart-1a85a0aa-6758-4b43-b85d-6eaea0bc6039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918537497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.1918537497
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_ram_cfg.3151701935
Short name T52
Test name
Test status
Simulation time 16602763 ps
CPU time 0.77 seconds
Started Mar 28 03:21:28 PM PDT 24
Finished Mar 28 03:21:29 PM PDT 24
Peak memory 216540 kb
Host smart-864ebb15-f9c2-4774-b5fe-b1f380e23108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151701935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_ram_cfg.3151701935
Directory /workspace/2.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.952128855
Short name T416
Test name
Test status
Simulation time 4819789126 ps
CPU time 6 seconds
Started Mar 28 03:21:27 PM PDT 24
Finished Mar 28 03:21:34 PM PDT 24
Peak memory 223464 kb
Host smart-c1dfff63-0e51-4fec-8d12-f90ebefbf0dd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=952128855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direc
t.952128855
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.2792108386
Short name T54
Test name
Test status
Simulation time 264441013 ps
CPU time 1.13 seconds
Started Mar 28 03:21:31 PM PDT 24
Finished Mar 28 03:21:33 PM PDT 24
Peak memory 235584 kb
Host smart-a2419c4d-0c38-4d08-b9bb-1a21c62d9d8e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792108386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.2792108386
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.778824757
Short name T415
Test name
Test status
Simulation time 38688054 ps
CPU time 0.99 seconds
Started Mar 28 03:21:32 PM PDT 24
Finished Mar 28 03:21:33 PM PDT 24
Peak memory 207044 kb
Host smart-f8c523b4-23b4-4411-b2ef-cef52c85ba80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778824757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stress
_all.778824757
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3826934177
Short name T470
Test name
Test status
Simulation time 8207882412 ps
CPU time 34.68 seconds
Started Mar 28 03:21:30 PM PDT 24
Finished Mar 28 03:22:05 PM PDT 24
Peak memory 216836 kb
Host smart-b7d3d027-db40-485c-a65d-f6405d5645cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826934177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3826934177
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.3148083465
Short name T677
Test name
Test status
Simulation time 7103978080 ps
CPU time 10.12 seconds
Started Mar 28 03:21:27 PM PDT 24
Finished Mar 28 03:21:38 PM PDT 24
Peak memory 216796 kb
Host smart-773985e9-5c7e-448e-9f41-f222598e21cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148083465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.3148083465
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.402617786
Short name T695
Test name
Test status
Simulation time 145583645 ps
CPU time 0.95 seconds
Started Mar 28 03:21:25 PM PDT 24
Finished Mar 28 03:21:26 PM PDT 24
Peak memory 208056 kb
Host smart-556a1143-7276-4cd7-9b13-4258cfaf6d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402617786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.402617786
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.4096068852
Short name T583
Test name
Test status
Simulation time 17522448 ps
CPU time 0.73 seconds
Started Mar 28 03:21:24 PM PDT 24
Finished Mar 28 03:21:25 PM PDT 24
Peak memory 206092 kb
Host smart-8c8f6bb3-0772-46bf-810e-df0a7098e885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096068852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.4096068852
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.2193343435
Short name T394
Test name
Test status
Simulation time 8417724089 ps
CPU time 7.51 seconds
Started Mar 28 03:21:24 PM PDT 24
Finished Mar 28 03:21:32 PM PDT 24
Peak memory 220804 kb
Host smart-59cfc912-0d63-44c7-8aa1-abdb1fc92096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193343435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.2193343435
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.77871079
Short name T303
Test name
Test status
Simulation time 48053080 ps
CPU time 0.71 seconds
Started Mar 28 03:22:49 PM PDT 24
Finished Mar 28 03:22:49 PM PDT 24
Peak memory 205256 kb
Host smart-3b10fc2b-b055-4746-a8f5-b224ac11ab11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77871079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.77871079
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.4096480796
Short name T921
Test name
Test status
Simulation time 2767749325 ps
CPU time 5.65 seconds
Started Mar 28 03:22:50 PM PDT 24
Finished Mar 28 03:22:55 PM PDT 24
Peak memory 234168 kb
Host smart-c0443874-51b4-46cc-8182-e68cdf200212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096480796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.4096480796
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.2120914659
Short name T770
Test name
Test status
Simulation time 13089975 ps
CPU time 0.75 seconds
Started Mar 28 03:22:33 PM PDT 24
Finished Mar 28 03:22:34 PM PDT 24
Peak memory 205984 kb
Host smart-1d23dc12-69d9-4858-a904-ff59433a3638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120914659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.2120914659
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.92026101
Short name T915
Test name
Test status
Simulation time 35625391238 ps
CPU time 168.07 seconds
Started Mar 28 03:22:47 PM PDT 24
Finished Mar 28 03:25:35 PM PDT 24
Peak memory 241436 kb
Host smart-2098daa2-b420-44c6-ba27-81d2a7b5c3e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92026101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.92026101
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.289546989
Short name T657
Test name
Test status
Simulation time 583096323 ps
CPU time 13.04 seconds
Started Mar 28 03:22:50 PM PDT 24
Finished Mar 28 03:23:04 PM PDT 24
Peak memory 249476 kb
Host smart-5ff56f84-5355-41d5-9f5e-d83636df73f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289546989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.289546989
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.186049827
Short name T164
Test name
Test status
Simulation time 1668905250 ps
CPU time 7.96 seconds
Started Mar 28 03:22:55 PM PDT 24
Finished Mar 28 03:23:03 PM PDT 24
Peak memory 224888 kb
Host smart-ece90b40-2b65-45f3-b465-c15ef1be5de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186049827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.186049827
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.91382233
Short name T41
Test name
Test status
Simulation time 2882027167 ps
CPU time 10.2 seconds
Started Mar 28 03:22:48 PM PDT 24
Finished Mar 28 03:22:59 PM PDT 24
Peak memory 220432 kb
Host smart-cf990883-7edd-4080-bddc-47da0a4aa296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91382233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.91382233
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.1678209334
Short name T952
Test name
Test status
Simulation time 12819346271 ps
CPU time 11.11 seconds
Started Mar 28 03:22:37 PM PDT 24
Finished Mar 28 03:22:49 PM PDT 24
Peak memory 236168 kb
Host smart-75dfc60c-5f13-4d7b-b13e-51e30372d1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678209334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.1678209334
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.794871655
Short name T767
Test name
Test status
Simulation time 23258128183 ps
CPU time 14.99 seconds
Started Mar 28 03:22:34 PM PDT 24
Finished Mar 28 03:22:49 PM PDT 24
Peak memory 225000 kb
Host smart-fc1a3a20-5278-4654-82df-6b635da16e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794871655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.794871655
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.2368960208
Short name T807
Test name
Test status
Simulation time 239318788 ps
CPU time 3.43 seconds
Started Mar 28 03:22:49 PM PDT 24
Finished Mar 28 03:22:53 PM PDT 24
Peak memory 220596 kb
Host smart-b6763a99-6d38-4ca4-a533-562fb0d0a7c2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2368960208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.2368960208
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.2900313263
Short name T129
Test name
Test status
Simulation time 564682598 ps
CPU time 0.98 seconds
Started Mar 28 03:22:45 PM PDT 24
Finished Mar 28 03:22:46 PM PDT 24
Peak memory 207032 kb
Host smart-929bf3bf-f80b-42d3-93ce-4771897324b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900313263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.2900313263
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.167504918
Short name T268
Test name
Test status
Simulation time 17502365140 ps
CPU time 78.6 seconds
Started Mar 28 03:22:38 PM PDT 24
Finished Mar 28 03:23:57 PM PDT 24
Peak memory 216780 kb
Host smart-aa6027f6-1052-46cc-9181-5d7b377dddd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167504918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.167504918
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.121946416
Short name T814
Test name
Test status
Simulation time 6369178476 ps
CPU time 6.06 seconds
Started Mar 28 03:22:37 PM PDT 24
Finished Mar 28 03:22:43 PM PDT 24
Peak memory 216692 kb
Host smart-39201a98-9bc4-4630-9d2f-0c9194ff7fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121946416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.121946416
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.2641837514
Short name T399
Test name
Test status
Simulation time 151199415 ps
CPU time 2.52 seconds
Started Mar 28 03:22:38 PM PDT 24
Finished Mar 28 03:22:41 PM PDT 24
Peak memory 216704 kb
Host smart-8d4a18e1-aecb-4eeb-abea-dc3145ff16aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641837514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.2641837514
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.3324346572
Short name T307
Test name
Test status
Simulation time 158969954 ps
CPU time 1 seconds
Started Mar 28 03:22:38 PM PDT 24
Finished Mar 28 03:22:39 PM PDT 24
Peak memory 206140 kb
Host smart-78d6599c-b999-4c19-ba0b-429c436afd9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324346572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.3324346572
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.4055545317
Short name T462
Test name
Test status
Simulation time 4129879909 ps
CPU time 23.9 seconds
Started Mar 28 03:22:51 PM PDT 24
Finished Mar 28 03:23:15 PM PDT 24
Peak memory 252560 kb
Host smart-a7e790ba-6c7d-4375-bd0e-3a801b4c94f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055545317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.4055545317
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.1520012711
Short name T298
Test name
Test status
Simulation time 13841159 ps
CPU time 0.68 seconds
Started Mar 28 03:22:47 PM PDT 24
Finished Mar 28 03:22:48 PM PDT 24
Peak memory 205888 kb
Host smart-1d006c11-de48-455d-a895-bf19541758e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520012711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
1520012711
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.1759262341
Short name T332
Test name
Test status
Simulation time 845748120 ps
CPU time 3.3 seconds
Started Mar 28 03:22:47 PM PDT 24
Finished Mar 28 03:22:50 PM PDT 24
Peak memory 219048 kb
Host smart-b7c7e0ec-e5c2-45d5-b6fc-9b108f034d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759262341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.1759262341
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.2036400873
Short name T664
Test name
Test status
Simulation time 14394932 ps
CPU time 0.73 seconds
Started Mar 28 03:22:54 PM PDT 24
Finished Mar 28 03:22:55 PM PDT 24
Peak memory 205740 kb
Host smart-85acf7a8-cbfa-40f3-a72e-0fc9ac65b4ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036400873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.2036400873
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.1960038558
Short name T200
Test name
Test status
Simulation time 3752731855 ps
CPU time 18.44 seconds
Started Mar 28 03:22:59 PM PDT 24
Finished Mar 28 03:23:17 PM PDT 24
Peak memory 238896 kb
Host smart-ff58518e-a24a-47b0-a96c-8edcfec5ed4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960038558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.1960038558
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.1625597794
Short name T505
Test name
Test status
Simulation time 9637126564 ps
CPU time 83.89 seconds
Started Mar 28 03:22:49 PM PDT 24
Finished Mar 28 03:24:13 PM PDT 24
Peak memory 256620 kb
Host smart-216c4309-da9f-49d3-a942-15d2bf1cd59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625597794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.1625597794
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.3658056133
Short name T789
Test name
Test status
Simulation time 13477007709 ps
CPU time 65.42 seconds
Started Mar 28 03:22:46 PM PDT 24
Finished Mar 28 03:23:51 PM PDT 24
Peak memory 251752 kb
Host smart-cfbc4e1a-266e-44a6-8778-56381d74e624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658056133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.3658056133
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.1124066559
Short name T422
Test name
Test status
Simulation time 399933271 ps
CPU time 9.76 seconds
Started Mar 28 03:22:46 PM PDT 24
Finished Mar 28 03:22:56 PM PDT 24
Peak memory 244696 kb
Host smart-4e3d1627-d2a2-4312-9224-5dd5b781177c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124066559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.1124066559
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.4170344204
Short name T573
Test name
Test status
Simulation time 242550020 ps
CPU time 3.29 seconds
Started Mar 28 03:22:44 PM PDT 24
Finished Mar 28 03:22:48 PM PDT 24
Peak memory 218948 kb
Host smart-602df210-58ed-471d-aad6-119aec1b8497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170344204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.4170344204
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.1775619151
Short name T63
Test name
Test status
Simulation time 1523823687 ps
CPU time 3.12 seconds
Started Mar 28 03:22:54 PM PDT 24
Finished Mar 28 03:22:57 PM PDT 24
Peak memory 219140 kb
Host smart-52be7549-07c0-40a7-85d0-4d7bd81bc563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775619151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.1775619151
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.3075374821
Short name T700
Test name
Test status
Simulation time 1453170731 ps
CPU time 5.18 seconds
Started Mar 28 03:22:52 PM PDT 24
Finished Mar 28 03:22:58 PM PDT 24
Peak memory 224916 kb
Host smart-e16b32e3-93d4-416a-b4bf-cc90770d92e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075374821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.3075374821
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.4099062099
Short name T523
Test name
Test status
Simulation time 122907741 ps
CPU time 2.76 seconds
Started Mar 28 03:22:55 PM PDT 24
Finished Mar 28 03:22:58 PM PDT 24
Peak memory 233308 kb
Host smart-58e71739-bcd9-4f70-8379-3047592fcba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099062099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.4099062099
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.23055162
Short name T829
Test name
Test status
Simulation time 5737382976 ps
CPU time 6.43 seconds
Started Mar 28 03:22:51 PM PDT 24
Finished Mar 28 03:22:57 PM PDT 24
Peak memory 220760 kb
Host smart-049782ea-4ac9-48e9-9706-23d4e4c27f57
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=23055162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_direc
t.23055162
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.200170437
Short name T613
Test name
Test status
Simulation time 86160065838 ps
CPU time 364.73 seconds
Started Mar 28 03:22:45 PM PDT 24
Finished Mar 28 03:28:50 PM PDT 24
Peak memory 267140 kb
Host smart-32a62bcf-f7d3-4e87-96f4-c051838633bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200170437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stres
s_all.200170437
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.424801026
Short name T334
Test name
Test status
Simulation time 7697614960 ps
CPU time 39.93 seconds
Started Mar 28 03:22:54 PM PDT 24
Finished Mar 28 03:23:34 PM PDT 24
Peak memory 216788 kb
Host smart-17a1dca7-3307-4eec-9879-2cc861d338b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424801026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.424801026
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.3393845212
Short name T364
Test name
Test status
Simulation time 10299674457 ps
CPU time 19.32 seconds
Started Mar 28 03:22:49 PM PDT 24
Finished Mar 28 03:23:09 PM PDT 24
Peak memory 216832 kb
Host smart-47708732-120d-41b7-8544-1819765f8cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393845212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.3393845212
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.646559157
Short name T444
Test name
Test status
Simulation time 50430693 ps
CPU time 1.94 seconds
Started Mar 28 03:22:54 PM PDT 24
Finished Mar 28 03:22:56 PM PDT 24
Peak memory 216728 kb
Host smart-39cc5e6b-beac-484d-a821-21eb2f32308c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646559157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.646559157
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.772840683
Short name T419
Test name
Test status
Simulation time 25645135 ps
CPU time 0.73 seconds
Started Mar 28 03:22:49 PM PDT 24
Finished Mar 28 03:22:50 PM PDT 24
Peak memory 206152 kb
Host smart-4428b490-e798-40a3-8037-fa627e971c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772840683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.772840683
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.3715897104
Short name T473
Test name
Test status
Simulation time 511202421 ps
CPU time 5.19 seconds
Started Mar 28 03:22:50 PM PDT 24
Finished Mar 28 03:22:56 PM PDT 24
Peak memory 234556 kb
Host smart-5c415268-aa39-4637-b8d0-89374734625c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715897104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.3715897104
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.1186201522
Short name T612
Test name
Test status
Simulation time 29559147 ps
CPU time 0.68 seconds
Started Mar 28 03:22:49 PM PDT 24
Finished Mar 28 03:22:50 PM PDT 24
Peak memory 205264 kb
Host smart-2ea3b7b9-c47b-4ac5-a81a-80891646bab7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186201522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
1186201522
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.551015264
Short name T735
Test name
Test status
Simulation time 2810087626 ps
CPU time 5.54 seconds
Started Mar 28 03:22:48 PM PDT 24
Finished Mar 28 03:22:53 PM PDT 24
Peak memory 220488 kb
Host smart-b5cf7e90-a858-4555-9fe1-99bd0da5c82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551015264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.551015264
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.3923658051
Short name T922
Test name
Test status
Simulation time 28588069 ps
CPU time 0.79 seconds
Started Mar 28 03:22:52 PM PDT 24
Finished Mar 28 03:22:53 PM PDT 24
Peak memory 206328 kb
Host smart-e36a92b0-718d-4d04-ae73-0d74d6df8134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923658051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.3923658051
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.1108559859
Short name T381
Test name
Test status
Simulation time 62659977563 ps
CPU time 57.55 seconds
Started Mar 28 03:22:53 PM PDT 24
Finished Mar 28 03:23:51 PM PDT 24
Peak memory 254000 kb
Host smart-1f60b8de-3d5b-4cbe-b724-7643035a9698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108559859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.1108559859
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.2588783233
Short name T653
Test name
Test status
Simulation time 4684571309 ps
CPU time 50.78 seconds
Started Mar 28 03:22:54 PM PDT 24
Finished Mar 28 03:23:44 PM PDT 24
Peak memory 249584 kb
Host smart-bf9c72df-b442-4a5d-b5c5-335f30106e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588783233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.2588783233
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.1673212929
Short name T585
Test name
Test status
Simulation time 10375762038 ps
CPU time 33.08 seconds
Started Mar 28 03:22:54 PM PDT 24
Finished Mar 28 03:23:28 PM PDT 24
Peak memory 239276 kb
Host smart-98b8b680-12fc-49b4-9667-7d7863351d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673212929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.1673212929
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.1345993386
Short name T887
Test name
Test status
Simulation time 481098686 ps
CPU time 2.58 seconds
Started Mar 28 03:22:47 PM PDT 24
Finished Mar 28 03:22:50 PM PDT 24
Peak memory 224920 kb
Host smart-d0c0c182-4495-4ffc-9771-81064a036f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345993386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.1345993386
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.3881775363
Short name T45
Test name
Test status
Simulation time 601318561 ps
CPU time 3.81 seconds
Started Mar 28 03:22:54 PM PDT 24
Finished Mar 28 03:22:57 PM PDT 24
Peak memory 218840 kb
Host smart-525e8d17-0958-4ab3-adc9-71252ab50d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881775363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.3881775363
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.266820397
Short name T570
Test name
Test status
Simulation time 483655852 ps
CPU time 3.06 seconds
Started Mar 28 03:22:50 PM PDT 24
Finished Mar 28 03:22:53 PM PDT 24
Peak memory 220184 kb
Host smart-6fa6f60e-6c07-4016-97a8-55b220c21092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266820397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap
.266820397
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.2101456780
Short name T187
Test name
Test status
Simulation time 5688233869 ps
CPU time 17.42 seconds
Started Mar 28 03:22:53 PM PDT 24
Finished Mar 28 03:23:10 PM PDT 24
Peak memory 228468 kb
Host smart-33f1a2c5-3aa2-4333-b34d-5258d059f031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101456780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.2101456780
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.3395621746
Short name T688
Test name
Test status
Simulation time 865222928 ps
CPU time 3.25 seconds
Started Mar 28 03:22:54 PM PDT 24
Finished Mar 28 03:22:58 PM PDT 24
Peak memory 219752 kb
Host smart-c2704c64-ac45-4090-9a48-3b664597ef83
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3395621746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.3395621746
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.3367915322
Short name T398
Test name
Test status
Simulation time 38018834 ps
CPU time 1.03 seconds
Started Mar 28 03:22:54 PM PDT 24
Finished Mar 28 03:22:56 PM PDT 24
Peak memory 207096 kb
Host smart-3f1d7d5a-896c-40a6-a6ec-babad1ef094e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367915322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.3367915322
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.471810904
Short name T300
Test name
Test status
Simulation time 5732147531 ps
CPU time 47.09 seconds
Started Mar 28 03:22:54 PM PDT 24
Finished Mar 28 03:23:41 PM PDT 24
Peak memory 216852 kb
Host smart-826d8213-7e70-4b9b-bbaa-951e87303a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471810904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.471810904
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.3671741746
Short name T61
Test name
Test status
Simulation time 54769360 ps
CPU time 1.02 seconds
Started Mar 28 03:22:48 PM PDT 24
Finished Mar 28 03:22:49 PM PDT 24
Peak memory 206272 kb
Host smart-f76e83ee-c77a-4d12-868a-4c797c125932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671741746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.3671741746
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.4244403552
Short name T345
Test name
Test status
Simulation time 20119289 ps
CPU time 1.18 seconds
Started Mar 28 03:22:47 PM PDT 24
Finished Mar 28 03:22:48 PM PDT 24
Peak memory 216716 kb
Host smart-27eeda4b-a541-410a-95ea-845df6f9a431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244403552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.4244403552
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.3057101847
Short name T899
Test name
Test status
Simulation time 40811284 ps
CPU time 0.98 seconds
Started Mar 28 03:22:54 PM PDT 24
Finished Mar 28 03:22:55 PM PDT 24
Peak memory 206484 kb
Host smart-8c348d82-960b-4ec9-b1c3-dba0360ba142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057101847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.3057101847
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.61833255
Short name T99
Test name
Test status
Simulation time 28293994497 ps
CPU time 26.35 seconds
Started Mar 28 03:22:54 PM PDT 24
Finished Mar 28 03:23:21 PM PDT 24
Peak memory 236160 kb
Host smart-2200bf8f-4f10-4024-88f6-8418b714d444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61833255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.61833255
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.2134884866
Short name T411
Test name
Test status
Simulation time 17291240 ps
CPU time 0.71 seconds
Started Mar 28 03:22:55 PM PDT 24
Finished Mar 28 03:22:56 PM PDT 24
Peak memory 205280 kb
Host smart-272899de-24c0-439d-8c9b-a2ca718a86e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134884866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
2134884866
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.2446584531
Short name T343
Test name
Test status
Simulation time 1934639153 ps
CPU time 5.09 seconds
Started Mar 28 03:22:54 PM PDT 24
Finished Mar 28 03:22:59 PM PDT 24
Peak memory 234756 kb
Host smart-2918c455-6478-4e93-a5b3-0cb2f0a15bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446584531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.2446584531
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.74805660
Short name T304
Test name
Test status
Simulation time 17869198 ps
CPU time 0.89 seconds
Started Mar 28 03:22:54 PM PDT 24
Finished Mar 28 03:22:55 PM PDT 24
Peak memory 207008 kb
Host smart-3f381310-1afe-45fb-a465-1de94c5c406c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74805660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.74805660
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.1658714895
Short name T346
Test name
Test status
Simulation time 27035109959 ps
CPU time 91.53 seconds
Started Mar 28 03:22:54 PM PDT 24
Finished Mar 28 03:24:26 PM PDT 24
Peak memory 254216 kb
Host smart-24663044-5a5d-4bf2-92bb-e0dbaf4fcd6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658714895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.1658714895
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.3895743673
Short name T242
Test name
Test status
Simulation time 2590756133 ps
CPU time 54.81 seconds
Started Mar 28 03:22:49 PM PDT 24
Finished Mar 28 03:23:44 PM PDT 24
Peak memory 249528 kb
Host smart-38407f8b-b41e-4909-be35-fe3e29593210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895743673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.3895743673
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.2923857856
Short name T619
Test name
Test status
Simulation time 45790333304 ps
CPU time 120.15 seconds
Started Mar 28 03:22:54 PM PDT 24
Finished Mar 28 03:24:54 PM PDT 24
Peak memory 256372 kb
Host smart-044bc99d-82d2-4ece-a142-a59f84221988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923857856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.2923857856
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.3282365562
Short name T44
Test name
Test status
Simulation time 16516905825 ps
CPU time 22.87 seconds
Started Mar 28 03:22:53 PM PDT 24
Finished Mar 28 03:23:16 PM PDT 24
Peak memory 233248 kb
Host smart-edb8614c-31da-4a04-8dc0-56ee8eaa00cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282365562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.3282365562
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.4288038207
Short name T434
Test name
Test status
Simulation time 5273523696 ps
CPU time 14.63 seconds
Started Mar 28 03:22:50 PM PDT 24
Finished Mar 28 03:23:05 PM PDT 24
Peak memory 222352 kb
Host smart-b2361f5a-8945-4362-a1b6-ca168f475042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288038207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.4288038207
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.2429708230
Short name T506
Test name
Test status
Simulation time 1483009981 ps
CPU time 6.86 seconds
Started Mar 28 03:22:55 PM PDT 24
Finished Mar 28 03:23:03 PM PDT 24
Peak memory 219148 kb
Host smart-5d905298-86fb-49ef-b85f-0d43bf052626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429708230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.2429708230
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.718674718
Short name T446
Test name
Test status
Simulation time 630748285 ps
CPU time 3.21 seconds
Started Mar 28 03:22:55 PM PDT 24
Finished Mar 28 03:22:58 PM PDT 24
Peak memory 224908 kb
Host smart-18c30fa7-dd25-4da8-a02a-969743239017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718674718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap
.718674718
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.597146779
Short name T151
Test name
Test status
Simulation time 1264594425 ps
CPU time 5.45 seconds
Started Mar 28 03:22:47 PM PDT 24
Finished Mar 28 03:22:53 PM PDT 24
Peak memory 233412 kb
Host smart-f8821348-14db-45df-96e6-637dfc822e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597146779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.597146779
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.1635526081
Short name T120
Test name
Test status
Simulation time 1829792871 ps
CPU time 4.17 seconds
Started Mar 28 03:22:54 PM PDT 24
Finished Mar 28 03:22:59 PM PDT 24
Peak memory 222924 kb
Host smart-d2adb8b0-2b12-4d0d-9562-d17a6e9ef7d8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1635526081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.1635526081
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.225622528
Short name T721
Test name
Test status
Simulation time 46033667107 ps
CPU time 316.64 seconds
Started Mar 28 03:22:54 PM PDT 24
Finished Mar 28 03:28:11 PM PDT 24
Peak memory 267204 kb
Host smart-7806e86c-9a71-4e37-a8aa-2f5af13e08ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225622528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stres
s_all.225622528
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.2793577691
Short name T527
Test name
Test status
Simulation time 18791438888 ps
CPU time 24.57 seconds
Started Mar 28 03:22:54 PM PDT 24
Finished Mar 28 03:23:19 PM PDT 24
Peak memory 216756 kb
Host smart-681d7d19-6aec-46f5-b5aa-5da604d0e0d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793577691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.2793577691
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.2210939218
Short name T609
Test name
Test status
Simulation time 802467757 ps
CPU time 3.06 seconds
Started Mar 28 03:22:54 PM PDT 24
Finished Mar 28 03:22:57 PM PDT 24
Peak memory 216332 kb
Host smart-65c693b8-5553-4bfd-830c-0fedde009597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210939218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.2210939218
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.687117184
Short name T552
Test name
Test status
Simulation time 186987099 ps
CPU time 1.75 seconds
Started Mar 28 03:22:52 PM PDT 24
Finished Mar 28 03:22:54 PM PDT 24
Peak memory 216676 kb
Host smart-71d4070e-0697-4d91-a651-84cc0a02a68e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687117184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.687117184
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.3913148559
Short name T360
Test name
Test status
Simulation time 158386727 ps
CPU time 0.83 seconds
Started Mar 28 03:22:54 PM PDT 24
Finished Mar 28 03:22:55 PM PDT 24
Peak memory 206196 kb
Host smart-fdf756e5-e5ca-402a-a1a0-e53e5a732a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913148559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.3913148559
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.658062161
Short name T723
Test name
Test status
Simulation time 2900193784 ps
CPU time 5.29 seconds
Started Mar 28 03:22:55 PM PDT 24
Finished Mar 28 03:23:00 PM PDT 24
Peak memory 223780 kb
Host smart-3b37114b-a5e6-4660-a059-375196294e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658062161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.658062161
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.2902144034
Short name T276
Test name
Test status
Simulation time 45841722 ps
CPU time 0.71 seconds
Started Mar 28 03:22:57 PM PDT 24
Finished Mar 28 03:22:57 PM PDT 24
Peak memory 205796 kb
Host smart-6f987d81-2120-471c-950f-b9876928444e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902144034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
2902144034
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.3744761608
Short name T336
Test name
Test status
Simulation time 7987903244 ps
CPU time 7.6 seconds
Started Mar 28 03:22:56 PM PDT 24
Finished Mar 28 03:23:03 PM PDT 24
Peak memory 234852 kb
Host smart-444f3153-57f7-45aa-b2c3-3378c828220e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744761608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.3744761608
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.2421711197
Short name T740
Test name
Test status
Simulation time 14214452 ps
CPU time 0.8 seconds
Started Mar 28 03:22:55 PM PDT 24
Finished Mar 28 03:22:56 PM PDT 24
Peak memory 207036 kb
Host smart-c099977d-fd87-43a0-a061-408bf3e923a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421711197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.2421711197
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.2125966797
Short name T30
Test name
Test status
Simulation time 12153254387 ps
CPU time 63.01 seconds
Started Mar 28 03:22:54 PM PDT 24
Finished Mar 28 03:23:58 PM PDT 24
Peak memory 249640 kb
Host smart-2f0c4441-d866-4b0d-9a79-f91b9dae703a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125966797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.2125966797
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.2591087135
Short name T191
Test name
Test status
Simulation time 134629719188 ps
CPU time 297.25 seconds
Started Mar 28 03:22:56 PM PDT 24
Finished Mar 28 03:27:53 PM PDT 24
Peak memory 256484 kb
Host smart-2517c21b-ba19-4be1-82f0-d946e44c1ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591087135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.2591087135
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.2778238831
Short name T678
Test name
Test status
Simulation time 18089471523 ps
CPU time 64.97 seconds
Started Mar 28 03:22:47 PM PDT 24
Finished Mar 28 03:23:52 PM PDT 24
Peak memory 257656 kb
Host smart-fbd7fc96-6030-4fd0-9a57-861419cd8247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778238831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.2778238831
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.2749681472
Short name T5
Test name
Test status
Simulation time 9188791520 ps
CPU time 50.76 seconds
Started Mar 28 03:22:55 PM PDT 24
Finished Mar 28 03:23:46 PM PDT 24
Peak memory 250476 kb
Host smart-6af538b6-fe40-44db-beb6-5235d07490ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749681472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.2749681472
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.3631227927
Short name T227
Test name
Test status
Simulation time 1027273938 ps
CPU time 6.93 seconds
Started Mar 28 03:22:55 PM PDT 24
Finished Mar 28 03:23:02 PM PDT 24
Peak memory 234992 kb
Host smart-5f27f7f2-73af-443b-846b-6d4a32764e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631227927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3631227927
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.2897398414
Short name T916
Test name
Test status
Simulation time 623524098 ps
CPU time 9.06 seconds
Started Mar 28 03:22:47 PM PDT 24
Finished Mar 28 03:22:56 PM PDT 24
Peak memory 238232 kb
Host smart-4c8ea127-680e-41b4-ad2b-e5028f416712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897398414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.2897398414
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.1362789643
Short name T169
Test name
Test status
Simulation time 16175545597 ps
CPU time 24.29 seconds
Started Mar 28 03:22:56 PM PDT 24
Finished Mar 28 03:23:21 PM PDT 24
Peak memory 233828 kb
Host smart-6534d6a9-3191-478e-8ffd-5e0070b8e359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362789643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.1362789643
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.1784681536
Short name T331
Test name
Test status
Simulation time 845760000 ps
CPU time 3.54 seconds
Started Mar 28 03:22:56 PM PDT 24
Finished Mar 28 03:23:00 PM PDT 24
Peak memory 218912 kb
Host smart-fcc7f8f6-583a-4565-a80d-4b99406f2162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784681536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.1784681536
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.4091823945
Short name T567
Test name
Test status
Simulation time 696221797 ps
CPU time 4.95 seconds
Started Mar 28 03:22:46 PM PDT 24
Finished Mar 28 03:22:51 PM PDT 24
Peak memory 219756 kb
Host smart-818be2b4-da57-4b5f-82d7-b349871579fe
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4091823945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.4091823945
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.3563308029
Short name T783
Test name
Test status
Simulation time 73535550263 ps
CPU time 248.81 seconds
Started Mar 28 03:22:54 PM PDT 24
Finished Mar 28 03:27:03 PM PDT 24
Peak memory 263192 kb
Host smart-5c9ae868-c48e-45ac-85fc-3e37b6996f38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563308029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.3563308029
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.3005277691
Short name T21
Test name
Test status
Simulation time 31623228546 ps
CPU time 29.23 seconds
Started Mar 28 03:22:55 PM PDT 24
Finished Mar 28 03:23:24 PM PDT 24
Peak memory 216872 kb
Host smart-60fb8051-df09-4b96-94fd-2c28c53f5642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005277691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.3005277691
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.404139538
Short name T370
Test name
Test status
Simulation time 2357449723 ps
CPU time 7.13 seconds
Started Mar 28 03:22:44 PM PDT 24
Finished Mar 28 03:22:52 PM PDT 24
Peak memory 216844 kb
Host smart-39e585b7-1768-46eb-b9e7-be53d5fc33fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404139538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.404139538
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.383423226
Short name T774
Test name
Test status
Simulation time 89272981 ps
CPU time 1.37 seconds
Started Mar 28 03:22:56 PM PDT 24
Finished Mar 28 03:22:58 PM PDT 24
Peak memory 216748 kb
Host smart-e645cb90-c360-480b-97f9-8f8752dfc010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383423226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.383423226
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.242581717
Short name T455
Test name
Test status
Simulation time 224275820 ps
CPU time 0.77 seconds
Started Mar 28 03:22:55 PM PDT 24
Finished Mar 28 03:22:56 PM PDT 24
Peak memory 206172 kb
Host smart-f764c644-a612-4284-9dcc-b88bda43b8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242581717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.242581717
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.4120519104
Short name T150
Test name
Test status
Simulation time 8102543886 ps
CPU time 30.78 seconds
Started Mar 28 03:22:55 PM PDT 24
Finished Mar 28 03:23:26 PM PDT 24
Peak memory 238920 kb
Host smart-808efa87-8fae-4a22-bd74-dad19e41bd24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120519104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.4120519104
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.4293439230
Short name T858
Test name
Test status
Simulation time 73254666 ps
CPU time 0.71 seconds
Started Mar 28 03:23:12 PM PDT 24
Finished Mar 28 03:23:13 PM PDT 24
Peak memory 205352 kb
Host smart-59fa1983-e298-4de1-8829-ad0a48d6f34f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293439230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
4293439230
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.3751860980
Short name T784
Test name
Test status
Simulation time 2291912072 ps
CPU time 3.51 seconds
Started Mar 28 03:22:56 PM PDT 24
Finished Mar 28 03:23:00 PM PDT 24
Peak memory 234124 kb
Host smart-ba7b9bd3-daac-42bf-9ab4-70be578aa95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751860980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.3751860980
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.625542588
Short name T273
Test name
Test status
Simulation time 15321685 ps
CPU time 0.8 seconds
Started Mar 28 03:22:55 PM PDT 24
Finished Mar 28 03:22:56 PM PDT 24
Peak memory 206928 kb
Host smart-23a9fcc7-2886-4bf0-92c4-05bfef2c49b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625542588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.625542588
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.1658655399
Short name T257
Test name
Test status
Simulation time 136132184230 ps
CPU time 207.64 seconds
Started Mar 28 03:23:19 PM PDT 24
Finished Mar 28 03:26:47 PM PDT 24
Peak memory 254888 kb
Host smart-9d713249-66be-4774-8538-6473a6cf9597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658655399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.1658655399
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.3211750295
Short name T31
Test name
Test status
Simulation time 4467966252 ps
CPU time 94.59 seconds
Started Mar 28 03:23:12 PM PDT 24
Finished Mar 28 03:24:47 PM PDT 24
Peak memory 249688 kb
Host smart-744f2fe2-691d-4514-bcb8-c5c2507d0edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211750295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.3211750295
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.1863953507
Short name T253
Test name
Test status
Simulation time 4858801820 ps
CPU time 105.35 seconds
Started Mar 28 03:23:16 PM PDT 24
Finished Mar 28 03:25:02 PM PDT 24
Peak memory 258304 kb
Host smart-a236d756-4939-4ed3-b8eb-e6bfb94e987a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863953507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.1863953507
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.2074580275
Short name T495
Test name
Test status
Simulation time 5596086353 ps
CPU time 29.97 seconds
Started Mar 28 03:22:53 PM PDT 24
Finished Mar 28 03:23:23 PM PDT 24
Peak memory 233856 kb
Host smart-1fc359a3-fa5c-443f-9b96-a0c8e2ddee50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074580275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.2074580275
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.1399585539
Short name T521
Test name
Test status
Simulation time 596665557 ps
CPU time 3.77 seconds
Started Mar 28 03:23:02 PM PDT 24
Finished Mar 28 03:23:06 PM PDT 24
Peak memory 219044 kb
Host smart-50e2f4d9-266a-433e-bea5-31fe81a39ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399585539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.1399585539
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.548663176
Short name T734
Test name
Test status
Simulation time 162434483 ps
CPU time 2.16 seconds
Started Mar 28 03:23:01 PM PDT 24
Finished Mar 28 03:23:03 PM PDT 24
Peak memory 218920 kb
Host smart-254330cc-03c8-46e7-a3d3-e946cce5feba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548663176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.548663176
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.3807274393
Short name T248
Test name
Test status
Simulation time 64396232 ps
CPU time 2.52 seconds
Started Mar 28 03:22:59 PM PDT 24
Finished Mar 28 03:23:01 PM PDT 24
Peak memory 233668 kb
Host smart-a47ea90c-0855-48a3-91ca-c457f0557bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807274393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.3807274393
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.4062640479
Short name T871
Test name
Test status
Simulation time 11107577068 ps
CPU time 10.63 seconds
Started Mar 28 03:22:52 PM PDT 24
Finished Mar 28 03:23:03 PM PDT 24
Peak memory 229524 kb
Host smart-6ea9b886-96a7-4b97-9d0a-dd029f16631c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062640479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.4062640479
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.3270841292
Short name T698
Test name
Test status
Simulation time 1303605985 ps
CPU time 4.27 seconds
Started Mar 28 03:23:17 PM PDT 24
Finished Mar 28 03:23:21 PM PDT 24
Peak memory 222940 kb
Host smart-a902e670-287c-414a-ae4f-64263c4598ce
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3270841292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.3270841292
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.3632445617
Short name T833
Test name
Test status
Simulation time 250388897974 ps
CPU time 877.22 seconds
Started Mar 28 03:23:09 PM PDT 24
Finished Mar 28 03:37:47 PM PDT 24
Peak memory 282644 kb
Host smart-2138115f-c78f-4ca2-9c04-3cbcc3419d99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632445617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.3632445617
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.4274980440
Short name T669
Test name
Test status
Simulation time 4896056100 ps
CPU time 14.97 seconds
Started Mar 28 03:22:47 PM PDT 24
Finished Mar 28 03:23:02 PM PDT 24
Peak memory 220204 kb
Host smart-072b7aab-6781-4dfb-8239-78048398447a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274980440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.4274980440
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.4014132352
Short name T15
Test name
Test status
Simulation time 5742190104 ps
CPU time 6.52 seconds
Started Mar 28 03:22:53 PM PDT 24
Finished Mar 28 03:22:59 PM PDT 24
Peak memory 216748 kb
Host smart-d5efc3f8-2ee7-458c-87f1-74d403753f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014132352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.4014132352
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.1715234591
Short name T16
Test name
Test status
Simulation time 235842501 ps
CPU time 2.82 seconds
Started Mar 28 03:22:49 PM PDT 24
Finished Mar 28 03:22:51 PM PDT 24
Peak memory 216620 kb
Host smart-75b08b3c-be6d-47b3-9e2f-eca8baa88891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715234591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.1715234591
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.2136262539
Short name T520
Test name
Test status
Simulation time 588863494 ps
CPU time 1 seconds
Started Mar 28 03:22:52 PM PDT 24
Finished Mar 28 03:22:53 PM PDT 24
Peak memory 206668 kb
Host smart-b1774048-e2a6-4f36-a280-fd28241451a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136262539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.2136262539
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.2830364985
Short name T232
Test name
Test status
Simulation time 10641965155 ps
CPU time 33.44 seconds
Started Mar 28 03:22:52 PM PDT 24
Finished Mar 28 03:23:25 PM PDT 24
Peak memory 228240 kb
Host smart-f624ecc9-4ba2-4662-84f1-185b6056cc76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830364985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.2830364985
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.1353998818
Short name T499
Test name
Test status
Simulation time 42468610 ps
CPU time 0.71 seconds
Started Mar 28 03:23:44 PM PDT 24
Finished Mar 28 03:23:45 PM PDT 24
Peak memory 205800 kb
Host smart-6723349c-96c2-4a65-b92c-faa44a276d65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353998818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
1353998818
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.1926238136
Short name T905
Test name
Test status
Simulation time 3941514334 ps
CPU time 10.14 seconds
Started Mar 28 03:23:10 PM PDT 24
Finished Mar 28 03:23:20 PM PDT 24
Peak memory 222840 kb
Host smart-196e9cec-19cc-4073-9c39-305f68283bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926238136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.1926238136
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.1440440937
Short name T668
Test name
Test status
Simulation time 59546499 ps
CPU time 0.77 seconds
Started Mar 28 03:23:12 PM PDT 24
Finished Mar 28 03:23:12 PM PDT 24
Peak memory 205996 kb
Host smart-c9c9ed8d-5bcc-48e6-8cae-5aa370e8a9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440440937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.1440440937
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.3707707226
Short name T27
Test name
Test status
Simulation time 35695441390 ps
CPU time 86.53 seconds
Started Mar 28 03:23:11 PM PDT 24
Finished Mar 28 03:24:38 PM PDT 24
Peak memory 241396 kb
Host smart-6404ebba-bfd2-428d-924d-ba3377f74ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707707226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.3707707226
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.1080263668
Short name T254
Test name
Test status
Simulation time 96772058915 ps
CPU time 402.97 seconds
Started Mar 28 03:23:10 PM PDT 24
Finished Mar 28 03:29:53 PM PDT 24
Peak memory 263720 kb
Host smart-3836df8e-4200-45ce-89ca-e7273f4d7b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080263668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.1080263668
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.3668544993
Short name T848
Test name
Test status
Simulation time 8118948161 ps
CPU time 13.93 seconds
Started Mar 28 03:23:10 PM PDT 24
Finished Mar 28 03:23:24 PM PDT 24
Peak memory 236260 kb
Host smart-aaf1f134-efd5-4b30-85d4-25003aa2b07b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668544993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.3668544993
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.2682932139
Short name T413
Test name
Test status
Simulation time 378171729 ps
CPU time 3.57 seconds
Started Mar 28 03:23:18 PM PDT 24
Finished Mar 28 03:23:23 PM PDT 24
Peak memory 233080 kb
Host smart-b22f9733-9511-47e7-9be8-ca8f28b1436c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682932139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.2682932139
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.261188704
Short name T173
Test name
Test status
Simulation time 7100572535 ps
CPU time 22.37 seconds
Started Mar 28 03:23:17 PM PDT 24
Finished Mar 28 03:23:39 PM PDT 24
Peak memory 233068 kb
Host smart-bebcc3e6-519c-412a-94f6-853b7071953a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261188704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.261188704
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.1612314470
Short name T630
Test name
Test status
Simulation time 16208678254 ps
CPU time 47.47 seconds
Started Mar 28 03:23:20 PM PDT 24
Finished Mar 28 03:24:09 PM PDT 24
Peak memory 239284 kb
Host smart-3007bbd8-8d63-4dc1-9c73-410026f4595c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612314470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.1612314470
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.496262115
Short name T825
Test name
Test status
Simulation time 3559623233 ps
CPU time 13.44 seconds
Started Mar 28 03:23:11 PM PDT 24
Finished Mar 28 03:23:24 PM PDT 24
Peak memory 237348 kb
Host smart-def41389-4d4f-46e0-a9b7-db3c2be0e10d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496262115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.496262115
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.1975961122
Short name T121
Test name
Test status
Simulation time 4316969642 ps
CPU time 5.79 seconds
Started Mar 28 03:23:11 PM PDT 24
Finished Mar 28 03:23:17 PM PDT 24
Peak memory 223568 kb
Host smart-f0ea7a72-971a-41f3-ab08-d049c1e476d9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1975961122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.1975961122
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.3357339740
Short name T827
Test name
Test status
Simulation time 14389694646 ps
CPU time 75.28 seconds
Started Mar 28 03:23:18 PM PDT 24
Finished Mar 28 03:24:34 PM PDT 24
Peak memory 257700 kb
Host smart-310ce71e-d615-4c95-9ed9-7adef3164bb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357339740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.3357339740
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.3222378420
Short name T876
Test name
Test status
Simulation time 14100015317 ps
CPU time 63.17 seconds
Started Mar 28 03:23:17 PM PDT 24
Finished Mar 28 03:24:20 PM PDT 24
Peak memory 216804 kb
Host smart-269cd42a-10a7-4709-8964-caca3c87d06c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222378420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.3222378420
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.507248007
Short name T350
Test name
Test status
Simulation time 11885313442 ps
CPU time 6.19 seconds
Started Mar 28 03:23:13 PM PDT 24
Finished Mar 28 03:23:19 PM PDT 24
Peak memory 216716 kb
Host smart-657454a0-27c5-438b-992d-6852cb010722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507248007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.507248007
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.426986731
Short name T935
Test name
Test status
Simulation time 1490547698 ps
CPU time 4.02 seconds
Started Mar 28 03:23:18 PM PDT 24
Finished Mar 28 03:23:22 PM PDT 24
Peak memory 216732 kb
Host smart-1c87272d-e07c-4489-b4c9-ed8639e64da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426986731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.426986731
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.2470403135
Short name T930
Test name
Test status
Simulation time 24762239 ps
CPU time 0.8 seconds
Started Mar 28 03:23:18 PM PDT 24
Finished Mar 28 03:23:20 PM PDT 24
Peak memory 206260 kb
Host smart-28c5977d-9325-4046-8c66-0a2cc5b672b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470403135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.2470403135
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.3196603261
Short name T488
Test name
Test status
Simulation time 15017852046 ps
CPU time 15.14 seconds
Started Mar 28 03:23:20 PM PDT 24
Finished Mar 28 03:23:36 PM PDT 24
Peak memory 224256 kb
Host smart-fab81a11-da51-470a-8f77-d23881315232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196603261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.3196603261
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.555791422
Short name T745
Test name
Test status
Simulation time 23825079 ps
CPU time 0.71 seconds
Started Mar 28 03:23:17 PM PDT 24
Finished Mar 28 03:23:18 PM PDT 24
Peak memory 205900 kb
Host smart-89e7fad9-ef4f-4982-8443-2f30830d161c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555791422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.555791422
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.1065499517
Short name T804
Test name
Test status
Simulation time 327921529 ps
CPU time 2.84 seconds
Started Mar 28 03:23:18 PM PDT 24
Finished Mar 28 03:23:22 PM PDT 24
Peak memory 218796 kb
Host smart-05058b93-e33e-4a32-b2a2-8fbadf441e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065499517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.1065499517
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.1384586229
Short name T602
Test name
Test status
Simulation time 31693683 ps
CPU time 0.78 seconds
Started Mar 28 03:23:17 PM PDT 24
Finished Mar 28 03:23:18 PM PDT 24
Peak memory 205992 kb
Host smart-df2055c2-7168-4368-a0a7-8e2e6513cc81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384586229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.1384586229
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.2865040369
Short name T576
Test name
Test status
Simulation time 4480052184 ps
CPU time 51.46 seconds
Started Mar 28 03:23:17 PM PDT 24
Finished Mar 28 03:24:09 PM PDT 24
Peak memory 238192 kb
Host smart-3658da75-3ebd-43a1-b4d6-b513acafac67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865040369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.2865040369
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.1370056893
Short name T512
Test name
Test status
Simulation time 7521650795 ps
CPU time 43.55 seconds
Started Mar 28 03:23:13 PM PDT 24
Finished Mar 28 03:23:57 PM PDT 24
Peak memory 241512 kb
Host smart-3d7111fc-4ca8-4a0d-80d4-42b9ef7f710f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370056893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.1370056893
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.3214864473
Short name T776
Test name
Test status
Simulation time 24069634855 ps
CPU time 28.72 seconds
Started Mar 28 03:23:14 PM PDT 24
Finished Mar 28 03:23:43 PM PDT 24
Peak memory 230644 kb
Host smart-372c412f-ac94-49d9-885a-ec80692b53d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214864473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.3214864473
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.215508958
Short name T159
Test name
Test status
Simulation time 2460344388 ps
CPU time 5.48 seconds
Started Mar 28 03:23:20 PM PDT 24
Finished Mar 28 03:23:27 PM PDT 24
Peak memory 220680 kb
Host smart-60dff8bc-f47f-4f8f-8881-b5859601dc58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215508958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.215508958
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.236327983
Short name T368
Test name
Test status
Simulation time 12918625753 ps
CPU time 15.6 seconds
Started Mar 28 03:23:19 PM PDT 24
Finished Mar 28 03:23:35 PM PDT 24
Peak memory 230032 kb
Host smart-1fbd94a8-2da1-4058-b511-ee42f7123ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236327983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.236327983
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.3680809456
Short name T385
Test name
Test status
Simulation time 266078129 ps
CPU time 3.18 seconds
Started Mar 28 03:23:13 PM PDT 24
Finished Mar 28 03:23:16 PM PDT 24
Peak memory 219232 kb
Host smart-99910127-b013-4d2a-aec5-9eac8c03e355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680809456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.3680809456
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.429401646
Short name T180
Test name
Test status
Simulation time 46117812864 ps
CPU time 19.01 seconds
Started Mar 28 03:23:17 PM PDT 24
Finished Mar 28 03:23:36 PM PDT 24
Peak memory 234468 kb
Host smart-24156f1b-1b91-4071-a260-38e5ccd14aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429401646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.429401646
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.1432649316
Short name T572
Test name
Test status
Simulation time 1265909921 ps
CPU time 3.7 seconds
Started Mar 28 03:23:12 PM PDT 24
Finished Mar 28 03:23:16 PM PDT 24
Peak memory 220284 kb
Host smart-651f373a-1ad5-4490-a181-9a2092a978d6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1432649316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.1432649316
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.4044643275
Short name T133
Test name
Test status
Simulation time 4791536114 ps
CPU time 78.07 seconds
Started Mar 28 03:23:17 PM PDT 24
Finished Mar 28 03:24:35 PM PDT 24
Peak memory 250184 kb
Host smart-ad7cfdbd-1d84-4955-b574-0bddf6e14786
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044643275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.4044643275
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.1255138758
Short name T840
Test name
Test status
Simulation time 4133170723 ps
CPU time 15.63 seconds
Started Mar 28 03:23:17 PM PDT 24
Finished Mar 28 03:23:32 PM PDT 24
Peak memory 220200 kb
Host smart-b9d267fb-c3b8-4bba-95ba-eb7916614a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255138758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.1255138758
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.1969931498
Short name T17
Test name
Test status
Simulation time 2318742335 ps
CPU time 9.31 seconds
Started Mar 28 03:23:17 PM PDT 24
Finished Mar 28 03:23:26 PM PDT 24
Peak memory 216652 kb
Host smart-8253be3f-a975-4eb8-8a42-e0a32a5f0a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969931498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.1969931498
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.773727581
Short name T581
Test name
Test status
Simulation time 120498816 ps
CPU time 1.42 seconds
Started Mar 28 03:23:19 PM PDT 24
Finished Mar 28 03:23:21 PM PDT 24
Peak memory 216856 kb
Host smart-8dfe01c2-17ec-4fb2-9c39-6bedcc939c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773727581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.773727581
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.3704654726
Short name T75
Test name
Test status
Simulation time 490270875 ps
CPU time 0.96 seconds
Started Mar 28 03:23:18 PM PDT 24
Finished Mar 28 03:23:20 PM PDT 24
Peak memory 207180 kb
Host smart-61de7b1c-3a16-4e2c-93a1-4079eb73d44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704654726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.3704654726
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.793000769
Short name T903
Test name
Test status
Simulation time 16562380313 ps
CPU time 52.9 seconds
Started Mar 28 03:23:12 PM PDT 24
Finished Mar 28 03:24:05 PM PDT 24
Peak memory 248928 kb
Host smart-f2d4d7d6-6e83-4fcb-988b-b5d570cd6543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793000769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.793000769
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.2378305489
Short name T42
Test name
Test status
Simulation time 69479941 ps
CPU time 0.69 seconds
Started Mar 28 03:23:30 PM PDT 24
Finished Mar 28 03:23:31 PM PDT 24
Peak memory 206204 kb
Host smart-6c5a763d-bfc4-4fa4-8e2a-230726dc8386
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378305489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
2378305489
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.663274481
Short name T525
Test name
Test status
Simulation time 126989467 ps
CPU time 2.84 seconds
Started Mar 28 03:23:26 PM PDT 24
Finished Mar 28 03:23:29 PM PDT 24
Peak memory 234060 kb
Host smart-b3559858-c460-4f33-ad8f-56e14c941aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663274481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.663274481
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.3938954718
Short name T461
Test name
Test status
Simulation time 19117389 ps
CPU time 0.8 seconds
Started Mar 28 03:23:19 PM PDT 24
Finished Mar 28 03:23:21 PM PDT 24
Peak memory 206952 kb
Host smart-34e070ca-4ad5-472a-992c-2d30464c5897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938954718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.3938954718
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.4191014261
Short name T534
Test name
Test status
Simulation time 28897922864 ps
CPU time 33.84 seconds
Started Mar 28 03:23:28 PM PDT 24
Finished Mar 28 03:24:02 PM PDT 24
Peak memory 235412 kb
Host smart-3912b330-6278-4449-833b-5f17197fc159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191014261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.4191014261
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.3115669553
Short name T913
Test name
Test status
Simulation time 71009133851 ps
CPU time 93.15 seconds
Started Mar 28 03:23:25 PM PDT 24
Finished Mar 28 03:24:59 PM PDT 24
Peak memory 235280 kb
Host smart-57dac26d-2416-4853-af9b-f181b135678e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115669553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.3115669553
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.4206466396
Short name T184
Test name
Test status
Simulation time 24060813553 ps
CPU time 108.45 seconds
Started Mar 28 03:23:25 PM PDT 24
Finished Mar 28 03:25:14 PM PDT 24
Peak memory 255744 kb
Host smart-794a55c2-dcfb-43cb-aba9-5e93448b1972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206466396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.4206466396
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.3330622049
Short name T885
Test name
Test status
Simulation time 3238267828 ps
CPU time 12.9 seconds
Started Mar 28 03:23:13 PM PDT 24
Finished Mar 28 03:23:26 PM PDT 24
Peak memory 234040 kb
Host smart-709cfefd-8c3d-4829-b43d-402e9d9841f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330622049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.3330622049
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.116606480
Short name T305
Test name
Test status
Simulation time 8181138948 ps
CPU time 6.35 seconds
Started Mar 28 03:23:12 PM PDT 24
Finished Mar 28 03:23:18 PM PDT 24
Peak memory 219192 kb
Host smart-764eabd1-9230-489e-9d91-6a518b0b6358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116606480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.116606480
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.3431358768
Short name T895
Test name
Test status
Simulation time 2360056475 ps
CPU time 4.96 seconds
Started Mar 28 03:23:20 PM PDT 24
Finished Mar 28 03:23:26 PM PDT 24
Peak memory 233908 kb
Host smart-ba0d4420-989b-4944-afc5-dee8aa08716b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431358768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.3431358768
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.3264120810
Short name T912
Test name
Test status
Simulation time 417805610 ps
CPU time 5.65 seconds
Started Mar 28 03:23:18 PM PDT 24
Finished Mar 28 03:23:24 PM PDT 24
Peak memory 233588 kb
Host smart-3100cf5d-344c-4581-bcc2-42526af4c381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264120810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.3264120810
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.2572665229
Short name T311
Test name
Test status
Simulation time 233769548 ps
CPU time 3.7 seconds
Started Mar 28 03:23:24 PM PDT 24
Finished Mar 28 03:23:28 PM PDT 24
Peak memory 219744 kb
Host smart-14bbdd85-6cd3-419f-9ad5-c87a83d54952
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2572665229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.2572665229
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.930964757
Short name T917
Test name
Test status
Simulation time 354388689 ps
CPU time 0.94 seconds
Started Mar 28 03:23:26 PM PDT 24
Finished Mar 28 03:23:27 PM PDT 24
Peak memory 207116 kb
Host smart-712565d1-e4d6-4623-aff1-e5e063a0a7fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930964757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stres
s_all.930964757
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.1623696314
Short name T908
Test name
Test status
Simulation time 21981486969 ps
CPU time 34.02 seconds
Started Mar 28 03:23:18 PM PDT 24
Finished Mar 28 03:23:52 PM PDT 24
Peak memory 216836 kb
Host smart-16337718-ae08-4e97-8a22-81ea10749ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623696314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.1623696314
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.303105858
Short name T502
Test name
Test status
Simulation time 946295639 ps
CPU time 4.02 seconds
Started Mar 28 03:23:11 PM PDT 24
Finished Mar 28 03:23:15 PM PDT 24
Peak memory 216620 kb
Host smart-a681a354-49f7-44fa-b884-96189b5f99fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303105858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.303105858
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.454273141
Short name T651
Test name
Test status
Simulation time 333238507 ps
CPU time 2.23 seconds
Started Mar 28 03:23:18 PM PDT 24
Finished Mar 28 03:23:22 PM PDT 24
Peak memory 216644 kb
Host smart-4d495f21-aa24-4450-8b2b-c1b7b63866c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454273141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.454273141
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.2485661254
Short name T280
Test name
Test status
Simulation time 105978564 ps
CPU time 0.93 seconds
Started Mar 28 03:23:19 PM PDT 24
Finished Mar 28 03:23:20 PM PDT 24
Peak memory 206000 kb
Host smart-13e4b9e1-1174-48c7-8a76-c1158872a7f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485661254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.2485661254
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.231392969
Short name T604
Test name
Test status
Simulation time 528637875 ps
CPU time 4.02 seconds
Started Mar 28 03:23:17 PM PDT 24
Finished Mar 28 03:23:21 PM PDT 24
Peak memory 218984 kb
Host smart-8a144410-096d-44fb-9156-c24ae6e302e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231392969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.231392969
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.506694287
Short name T553
Test name
Test status
Simulation time 15350471 ps
CPU time 0.72 seconds
Started Mar 28 03:23:29 PM PDT 24
Finished Mar 28 03:23:30 PM PDT 24
Peak memory 205888 kb
Host smart-b9ea2381-cc13-4fca-9387-6227447c4547
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506694287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.506694287
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.854437339
Short name T355
Test name
Test status
Simulation time 3471445044 ps
CPU time 11.56 seconds
Started Mar 28 03:23:26 PM PDT 24
Finished Mar 28 03:23:38 PM PDT 24
Peak memory 234884 kb
Host smart-8b3b51ba-9dda-4a40-824b-ce0a1f7af43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854437339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.854437339
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.3609800158
Short name T498
Test name
Test status
Simulation time 109648174 ps
CPU time 0.75 seconds
Started Mar 28 03:23:24 PM PDT 24
Finished Mar 28 03:23:25 PM PDT 24
Peak memory 205968 kb
Host smart-68d4c5ab-df53-4da6-bbed-59a10e3c0c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609800158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.3609800158
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.3559451249
Short name T600
Test name
Test status
Simulation time 17328794354 ps
CPU time 87.53 seconds
Started Mar 28 03:23:30 PM PDT 24
Finished Mar 28 03:24:58 PM PDT 24
Peak memory 239316 kb
Host smart-917471a5-15ba-41be-b532-21a3a0f5cd36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559451249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.3559451249
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.4025031560
Short name T388
Test name
Test status
Simulation time 13327904643 ps
CPU time 97.7 seconds
Started Mar 28 03:23:26 PM PDT 24
Finished Mar 28 03:25:04 PM PDT 24
Peak memory 235708 kb
Host smart-fc069107-aaab-433f-8da0-d1c92a7a19c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025031560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.4025031560
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.50138896
Short name T608
Test name
Test status
Simulation time 58814646588 ps
CPU time 117.68 seconds
Started Mar 28 03:23:27 PM PDT 24
Finished Mar 28 03:25:27 PM PDT 24
Peak memory 241460 kb
Host smart-047d6414-894f-4858-b4a4-50847753d8fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50138896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle.50138896
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.730178764
Short name T171
Test name
Test status
Simulation time 16600291204 ps
CPU time 17.52 seconds
Started Mar 28 03:23:27 PM PDT 24
Finished Mar 28 03:23:45 PM PDT 24
Peak memory 239048 kb
Host smart-6d70aed5-25da-40f2-adb6-24463a1597cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730178764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.730178764
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.826163302
Short name T438
Test name
Test status
Simulation time 7425569866 ps
CPU time 14.63 seconds
Started Mar 28 03:23:28 PM PDT 24
Finished Mar 28 03:23:43 PM PDT 24
Peak memory 220296 kb
Host smart-926911a5-35a3-4054-b398-17f412db58c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826163302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.826163302
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.3577180483
Short name T349
Test name
Test status
Simulation time 7360201161 ps
CPU time 22.45 seconds
Started Mar 28 03:23:29 PM PDT 24
Finished Mar 28 03:23:52 PM PDT 24
Peak memory 231364 kb
Host smart-8882afcd-74c4-4919-a113-a99950ee7c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577180483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.3577180483
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.2479083826
Short name T870
Test name
Test status
Simulation time 98749662760 ps
CPU time 14.14 seconds
Started Mar 28 03:23:26 PM PDT 24
Finished Mar 28 03:23:40 PM PDT 24
Peak memory 228880 kb
Host smart-d9d97d35-f19b-4986-85db-3d54928e173c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479083826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.2479083826
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.1803139706
Short name T696
Test name
Test status
Simulation time 6494219548 ps
CPU time 7.84 seconds
Started Mar 28 03:23:25 PM PDT 24
Finished Mar 28 03:23:33 PM PDT 24
Peak memory 233668 kb
Host smart-0caec0b2-3343-4290-bbf3-65411cbb8254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803139706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.1803139706
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.3922461548
Short name T284
Test name
Test status
Simulation time 1056116324 ps
CPU time 3.61 seconds
Started Mar 28 03:23:27 PM PDT 24
Finished Mar 28 03:23:32 PM PDT 24
Peak memory 219688 kb
Host smart-f468b1a2-7f7e-4d22-aa72-ad170ed1fec8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3922461548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.3922461548
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.516915912
Short name T393
Test name
Test status
Simulation time 1405680675 ps
CPU time 23.49 seconds
Started Mar 28 03:23:27 PM PDT 24
Finished Mar 28 03:23:51 PM PDT 24
Peak memory 221508 kb
Host smart-0cd3a486-eed3-4b15-bff2-f97180dc861d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516915912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stres
s_all.516915912
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.2140934297
Short name T593
Test name
Test status
Simulation time 8701605348 ps
CPU time 45.08 seconds
Started Mar 28 03:23:30 PM PDT 24
Finished Mar 28 03:24:15 PM PDT 24
Peak memory 216876 kb
Host smart-14bbf9bf-34c0-40a5-a47a-c465fb43f235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140934297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.2140934297
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.3057198821
Short name T286
Test name
Test status
Simulation time 3152705096 ps
CPU time 8.04 seconds
Started Mar 28 03:23:24 PM PDT 24
Finished Mar 28 03:23:32 PM PDT 24
Peak memory 216748 kb
Host smart-2e59b717-8a98-4e18-88c6-7bf68fab96af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057198821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.3057198821
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.1806090500
Short name T431
Test name
Test status
Simulation time 113497620 ps
CPU time 1.09 seconds
Started Mar 28 03:23:29 PM PDT 24
Finished Mar 28 03:23:30 PM PDT 24
Peak memory 208216 kb
Host smart-e9f2a4e9-ba19-4067-a70a-47b75ff8110e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806090500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.1806090500
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.504936016
Short name T278
Test name
Test status
Simulation time 113238432 ps
CPU time 1.02 seconds
Started Mar 28 03:23:24 PM PDT 24
Finished Mar 28 03:23:25 PM PDT 24
Peak memory 206124 kb
Host smart-f1e855dc-35f0-4fc8-9044-6beb616a4e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504936016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.504936016
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.1061191765
Short name T214
Test name
Test status
Simulation time 17096072383 ps
CPU time 13.72 seconds
Started Mar 28 03:23:26 PM PDT 24
Finished Mar 28 03:23:40 PM PDT 24
Peak memory 236088 kb
Host smart-61bb1c54-217e-445a-9cc1-58b524cd0c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061191765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.1061191765
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.3077435095
Short name T492
Test name
Test status
Simulation time 22042856 ps
CPU time 0.74 seconds
Started Mar 28 03:21:30 PM PDT 24
Finished Mar 28 03:21:30 PM PDT 24
Peak memory 205712 kb
Host smart-94ac7d8f-5a92-4e90-814a-f337012385d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077435095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.3
077435095
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.2331753983
Short name T410
Test name
Test status
Simulation time 1490979043 ps
CPU time 4.86 seconds
Started Mar 28 03:21:32 PM PDT 24
Finished Mar 28 03:21:37 PM PDT 24
Peak memory 233940 kb
Host smart-171f72fe-c40c-4899-b61d-574ededc5f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331753983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.2331753983
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.350080399
Short name T320
Test name
Test status
Simulation time 82560099 ps
CPU time 0.72 seconds
Started Mar 28 03:21:31 PM PDT 24
Finished Mar 28 03:21:31 PM PDT 24
Peak memory 206136 kb
Host smart-7d5052cf-8857-4728-912f-e3a1f28cd9ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350080399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.350080399
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.2555836981
Short name T500
Test name
Test status
Simulation time 56653920253 ps
CPU time 121.6 seconds
Started Mar 28 03:21:26 PM PDT 24
Finished Mar 28 03:23:28 PM PDT 24
Peak memory 253572 kb
Host smart-22a58a45-3080-4240-9302-fa04bddf2163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555836981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.2555836981
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.2158734832
Short name T259
Test name
Test status
Simulation time 1690999394 ps
CPU time 16.25 seconds
Started Mar 28 03:21:32 PM PDT 24
Finished Mar 28 03:21:48 PM PDT 24
Peak memory 233036 kb
Host smart-5f390d79-bc79-4ada-9441-89a3375d1a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158734832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.2158734832
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.3368230474
Short name T209
Test name
Test status
Simulation time 268819497 ps
CPU time 3.37 seconds
Started Mar 28 03:21:30 PM PDT 24
Finished Mar 28 03:21:34 PM PDT 24
Peak memory 235008 kb
Host smart-3fbabb02-7459-4117-91cc-64355fed8687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368230474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.3368230474
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.95004720
Short name T647
Test name
Test status
Simulation time 4033327966 ps
CPU time 15.16 seconds
Started Mar 28 03:21:31 PM PDT 24
Finished Mar 28 03:21:46 PM PDT 24
Peak memory 234248 kb
Host smart-76fd076d-84e7-4464-bfe5-9a03b7737e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95004720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.95004720
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.370958620
Short name T412
Test name
Test status
Simulation time 5665251364 ps
CPU time 7.84 seconds
Started Mar 28 03:21:28 PM PDT 24
Finished Mar 28 03:21:37 PM PDT 24
Peak memory 234128 kb
Host smart-0dc56113-811f-4d39-91fb-f27e9b7326d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370958620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.
370958620
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.3930423916
Short name T672
Test name
Test status
Simulation time 818197606 ps
CPU time 9.58 seconds
Started Mar 28 03:21:25 PM PDT 24
Finished Mar 28 03:21:35 PM PDT 24
Peak memory 241104 kb
Host smart-3db72131-50b8-49dd-a14c-dbdc26f52524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930423916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.3930423916
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_ram_cfg.252288437
Short name T566
Test name
Test status
Simulation time 15965302 ps
CPU time 0.72 seconds
Started Mar 28 03:21:28 PM PDT 24
Finished Mar 28 03:21:30 PM PDT 24
Peak memory 216580 kb
Host smart-05f2bd48-d1db-4f0c-9ef2-8e642615cf0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252288437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_ram_cfg.252288437
Directory /workspace/3.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.3103622185
Short name T648
Test name
Test status
Simulation time 128462223 ps
CPU time 3.98 seconds
Started Mar 28 03:21:23 PM PDT 24
Finished Mar 28 03:21:27 PM PDT 24
Peak memory 222884 kb
Host smart-81960c11-749e-464f-99e0-2f4951c8f0ee
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3103622185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.3103622185
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.2019808568
Short name T56
Test name
Test status
Simulation time 61589055 ps
CPU time 1.15 seconds
Started Mar 28 03:21:27 PM PDT 24
Finished Mar 28 03:21:29 PM PDT 24
Peak memory 235640 kb
Host smart-5b3c78a2-746e-47ea-af74-d257062ecdab
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019808568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.2019808568
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.2091741048
Short name T636
Test name
Test status
Simulation time 10887599569 ps
CPU time 97.76 seconds
Started Mar 28 03:21:24 PM PDT 24
Finished Mar 28 03:23:02 PM PDT 24
Peak memory 257560 kb
Host smart-e2818047-e400-4978-9d25-92b41f8e04b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091741048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.2091741048
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.86636069
Short name T516
Test name
Test status
Simulation time 25418791846 ps
CPU time 65.67 seconds
Started Mar 28 03:21:32 PM PDT 24
Finished Mar 28 03:22:37 PM PDT 24
Peak memory 216924 kb
Host smart-ab364b6e-ce55-4fbd-a0b4-8bcf797dcdb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86636069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.86636069
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.2748005090
Short name T497
Test name
Test status
Simulation time 6693895108 ps
CPU time 18.47 seconds
Started Mar 28 03:21:35 PM PDT 24
Finished Mar 28 03:21:54 PM PDT 24
Peak memory 216824 kb
Host smart-749bcbd3-1661-4d70-99c6-741a565dc524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748005090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.2748005090
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.756121777
Short name T324
Test name
Test status
Simulation time 759863322 ps
CPU time 9.01 seconds
Started Mar 28 03:21:24 PM PDT 24
Finished Mar 28 03:21:34 PM PDT 24
Peak memory 216660 kb
Host smart-640a780d-af14-4188-88a2-56bd8739d29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756121777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.756121777
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.1572157164
Short name T76
Test name
Test status
Simulation time 104404518 ps
CPU time 1.09 seconds
Started Mar 28 03:21:24 PM PDT 24
Finished Mar 28 03:21:26 PM PDT 24
Peak memory 207196 kb
Host smart-020c3e1b-5c4b-467f-83a9-f7413d7589f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572157164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.1572157164
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.1193108456
Short name T493
Test name
Test status
Simulation time 2790068577 ps
CPU time 5.99 seconds
Started Mar 28 03:21:32 PM PDT 24
Finished Mar 28 03:21:38 PM PDT 24
Peak memory 221696 kb
Host smart-03f9288b-a2b2-4b27-b374-1e6d4798832c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193108456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.1193108456
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.18800106
Short name T666
Test name
Test status
Simulation time 12973594 ps
CPU time 0.73 seconds
Started Mar 28 03:23:27 PM PDT 24
Finished Mar 28 03:23:29 PM PDT 24
Peak memory 205884 kb
Host smart-afa0aac2-676b-41a9-a791-128c1192078d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18800106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.18800106
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.673311865
Short name T203
Test name
Test status
Simulation time 874853069 ps
CPU time 4.19 seconds
Started Mar 28 03:23:27 PM PDT 24
Finished Mar 28 03:23:31 PM PDT 24
Peak memory 221028 kb
Host smart-cde828f2-0373-4dc7-b784-8c01b799230b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673311865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.673311865
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.292090078
Short name T295
Test name
Test status
Simulation time 42196269 ps
CPU time 0.82 seconds
Started Mar 28 03:23:23 PM PDT 24
Finished Mar 28 03:23:25 PM PDT 24
Peak memory 207368 kb
Host smart-bbfeab3b-0690-4f53-b193-9cc6bf99c08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292090078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.292090078
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.3934103668
Short name T155
Test name
Test status
Simulation time 3183154904 ps
CPU time 54.77 seconds
Started Mar 28 03:23:27 PM PDT 24
Finished Mar 28 03:24:23 PM PDT 24
Peak memory 256904 kb
Host smart-45261d0e-b304-4290-8266-cec5920d50d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934103668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.3934103668
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.1724419632
Short name T116
Test name
Test status
Simulation time 76695804888 ps
CPU time 273.63 seconds
Started Mar 28 03:23:22 PM PDT 24
Finished Mar 28 03:27:57 PM PDT 24
Peak memory 249660 kb
Host smart-dbad6758-defc-4f9d-bb53-2977bff4dadb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724419632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.1724419632
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.3355648238
Short name T223
Test name
Test status
Simulation time 18450800041 ps
CPU time 48.03 seconds
Started Mar 28 03:23:30 PM PDT 24
Finished Mar 28 03:24:18 PM PDT 24
Peak memory 256264 kb
Host smart-f2da14e8-ec28-4bbc-8ca9-17071d7dc339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355648238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.3355648238
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.2176820059
Short name T704
Test name
Test status
Simulation time 2339790522 ps
CPU time 18.38 seconds
Started Mar 28 03:23:28 PM PDT 24
Finished Mar 28 03:23:47 PM PDT 24
Peak memory 247220 kb
Host smart-ef38e960-1781-43a8-a2f9-1bb1b5431397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176820059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.2176820059
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.4211750567
Short name T968
Test name
Test status
Simulation time 2357332857 ps
CPU time 8.61 seconds
Started Mar 28 03:23:26 PM PDT 24
Finished Mar 28 03:23:35 PM PDT 24
Peak memory 233756 kb
Host smart-707ce656-5ed5-4645-a49a-5f3f8984cc2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211750567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.4211750567
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.2954420817
Short name T605
Test name
Test status
Simulation time 5375528319 ps
CPU time 20.06 seconds
Started Mar 28 03:23:26 PM PDT 24
Finished Mar 28 03:23:46 PM PDT 24
Peak memory 248836 kb
Host smart-00db1513-0efe-4bda-8f23-f3fa38b19711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954420817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.2954420817
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.142938989
Short name T163
Test name
Test status
Simulation time 8257605197 ps
CPU time 11.52 seconds
Started Mar 28 03:23:30 PM PDT 24
Finished Mar 28 03:23:41 PM PDT 24
Peak memory 234236 kb
Host smart-74385e72-c6b0-4ba4-b8a0-82dc713c31bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142938989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap
.142938989
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.21364662
Short name T919
Test name
Test status
Simulation time 1147988764 ps
CPU time 6.46 seconds
Started Mar 28 03:23:27 PM PDT 24
Finished Mar 28 03:23:33 PM PDT 24
Peak memory 234220 kb
Host smart-5bebffa1-de8f-4540-b981-92b8962894c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21364662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.21364662
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.482694884
Short name T321
Test name
Test status
Simulation time 18421002750 ps
CPU time 5.59 seconds
Started Mar 28 03:23:30 PM PDT 24
Finished Mar 28 03:23:36 PM PDT 24
Peak memory 219220 kb
Host smart-9c44230e-5bf1-4974-b804-5426c91cf3e4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=482694884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dire
ct.482694884
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.1029418839
Short name T884
Test name
Test status
Simulation time 229599001 ps
CPU time 1.05 seconds
Started Mar 28 03:23:29 PM PDT 24
Finished Mar 28 03:23:30 PM PDT 24
Peak memory 207404 kb
Host smart-38b5bf72-0425-4a3d-a224-7cd443543b34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029418839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.1029418839
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.2052974188
Short name T902
Test name
Test status
Simulation time 16802230769 ps
CPU time 35.87 seconds
Started Mar 28 03:23:28 PM PDT 24
Finished Mar 28 03:24:05 PM PDT 24
Peak memory 216788 kb
Host smart-28cdc4bf-685a-4acf-a657-a6cb672f6a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052974188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.2052974188
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.509559289
Short name T868
Test name
Test status
Simulation time 477101849 ps
CPU time 1.93 seconds
Started Mar 28 03:23:27 PM PDT 24
Finished Mar 28 03:23:30 PM PDT 24
Peak memory 208192 kb
Host smart-c7ea7f56-e5ad-400c-819f-76535be27455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509559289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.509559289
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.2505004969
Short name T665
Test name
Test status
Simulation time 50539786 ps
CPU time 0.87 seconds
Started Mar 28 03:23:24 PM PDT 24
Finished Mar 28 03:23:25 PM PDT 24
Peak memory 206392 kb
Host smart-c5a922bd-6180-4dc3-8432-01341f3c1a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505004969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.2505004969
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.2965056516
Short name T318
Test name
Test status
Simulation time 65784864 ps
CPU time 0.96 seconds
Started Mar 28 03:23:28 PM PDT 24
Finished Mar 28 03:23:30 PM PDT 24
Peak memory 206188 kb
Host smart-dc61f693-b3e4-4b6b-862d-e555396e2930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965056516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.2965056516
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.3795978278
Short name T658
Test name
Test status
Simulation time 11432860474 ps
CPU time 13.39 seconds
Started Mar 28 03:23:27 PM PDT 24
Finished Mar 28 03:23:41 PM PDT 24
Peak memory 236516 kb
Host smart-4b96900c-6365-4b04-a92c-9634a2e82836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795978278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.3795978278
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.2134923438
Short name T319
Test name
Test status
Simulation time 38883628 ps
CPU time 0.74 seconds
Started Mar 28 03:23:26 PM PDT 24
Finished Mar 28 03:23:26 PM PDT 24
Peak memory 206104 kb
Host smart-558ca01d-248f-4268-9482-9b96571b3555
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134923438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
2134923438
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.4196903526
Short name T650
Test name
Test status
Simulation time 629032870 ps
CPU time 3.35 seconds
Started Mar 28 03:23:29 PM PDT 24
Finished Mar 28 03:23:33 PM PDT 24
Peak memory 220228 kb
Host smart-8ea80942-5495-4dc3-932b-df96e21be8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196903526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.4196903526
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.1709163146
Short name T1
Test name
Test status
Simulation time 107513285 ps
CPU time 0.81 seconds
Started Mar 28 03:23:30 PM PDT 24
Finished Mar 28 03:23:31 PM PDT 24
Peak memory 207028 kb
Host smart-46a15d62-378d-49ba-abaf-28939270bd80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709163146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.1709163146
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.2225795115
Short name T154
Test name
Test status
Simulation time 201475985618 ps
CPU time 247.47 seconds
Started Mar 28 03:23:30 PM PDT 24
Finished Mar 28 03:27:38 PM PDT 24
Peak memory 250440 kb
Host smart-401ff58e-c204-4f5c-b811-b9091017e3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225795115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.2225795115
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.3429247968
Short name T176
Test name
Test status
Simulation time 98546636406 ps
CPU time 376.06 seconds
Started Mar 28 03:23:29 PM PDT 24
Finished Mar 28 03:29:45 PM PDT 24
Peak memory 257120 kb
Host smart-2320dc80-7d63-4700-bbb4-9c5ea258eb98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429247968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.3429247968
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.854116152
Short name T477
Test name
Test status
Simulation time 52735732824 ps
CPU time 234.12 seconds
Started Mar 28 03:23:32 PM PDT 24
Finished Mar 28 03:27:27 PM PDT 24
Peak memory 254692 kb
Host smart-60c85008-a24a-4081-8e21-c8f9158fb23e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854116152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idle
.854116152
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.3819365386
Short name T575
Test name
Test status
Simulation time 9805579629 ps
CPU time 27.8 seconds
Started Mar 28 03:23:28 PM PDT 24
Finished Mar 28 03:23:57 PM PDT 24
Peak memory 239952 kb
Host smart-041500df-82d7-4ceb-9f29-fe231504466f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819365386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.3819365386
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.1437793183
Short name T836
Test name
Test status
Simulation time 13657499109 ps
CPU time 12.58 seconds
Started Mar 28 03:23:28 PM PDT 24
Finished Mar 28 03:23:41 PM PDT 24
Peak memory 233976 kb
Host smart-b24fcf4b-4aab-4c7a-801a-fd0114141680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437793183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.1437793183
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.3429138550
Short name T205
Test name
Test status
Simulation time 14169558549 ps
CPU time 11.38 seconds
Started Mar 28 03:23:30 PM PDT 24
Finished Mar 28 03:23:42 PM PDT 24
Peak memory 235008 kb
Host smart-ba1de48d-b728-415c-af3d-d192897e1a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429138550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.3429138550
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.3993430646
Short name T756
Test name
Test status
Simulation time 10420535933 ps
CPU time 29.41 seconds
Started Mar 28 03:23:26 PM PDT 24
Finished Mar 28 03:23:55 PM PDT 24
Peak memory 241252 kb
Host smart-aa83c3b9-55a8-4827-9da1-ecf5510e022e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993430646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.3993430646
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.2360574971
Short name T725
Test name
Test status
Simulation time 907283224 ps
CPU time 4.34 seconds
Started Mar 28 03:23:30 PM PDT 24
Finished Mar 28 03:23:35 PM PDT 24
Peak memory 218960 kb
Host smart-afbaa3fe-6397-43f7-841b-e9d0deba888e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360574971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.2360574971
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.2710050197
Short name T308
Test name
Test status
Simulation time 9415885636 ps
CPU time 8.81 seconds
Started Mar 28 03:23:27 PM PDT 24
Finished Mar 28 03:23:37 PM PDT 24
Peak memory 219564 kb
Host smart-5ab19981-19e9-434c-b3af-fcc32a48ca7f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2710050197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.2710050197
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.3333471163
Short name T733
Test name
Test status
Simulation time 165273498 ps
CPU time 1.08 seconds
Started Mar 28 03:23:32 PM PDT 24
Finished Mar 28 03:23:33 PM PDT 24
Peak memory 207392 kb
Host smart-fa9dd871-c98f-4c90-af60-2ae399759c15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333471163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.3333471163
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.1044533665
Short name T547
Test name
Test status
Simulation time 4665209975 ps
CPU time 48.68 seconds
Started Mar 28 03:23:26 PM PDT 24
Finished Mar 28 03:24:15 PM PDT 24
Peak memory 221440 kb
Host smart-9769dd46-9d5a-436c-972f-3b88fe8b81a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044533665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.1044533665
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.4030028331
Short name T283
Test name
Test status
Simulation time 2529699248 ps
CPU time 6.36 seconds
Started Mar 28 03:23:27 PM PDT 24
Finished Mar 28 03:23:34 PM PDT 24
Peak memory 216744 kb
Host smart-4244f848-681c-4045-a5f3-a72a1561b53f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030028331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.4030028331
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.320720177
Short name T711
Test name
Test status
Simulation time 33719982 ps
CPU time 1.34 seconds
Started Mar 28 03:23:28 PM PDT 24
Finished Mar 28 03:23:30 PM PDT 24
Peak memory 216420 kb
Host smart-f36343f5-b3d9-4547-84f6-f2d7a747d09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320720177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.320720177
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.2201286482
Short name T377
Test name
Test status
Simulation time 186957286 ps
CPU time 0.82 seconds
Started Mar 28 03:23:27 PM PDT 24
Finished Mar 28 03:23:28 PM PDT 24
Peak memory 206184 kb
Host smart-dcbc964d-79e1-4b0e-aa91-6a7c8120a4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201286482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.2201286482
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.1482139009
Short name T194
Test name
Test status
Simulation time 22576598966 ps
CPU time 36.97 seconds
Started Mar 28 03:23:27 PM PDT 24
Finished Mar 28 03:24:05 PM PDT 24
Peak memory 237088 kb
Host smart-a75a3f4e-d4e1-4f31-a75b-222c04a4a3eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482139009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.1482139009
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.4184901435
Short name T560
Test name
Test status
Simulation time 12794678 ps
CPU time 0.72 seconds
Started Mar 28 03:23:25 PM PDT 24
Finished Mar 28 03:23:26 PM PDT 24
Peak memory 205852 kb
Host smart-38843f22-11e3-43ae-a6e2-66ff3d6cd222
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184901435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
4184901435
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.2689676859
Short name T425
Test name
Test status
Simulation time 7022615893 ps
CPU time 8.72 seconds
Started Mar 28 03:23:28 PM PDT 24
Finished Mar 28 03:23:37 PM PDT 24
Peak memory 239944 kb
Host smart-bcc069fa-0180-4438-b34e-7a59075ffd0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689676859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.2689676859
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.3966910217
Short name T361
Test name
Test status
Simulation time 70549087 ps
CPU time 0.86 seconds
Started Mar 28 03:23:32 PM PDT 24
Finished Mar 28 03:23:33 PM PDT 24
Peak memory 206924 kb
Host smart-7cf26322-4f18-4787-a4e4-02c724a8f1b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966910217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.3966910217
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.2801573041
Short name T375
Test name
Test status
Simulation time 16770543805 ps
CPU time 28.33 seconds
Started Mar 28 03:23:32 PM PDT 24
Finished Mar 28 03:24:01 PM PDT 24
Peak memory 235972 kb
Host smart-43edf2e0-0829-4142-9f6b-fc2d86caaa01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801573041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.2801573041
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.219540548
Short name T769
Test name
Test status
Simulation time 2078902209 ps
CPU time 24.73 seconds
Started Mar 28 03:23:26 PM PDT 24
Finished Mar 28 03:23:51 PM PDT 24
Peak memory 238540 kb
Host smart-b86316ec-634a-49f5-8eb1-1dbc6254aef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219540548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle
.219540548
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.2747621374
Short name T437
Test name
Test status
Simulation time 84233412601 ps
CPU time 24.2 seconds
Started Mar 28 03:23:30 PM PDT 24
Finished Mar 28 03:23:54 PM PDT 24
Peak memory 248060 kb
Host smart-dabc7b94-bc36-4e71-ac1f-985ee8d22713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747621374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.2747621374
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.2050744126
Short name T551
Test name
Test status
Simulation time 12505362557 ps
CPU time 7.05 seconds
Started Mar 28 03:23:29 PM PDT 24
Finished Mar 28 03:23:36 PM PDT 24
Peak memory 233696 kb
Host smart-8ffb1fcd-b0dc-4d0c-8de3-c76cd327114c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050744126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.2050744126
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.3218805568
Short name T519
Test name
Test status
Simulation time 2013446334 ps
CPU time 8.69 seconds
Started Mar 28 03:23:30 PM PDT 24
Finished Mar 28 03:23:39 PM PDT 24
Peak memory 240276 kb
Host smart-4728bed7-af26-40fa-9f3e-87af35ff7876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218805568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.3218805568
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.3405708380
Short name T341
Test name
Test status
Simulation time 47190400472 ps
CPU time 22.24 seconds
Started Mar 28 03:23:28 PM PDT 24
Finished Mar 28 03:23:51 PM PDT 24
Peak memory 239120 kb
Host smart-e9b1c146-bdf3-40ca-9fc7-bf7e96110fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405708380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.3405708380
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.4240021847
Short name T947
Test name
Test status
Simulation time 32868252035 ps
CPU time 43.68 seconds
Started Mar 28 03:23:32 PM PDT 24
Finished Mar 28 03:24:16 PM PDT 24
Peak memory 237752 kb
Host smart-2098d7ce-b9ab-4a70-a601-d0a18140cb5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240021847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.4240021847
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.1705968705
Short name T378
Test name
Test status
Simulation time 621643741 ps
CPU time 5.14 seconds
Started Mar 28 03:23:26 PM PDT 24
Finished Mar 28 03:23:31 PM PDT 24
Peak memory 222688 kb
Host smart-15a1aabf-43c0-47b5-b19d-b691e8339d06
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1705968705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.1705968705
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.3918004310
Short name T863
Test name
Test status
Simulation time 747717095 ps
CPU time 1.14 seconds
Started Mar 28 03:23:30 PM PDT 24
Finished Mar 28 03:23:31 PM PDT 24
Peak memory 207552 kb
Host smart-504d79d5-b1da-4364-8a70-1b6c1bd7526c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918004310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.3918004310
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.1254437050
Short name T445
Test name
Test status
Simulation time 2921444863 ps
CPU time 9.38 seconds
Started Mar 28 03:23:27 PM PDT 24
Finished Mar 28 03:23:37 PM PDT 24
Peak memory 216768 kb
Host smart-77ed0d4f-c53d-4b07-826e-a794ec908a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254437050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.1254437050
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.1112977013
Short name T941
Test name
Test status
Simulation time 213029096 ps
CPU time 2.39 seconds
Started Mar 28 03:23:38 PM PDT 24
Finished Mar 28 03:23:41 PM PDT 24
Peak memory 216672 kb
Host smart-223c4f4d-de8e-43ce-954f-7caf101143fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112977013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1112977013
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.3211134427
Short name T478
Test name
Test status
Simulation time 157764253 ps
CPU time 0.84 seconds
Started Mar 28 03:23:27 PM PDT 24
Finished Mar 28 03:23:28 PM PDT 24
Peak memory 206100 kb
Host smart-71c295f0-9c0d-45b2-9bd8-4a077a218a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211134427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.3211134427
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.911177095
Short name T904
Test name
Test status
Simulation time 6346342194 ps
CPU time 12.8 seconds
Started Mar 28 03:23:27 PM PDT 24
Finished Mar 28 03:23:40 PM PDT 24
Peak memory 234640 kb
Host smart-07e5d30a-126e-4bdb-affe-534e77dbc457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911177095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.911177095
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.3710462398
Short name T371
Test name
Test status
Simulation time 29272744 ps
CPU time 0.71 seconds
Started Mar 28 03:23:43 PM PDT 24
Finished Mar 28 03:23:44 PM PDT 24
Peak memory 205788 kb
Host smart-6d1b8586-b290-45d5-b83f-d2be2456da13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710462398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
3710462398
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.3284215739
Short name T10
Test name
Test status
Simulation time 279832098 ps
CPU time 3.83 seconds
Started Mar 28 03:23:42 PM PDT 24
Finished Mar 28 03:23:46 PM PDT 24
Peak memory 220136 kb
Host smart-b067f7a0-087a-48c2-8d0b-b8a4b6678ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284215739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.3284215739
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.3156868794
Short name T736
Test name
Test status
Simulation time 30595010 ps
CPU time 0.78 seconds
Started Mar 28 03:23:27 PM PDT 24
Finished Mar 28 03:23:29 PM PDT 24
Peak memory 206292 kb
Host smart-4a3d4784-4c80-4306-9367-40ac51563c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156868794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.3156868794
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.993869285
Short name T549
Test name
Test status
Simulation time 16785363986 ps
CPU time 117.9 seconds
Started Mar 28 03:23:44 PM PDT 24
Finished Mar 28 03:25:43 PM PDT 24
Peak memory 251640 kb
Host smart-9ff71567-1869-4aed-81fb-dd9b23597550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993869285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.993869285
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.4293103192
Short name T215
Test name
Test status
Simulation time 4359110706 ps
CPU time 82.43 seconds
Started Mar 28 03:23:43 PM PDT 24
Finished Mar 28 03:25:06 PM PDT 24
Peak memory 257128 kb
Host smart-1a521261-a5d8-48a0-8b51-891777a17148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293103192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.4293103192
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.1346887036
Short name T732
Test name
Test status
Simulation time 11661275168 ps
CPU time 20.6 seconds
Started Mar 28 03:23:43 PM PDT 24
Finished Mar 28 03:24:03 PM PDT 24
Peak memory 234424 kb
Host smart-d0db6440-bd94-4847-aef5-afabed3c9c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346887036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.1346887036
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.928807753
Short name T509
Test name
Test status
Simulation time 602631676 ps
CPU time 5.52 seconds
Started Mar 28 03:23:33 PM PDT 24
Finished Mar 28 03:23:38 PM PDT 24
Peak memory 220128 kb
Host smart-df1126d6-8a60-4df7-88c6-d6b2cb70bfd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928807753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.928807753
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.936304350
Short name T684
Test name
Test status
Simulation time 18992554480 ps
CPU time 14.35 seconds
Started Mar 28 03:23:32 PM PDT 24
Finished Mar 28 03:23:46 PM PDT 24
Peak memory 223392 kb
Host smart-2c264fe1-accd-4dfd-88fd-4a231baa8c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936304350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.936304350
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.2127939208
Short name T188
Test name
Test status
Simulation time 16756129465 ps
CPU time 45.79 seconds
Started Mar 28 03:23:30 PM PDT 24
Finished Mar 28 03:24:16 PM PDT 24
Peak memory 238128 kb
Host smart-505386ad-dfe3-4a52-a0d9-a25ecf2d6f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127939208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.2127939208
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.281917099
Short name T40
Test name
Test status
Simulation time 1338589924 ps
CPU time 2.43 seconds
Started Mar 28 03:23:27 PM PDT 24
Finished Mar 28 03:23:31 PM PDT 24
Peak memory 224876 kb
Host smart-64f9b518-72c4-4d7e-a2c3-f3006e82e231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281917099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.281917099
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.1827033461
Short name T39
Test name
Test status
Simulation time 110047021 ps
CPU time 3.65 seconds
Started Mar 28 03:23:42 PM PDT 24
Finished Mar 28 03:23:46 PM PDT 24
Peak memory 222616 kb
Host smart-9547465e-a2b5-44b8-a540-78ca4c0a955e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1827033461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.1827033461
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.359171624
Short name T380
Test name
Test status
Simulation time 2161936926 ps
CPU time 22.62 seconds
Started Mar 28 03:23:27 PM PDT 24
Finished Mar 28 03:23:51 PM PDT 24
Peak memory 216836 kb
Host smart-533905ad-e19a-4d6a-ae27-8a62c3abc7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359171624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.359171624
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.2535135221
Short name T645
Test name
Test status
Simulation time 8788132523 ps
CPU time 28.3 seconds
Started Mar 28 03:23:32 PM PDT 24
Finished Mar 28 03:24:00 PM PDT 24
Peak memory 216812 kb
Host smart-e16775e7-7fcd-44f2-a678-cc094d85eedb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535135221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.2535135221
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.3958081523
Short name T471
Test name
Test status
Simulation time 81755988 ps
CPU time 1.35 seconds
Started Mar 28 03:23:32 PM PDT 24
Finished Mar 28 03:23:33 PM PDT 24
Peak memory 216728 kb
Host smart-a7cc575c-9c42-484d-a952-1e4eae554248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958081523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.3958081523
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.1346948608
Short name T797
Test name
Test status
Simulation time 42447998 ps
CPU time 0.69 seconds
Started Mar 28 03:23:27 PM PDT 24
Finished Mar 28 03:23:29 PM PDT 24
Peak memory 206208 kb
Host smart-2fb92177-2bcf-4321-9d3f-11dbe3313447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346948608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.1346948608
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.2381795761
Short name T743
Test name
Test status
Simulation time 4354394798 ps
CPU time 6.74 seconds
Started Mar 28 03:23:29 PM PDT 24
Finished Mar 28 03:23:36 PM PDT 24
Peak memory 237580 kb
Host smart-2f944418-0ba2-402c-9fb9-10633c4893bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381795761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.2381795761
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.3863366505
Short name T351
Test name
Test status
Simulation time 39855208 ps
CPU time 0.72 seconds
Started Mar 28 03:23:42 PM PDT 24
Finished Mar 28 03:23:43 PM PDT 24
Peak memory 205280 kb
Host smart-3c00ce98-5809-4aaa-bde2-6bc74889f4cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863366505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
3863366505
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.1520682784
Short name T199
Test name
Test status
Simulation time 4696418481 ps
CPU time 9.33 seconds
Started Mar 28 03:23:48 PM PDT 24
Finished Mar 28 03:23:57 PM PDT 24
Peak memory 220848 kb
Host smart-469c448d-6403-44fd-98bb-94e505faa004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520682784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.1520682784
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.3124899948
Short name T465
Test name
Test status
Simulation time 39284635 ps
CPU time 0.78 seconds
Started Mar 28 03:23:45 PM PDT 24
Finished Mar 28 03:23:46 PM PDT 24
Peak memory 207248 kb
Host smart-0e2fa9bd-7eb3-4f2c-a3a3-860491ec5c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124899948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.3124899948
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.3661505716
Short name T799
Test name
Test status
Simulation time 1165515742 ps
CPU time 18 seconds
Started Mar 28 03:23:48 PM PDT 24
Finished Mar 28 03:24:06 PM PDT 24
Peak memory 224896 kb
Host smart-3182868e-29a2-4b6b-b7f7-3e8f396f43a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661505716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.3661505716
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.388106620
Short name T220
Test name
Test status
Simulation time 60192275729 ps
CPU time 176.63 seconds
Started Mar 28 03:23:49 PM PDT 24
Finished Mar 28 03:26:47 PM PDT 24
Peak memory 265240 kb
Host smart-b6025bb6-e1d9-4885-b93f-841f6a73dd24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388106620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.388106620
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.1766930257
Short name T607
Test name
Test status
Simulation time 42249372317 ps
CPU time 293.22 seconds
Started Mar 28 03:23:47 PM PDT 24
Finished Mar 28 03:28:41 PM PDT 24
Peak memory 249712 kb
Host smart-ce897ce3-22f7-4c52-9a6f-03f06425cb77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766930257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.1766930257
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.2511440002
Short name T963
Test name
Test status
Simulation time 868333189 ps
CPU time 7.92 seconds
Started Mar 28 03:23:45 PM PDT 24
Finished Mar 28 03:23:53 PM PDT 24
Peak memory 239308 kb
Host smart-2edacc8f-4875-4e63-9103-9f8cf8a8020c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511440002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.2511440002
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.707040200
Short name T439
Test name
Test status
Simulation time 12217988067 ps
CPU time 13.37 seconds
Started Mar 28 03:23:49 PM PDT 24
Finished Mar 28 03:24:04 PM PDT 24
Peak memory 234976 kb
Host smart-ced1b86e-3934-45df-9b57-311159d60fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707040200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.707040200
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.4043765470
Short name T372
Test name
Test status
Simulation time 29154190413 ps
CPU time 20.34 seconds
Started Mar 28 03:23:42 PM PDT 24
Finished Mar 28 03:24:03 PM PDT 24
Peak memory 219156 kb
Host smart-3d75cb53-822c-425f-a76b-1683f2cee1bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043765470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.4043765470
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.1410267496
Short name T358
Test name
Test status
Simulation time 2715476318 ps
CPU time 8.89 seconds
Started Mar 28 03:23:41 PM PDT 24
Finished Mar 28 03:23:50 PM PDT 24
Peak memory 227588 kb
Host smart-a6e8172f-fde4-487c-803d-2c202fc5f6c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410267496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.1410267496
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.2628137330
Short name T168
Test name
Test status
Simulation time 4729450363 ps
CPU time 8.99 seconds
Started Mar 28 03:23:42 PM PDT 24
Finished Mar 28 03:23:51 PM PDT 24
Peak memory 218380 kb
Host smart-301ee716-9285-4d7e-a9b1-0c7f8582e792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628137330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.2628137330
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.3838299141
Short name T826
Test name
Test status
Simulation time 8964601401 ps
CPU time 5.26 seconds
Started Mar 28 03:23:45 PM PDT 24
Finished Mar 28 03:23:50 PM PDT 24
Peak memory 220876 kb
Host smart-a3ae3ad9-6ddb-4092-b0d6-4a1a37d7d617
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3838299141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.3838299141
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.3321469386
Short name T574
Test name
Test status
Simulation time 41728714028 ps
CPU time 282.63 seconds
Started Mar 28 03:23:45 PM PDT 24
Finished Mar 28 03:28:28 PM PDT 24
Peak memory 249692 kb
Host smart-255a8497-8b3a-47ee-91e2-7a02741ae159
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321469386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.3321469386
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.583628595
Short name T264
Test name
Test status
Simulation time 10092688138 ps
CPU time 51.36 seconds
Started Mar 28 03:23:46 PM PDT 24
Finished Mar 28 03:24:38 PM PDT 24
Peak memory 216768 kb
Host smart-e8564e3b-e8ac-43d7-883c-c6c1708ac2ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583628595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.583628595
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.4158466726
Short name T272
Test name
Test status
Simulation time 2011320466 ps
CPU time 3.72 seconds
Started Mar 28 03:23:49 PM PDT 24
Finished Mar 28 03:23:54 PM PDT 24
Peak memory 216668 kb
Host smart-adc2c3d1-45ce-4d04-806e-f13ba8d8ac98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158466726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.4158466726
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.3757609311
Short name T911
Test name
Test status
Simulation time 146167720 ps
CPU time 1.01 seconds
Started Mar 28 03:23:47 PM PDT 24
Finished Mar 28 03:23:48 PM PDT 24
Peak memory 207412 kb
Host smart-adebacb9-ebdb-4405-a3b6-b3c5ae16b3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757609311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.3757609311
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.1704127235
Short name T67
Test name
Test status
Simulation time 126394593 ps
CPU time 0.82 seconds
Started Mar 28 03:23:44 PM PDT 24
Finished Mar 28 03:23:46 PM PDT 24
Peak memory 206192 kb
Host smart-8793db39-0bd9-4d71-a730-fa0719f10e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704127235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.1704127235
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.1763174220
Short name T897
Test name
Test status
Simulation time 5863350247 ps
CPU time 20.6 seconds
Started Mar 28 03:23:48 PM PDT 24
Finished Mar 28 03:24:09 PM PDT 24
Peak memory 239428 kb
Host smart-94f63ddf-3bbc-4046-8a3d-849c30f2f2e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763174220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.1763174220
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.3016857385
Short name T973
Test name
Test status
Simulation time 35435847 ps
CPU time 0.78 seconds
Started Mar 28 03:23:45 PM PDT 24
Finished Mar 28 03:23:46 PM PDT 24
Peak memory 206228 kb
Host smart-c94adfbf-7dc7-4c10-ac1d-0f56e7091068
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016857385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
3016857385
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.2839056516
Short name T356
Test name
Test status
Simulation time 4321450755 ps
CPU time 8.24 seconds
Started Mar 28 03:23:45 PM PDT 24
Finished Mar 28 03:23:54 PM PDT 24
Peak memory 220636 kb
Host smart-ac01b3c7-f0ca-487e-b4d6-137414d326bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839056516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.2839056516
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.2450240076
Short name T850
Test name
Test status
Simulation time 46449894 ps
CPU time 0.82 seconds
Started Mar 28 03:23:47 PM PDT 24
Finished Mar 28 03:23:48 PM PDT 24
Peak memory 206020 kb
Host smart-ffe5d00a-59b5-4c3b-a7d1-cc5acab3721a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450240076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.2450240076
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.2512879624
Short name T859
Test name
Test status
Simulation time 26751695193 ps
CPU time 43.37 seconds
Started Mar 28 03:23:48 PM PDT 24
Finished Mar 28 03:24:32 PM PDT 24
Peak memory 249236 kb
Host smart-451b43e8-0f0b-4609-b14f-dde6d5046a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512879624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.2512879624
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.3997825430
Short name T866
Test name
Test status
Simulation time 16452615444 ps
CPU time 162.42 seconds
Started Mar 28 03:23:45 PM PDT 24
Finished Mar 28 03:26:27 PM PDT 24
Peak memory 257900 kb
Host smart-f89fa795-0be3-4573-ab8f-11f70980fd78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997825430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.3997825430
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.3440736785
Short name T910
Test name
Test status
Simulation time 94599179276 ps
CPU time 166.37 seconds
Started Mar 28 03:23:44 PM PDT 24
Finished Mar 28 03:26:31 PM PDT 24
Peak memory 262772 kb
Host smart-cc2d8a57-cf70-4f24-b11d-c0e12ec0d908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440736785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.3440736785
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.3409694778
Short name T571
Test name
Test status
Simulation time 18292572298 ps
CPU time 49.17 seconds
Started Mar 28 03:23:43 PM PDT 24
Finished Mar 28 03:24:33 PM PDT 24
Peak memory 235112 kb
Host smart-d9183e64-62fa-44d9-9349-8bb8c471a00f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409694778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.3409694778
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.3914679623
Short name T524
Test name
Test status
Simulation time 691005757 ps
CPU time 4.58 seconds
Started Mar 28 03:23:43 PM PDT 24
Finished Mar 28 03:23:47 PM PDT 24
Peak memory 234032 kb
Host smart-8452adc2-20c5-4dfe-90d9-a6cad248aa31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914679623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.3914679623
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.4070709411
Short name T374
Test name
Test status
Simulation time 30949053780 ps
CPU time 21.98 seconds
Started Mar 28 03:23:45 PM PDT 24
Finished Mar 28 03:24:07 PM PDT 24
Peak memory 241424 kb
Host smart-757a965c-0d1c-485b-ad3a-6e6c76fe2715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070709411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.4070709411
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.3965015279
Short name T818
Test name
Test status
Simulation time 5243213373 ps
CPU time 6.82 seconds
Started Mar 28 03:23:50 PM PDT 24
Finished Mar 28 03:23:57 PM PDT 24
Peak memory 236496 kb
Host smart-adb2efee-389f-4fa8-9045-f6ab10c48367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965015279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.3965015279
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.4055209637
Short name T603
Test name
Test status
Simulation time 10812998573 ps
CPU time 11.78 seconds
Started Mar 28 03:23:43 PM PDT 24
Finished Mar 28 03:23:55 PM PDT 24
Peak memory 234692 kb
Host smart-8f3244c5-a826-46e8-9165-e53bf0ab8072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055209637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.4055209637
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.1086715171
Short name T679
Test name
Test status
Simulation time 8514482408 ps
CPU time 5.52 seconds
Started Mar 28 03:23:44 PM PDT 24
Finished Mar 28 03:23:50 PM PDT 24
Peak memory 222656 kb
Host smart-a0e170f3-17c7-4fbe-ac6b-b77152dca0ad
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1086715171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.1086715171
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.674899819
Short name T132
Test name
Test status
Simulation time 70832247 ps
CPU time 1.22 seconds
Started Mar 28 03:23:45 PM PDT 24
Finished Mar 28 03:23:46 PM PDT 24
Peak memory 207644 kb
Host smart-253b78c5-cf51-4da2-8097-f03b56c1ca32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674899819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stres
s_all.674899819
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.80532247
Short name T267
Test name
Test status
Simulation time 8891934608 ps
CPU time 17.53 seconds
Started Mar 28 03:23:44 PM PDT 24
Finished Mar 28 03:24:02 PM PDT 24
Peak memory 216904 kb
Host smart-ca9b53f3-a977-4519-ae11-9b2080eaf93b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80532247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.80532247
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.4130850667
Short name T287
Test name
Test status
Simulation time 21796717715 ps
CPU time 16.5 seconds
Started Mar 28 03:23:43 PM PDT 24
Finished Mar 28 03:24:00 PM PDT 24
Peak memory 216796 kb
Host smart-d6d51e49-c634-4c1b-8ad5-7dd78576de13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130850667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.4130850667
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.2846473289
Short name T22
Test name
Test status
Simulation time 548672031 ps
CPU time 11.85 seconds
Started Mar 28 03:23:43 PM PDT 24
Finished Mar 28 03:23:55 PM PDT 24
Peak memory 216680 kb
Host smart-80076542-f2a1-496d-9817-4b82b38b1882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846473289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.2846473289
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.2087534530
Short name T964
Test name
Test status
Simulation time 27762639 ps
CPU time 0.77 seconds
Started Mar 28 03:23:46 PM PDT 24
Finished Mar 28 03:23:47 PM PDT 24
Peak memory 206192 kb
Host smart-7a49ce8d-b226-451f-bdd2-7275cea22e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087534530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.2087534530
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.2045870618
Short name T894
Test name
Test status
Simulation time 6044269838 ps
CPU time 21.57 seconds
Started Mar 28 03:23:48 PM PDT 24
Finished Mar 28 03:24:09 PM PDT 24
Peak memory 236064 kb
Host smart-d52e29a3-713c-4f85-8fbb-132e69aa6465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045870618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.2045870618
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.459190851
Short name T843
Test name
Test status
Simulation time 16342420 ps
CPU time 0.79 seconds
Started Mar 28 03:23:51 PM PDT 24
Finished Mar 28 03:23:53 PM PDT 24
Peak memory 205852 kb
Host smart-2284c3fe-3aef-4df5-9bc2-67e3c8e44856
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459190851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.459190851
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.275519541
Short name T660
Test name
Test status
Simulation time 223534323 ps
CPU time 3.1 seconds
Started Mar 28 03:23:45 PM PDT 24
Finished Mar 28 03:23:48 PM PDT 24
Peak memory 219008 kb
Host smart-7bf18d1c-a6e1-4943-9d45-fdd8710887af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275519541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.275519541
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.2498935452
Short name T513
Test name
Test status
Simulation time 20466402 ps
CPU time 0.85 seconds
Started Mar 28 03:23:46 PM PDT 24
Finished Mar 28 03:23:47 PM PDT 24
Peak memory 207016 kb
Host smart-81795b9d-a536-4bb0-b989-8e28b2bc23c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498935452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.2498935452
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.1167978823
Short name T247
Test name
Test status
Simulation time 293043086012 ps
CPU time 375.56 seconds
Started Mar 28 03:23:48 PM PDT 24
Finished Mar 28 03:30:04 PM PDT 24
Peak memory 263164 kb
Host smart-bca39dc0-9810-402f-a728-6286dada8acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167978823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.1167978823
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.2564449573
Short name T719
Test name
Test status
Simulation time 37706778436 ps
CPU time 95.99 seconds
Started Mar 28 03:23:48 PM PDT 24
Finished Mar 28 03:25:25 PM PDT 24
Peak memory 249548 kb
Host smart-96fa5d0d-14dc-40d3-bc79-f3abddcd6195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564449573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.2564449573
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.2935019146
Short name T218
Test name
Test status
Simulation time 99283667327 ps
CPU time 368.75 seconds
Started Mar 28 03:23:47 PM PDT 24
Finished Mar 28 03:29:56 PM PDT 24
Peak memory 269040 kb
Host smart-68b1b176-88c5-4c79-90df-fa530814fd01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935019146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.2935019146
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.953612395
Short name T456
Test name
Test status
Simulation time 670557511 ps
CPU time 9.63 seconds
Started Mar 28 03:23:48 PM PDT 24
Finished Mar 28 03:23:58 PM PDT 24
Peak memory 227480 kb
Host smart-21fdebc5-c3f5-476d-b60c-142338dc1c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953612395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.953612395
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.421550135
Short name T166
Test name
Test status
Simulation time 1294817642 ps
CPU time 3.4 seconds
Started Mar 28 03:23:47 PM PDT 24
Finished Mar 28 03:23:51 PM PDT 24
Peak memory 218996 kb
Host smart-5d2a87ba-e27b-4c6a-929c-af488519e02c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421550135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.421550135
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.1859989505
Short name T617
Test name
Test status
Simulation time 2041655924 ps
CPU time 13.72 seconds
Started Mar 28 03:23:46 PM PDT 24
Finished Mar 28 03:24:00 PM PDT 24
Peak memory 228892 kb
Host smart-12010040-67bd-48f8-a5fb-1f55a9de4d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859989505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.1859989505
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.1905996254
Short name T406
Test name
Test status
Simulation time 528226737 ps
CPU time 3.5 seconds
Started Mar 28 03:23:49 PM PDT 24
Finished Mar 28 03:23:53 PM PDT 24
Peak memory 234100 kb
Host smart-9be50db8-1b7a-42a7-8cec-b6574ffb3da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905996254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.1905996254
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.1279503680
Short name T686
Test name
Test status
Simulation time 6385069747 ps
CPU time 19.6 seconds
Started Mar 28 03:23:44 PM PDT 24
Finished Mar 28 03:24:04 PM PDT 24
Peak memory 241344 kb
Host smart-ee64aff0-4cc0-4d84-89e8-228cb380848f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279503680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.1279503680
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.3423928017
Short name T924
Test name
Test status
Simulation time 1458389256 ps
CPU time 3.66 seconds
Started Mar 28 03:23:48 PM PDT 24
Finished Mar 28 03:23:52 PM PDT 24
Peak memory 222684 kb
Host smart-f5178226-45a0-4b05-9412-1049d12c64be
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3423928017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.3423928017
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.910736367
Short name T236
Test name
Test status
Simulation time 372086785629 ps
CPU time 631.93 seconds
Started Mar 28 03:23:47 PM PDT 24
Finished Mar 28 03:34:19 PM PDT 24
Peak memory 272168 kb
Host smart-ed726d2d-18e5-4fe1-8ed3-9522850203ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910736367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stres
s_all.910736367
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.4205579671
Short name T626
Test name
Test status
Simulation time 2763921114 ps
CPU time 28.57 seconds
Started Mar 28 03:23:43 PM PDT 24
Finished Mar 28 03:24:12 PM PDT 24
Peak memory 217032 kb
Host smart-35f4b71a-0257-4708-90eb-a3e716e37e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205579671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.4205579671
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.625460445
Short name T918
Test name
Test status
Simulation time 5448284858 ps
CPU time 5.58 seconds
Started Mar 28 03:23:47 PM PDT 24
Finished Mar 28 03:23:53 PM PDT 24
Peak memory 216752 kb
Host smart-1d8651ad-127a-483c-8cae-3feee28953b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625460445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.625460445
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.2102749296
Short name T277
Test name
Test status
Simulation time 1621586104 ps
CPU time 18.32 seconds
Started Mar 28 03:23:44 PM PDT 24
Finished Mar 28 03:24:03 PM PDT 24
Peak memory 216648 kb
Host smart-dd60fac5-d9b0-4dfc-87ad-8af13d19687c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102749296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.2102749296
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.2751234859
Short name T730
Test name
Test status
Simulation time 95133823 ps
CPU time 0.83 seconds
Started Mar 28 03:23:46 PM PDT 24
Finished Mar 28 03:23:47 PM PDT 24
Peak memory 206164 kb
Host smart-2643b8b0-acb4-4827-96fe-7431f4d2a9a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751234859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.2751234859
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.2349342546
Short name T369
Test name
Test status
Simulation time 15535738470 ps
CPU time 18.49 seconds
Started Mar 28 03:23:47 PM PDT 24
Finished Mar 28 03:24:06 PM PDT 24
Peak memory 245340 kb
Host smart-1c308989-e089-4a0f-854e-43ea784c0ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349342546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.2349342546
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.3689028319
Short name T510
Test name
Test status
Simulation time 11809474 ps
CPU time 0.7 seconds
Started Mar 28 03:23:59 PM PDT 24
Finished Mar 28 03:24:01 PM PDT 24
Peak memory 205844 kb
Host smart-5e34dfb3-31cb-4c7a-aba1-3e0da37ca45b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689028319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
3689028319
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.1069422618
Short name T689
Test name
Test status
Simulation time 506092643 ps
CPU time 4.06 seconds
Started Mar 28 03:23:51 PM PDT 24
Finished Mar 28 03:23:56 PM PDT 24
Peak memory 236528 kb
Host smart-a6f3cf4e-5e7f-4a37-91fa-eef4c0ee4b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069422618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.1069422618
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.1186319780
Short name T701
Test name
Test status
Simulation time 12281430 ps
CPU time 0.73 seconds
Started Mar 28 03:23:44 PM PDT 24
Finished Mar 28 03:23:45 PM PDT 24
Peak memory 205940 kb
Host smart-c982f67d-1b58-4927-85fe-5173ea0ff77c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186319780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.1186319780
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.1048803737
Short name T816
Test name
Test status
Simulation time 228484998 ps
CPU time 4.84 seconds
Started Mar 28 03:23:51 PM PDT 24
Finished Mar 28 03:23:57 PM PDT 24
Peak memory 235756 kb
Host smart-f5979472-3e80-42fb-a02d-8145ed03699b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048803737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.1048803737
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.1700625181
Short name T971
Test name
Test status
Simulation time 28597090987 ps
CPU time 58.7 seconds
Started Mar 28 03:23:51 PM PDT 24
Finished Mar 28 03:24:50 PM PDT 24
Peak memory 238596 kb
Host smart-9b75df21-4555-43e3-a356-83aeb35fafff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700625181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.1700625181
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.1270244034
Short name T529
Test name
Test status
Simulation time 5274665756 ps
CPU time 14.7 seconds
Started Mar 28 03:23:47 PM PDT 24
Finished Mar 28 03:24:02 PM PDT 24
Peak memory 233088 kb
Host smart-f0759b5c-54ad-48b4-8997-73af974c9e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270244034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.1270244034
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.1671502409
Short name T178
Test name
Test status
Simulation time 3804123794 ps
CPU time 8.08 seconds
Started Mar 28 03:23:48 PM PDT 24
Finished Mar 28 03:23:56 PM PDT 24
Peak memory 221612 kb
Host smart-29147e1b-31ee-4add-9c1e-9ec45086208f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671502409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.1671502409
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.3139958270
Short name T333
Test name
Test status
Simulation time 21069217800 ps
CPU time 24.31 seconds
Started Mar 28 03:23:51 PM PDT 24
Finished Mar 28 03:24:16 PM PDT 24
Peak memory 227308 kb
Host smart-9d49d829-fe7d-4cb4-965d-8526941efd45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139958270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.3139958270
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.3053946860
Short name T170
Test name
Test status
Simulation time 1944595024 ps
CPU time 7.15 seconds
Started Mar 28 03:23:49 PM PDT 24
Finished Mar 28 03:23:56 PM PDT 24
Peak memory 222960 kb
Host smart-ce4284a7-1e94-46fa-9035-256a30de94f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053946860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.3053946860
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.1417146749
Short name T765
Test name
Test status
Simulation time 28017987977 ps
CPU time 40.51 seconds
Started Mar 28 03:23:47 PM PDT 24
Finished Mar 28 03:24:28 PM PDT 24
Peak memory 233820 kb
Host smart-fc809a31-1fc9-47e3-9ac8-426bce7812b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417146749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.1417146749
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.807303493
Short name T314
Test name
Test status
Simulation time 3402360760 ps
CPU time 4.27 seconds
Started Mar 28 03:23:46 PM PDT 24
Finished Mar 28 03:23:51 PM PDT 24
Peak memory 219316 kb
Host smart-a62f301a-05f3-4577-9423-127f36c4244a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=807303493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dire
ct.807303493
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.3704624830
Short name T642
Test name
Test status
Simulation time 200233399 ps
CPU time 1.11 seconds
Started Mar 28 03:23:58 PM PDT 24
Finished Mar 28 03:24:00 PM PDT 24
Peak memory 207212 kb
Host smart-9b3b5bee-2d56-4cb2-ac3c-0fbf8665b9f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704624830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.3704624830
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.2030536510
Short name T673
Test name
Test status
Simulation time 5795249587 ps
CPU time 9.77 seconds
Started Mar 28 03:23:48 PM PDT 24
Finished Mar 28 03:23:58 PM PDT 24
Peak memory 216804 kb
Host smart-306733fb-8663-48f7-81c5-274356231c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030536510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.2030536510
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.2353830789
Short name T847
Test name
Test status
Simulation time 8861836191 ps
CPU time 26.23 seconds
Started Mar 28 03:23:51 PM PDT 24
Finished Mar 28 03:24:18 PM PDT 24
Peak memory 216768 kb
Host smart-6b65d4e9-43e2-4e75-98a1-3c2ab4f0a4d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353830789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.2353830789
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.2041092269
Short name T328
Test name
Test status
Simulation time 321585200 ps
CPU time 1.18 seconds
Started Mar 28 03:23:49 PM PDT 24
Finished Mar 28 03:23:51 PM PDT 24
Peak memory 207528 kb
Host smart-dd16790d-0ab5-4176-b84a-072ef0863164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041092269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.2041092269
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.1016242314
Short name T582
Test name
Test status
Simulation time 49739505 ps
CPU time 0.91 seconds
Started Mar 28 03:23:45 PM PDT 24
Finished Mar 28 03:23:46 PM PDT 24
Peak memory 206672 kb
Host smart-90859048-c454-4f05-9813-176d15cb2092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016242314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.1016242314
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.4126366335
Short name T201
Test name
Test status
Simulation time 601276573 ps
CPU time 6.43 seconds
Started Mar 28 03:23:45 PM PDT 24
Finished Mar 28 03:23:52 PM PDT 24
Peak memory 233080 kb
Host smart-46612b9a-7ab8-44e7-a294-41269837f607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126366335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.4126366335
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.2998301962
Short name T542
Test name
Test status
Simulation time 30171475 ps
CPU time 0.69 seconds
Started Mar 28 03:24:00 PM PDT 24
Finished Mar 28 03:24:01 PM PDT 24
Peak memory 206228 kb
Host smart-f47b1a69-4190-4194-9854-18aff0a1f57c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998301962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
2998301962
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.724540988
Short name T382
Test name
Test status
Simulation time 1662901616 ps
CPU time 3.28 seconds
Started Mar 28 03:24:01 PM PDT 24
Finished Mar 28 03:24:05 PM PDT 24
Peak memory 234956 kb
Host smart-254712c9-f78f-4550-b812-f8c430f2b8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724540988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.724540988
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.2469590594
Short name T720
Test name
Test status
Simulation time 12766420 ps
CPU time 0.8 seconds
Started Mar 28 03:24:02 PM PDT 24
Finished Mar 28 03:24:03 PM PDT 24
Peak memory 206952 kb
Host smart-4327ad51-1bc1-44d5-8d23-1eb33afa9a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469590594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.2469590594
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.1502404066
Short name T812
Test name
Test status
Simulation time 58088598370 ps
CPU time 50.92 seconds
Started Mar 28 03:24:09 PM PDT 24
Finished Mar 28 03:25:00 PM PDT 24
Peak memory 239468 kb
Host smart-8fdf64c1-124b-440a-b1d3-4e31a9ff112d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502404066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.1502404066
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.2809787485
Short name T362
Test name
Test status
Simulation time 19491981400 ps
CPU time 65.67 seconds
Started Mar 28 03:24:02 PM PDT 24
Finished Mar 28 03:25:08 PM PDT 24
Peak memory 222840 kb
Host smart-b4e5540b-2c3d-44cd-9c44-bbbb0ef48540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809787485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.2809787485
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.2482772317
Short name T13
Test name
Test status
Simulation time 202234204278 ps
CPU time 85.97 seconds
Started Mar 28 03:24:01 PM PDT 24
Finished Mar 28 03:25:27 PM PDT 24
Peak memory 249660 kb
Host smart-79165529-6cee-430f-8e2a-169d5c20655f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482772317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.2482772317
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.3157632631
Short name T424
Test name
Test status
Simulation time 1640353185 ps
CPU time 16.29 seconds
Started Mar 28 03:24:04 PM PDT 24
Finished Mar 28 03:24:21 PM PDT 24
Peak memory 244952 kb
Host smart-b1c4bbed-6871-4443-af68-ab03995b8cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157632631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.3157632631
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.2061742205
Short name T596
Test name
Test status
Simulation time 935103214 ps
CPU time 5.03 seconds
Started Mar 28 03:24:04 PM PDT 24
Finished Mar 28 03:24:09 PM PDT 24
Peak memory 234152 kb
Host smart-b606c3de-3c69-4229-9604-741500d8381a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061742205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.2061742205
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.3299810629
Short name T467
Test name
Test status
Simulation time 5138092563 ps
CPU time 10.82 seconds
Started Mar 28 03:24:01 PM PDT 24
Finished Mar 28 03:24:12 PM PDT 24
Peak memory 232896 kb
Host smart-e43417ba-fec4-42b5-a681-d420e7b9369e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299810629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.3299810629
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.1003050201
Short name T216
Test name
Test status
Simulation time 14382872427 ps
CPU time 37.65 seconds
Started Mar 28 03:23:59 PM PDT 24
Finished Mar 28 03:24:37 PM PDT 24
Peak memory 240820 kb
Host smart-9e7dab29-6896-4e5b-bb5c-08b26d546f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003050201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.1003050201
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.3793386757
Short name T453
Test name
Test status
Simulation time 20025980642 ps
CPU time 31.22 seconds
Started Mar 28 03:24:01 PM PDT 24
Finished Mar 28 03:24:33 PM PDT 24
Peak memory 227552 kb
Host smart-251596b1-1124-4bf4-95fe-285b7e184afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793386757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.3793386757
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.4050371915
Short name T428
Test name
Test status
Simulation time 1465987761 ps
CPU time 4.02 seconds
Started Mar 28 03:24:01 PM PDT 24
Finished Mar 28 03:24:06 PM PDT 24
Peak memory 219876 kb
Host smart-b1db3c9d-8de2-4eb8-905b-9453cc547bb2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4050371915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.4050371915
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.3208713989
Short name T640
Test name
Test status
Simulation time 57117885 ps
CPU time 1.08 seconds
Started Mar 28 03:24:01 PM PDT 24
Finished Mar 28 03:24:03 PM PDT 24
Peak memory 207620 kb
Host smart-54a7f5ed-0703-4d9a-8a40-689c05f56d7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208713989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.3208713989
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.312091419
Short name T706
Test name
Test status
Simulation time 4450846634 ps
CPU time 32.98 seconds
Started Mar 28 03:24:08 PM PDT 24
Finished Mar 28 03:24:41 PM PDT 24
Peak memory 216872 kb
Host smart-9f1491a0-bce2-4345-8c8c-3cbbbfa3fc22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312091419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.312091419
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.356434541
Short name T546
Test name
Test status
Simulation time 1843043934 ps
CPU time 8 seconds
Started Mar 28 03:24:06 PM PDT 24
Finished Mar 28 03:24:14 PM PDT 24
Peak memory 216640 kb
Host smart-18b656fd-4683-4e25-8e47-210c959976bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356434541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.356434541
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.1447607768
Short name T864
Test name
Test status
Simulation time 381832013 ps
CPU time 3.44 seconds
Started Mar 28 03:23:59 PM PDT 24
Finished Mar 28 03:24:02 PM PDT 24
Peak memory 216884 kb
Host smart-06cfac40-0be8-46ac-a9b7-725918fd6c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447607768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.1447607768
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.3889798153
Short name T296
Test name
Test status
Simulation time 29258821 ps
CPU time 0.78 seconds
Started Mar 28 03:24:02 PM PDT 24
Finished Mar 28 03:24:03 PM PDT 24
Peak memory 206004 kb
Host smart-6335433b-ef2d-4c33-8b3a-e5c9ba3747ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889798153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.3889798153
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.1371763147
Short name T485
Test name
Test status
Simulation time 6994834855 ps
CPU time 11.92 seconds
Started Mar 28 03:24:02 PM PDT 24
Finished Mar 28 03:24:14 PM PDT 24
Peak memory 239916 kb
Host smart-02d8a807-4ca3-4f40-81c0-52542b4feeb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371763147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.1371763147
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.4283497945
Short name T675
Test name
Test status
Simulation time 45713310 ps
CPU time 0.73 seconds
Started Mar 28 03:24:06 PM PDT 24
Finished Mar 28 03:24:07 PM PDT 24
Peak memory 205304 kb
Host smart-0b664395-2b74-49ac-80d1-193d5dce9477
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283497945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
4283497945
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.1158156623
Short name T474
Test name
Test status
Simulation time 2075390675 ps
CPU time 4.57 seconds
Started Mar 28 03:24:01 PM PDT 24
Finished Mar 28 03:24:06 PM PDT 24
Peak memory 234564 kb
Host smart-31aff2c7-e145-40e6-a89e-c911bcad70ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158156623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.1158156623
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.1951165723
Short name T313
Test name
Test status
Simulation time 43785937 ps
CPU time 0.73 seconds
Started Mar 28 03:24:01 PM PDT 24
Finished Mar 28 03:24:02 PM PDT 24
Peak memory 206020 kb
Host smart-26ad49d9-9964-44d9-93d0-eb8267b2c4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951165723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.1951165723
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.2085091490
Short name T354
Test name
Test status
Simulation time 4011964463 ps
CPU time 42.23 seconds
Started Mar 28 03:24:01 PM PDT 24
Finished Mar 28 03:24:44 PM PDT 24
Peak memory 241372 kb
Host smart-7916513c-3502-42dc-ac2c-c56cfdf99993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085091490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.2085091490
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.1660807342
Short name T35
Test name
Test status
Simulation time 193655085256 ps
CPU time 604.07 seconds
Started Mar 28 03:24:09 PM PDT 24
Finished Mar 28 03:34:13 PM PDT 24
Peak memory 256360 kb
Host smart-12278321-1236-4a6b-8bb0-2944b06a1caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660807342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.1660807342
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.1901543293
Short name T32
Test name
Test status
Simulation time 6009192595 ps
CPU time 110.05 seconds
Started Mar 28 03:24:01 PM PDT 24
Finished Mar 28 03:25:52 PM PDT 24
Peak memory 253304 kb
Host smart-df6f4c59-9467-4907-91d7-2b4fa7e77961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901543293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.1901543293
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.2574223929
Short name T548
Test name
Test status
Simulation time 1071042359 ps
CPU time 11.3 seconds
Started Mar 28 03:24:05 PM PDT 24
Finished Mar 28 03:24:16 PM PDT 24
Peak memory 236616 kb
Host smart-c83e94ac-ca07-42da-a3b8-8e353d39827a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574223929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.2574223929
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.1876491601
Short name T233
Test name
Test status
Simulation time 1481120545 ps
CPU time 4.19 seconds
Started Mar 28 03:24:05 PM PDT 24
Finished Mar 28 03:24:09 PM PDT 24
Peak memory 219008 kb
Host smart-d762e900-cdf1-4719-902f-530bbe877f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876491601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.1876491601
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.230523066
Short name T649
Test name
Test status
Simulation time 776139937 ps
CPU time 7.43 seconds
Started Mar 28 03:24:00 PM PDT 24
Finished Mar 28 03:24:08 PM PDT 24
Peak memory 241264 kb
Host smart-4118ef40-2558-4c1a-91e5-df592bec1595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230523066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.230523066
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.2187756673
Short name T873
Test name
Test status
Simulation time 17500660864 ps
CPU time 25.77 seconds
Started Mar 28 03:24:00 PM PDT 24
Finished Mar 28 03:24:26 PM PDT 24
Peak memory 221704 kb
Host smart-95dccdba-f05c-428a-a1b4-b06e1a015343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187756673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.2187756673
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.514823830
Short name T949
Test name
Test status
Simulation time 19634481286 ps
CPU time 21.99 seconds
Started Mar 28 03:23:59 PM PDT 24
Finished Mar 28 03:24:22 PM PDT 24
Peak memory 225024 kb
Host smart-2b08c6e3-4ae4-4a5a-8232-440f176d8a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514823830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.514823830
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.4103999149
Short name T611
Test name
Test status
Simulation time 838708259 ps
CPU time 4.03 seconds
Started Mar 28 03:24:00 PM PDT 24
Finished Mar 28 03:24:05 PM PDT 24
Peak memory 223368 kb
Host smart-68727925-72a2-460b-8f8a-a496ba6f14d4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4103999149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.4103999149
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.245867291
Short name T126
Test name
Test status
Simulation time 228054614 ps
CPU time 1 seconds
Started Mar 28 03:24:06 PM PDT 24
Finished Mar 28 03:24:08 PM PDT 24
Peak memory 207416 kb
Host smart-ba785b70-0518-4efb-b5dd-300c6a9571eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245867291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stres
s_all.245867291
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.2293839955
Short name T338
Test name
Test status
Simulation time 14599954951 ps
CPU time 33.4 seconds
Started Mar 28 03:24:00 PM PDT 24
Finished Mar 28 03:24:34 PM PDT 24
Peak memory 216748 kb
Host smart-480f26f0-ff49-4fde-8f61-0e93e4209fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293839955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.2293839955
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.3680782393
Short name T914
Test name
Test status
Simulation time 750772930 ps
CPU time 2.95 seconds
Started Mar 28 03:24:07 PM PDT 24
Finished Mar 28 03:24:10 PM PDT 24
Peak memory 216760 kb
Host smart-5585bea3-0bae-40d0-92a0-fe270ff2cf2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680782393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.3680782393
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.4265897234
Short name T468
Test name
Test status
Simulation time 150028553 ps
CPU time 2.17 seconds
Started Mar 28 03:24:03 PM PDT 24
Finished Mar 28 03:24:05 PM PDT 24
Peak memory 216588 kb
Host smart-54d57e9a-bae9-4fa1-b06f-0fc56c606061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265897234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.4265897234
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.1473811134
Short name T479
Test name
Test status
Simulation time 301610252 ps
CPU time 0.99 seconds
Started Mar 28 03:24:02 PM PDT 24
Finished Mar 28 03:24:03 PM PDT 24
Peak memory 206180 kb
Host smart-bed9c1d9-da4d-49f1-84f3-aaf6c39591d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473811134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.1473811134
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.3740404599
Short name T671
Test name
Test status
Simulation time 787937000 ps
CPU time 12.37 seconds
Started Mar 28 03:24:02 PM PDT 24
Finished Mar 28 03:24:14 PM PDT 24
Peak memory 241240 kb
Host smart-20a44e6d-16db-4ffe-9b98-8523e599162b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740404599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.3740404599
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.3053088844
Short name T946
Test name
Test status
Simulation time 10832801 ps
CPU time 0.73 seconds
Started Mar 28 03:21:32 PM PDT 24
Finished Mar 28 03:21:32 PM PDT 24
Peak memory 205836 kb
Host smart-0f088b21-7d18-4d11-be8f-32b6d55cb07e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053088844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.3
053088844
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.4013506207
Short name T202
Test name
Test status
Simulation time 3844012546 ps
CPU time 4.47 seconds
Started Mar 28 03:21:29 PM PDT 24
Finished Mar 28 03:21:34 PM PDT 24
Peak memory 221168 kb
Host smart-8c99e254-efb2-4999-976b-91e7df40e5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013506207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.4013506207
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.2924218443
Short name T562
Test name
Test status
Simulation time 60637137 ps
CPU time 0.77 seconds
Started Mar 28 03:21:30 PM PDT 24
Finished Mar 28 03:21:31 PM PDT 24
Peak memory 207028 kb
Host smart-1c8122ee-519b-48ff-830f-f52d8c4e18db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924218443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.2924218443
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.1496228594
Short name T900
Test name
Test status
Simulation time 173309539658 ps
CPU time 205.89 seconds
Started Mar 28 03:21:31 PM PDT 24
Finished Mar 28 03:24:57 PM PDT 24
Peak memory 252740 kb
Host smart-88a407c2-9edf-49c2-9ec6-d5f9e0144e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496228594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.1496228594
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.707014265
Short name T483
Test name
Test status
Simulation time 14958743924 ps
CPU time 86.57 seconds
Started Mar 28 03:21:25 PM PDT 24
Finished Mar 28 03:22:52 PM PDT 24
Peak memory 255680 kb
Host smart-caff13dd-3933-400f-9328-6cb7bee24f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707014265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.707014265
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.3592850631
Short name T621
Test name
Test status
Simulation time 4652273102 ps
CPU time 103.57 seconds
Started Mar 28 03:21:30 PM PDT 24
Finished Mar 28 03:23:13 PM PDT 24
Peak memory 253660 kb
Host smart-16cfac14-53a4-47b8-82c0-015d73d5144b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592850631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.3592850631
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.2681035724
Short name T262
Test name
Test status
Simulation time 8998145824 ps
CPU time 34.02 seconds
Started Mar 28 03:21:30 PM PDT 24
Finished Mar 28 03:22:04 PM PDT 24
Peak memory 250304 kb
Host smart-614b3e2b-fea6-4b25-8059-063dded92569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681035724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.2681035724
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.2587396760
Short name T404
Test name
Test status
Simulation time 748351902 ps
CPU time 2.69 seconds
Started Mar 28 03:21:31 PM PDT 24
Finished Mar 28 03:21:33 PM PDT 24
Peak memory 219008 kb
Host smart-6e82cfae-9445-4c20-8533-b0a95c6c2487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587396760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.2587396760
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.1802160650
Short name T288
Test name
Test status
Simulation time 610342092 ps
CPU time 5.7 seconds
Started Mar 28 03:21:30 PM PDT 24
Finished Mar 28 03:21:36 PM PDT 24
Peak memory 233108 kb
Host smart-5b7779d3-80bb-4c16-a333-9b421c52c64c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802160650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.1802160650
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.64761249
Short name T217
Test name
Test status
Simulation time 12100599870 ps
CPU time 9.71 seconds
Started Mar 28 03:21:30 PM PDT 24
Finished Mar 28 03:21:40 PM PDT 24
Peak memory 220028 kb
Host smart-4b6d06ce-79d1-4d6e-84ce-dd8a029ee8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64761249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.64761249
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.1293583748
Short name T757
Test name
Test status
Simulation time 98286786 ps
CPU time 2.46 seconds
Started Mar 28 03:21:23 PM PDT 24
Finished Mar 28 03:21:26 PM PDT 24
Peak memory 219196 kb
Host smart-f3954909-bc39-44cd-a2fc-7e58b89f3675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293583748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.1293583748
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_ram_cfg.3995822413
Short name T427
Test name
Test status
Simulation time 20604691 ps
CPU time 0.77 seconds
Started Mar 28 03:21:32 PM PDT 24
Finished Mar 28 03:21:33 PM PDT 24
Peak memory 216508 kb
Host smart-81b4a489-68f3-4462-a3d7-08ca86c2ad73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995822413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_ram_cfg.3995822413
Directory /workspace/4.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.2647735463
Short name T969
Test name
Test status
Simulation time 1128364140 ps
CPU time 3.85 seconds
Started Mar 28 03:21:31 PM PDT 24
Finished Mar 28 03:21:35 PM PDT 24
Peak memory 220820 kb
Host smart-8e3a250f-1bfe-46df-8e2f-80e5d42ed4e7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2647735463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.2647735463
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.3954612748
Short name T58
Test name
Test status
Simulation time 171894004 ps
CPU time 1.17 seconds
Started Mar 28 03:21:31 PM PDT 24
Finished Mar 28 03:21:33 PM PDT 24
Peak memory 235588 kb
Host smart-9f0d3d62-4b7a-47c9-b075-9f32658ecba7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954612748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.3954612748
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.2360040938
Short name T28
Test name
Test status
Simulation time 89143890183 ps
CPU time 626.46 seconds
Started Mar 28 03:21:32 PM PDT 24
Finished Mar 28 03:31:59 PM PDT 24
Peak memory 261196 kb
Host smart-55b2ccac-5e7c-49fa-b91c-7c920de03bd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360040938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.2360040938
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.1003955526
Short name T266
Test name
Test status
Simulation time 3857918970 ps
CPU time 32.56 seconds
Started Mar 28 03:21:24 PM PDT 24
Finished Mar 28 03:21:57 PM PDT 24
Peak memory 216876 kb
Host smart-f4301c16-d6f2-446b-8cd5-b8149b746ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003955526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.1003955526
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.730596705
Short name T530
Test name
Test status
Simulation time 17209826607 ps
CPU time 13.24 seconds
Started Mar 28 03:21:26 PM PDT 24
Finished Mar 28 03:21:39 PM PDT 24
Peak memory 216808 kb
Host smart-0700fe9a-6026-4d84-9517-30a0b9e7a8db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730596705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.730596705
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.1635150036
Short name T285
Test name
Test status
Simulation time 364807995 ps
CPU time 14.83 seconds
Started Mar 28 03:21:31 PM PDT 24
Finished Mar 28 03:21:46 PM PDT 24
Peak memory 216696 kb
Host smart-37a8432e-338e-4f29-8b3f-fea5a5059a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635150036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.1635150036
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.3685315515
Short name T670
Test name
Test status
Simulation time 104729987 ps
CPU time 0.95 seconds
Started Mar 28 03:21:30 PM PDT 24
Finished Mar 28 03:21:31 PM PDT 24
Peak memory 207212 kb
Host smart-7e28f9cc-281e-4bd8-bc63-642cbd80cd70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685315515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.3685315515
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.3102805102
Short name T421
Test name
Test status
Simulation time 713813213 ps
CPU time 9.18 seconds
Started Mar 28 03:21:31 PM PDT 24
Finished Mar 28 03:21:40 PM PDT 24
Peak memory 235812 kb
Host smart-28eb350d-3763-448b-a91c-fef998fbe30e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102805102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.3102805102
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.3502104429
Short name T464
Test name
Test status
Simulation time 71430248 ps
CPU time 0.75 seconds
Started Mar 28 03:24:07 PM PDT 24
Finished Mar 28 03:24:08 PM PDT 24
Peak memory 205352 kb
Host smart-cad163b2-660d-44d2-ba1b-43ed1d0c6de0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502104429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
3502104429
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.50169796
Short name T463
Test name
Test status
Simulation time 298622246 ps
CPU time 3.54 seconds
Started Mar 28 03:24:01 PM PDT 24
Finished Mar 28 03:24:05 PM PDT 24
Peak memory 234232 kb
Host smart-4ee240fb-ef6d-4354-b569-cfc3196ca869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50169796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.50169796
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.3099790133
Short name T835
Test name
Test status
Simulation time 18670540 ps
CPU time 0.77 seconds
Started Mar 28 03:24:06 PM PDT 24
Finished Mar 28 03:24:07 PM PDT 24
Peak memory 206000 kb
Host smart-e9f63444-fb5b-455b-9ef5-4e65e762a764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099790133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.3099790133
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.3148850867
Short name T929
Test name
Test status
Simulation time 5199245315 ps
CPU time 12.87 seconds
Started Mar 28 03:24:01 PM PDT 24
Finished Mar 28 03:24:14 PM PDT 24
Peak memory 233288 kb
Host smart-041b054f-9aab-4f89-8afe-d5bb674ce188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148850867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.3148850867
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.500587
Short name T764
Test name
Test status
Simulation time 149230361708 ps
CPU time 286.11 seconds
Started Mar 28 03:24:08 PM PDT 24
Finished Mar 28 03:28:54 PM PDT 24
Peak memory 250608 kb
Host smart-3140c356-b808-4ac3-8f46-3cd3d0a569d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.500587
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.3938524789
Short name T245
Test name
Test status
Simulation time 145275948107 ps
CPU time 306.31 seconds
Started Mar 28 03:24:01 PM PDT 24
Finished Mar 28 03:29:08 PM PDT 24
Peak memory 265156 kb
Host smart-7831045e-94b2-4d9c-9055-3d7d25fad758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938524789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.3938524789
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.3289335982
Short name T821
Test name
Test status
Simulation time 398525171 ps
CPU time 16.82 seconds
Started Mar 28 03:24:02 PM PDT 24
Finished Mar 28 03:24:19 PM PDT 24
Peak memory 233032 kb
Host smart-bef0814e-6f3e-404a-960d-d5e2637f79b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289335982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.3289335982
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.1626589133
Short name T458
Test name
Test status
Simulation time 2209251575 ps
CPU time 7.96 seconds
Started Mar 28 03:24:02 PM PDT 24
Finished Mar 28 03:24:10 PM PDT 24
Peak memory 234232 kb
Host smart-ad413c33-1291-4904-b359-ff4bcb95c684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626589133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.1626589133
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.699974909
Short name T312
Test name
Test status
Simulation time 775324944 ps
CPU time 5.83 seconds
Started Mar 28 03:24:01 PM PDT 24
Finished Mar 28 03:24:07 PM PDT 24
Peak memory 234044 kb
Host smart-ca076d79-5978-4c5e-afc6-280183be601a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699974909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.699974909
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.197319314
Short name T842
Test name
Test status
Simulation time 61240749137 ps
CPU time 34.6 seconds
Started Mar 28 03:24:02 PM PDT 24
Finished Mar 28 03:24:37 PM PDT 24
Peak memory 232532 kb
Host smart-5d68c8d5-c29e-4eb3-9ef5-fd61b80c84ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197319314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap
.197319314
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.1979193434
Short name T892
Test name
Test status
Simulation time 1320796776 ps
CPU time 6.73 seconds
Started Mar 28 03:24:01 PM PDT 24
Finished Mar 28 03:24:08 PM PDT 24
Peak memory 233280 kb
Host smart-9ce840b7-de7e-4d24-90aa-f3c084ab8f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979193434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.1979193434
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.1731055346
Short name T691
Test name
Test status
Simulation time 986266088 ps
CPU time 4.29 seconds
Started Mar 28 03:24:00 PM PDT 24
Finished Mar 28 03:24:04 PM PDT 24
Peak memory 219600 kb
Host smart-fe846e62-8c63-4f2d-8550-176dea1b30f1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1731055346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.1731055346
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.3263461131
Short name T714
Test name
Test status
Simulation time 5118295615 ps
CPU time 18.17 seconds
Started Mar 28 03:24:02 PM PDT 24
Finished Mar 28 03:24:20 PM PDT 24
Peak memory 217008 kb
Host smart-aa271b56-d940-4b76-908a-25177161a976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263461131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.3263461131
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.1687431532
Short name T480
Test name
Test status
Simulation time 1381916501 ps
CPU time 3.72 seconds
Started Mar 28 03:24:09 PM PDT 24
Finished Mar 28 03:24:13 PM PDT 24
Peak memory 216696 kb
Host smart-dc123ec2-71a6-4908-9dd5-268439e03503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687431532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.1687431532
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.1114911426
Short name T777
Test name
Test status
Simulation time 591504400 ps
CPU time 2.96 seconds
Started Mar 28 03:24:01 PM PDT 24
Finished Mar 28 03:24:05 PM PDT 24
Peak memory 216728 kb
Host smart-863d1630-5d97-4bf1-a4cd-488550001cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114911426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.1114911426
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.3479729024
Short name T289
Test name
Test status
Simulation time 90712770 ps
CPU time 1.01 seconds
Started Mar 28 03:23:59 PM PDT 24
Finished Mar 28 03:24:01 PM PDT 24
Peak memory 206672 kb
Host smart-bae87aa0-5796-4051-8b16-fac752332803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479729024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.3479729024
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.62317770
Short name T323
Test name
Test status
Simulation time 17274467139 ps
CPU time 46.32 seconds
Started Mar 28 03:24:02 PM PDT 24
Finished Mar 28 03:24:48 PM PDT 24
Peak memory 233140 kb
Host smart-d962c51d-a31d-4b41-b7af-6cc0f20fce43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62317770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.62317770
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.2214718049
Short name T687
Test name
Test status
Simulation time 15500713 ps
CPU time 0.76 seconds
Started Mar 28 03:24:28 PM PDT 24
Finished Mar 28 03:24:30 PM PDT 24
Peak memory 205948 kb
Host smart-b4b27343-c66c-406f-a252-4fe42e00f93f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214718049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
2214718049
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.4047009480
Short name T269
Test name
Test status
Simulation time 316540137 ps
CPU time 4.42 seconds
Started Mar 28 03:24:02 PM PDT 24
Finished Mar 28 03:24:06 PM PDT 24
Peak memory 220104 kb
Host smart-d40da1c9-20d0-4c28-94ad-a59be85924a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047009480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.4047009480
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.1516374118
Short name T389
Test name
Test status
Simulation time 48347923 ps
CPU time 0.75 seconds
Started Mar 28 03:24:01 PM PDT 24
Finished Mar 28 03:24:02 PM PDT 24
Peak memory 207304 kb
Host smart-259a40ab-2686-4954-bc1a-ecf6440d8218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516374118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.1516374118
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.3706944517
Short name T712
Test name
Test status
Simulation time 5275451008 ps
CPU time 56.12 seconds
Started Mar 28 03:24:02 PM PDT 24
Finished Mar 28 03:24:58 PM PDT 24
Peak memory 249660 kb
Host smart-d36adfd2-1839-40ae-9473-9e13fbc6a13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706944517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.3706944517
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.1849810626
Short name T251
Test name
Test status
Simulation time 43679641178 ps
CPU time 100.74 seconds
Started Mar 28 03:24:28 PM PDT 24
Finished Mar 28 03:26:10 PM PDT 24
Peak memory 266040 kb
Host smart-499a4bcc-9c70-4e93-8380-8322bf981a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849810626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.1849810626
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.2075085416
Short name T23
Test name
Test status
Simulation time 4986779262 ps
CPU time 66.54 seconds
Started Mar 28 03:24:23 PM PDT 24
Finished Mar 28 03:25:30 PM PDT 24
Peak memory 249616 kb
Host smart-544497b0-6c41-4881-9cfd-89eb38c30823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075085416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.2075085416
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.2647717593
Short name T901
Test name
Test status
Simulation time 3374839856 ps
CPU time 21.39 seconds
Started Mar 28 03:24:06 PM PDT 24
Finished Mar 28 03:24:28 PM PDT 24
Peak memory 233172 kb
Host smart-fa39148c-643d-45be-98f9-98ba8bc2b9d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647717593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.2647717593
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.3290602027
Short name T175
Test name
Test status
Simulation time 1738371467 ps
CPU time 4.96 seconds
Started Mar 28 03:24:02 PM PDT 24
Finished Mar 28 03:24:07 PM PDT 24
Peak memory 220140 kb
Host smart-4c82f2fc-c58f-4d88-a580-830b584708cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290602027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.3290602027
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.1447805522
Short name T772
Test name
Test status
Simulation time 2883756454 ps
CPU time 14.1 seconds
Started Mar 28 03:24:02 PM PDT 24
Finished Mar 28 03:24:16 PM PDT 24
Peak memory 227292 kb
Host smart-bbbbf7ae-a302-486c-b0ab-0e9e3710e969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447805522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.1447805522
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.1305683631
Short name T219
Test name
Test status
Simulation time 3731730888 ps
CPU time 3.55 seconds
Started Mar 28 03:24:02 PM PDT 24
Finished Mar 28 03:24:06 PM PDT 24
Peak memory 219408 kb
Host smart-78caa474-7908-4689-abaa-791c7a871f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305683631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.1305683631
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.1167815632
Short name T390
Test name
Test status
Simulation time 107027002 ps
CPU time 2.3 seconds
Started Mar 28 03:24:06 PM PDT 24
Finished Mar 28 03:24:09 PM PDT 24
Peak memory 217288 kb
Host smart-0bb1e3d4-1a12-491e-b56d-e0b713b95110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167815632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.1167815632
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.2648291160
Short name T805
Test name
Test status
Simulation time 4907173236 ps
CPU time 3.81 seconds
Started Mar 28 03:24:04 PM PDT 24
Finished Mar 28 03:24:08 PM PDT 24
Peak memory 219060 kb
Host smart-7aaf61aa-71e9-4b36-8fb2-24ed9dd7de90
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2648291160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.2648291160
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.3037112591
Short name T66
Test name
Test status
Simulation time 125333622 ps
CPU time 1.09 seconds
Started Mar 28 03:24:27 PM PDT 24
Finished Mar 28 03:24:28 PM PDT 24
Peak memory 207708 kb
Host smart-7632f8c8-064f-4b0f-a367-619f0a326884
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037112591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.3037112591
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.2256047368
Short name T73
Test name
Test status
Simulation time 25115584350 ps
CPU time 37.69 seconds
Started Mar 28 03:24:08 PM PDT 24
Finished Mar 28 03:24:46 PM PDT 24
Peak memory 216784 kb
Host smart-600c66f8-454c-41ea-b8ef-d940157b24ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256047368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.2256047368
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.3058205223
Short name T931
Test name
Test status
Simulation time 6624721446 ps
CPU time 12.47 seconds
Started Mar 28 03:24:07 PM PDT 24
Finished Mar 28 03:24:20 PM PDT 24
Peak memory 216916 kb
Host smart-0a57fbd4-c1f7-44ab-8cf8-76c40c7186a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058205223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.3058205223
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.260443658
Short name T683
Test name
Test status
Simulation time 164397106 ps
CPU time 2.63 seconds
Started Mar 28 03:24:01 PM PDT 24
Finished Mar 28 03:24:04 PM PDT 24
Peak memory 216680 kb
Host smart-dd0fd158-db8f-4976-94af-b017e096c36f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260443658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.260443658
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.2636312408
Short name T561
Test name
Test status
Simulation time 46096848 ps
CPU time 0.9 seconds
Started Mar 28 03:24:07 PM PDT 24
Finished Mar 28 03:24:09 PM PDT 24
Peak memory 207280 kb
Host smart-f7125b1d-2816-4c2e-a932-62fb13808293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636312408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.2636312408
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.2079720106
Short name T77
Test name
Test status
Simulation time 1208831331 ps
CPU time 10.21 seconds
Started Mar 28 03:23:58 PM PDT 24
Finished Mar 28 03:24:08 PM PDT 24
Peak memory 241224 kb
Host smart-c0c3b316-c9fe-4f26-82e2-4017d324e2c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079720106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.2079720106
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.1357706832
Short name T555
Test name
Test status
Simulation time 46534243 ps
CPU time 0.7 seconds
Started Mar 28 03:24:26 PM PDT 24
Finished Mar 28 03:24:26 PM PDT 24
Peak memory 206188 kb
Host smart-cff60d83-0d6e-41a9-8b1b-6652774fa375
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357706832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
1357706832
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.2374133317
Short name T933
Test name
Test status
Simulation time 844196882 ps
CPU time 4.15 seconds
Started Mar 28 03:24:32 PM PDT 24
Finished Mar 28 03:24:36 PM PDT 24
Peak memory 220224 kb
Host smart-ac55cd88-08e1-4d7e-87f3-08037313c36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374133317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.2374133317
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.2909096801
Short name T337
Test name
Test status
Simulation time 40069104 ps
CPU time 0.77 seconds
Started Mar 28 03:24:26 PM PDT 24
Finished Mar 28 03:24:27 PM PDT 24
Peak memory 206320 kb
Host smart-833b7bfb-9487-43c4-9826-9f13fc445bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909096801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2909096801
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.681364918
Short name T68
Test name
Test status
Simulation time 31422710373 ps
CPU time 63.38 seconds
Started Mar 28 03:24:28 PM PDT 24
Finished Mar 28 03:25:32 PM PDT 24
Peak memory 252508 kb
Host smart-313e45bf-dbfc-472b-a66a-9efc5af6a0d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681364918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.681364918
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.2395947029
Short name T460
Test name
Test status
Simulation time 43028007373 ps
CPU time 172.84 seconds
Started Mar 28 03:24:29 PM PDT 24
Finished Mar 28 03:27:22 PM PDT 24
Peak memory 257224 kb
Host smart-5aaabb95-d02c-4bc4-a2f1-3f83421ce554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395947029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.2395947029
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.3447131412
Short name T749
Test name
Test status
Simulation time 8871339024 ps
CPU time 23.36 seconds
Started Mar 28 03:24:28 PM PDT 24
Finished Mar 28 03:24:51 PM PDT 24
Peak memory 230296 kb
Host smart-03eec401-7cf1-4597-b4fa-048e7d0cbe53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447131412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.3447131412
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.2047988645
Short name T98
Test name
Test status
Simulation time 1239125968 ps
CPU time 4.18 seconds
Started Mar 28 03:24:28 PM PDT 24
Finished Mar 28 03:24:33 PM PDT 24
Peak memory 234088 kb
Host smart-8b9db573-cdfb-4e9a-bc5a-24f7c93fcd4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047988645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.2047988645
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.3454740874
Short name T794
Test name
Test status
Simulation time 4048114011 ps
CPU time 17.35 seconds
Started Mar 28 03:24:28 PM PDT 24
Finished Mar 28 03:24:45 PM PDT 24
Peak memory 235112 kb
Host smart-5288f68e-c794-4d61-956e-102fc249e51f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454740874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.3454740874
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.413609711
Short name T956
Test name
Test status
Simulation time 18216028146 ps
CPU time 12.58 seconds
Started Mar 28 03:24:28 PM PDT 24
Finished Mar 28 03:24:41 PM PDT 24
Peak memory 218364 kb
Host smart-f4487a86-9b09-4672-a0ba-abcec21fe4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413609711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap
.413609711
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.4163848627
Short name T715
Test name
Test status
Simulation time 485461450 ps
CPU time 2.67 seconds
Started Mar 28 03:24:25 PM PDT 24
Finished Mar 28 03:24:27 PM PDT 24
Peak memory 217776 kb
Host smart-483b05f6-a8c9-43d5-b34e-a93d915ccf16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163848627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.4163848627
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.845358169
Short name T535
Test name
Test status
Simulation time 213325660 ps
CPU time 4.27 seconds
Started Mar 28 03:24:28 PM PDT 24
Finished Mar 28 03:24:33 PM PDT 24
Peak memory 223236 kb
Host smart-cc030a62-4ba7-49aa-8278-1e31da11de73
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=845358169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dire
ct.845358169
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.520416680
Short name T64
Test name
Test status
Simulation time 36302390 ps
CPU time 0.94 seconds
Started Mar 28 03:24:32 PM PDT 24
Finished Mar 28 03:24:33 PM PDT 24
Peak memory 207308 kb
Host smart-ab3bf5d6-d86e-4322-a915-9def314a4799
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520416680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stres
s_all.520416680
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.3565692252
Short name T717
Test name
Test status
Simulation time 17650850275 ps
CPU time 88.65 seconds
Started Mar 28 03:24:30 PM PDT 24
Finished Mar 28 03:25:59 PM PDT 24
Peak memory 216512 kb
Host smart-bece9697-84d1-4849-885b-cb2432de1178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565692252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.3565692252
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.3393594117
Short name T447
Test name
Test status
Simulation time 2534285905 ps
CPU time 9.07 seconds
Started Mar 28 03:24:28 PM PDT 24
Finished Mar 28 03:24:38 PM PDT 24
Peak memory 216816 kb
Host smart-a9749c9f-4389-4d51-9ffb-4f0f391c3b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393594117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3393594117
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.1597312429
Short name T803
Test name
Test status
Simulation time 917221590 ps
CPU time 6.51 seconds
Started Mar 28 03:24:28 PM PDT 24
Finished Mar 28 03:24:35 PM PDT 24
Peak memory 215836 kb
Host smart-ee64aa4f-b17a-40ad-be2c-afeb55f67437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597312429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.1597312429
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.1759455612
Short name T533
Test name
Test status
Simulation time 618575264 ps
CPU time 1.07 seconds
Started Mar 28 03:24:28 PM PDT 24
Finished Mar 28 03:24:29 PM PDT 24
Peak memory 207184 kb
Host smart-dd1e3334-19bf-4f01-b315-9d96aaabb38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759455612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.1759455612
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.1123201386
Short name T536
Test name
Test status
Simulation time 2544896188 ps
CPU time 11.22 seconds
Started Mar 28 03:24:30 PM PDT 24
Finished Mar 28 03:24:41 PM PDT 24
Peak memory 238960 kb
Host smart-b5cebf4b-3acf-46e8-969f-1cdd80a3b15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123201386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.1123201386
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.2833535388
Short name T544
Test name
Test status
Simulation time 78378287 ps
CPU time 0.71 seconds
Started Mar 28 03:24:32 PM PDT 24
Finished Mar 28 03:24:32 PM PDT 24
Peak memory 205264 kb
Host smart-39da4521-3302-4023-b0ab-26668b6a75e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833535388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
2833535388
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.2507938056
Short name T441
Test name
Test status
Simulation time 68914351 ps
CPU time 3.03 seconds
Started Mar 28 03:24:28 PM PDT 24
Finished Mar 28 03:24:32 PM PDT 24
Peak memory 234084 kb
Host smart-e3a9972e-df9a-44a7-964f-6c249e1821a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507938056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.2507938056
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.2146854165
Short name T950
Test name
Test status
Simulation time 47967755 ps
CPU time 0.81 seconds
Started Mar 28 03:24:34 PM PDT 24
Finished Mar 28 03:24:35 PM PDT 24
Peak memory 207016 kb
Host smart-75eb5590-86bd-4589-9a64-d499869b4dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146854165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.2146854165
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.1718080088
Short name T34
Test name
Test status
Simulation time 70021484832 ps
CPU time 300.55 seconds
Started Mar 28 03:24:32 PM PDT 24
Finished Mar 28 03:29:32 PM PDT 24
Peak memory 265936 kb
Host smart-12099ee2-6c0a-4a98-90ff-896fd63c63b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718080088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.1718080088
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.3103732758
Short name T934
Test name
Test status
Simulation time 10374518159 ps
CPU time 34.51 seconds
Started Mar 28 03:24:32 PM PDT 24
Finished Mar 28 03:25:06 PM PDT 24
Peak memory 224944 kb
Host smart-b589fa3f-f529-46eb-ba4a-b2886572f14e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103732758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.3103732758
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.49737214
Short name T508
Test name
Test status
Simulation time 9631818242 ps
CPU time 40.99 seconds
Started Mar 28 03:24:26 PM PDT 24
Finished Mar 28 03:25:07 PM PDT 24
Peak memory 223168 kb
Host smart-49ca1d8c-bb19-43ca-8487-fcaaeaebc577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49737214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idle.49737214
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.3921084690
Short name T779
Test name
Test status
Simulation time 7222229785 ps
CPU time 32.98 seconds
Started Mar 28 03:24:29 PM PDT 24
Finished Mar 28 03:25:02 PM PDT 24
Peak memory 240768 kb
Host smart-59173780-4616-4b1e-a0bb-c604cffec29f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921084690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.3921084690
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.1481734087
Short name T674
Test name
Test status
Simulation time 1722621688 ps
CPU time 5.69 seconds
Started Mar 28 03:24:30 PM PDT 24
Finished Mar 28 03:24:36 PM PDT 24
Peak memory 233984 kb
Host smart-47d988e5-0f71-417c-a891-8a459c73a770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481734087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.1481734087
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.1627837630
Short name T224
Test name
Test status
Simulation time 15169853161 ps
CPU time 15.38 seconds
Started Mar 28 03:24:30 PM PDT 24
Finished Mar 28 03:24:45 PM PDT 24
Peak memory 221400 kb
Host smart-64788872-f181-450d-ac7e-75af9a18976d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627837630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.1627837630
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.3773573834
Short name T828
Test name
Test status
Simulation time 57360604818 ps
CPU time 42.34 seconds
Started Mar 28 03:24:29 PM PDT 24
Finished Mar 28 03:25:12 PM PDT 24
Peak memory 233940 kb
Host smart-90a1062e-2c34-4b3a-be11-13ce0ddec694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773573834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.3773573834
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.2288529206
Short name T11
Test name
Test status
Simulation time 1211594803 ps
CPU time 11.08 seconds
Started Mar 28 03:24:27 PM PDT 24
Finished Mar 28 03:24:38 PM PDT 24
Peak memory 229856 kb
Host smart-4862ceb2-1d70-475f-9d4b-5765550a320c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288529206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.2288529206
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.3051444967
Short name T119
Test name
Test status
Simulation time 259712920 ps
CPU time 3.63 seconds
Started Mar 28 03:24:28 PM PDT 24
Finished Mar 28 03:24:33 PM PDT 24
Peak memory 219636 kb
Host smart-323ccfcf-9e9a-4919-a1c4-161f6d806200
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3051444967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.3051444967
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.1050615618
Short name T252
Test name
Test status
Simulation time 15668521784 ps
CPU time 129.89 seconds
Started Mar 28 03:24:26 PM PDT 24
Finished Mar 28 03:26:36 PM PDT 24
Peak memory 249640 kb
Host smart-e3760682-ec10-45e8-a122-0322a139ff81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050615618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.1050615618
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.249850172
Short name T729
Test name
Test status
Simulation time 1406749476 ps
CPU time 8.55 seconds
Started Mar 28 03:24:28 PM PDT 24
Finished Mar 28 03:24:38 PM PDT 24
Peak memory 216724 kb
Host smart-d6761e1e-a5c7-4214-b297-ce6786581bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249850172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.249850172
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.452319778
Short name T832
Test name
Test status
Simulation time 18848541832 ps
CPU time 13.59 seconds
Started Mar 28 03:24:34 PM PDT 24
Finished Mar 28 03:24:47 PM PDT 24
Peak memory 216756 kb
Host smart-00afe515-1cc6-4232-a3ae-ff2ae59fc1fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452319778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.452319778
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.4099154955
Short name T710
Test name
Test status
Simulation time 57276437 ps
CPU time 0.78 seconds
Started Mar 28 03:24:28 PM PDT 24
Finished Mar 28 03:24:29 PM PDT 24
Peak memory 206144 kb
Host smart-8951d0b7-84e8-4918-9ae5-eb114e297801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099154955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.4099154955
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.2575795373
Short name T926
Test name
Test status
Simulation time 246025779 ps
CPU time 0.93 seconds
Started Mar 28 03:24:30 PM PDT 24
Finished Mar 28 03:24:31 PM PDT 24
Peak memory 207164 kb
Host smart-421e1c11-45e5-4917-ba60-1e618f3d4cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575795373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.2575795373
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.3946196833
Short name T196
Test name
Test status
Simulation time 2597944059 ps
CPU time 5.57 seconds
Started Mar 28 03:24:27 PM PDT 24
Finished Mar 28 03:24:33 PM PDT 24
Peak memory 234368 kb
Host smart-8dffe440-06b0-4338-a26a-2bcd39f432c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946196833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3946196833
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.401144401
Short name T342
Test name
Test status
Simulation time 177461199 ps
CPU time 0.68 seconds
Started Mar 28 03:24:26 PM PDT 24
Finished Mar 28 03:24:26 PM PDT 24
Peak memory 205884 kb
Host smart-a841ff83-f8e3-408f-9aed-69cb113ecd76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401144401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.401144401
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.1928269903
Short name T195
Test name
Test status
Simulation time 6542137290 ps
CPU time 8.87 seconds
Started Mar 28 03:24:28 PM PDT 24
Finished Mar 28 03:24:37 PM PDT 24
Peak memory 234820 kb
Host smart-954ab7cf-b86d-4048-b53c-ada1cd85fedc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928269903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.1928269903
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.150416581
Short name T758
Test name
Test status
Simulation time 59430970 ps
CPU time 0.83 seconds
Started Mar 28 03:24:28 PM PDT 24
Finished Mar 28 03:24:29 PM PDT 24
Peak memory 207288 kb
Host smart-9aeaeafd-a317-419a-8b0d-fd91314cb5df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150416581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.150416581
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.775925408
Short name T281
Test name
Test status
Simulation time 94692155785 ps
CPU time 67.54 seconds
Started Mar 28 03:24:26 PM PDT 24
Finished Mar 28 03:25:33 PM PDT 24
Peak memory 241356 kb
Host smart-0760beda-9681-41e7-924a-2a170cb0f38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775925408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.775925408
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.909103287
Short name T152
Test name
Test status
Simulation time 8565037414 ps
CPU time 50.46 seconds
Started Mar 28 03:24:32 PM PDT 24
Finished Mar 28 03:25:22 PM PDT 24
Peak memory 237032 kb
Host smart-6d2e3429-56a8-4907-a3ce-e3f6a100596c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909103287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.909103287
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.1278716962
Short name T186
Test name
Test status
Simulation time 186672400313 ps
CPU time 334.61 seconds
Started Mar 28 03:24:29 PM PDT 24
Finished Mar 28 03:30:04 PM PDT 24
Peak memory 265580 kb
Host smart-ed6a33f8-29af-440c-8e87-8e65188bb236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278716962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.1278716962
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.1345727098
Short name T713
Test name
Test status
Simulation time 6027437462 ps
CPU time 22 seconds
Started Mar 28 03:24:30 PM PDT 24
Finished Mar 28 03:24:53 PM PDT 24
Peak memory 236940 kb
Host smart-29db73de-d814-4220-8c16-888fe6d054db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345727098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.1345727098
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.1120338963
Short name T522
Test name
Test status
Simulation time 141398452 ps
CPU time 2.82 seconds
Started Mar 28 03:24:27 PM PDT 24
Finished Mar 28 03:24:30 PM PDT 24
Peak memory 216872 kb
Host smart-c57b458e-44d1-4f1f-91a3-9786f7aacfe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120338963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.1120338963
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.2264440496
Short name T925
Test name
Test status
Simulation time 24112882304 ps
CPU time 14.38 seconds
Started Mar 28 03:24:30 PM PDT 24
Finished Mar 28 03:24:45 PM PDT 24
Peak memory 224848 kb
Host smart-6a34526a-8c58-4b4b-bd46-682df79fbae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264440496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.2264440496
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3121673521
Short name T565
Test name
Test status
Simulation time 6401468281 ps
CPU time 18.17 seconds
Started Mar 28 03:24:27 PM PDT 24
Finished Mar 28 03:24:45 PM PDT 24
Peak memory 235968 kb
Host smart-7cf80f6e-0f6f-42e5-9faa-6941af345754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121673521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.3121673521
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.1343864681
Short name T373
Test name
Test status
Simulation time 4023870089 ps
CPU time 11.42 seconds
Started Mar 28 03:24:29 PM PDT 24
Finished Mar 28 03:24:41 PM PDT 24
Peak memory 236528 kb
Host smart-771c854d-0e78-4939-bfc2-1d3498578b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343864681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.1343864681
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.1538854038
Short name T865
Test name
Test status
Simulation time 227522122 ps
CPU time 3.95 seconds
Started Mar 28 03:24:31 PM PDT 24
Finished Mar 28 03:24:35 PM PDT 24
Peak memory 223448 kb
Host smart-0ec0bb36-db47-44a4-b0c3-6a6216cb7de0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1538854038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.1538854038
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.166597369
Short name T970
Test name
Test status
Simulation time 9437631290 ps
CPU time 59.34 seconds
Started Mar 28 03:24:32 PM PDT 24
Finished Mar 28 03:25:31 PM PDT 24
Peak memory 241444 kb
Host smart-582078c4-9636-4956-97ae-b8404dc3541a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166597369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stres
s_all.166597369
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.1331915894
Short name T433
Test name
Test status
Simulation time 6456950864 ps
CPU time 10.23 seconds
Started Mar 28 03:24:31 PM PDT 24
Finished Mar 28 03:24:42 PM PDT 24
Peak memory 216844 kb
Host smart-7c9079ea-b1c0-49d1-b18e-7f701c4b5553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331915894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.1331915894
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.792031059
Short name T791
Test name
Test status
Simulation time 1405985978 ps
CPU time 5.48 seconds
Started Mar 28 03:24:28 PM PDT 24
Finished Mar 28 03:24:34 PM PDT 24
Peak memory 215888 kb
Host smart-52341b7b-5bfa-4b98-83ab-523ff0c419a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792031059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.792031059
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.2363086067
Short name T813
Test name
Test status
Simulation time 76898519 ps
CPU time 1.02 seconds
Started Mar 28 03:24:31 PM PDT 24
Finished Mar 28 03:24:32 PM PDT 24
Peak memory 207608 kb
Host smart-ebec16a2-45bf-497d-9a3c-9833cd76b7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363086067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.2363086067
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.2176486782
Short name T760
Test name
Test status
Simulation time 67044387 ps
CPU time 1.06 seconds
Started Mar 28 03:24:27 PM PDT 24
Finished Mar 28 03:24:28 PM PDT 24
Peak memory 207204 kb
Host smart-3a2d86bb-559d-4a7b-8d14-0139e66a53c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176486782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.2176486782
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.702315833
Short name T207
Test name
Test status
Simulation time 2197621638 ps
CPU time 6.4 seconds
Started Mar 28 03:24:29 PM PDT 24
Finished Mar 28 03:24:36 PM PDT 24
Peak memory 234484 kb
Host smart-16b9e41a-6863-4f55-a6c4-ab56afab1981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702315833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.702315833
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.3241603764
Short name T482
Test name
Test status
Simulation time 14431501 ps
CPU time 0.75 seconds
Started Mar 28 03:24:30 PM PDT 24
Finished Mar 28 03:24:31 PM PDT 24
Peak memory 205868 kb
Host smart-3b1e8998-0bcd-49c0-8338-264f478483ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241603764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
3241603764
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.287744746
Short name T429
Test name
Test status
Simulation time 3262947958 ps
CPU time 7.21 seconds
Started Mar 28 03:24:30 PM PDT 24
Finished Mar 28 03:24:38 PM PDT 24
Peak memory 220948 kb
Host smart-fe628fe0-5a04-4760-a181-ef37a9fd637e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287744746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.287744746
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.3603426900
Short name T401
Test name
Test status
Simulation time 65314713 ps
CPU time 0.9 seconds
Started Mar 28 03:24:31 PM PDT 24
Finished Mar 28 03:24:32 PM PDT 24
Peak memory 207028 kb
Host smart-42332904-2681-4fcb-ab2c-1a003ff719c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603426900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.3603426900
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.1099500828
Short name T418
Test name
Test status
Simulation time 121241526474 ps
CPU time 166.42 seconds
Started Mar 28 03:24:29 PM PDT 24
Finished Mar 28 03:27:16 PM PDT 24
Peak memory 257144 kb
Host smart-cf0144a6-3cd6-4193-bb4f-219bc993b83b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099500828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.1099500828
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.1350632096
Short name T246
Test name
Test status
Simulation time 10413756731 ps
CPU time 132.18 seconds
Started Mar 28 03:24:29 PM PDT 24
Finished Mar 28 03:26:42 PM PDT 24
Peak memory 249652 kb
Host smart-8ef48679-1c6f-49bc-9467-4ba07d19a84f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350632096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.1350632096
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.204490303
Short name T36
Test name
Test status
Simulation time 5939126165 ps
CPU time 68.59 seconds
Started Mar 28 03:24:28 PM PDT 24
Finished Mar 28 03:25:37 PM PDT 24
Peak memory 249932 kb
Host smart-12865b2f-a454-4456-8057-7fd796bcde9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204490303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idle
.204490303
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.371479130
Short name T260
Test name
Test status
Simulation time 2775303155 ps
CPU time 15.74 seconds
Started Mar 28 03:24:29 PM PDT 24
Finished Mar 28 03:24:45 PM PDT 24
Peak memory 238924 kb
Host smart-5b73be9a-919c-43e4-80b3-ddf092a3ee74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371479130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.371479130
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.2713370814
Short name T226
Test name
Test status
Simulation time 460810178 ps
CPU time 3.53 seconds
Started Mar 28 03:24:26 PM PDT 24
Finished Mar 28 03:24:30 PM PDT 24
Peak memory 219284 kb
Host smart-11beb2e8-05be-49aa-b8b6-24d108644a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713370814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.2713370814
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.3012916139
Short name T432
Test name
Test status
Simulation time 3713297422 ps
CPU time 13.05 seconds
Started Mar 28 03:24:33 PM PDT 24
Finished Mar 28 03:24:46 PM PDT 24
Peak memory 224940 kb
Host smart-1fad03ac-aff5-43ba-be35-5cb50a0cca6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012916139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.3012916139
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.1288191027
Short name T158
Test name
Test status
Simulation time 2253148920 ps
CPU time 7.63 seconds
Started Mar 28 03:24:27 PM PDT 24
Finished Mar 28 03:24:34 PM PDT 24
Peak memory 218368 kb
Host smart-e3330a55-5c13-4bf4-b5c5-35f798be6217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288191027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.1288191027
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.1761947442
Short name T628
Test name
Test status
Simulation time 370218705 ps
CPU time 4.4 seconds
Started Mar 28 03:24:34 PM PDT 24
Finished Mar 28 03:24:38 PM PDT 24
Peak memory 218844 kb
Host smart-610e3f7d-ae4b-41ba-81bd-568c4e5af5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761947442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.1761947442
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.2149993588
Short name T365
Test name
Test status
Simulation time 1174797573 ps
CPU time 5.92 seconds
Started Mar 28 03:24:30 PM PDT 24
Finished Mar 28 03:24:36 PM PDT 24
Peak memory 221036 kb
Host smart-dc5e8bdd-5332-4cd7-89a3-1fbca71cd151
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2149993588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.2149993588
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.795288129
Short name T448
Test name
Test status
Simulation time 3083453894 ps
CPU time 43.4 seconds
Started Mar 28 03:24:26 PM PDT 24
Finished Mar 28 03:25:09 PM PDT 24
Peak memory 216784 kb
Host smart-60fcd870-05fa-4fb7-8549-457f99dc799f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795288129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.795288129
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.3536014187
Short name T654
Test name
Test status
Simulation time 30662291006 ps
CPU time 22.18 seconds
Started Mar 28 03:24:31 PM PDT 24
Finished Mar 28 03:24:54 PM PDT 24
Peak memory 217952 kb
Host smart-31919e51-ce5a-424f-b0dc-652081e6950f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536014187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.3536014187
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.376678143
Short name T24
Test name
Test status
Simulation time 2341119414 ps
CPU time 6.45 seconds
Started Mar 28 03:24:30 PM PDT 24
Finished Mar 28 03:24:36 PM PDT 24
Peak memory 216892 kb
Host smart-c1fc9215-d24e-473a-8f1c-cbfd065e8796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376678143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.376678143
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.2386203761
Short name T293
Test name
Test status
Simulation time 82903431 ps
CPU time 0.72 seconds
Started Mar 28 03:24:29 PM PDT 24
Finished Mar 28 03:24:30 PM PDT 24
Peak memory 206208 kb
Host smart-42ef80a6-53c5-48c4-917b-ccb042c4d0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386203761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.2386203761
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.1968999446
Short name T888
Test name
Test status
Simulation time 512882207 ps
CPU time 4.8 seconds
Started Mar 28 03:24:30 PM PDT 24
Finished Mar 28 03:24:35 PM PDT 24
Peak memory 219340 kb
Host smart-e42c0251-f93e-45bd-a002-1407c01fe240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968999446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.1968999446
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.3796918923
Short name T531
Test name
Test status
Simulation time 15118861 ps
CPU time 0.71 seconds
Started Mar 28 03:24:44 PM PDT 24
Finished Mar 28 03:24:45 PM PDT 24
Peak memory 205860 kb
Host smart-5f959a03-989b-4588-b2a0-c18201dbe53d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796918923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
3796918923
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.1638896832
Short name T556
Test name
Test status
Simulation time 452067220 ps
CPU time 2.67 seconds
Started Mar 28 03:24:47 PM PDT 24
Finished Mar 28 03:24:50 PM PDT 24
Peak memory 235136 kb
Host smart-b260de19-c0cd-4b8e-92dd-a0f3d8b08bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638896832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.1638896832
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.1075832030
Short name T881
Test name
Test status
Simulation time 177086522 ps
CPU time 0.81 seconds
Started Mar 28 03:24:29 PM PDT 24
Finished Mar 28 03:24:30 PM PDT 24
Peak memory 206952 kb
Host smart-cf764bfb-5055-4c80-9f24-8d3de024ee44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075832030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.1075832030
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.3790810580
Short name T172
Test name
Test status
Simulation time 10870045788 ps
CPU time 55.22 seconds
Started Mar 28 03:24:46 PM PDT 24
Finished Mar 28 03:25:41 PM PDT 24
Peak memory 233288 kb
Host smart-05a55f28-4a5c-498e-bb80-0a73b5f90291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790810580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.3790810580
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.192491
Short name T877
Test name
Test status
Simulation time 25201105170 ps
CPU time 218.02 seconds
Started Mar 28 03:24:46 PM PDT 24
Finished Mar 28 03:28:24 PM PDT 24
Peak memory 257632 kb
Host smart-a488ad44-26a3-49c0-8eef-5b93df1d4dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle.192491
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.4159443600
Short name T718
Test name
Test status
Simulation time 4551511903 ps
CPU time 34.77 seconds
Started Mar 28 03:24:47 PM PDT 24
Finished Mar 28 03:25:22 PM PDT 24
Peak memory 232232 kb
Host smart-61496988-8854-4664-b91e-c1f73c31ae54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159443600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.4159443600
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.682804309
Short name T809
Test name
Test status
Simulation time 478301058 ps
CPU time 3.35 seconds
Started Mar 28 03:24:44 PM PDT 24
Finished Mar 28 03:24:48 PM PDT 24
Peak memory 216804 kb
Host smart-f8dfa2f8-4e2c-4283-99f1-694378c9041f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682804309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.682804309
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.2961430053
Short name T270
Test name
Test status
Simulation time 264870455 ps
CPU time 2.93 seconds
Started Mar 28 03:24:44 PM PDT 24
Finished Mar 28 03:24:47 PM PDT 24
Peak memory 219064 kb
Host smart-e7651c45-2578-4720-852f-b70cc94c2475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961430053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.2961430053
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.1381095444
Short name T185
Test name
Test status
Simulation time 3138075048 ps
CPU time 13.2 seconds
Started Mar 28 03:24:47 PM PDT 24
Finished Mar 28 03:25:01 PM PDT 24
Peak memory 228712 kb
Host smart-76fe948d-39d5-47b8-adae-03cae90c1f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381095444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.1381095444
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.3116960129
Short name T486
Test name
Test status
Simulation time 1435297789 ps
CPU time 9.75 seconds
Started Mar 28 03:24:44 PM PDT 24
Finished Mar 28 03:24:54 PM PDT 24
Peak memory 234080 kb
Host smart-04c9e2db-28c8-4924-b715-b0a6ecfd8bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116960129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.3116960129
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.3168927227
Short name T592
Test name
Test status
Simulation time 556273927 ps
CPU time 4.16 seconds
Started Mar 28 03:24:47 PM PDT 24
Finished Mar 28 03:24:51 PM PDT 24
Peak memory 223268 kb
Host smart-cfe384df-ef31-408c-8f70-f96ad52aac2d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3168927227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.3168927227
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.2047970361
Short name T610
Test name
Test status
Simulation time 11038232486 ps
CPU time 38.63 seconds
Started Mar 28 03:24:29 PM PDT 24
Finished Mar 28 03:25:08 PM PDT 24
Peak memory 216800 kb
Host smart-f935bcca-4358-4ee0-9727-279186ca2c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047970361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.2047970361
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2670206946
Short name T352
Test name
Test status
Simulation time 2380985889 ps
CPU time 8.48 seconds
Started Mar 28 03:24:32 PM PDT 24
Finished Mar 28 03:24:40 PM PDT 24
Peak memory 216760 kb
Host smart-b401e711-768b-4551-a861-aaaf29b55f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670206946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2670206946
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.2901935440
Short name T274
Test name
Test status
Simulation time 306639358 ps
CPU time 1.68 seconds
Started Mar 28 03:24:43 PM PDT 24
Finished Mar 28 03:24:45 PM PDT 24
Peak memory 216696 kb
Host smart-6da2470c-b3ca-4927-aa8e-d7e33b4493b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901935440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.2901935440
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.200106924
Short name T802
Test name
Test status
Simulation time 44979163 ps
CPU time 0.96 seconds
Started Mar 28 03:24:47 PM PDT 24
Finished Mar 28 03:24:48 PM PDT 24
Peak memory 207240 kb
Host smart-9b044e89-48a4-4aab-be27-b1861d9e96c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200106924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.200106924
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.3822470337
Short name T792
Test name
Test status
Simulation time 176360338 ps
CPU time 2.9 seconds
Started Mar 28 03:24:49 PM PDT 24
Finished Mar 28 03:24:52 PM PDT 24
Peak memory 233868 kb
Host smart-b4e4d231-3aed-4151-876a-ac9e851a246f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822470337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.3822470337
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.2109412893
Short name T588
Test name
Test status
Simulation time 30387953 ps
CPU time 0.7 seconds
Started Mar 28 03:24:43 PM PDT 24
Finished Mar 28 03:24:44 PM PDT 24
Peak memory 205896 kb
Host smart-69603c87-a144-40bf-8f99-7af6dd573259
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109412893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
2109412893
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.2949893959
Short name T661
Test name
Test status
Simulation time 862283397 ps
CPU time 3.14 seconds
Started Mar 28 03:24:49 PM PDT 24
Finished Mar 28 03:24:52 PM PDT 24
Peak memory 219940 kb
Host smart-e4e7e197-9073-4c8d-b48b-1dc6bc7d9a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949893959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.2949893959
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.621067577
Short name T426
Test name
Test status
Simulation time 50903266 ps
CPU time 0.81 seconds
Started Mar 28 03:24:44 PM PDT 24
Finished Mar 28 03:24:45 PM PDT 24
Peak memory 207000 kb
Host smart-37bf1c26-902f-49c0-8de7-b0764a56d18e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621067577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.621067577
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.3754203063
Short name T436
Test name
Test status
Simulation time 23077646727 ps
CPU time 112.02 seconds
Started Mar 28 03:24:45 PM PDT 24
Finished Mar 28 03:26:37 PM PDT 24
Peak memory 250596 kb
Host smart-eb27e307-9774-4bc3-94cd-c389bae6c797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754203063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.3754203063
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.1732094817
Short name T157
Test name
Test status
Simulation time 615556660944 ps
CPU time 376.79 seconds
Started Mar 28 03:24:45 PM PDT 24
Finished Mar 28 03:31:02 PM PDT 24
Peak memory 256052 kb
Host smart-c9734cbc-aade-451b-9374-28d810e262f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732094817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.1732094817
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.4087812311
Short name T340
Test name
Test status
Simulation time 14505200191 ps
CPU time 138.07 seconds
Started Mar 28 03:24:45 PM PDT 24
Finished Mar 28 03:27:04 PM PDT 24
Peak memory 249648 kb
Host smart-137aa8f9-3b89-4fdd-821e-14d87a5c7bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087812311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.4087812311
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.600931304
Short name T409
Test name
Test status
Simulation time 1833784860 ps
CPU time 16.71 seconds
Started Mar 28 03:24:48 PM PDT 24
Finished Mar 28 03:25:05 PM PDT 24
Peak memory 241120 kb
Host smart-8c80c57a-a072-4431-952c-bb1dc55444d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600931304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.600931304
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.1369469647
Short name T716
Test name
Test status
Simulation time 11357226267 ps
CPU time 7.17 seconds
Started Mar 28 03:24:45 PM PDT 24
Finished Mar 28 03:24:53 PM PDT 24
Peak memory 220116 kb
Host smart-b794179f-cd71-42c4-bfec-cbf796406e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369469647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.1369469647
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.2671321311
Short name T623
Test name
Test status
Simulation time 3747085441 ps
CPU time 6.92 seconds
Started Mar 28 03:24:45 PM PDT 24
Finished Mar 28 03:24:52 PM PDT 24
Peak memory 219188 kb
Host smart-9a0ca0ec-b813-445f-9100-b6140af2dd95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671321311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.2671321311
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.3170337056
Short name T376
Test name
Test status
Simulation time 476285594 ps
CPU time 3.19 seconds
Started Mar 28 03:24:44 PM PDT 24
Finished Mar 28 03:24:47 PM PDT 24
Peak memory 219716 kb
Host smart-c335d0b8-2fc5-415d-afad-ea76cce6482b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170337056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.3170337056
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.742210692
Short name T746
Test name
Test status
Simulation time 38201506045 ps
CPU time 28.45 seconds
Started Mar 28 03:24:43 PM PDT 24
Finished Mar 28 03:25:11 PM PDT 24
Peak memory 233136 kb
Host smart-f267d893-faf6-429c-996f-f685c01ee4e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742210692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.742210692
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.3342269348
Short name T685
Test name
Test status
Simulation time 986017911 ps
CPU time 3.62 seconds
Started Mar 28 03:24:52 PM PDT 24
Finished Mar 28 03:24:56 PM PDT 24
Peak memory 219732 kb
Host smart-04930897-7ec8-4d97-8a5c-c2cfa52720c9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3342269348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.3342269348
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.2106454146
Short name T705
Test name
Test status
Simulation time 86111087139 ps
CPU time 146.34 seconds
Started Mar 28 03:24:45 PM PDT 24
Finished Mar 28 03:27:12 PM PDT 24
Peak memory 236660 kb
Host smart-b76173cc-5456-4306-a103-3b3bd79c4851
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106454146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.2106454146
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.1811362454
Short name T948
Test name
Test status
Simulation time 27160951757 ps
CPU time 11.76 seconds
Started Mar 28 03:24:47 PM PDT 24
Finished Mar 28 03:24:59 PM PDT 24
Peak memory 216808 kb
Host smart-361ef395-15af-4fc6-b976-d11065a06127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811362454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.1811362454
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.138681866
Short name T632
Test name
Test status
Simulation time 9119578571 ps
CPU time 6.48 seconds
Started Mar 28 03:24:50 PM PDT 24
Finished Mar 28 03:24:56 PM PDT 24
Peak memory 216660 kb
Host smart-cfd225a6-afed-43ac-b7fb-3ac3f9f8fd73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138681866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.138681866
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.135492423
Short name T316
Test name
Test status
Simulation time 135549558 ps
CPU time 1.25 seconds
Started Mar 28 03:24:47 PM PDT 24
Finished Mar 28 03:24:49 PM PDT 24
Peak memory 216740 kb
Host smart-02af3f07-d882-417a-beea-68c8551bfeba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135492423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.135492423
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.811531093
Short name T348
Test name
Test status
Simulation time 327599165 ps
CPU time 0.92 seconds
Started Mar 28 03:24:46 PM PDT 24
Finished Mar 28 03:24:47 PM PDT 24
Peak memory 207208 kb
Host smart-f310733f-7d70-4b5c-b58e-b2d79a60f25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811531093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.811531093
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.2462551545
Short name T663
Test name
Test status
Simulation time 1397183164 ps
CPU time 7.47 seconds
Started Mar 28 03:24:43 PM PDT 24
Finished Mar 28 03:24:50 PM PDT 24
Peak memory 219828 kb
Host smart-882c9fbb-89f5-4c57-b3bc-b0e88edc4e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462551545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.2462551545
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.3019142445
Short name T580
Test name
Test status
Simulation time 13729838 ps
CPU time 0.72 seconds
Started Mar 28 03:24:45 PM PDT 24
Finished Mar 28 03:24:46 PM PDT 24
Peak memory 205868 kb
Host smart-aff8a1be-69e1-4e4b-99ae-9a480a7e7a48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019142445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
3019142445
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.435709076
Short name T739
Test name
Test status
Simulation time 3151341165 ps
CPU time 5.19 seconds
Started Mar 28 03:24:46 PM PDT 24
Finished Mar 28 03:24:52 PM PDT 24
Peak memory 237848 kb
Host smart-b2a70866-7567-45a6-a862-6fb8f6107b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435709076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.435709076
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.1858754151
Short name T932
Test name
Test status
Simulation time 28255192 ps
CPU time 0.79 seconds
Started Mar 28 03:24:47 PM PDT 24
Finished Mar 28 03:24:48 PM PDT 24
Peak memory 207020 kb
Host smart-60148ba7-9798-40b7-805b-021b84a672e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858754151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.1858754151
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.3764160423
Short name T241
Test name
Test status
Simulation time 7464938494 ps
CPU time 66.83 seconds
Started Mar 28 03:24:47 PM PDT 24
Finished Mar 28 03:25:54 PM PDT 24
Peak memory 249524 kb
Host smart-e197e093-3f55-4b33-b7cb-07d2c9c362d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764160423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.3764160423
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.9333594
Short name T112
Test name
Test status
Simulation time 156792687255 ps
CPU time 254.6 seconds
Started Mar 28 03:24:45 PM PDT 24
Finished Mar 28 03:28:59 PM PDT 24
Peak memory 254224 kb
Host smart-29d13e03-641a-4f20-ad1b-185e58ca2c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9333594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.9333594
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.12781965
Short name T330
Test name
Test status
Simulation time 10184619110 ps
CPU time 50.75 seconds
Started Mar 28 03:24:44 PM PDT 24
Finished Mar 28 03:25:35 PM PDT 24
Peak memory 249740 kb
Host smart-22a86ad7-a003-40f7-9e6b-5af0cb931669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12781965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idle.12781965
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.2746186182
Short name T261
Test name
Test status
Simulation time 2591708263 ps
CPU time 16.52 seconds
Started Mar 28 03:24:49 PM PDT 24
Finished Mar 28 03:25:06 PM PDT 24
Peak memory 234560 kb
Host smart-049314dd-4efc-4600-8c20-0a5e3c238881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746186182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.2746186182
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.1014307269
Short name T359
Test name
Test status
Simulation time 74903135 ps
CPU time 2.71 seconds
Started Mar 28 03:24:47 PM PDT 24
Finished Mar 28 03:24:49 PM PDT 24
Peak memory 233988 kb
Host smart-29bd2269-cf02-431f-979a-18fb609f4fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014307269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.1014307269
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.3568601377
Short name T466
Test name
Test status
Simulation time 2799448752 ps
CPU time 10.6 seconds
Started Mar 28 03:24:50 PM PDT 24
Finished Mar 28 03:25:00 PM PDT 24
Peak memory 241208 kb
Host smart-f7b45b9d-3452-4fb2-af47-fd468362dd35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568601377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.3568601377
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.1386398866
Short name T62
Test name
Test status
Simulation time 5179210770 ps
CPU time 5.21 seconds
Started Mar 28 03:24:43 PM PDT 24
Finished Mar 28 03:24:49 PM PDT 24
Peak memory 217392 kb
Host smart-f57d87ba-6552-428c-83df-6c36e5ac72b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386398866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.1386398866
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.48521171
Short name T639
Test name
Test status
Simulation time 925952950 ps
CPU time 6.86 seconds
Started Mar 28 03:24:44 PM PDT 24
Finished Mar 28 03:24:51 PM PDT 24
Peak memory 221680 kb
Host smart-753a3e78-294f-4144-9916-524b920ac4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48521171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.48521171
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.45635722
Short name T291
Test name
Test status
Simulation time 4051236128 ps
CPU time 4.84 seconds
Started Mar 28 03:24:45 PM PDT 24
Finished Mar 28 03:24:50 PM PDT 24
Peak memory 219912 kb
Host smart-1ac11b31-cdc6-4970-9b8c-8849b51dd38e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=45635722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_direc
t.45635722
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.2295706697
Short name T396
Test name
Test status
Simulation time 27136847574 ps
CPU time 150.32 seconds
Started Mar 28 03:24:50 PM PDT 24
Finished Mar 28 03:27:20 PM PDT 24
Peak memory 252128 kb
Host smart-70c41397-1922-4b35-b9d7-ddaa2c2057f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295706697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.2295706697
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.1165463235
Short name T787
Test name
Test status
Simulation time 3640993237 ps
CPU time 37.55 seconds
Started Mar 28 03:24:46 PM PDT 24
Finished Mar 28 03:25:24 PM PDT 24
Peak memory 216876 kb
Host smart-d3f04494-a657-446e-abb4-52f1dbbbca2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165463235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.1165463235
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.1738345474
Short name T942
Test name
Test status
Simulation time 901304289 ps
CPU time 2.36 seconds
Started Mar 28 03:24:50 PM PDT 24
Finished Mar 28 03:24:52 PM PDT 24
Peak memory 216632 kb
Host smart-6dd53ada-1c09-4aa8-a442-741f8a87ef96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738345474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.1738345474
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.1408299134
Short name T768
Test name
Test status
Simulation time 147364441 ps
CPU time 1.16 seconds
Started Mar 28 03:24:43 PM PDT 24
Finished Mar 28 03:24:44 PM PDT 24
Peak memory 216484 kb
Host smart-44826254-d8dd-446b-90b0-e58dfb6847ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408299134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.1408299134
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.248901446
Short name T408
Test name
Test status
Simulation time 17821462 ps
CPU time 0.71 seconds
Started Mar 28 03:24:44 PM PDT 24
Finished Mar 28 03:24:44 PM PDT 24
Peak memory 206192 kb
Host smart-6967fe39-b0f6-4944-a813-567a2e75826b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248901446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.248901446
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.2780532070
Short name T387
Test name
Test status
Simulation time 3749450539 ps
CPU time 13.91 seconds
Started Mar 28 03:24:45 PM PDT 24
Finished Mar 28 03:24:59 PM PDT 24
Peak memory 230400 kb
Host smart-2edf1e4f-ebcb-4746-a90c-9f734d4b874c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780532070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.2780532070
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.673448682
Short name T397
Test name
Test status
Simulation time 14805371 ps
CPU time 0.72 seconds
Started Mar 28 03:24:51 PM PDT 24
Finished Mar 28 03:24:52 PM PDT 24
Peak memory 205888 kb
Host smart-39fa856c-af81-45e2-b878-038646b4bb58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673448682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.673448682
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.719042031
Short name T539
Test name
Test status
Simulation time 1431106072 ps
CPU time 3.64 seconds
Started Mar 28 03:24:48 PM PDT 24
Finished Mar 28 03:24:51 PM PDT 24
Peak memory 219984 kb
Host smart-ab446ef3-e577-432d-b09b-16cd84bac6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719042031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.719042031
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.3067844357
Short name T366
Test name
Test status
Simulation time 73665980 ps
CPU time 0.82 seconds
Started Mar 28 03:24:49 PM PDT 24
Finished Mar 28 03:24:50 PM PDT 24
Peak memory 207348 kb
Host smart-18618db4-4427-4229-8e41-1f515d8f3954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067844357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.3067844357
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.1264397393
Short name T221
Test name
Test status
Simulation time 15946429653 ps
CPU time 113.54 seconds
Started Mar 28 03:24:52 PM PDT 24
Finished Mar 28 03:26:46 PM PDT 24
Peak memory 265956 kb
Host smart-bef842af-6c99-4a95-a608-8d2f1bd08005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264397393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.1264397393
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.2654793876
Short name T742
Test name
Test status
Simulation time 83712201066 ps
CPU time 148.51 seconds
Started Mar 28 03:24:52 PM PDT 24
Finished Mar 28 03:27:21 PM PDT 24
Peak memory 254300 kb
Host smart-b27adfb2-6a22-46dc-94d4-0d0732e4482c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654793876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.2654793876
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.3470450317
Short name T65
Test name
Test status
Simulation time 196553122716 ps
CPU time 315.94 seconds
Started Mar 28 03:24:51 PM PDT 24
Finished Mar 28 03:30:07 PM PDT 24
Peak memory 249576 kb
Host smart-ee4abede-fb44-43e5-9d6a-b121e1d71806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470450317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.3470450317
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.2622442778
Short name T258
Test name
Test status
Simulation time 13066605670 ps
CPU time 29.53 seconds
Started Mar 28 03:24:52 PM PDT 24
Finished Mar 28 03:25:22 PM PDT 24
Peak memory 248952 kb
Host smart-93cded7d-ddbf-471a-b001-ff4fed73f079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622442778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.2622442778
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.3406420799
Short name T213
Test name
Test status
Simulation time 10434520051 ps
CPU time 9.45 seconds
Started Mar 28 03:24:49 PM PDT 24
Finished Mar 28 03:24:58 PM PDT 24
Peak memory 235656 kb
Host smart-03550ef6-012d-4482-a03e-0f323a7a495c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406420799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.3406420799
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.1021510103
Short name T179
Test name
Test status
Simulation time 9513899303 ps
CPU time 30.25 seconds
Started Mar 28 03:24:50 PM PDT 24
Finished Mar 28 03:25:20 PM PDT 24
Peak memory 238364 kb
Host smart-6352b168-77fc-448d-841e-4265f71f1683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021510103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.1021510103
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.2849228810
Short name T780
Test name
Test status
Simulation time 1943904381 ps
CPU time 3.6 seconds
Started Mar 28 03:24:49 PM PDT 24
Finished Mar 28 03:24:53 PM PDT 24
Peak memory 234064 kb
Host smart-f8bb118d-4a64-4a41-8e3a-445e734026e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849228810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.2849228810
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.586853762
Short name T793
Test name
Test status
Simulation time 20082395941 ps
CPU time 32.78 seconds
Started Mar 28 03:24:48 PM PDT 24
Finished Mar 28 03:25:21 PM PDT 24
Peak memory 246992 kb
Host smart-df3d1626-2126-4bc1-84c4-341af6596c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586853762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.586853762
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.3701107955
Short name T955
Test name
Test status
Simulation time 1530269901 ps
CPU time 6.46 seconds
Started Mar 28 03:24:52 PM PDT 24
Finished Mar 28 03:24:58 PM PDT 24
Peak memory 219212 kb
Host smart-a286d8c9-6298-4f49-b2f1-150938750bb7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3701107955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.3701107955
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.3662118771
Short name T709
Test name
Test status
Simulation time 3446201978 ps
CPU time 62.73 seconds
Started Mar 28 03:24:51 PM PDT 24
Finished Mar 28 03:25:54 PM PDT 24
Peak memory 265312 kb
Host smart-e0f0bf8a-4142-457e-a84f-1856f991c4a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662118771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.3662118771
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.3108241053
Short name T960
Test name
Test status
Simulation time 1724074234 ps
CPU time 12.81 seconds
Started Mar 28 03:24:49 PM PDT 24
Finished Mar 28 03:25:02 PM PDT 24
Peak memory 220216 kb
Host smart-d1c42b73-112e-493f-8256-1cd0272eec19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108241053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.3108241053
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.46455337
Short name T893
Test name
Test status
Simulation time 678337496 ps
CPU time 5.59 seconds
Started Mar 28 03:24:51 PM PDT 24
Finished Mar 28 03:24:57 PM PDT 24
Peak memory 216668 kb
Host smart-23686041-a45f-42ad-9c92-2ccf46a62ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46455337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.46455337
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.1242605194
Short name T624
Test name
Test status
Simulation time 276656391 ps
CPU time 3.35 seconds
Started Mar 28 03:24:48 PM PDT 24
Finished Mar 28 03:24:51 PM PDT 24
Peak memory 216704 kb
Host smart-83d40250-7590-4ffa-918a-d9b51a7517d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242605194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.1242605194
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.1895278786
Short name T839
Test name
Test status
Simulation time 163823286 ps
CPU time 0.93 seconds
Started Mar 28 03:24:49 PM PDT 24
Finished Mar 28 03:24:50 PM PDT 24
Peak memory 207192 kb
Host smart-99eff416-a975-4f45-a54b-3012a3680de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895278786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.1895278786
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.3186177912
Short name T587
Test name
Test status
Simulation time 1541764764 ps
CPU time 9.72 seconds
Started Mar 28 03:24:50 PM PDT 24
Finished Mar 28 03:25:00 PM PDT 24
Peak memory 239628 kb
Host smart-e43b27a1-01ff-441c-9111-5a49e6b38540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186177912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.3186177912
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.240033680
Short name T724
Test name
Test status
Simulation time 12308758 ps
CPU time 0.74 seconds
Started Mar 28 03:21:44 PM PDT 24
Finished Mar 28 03:21:45 PM PDT 24
Peak memory 206180 kb
Host smart-f5c7b561-4bc7-436d-8cd8-386013a7af92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240033680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.240033680
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.3597587986
Short name T795
Test name
Test status
Simulation time 2342072304 ps
CPU time 6.98 seconds
Started Mar 28 03:21:28 PM PDT 24
Finished Mar 28 03:21:35 PM PDT 24
Peak memory 234256 kb
Host smart-ee17ae7a-9118-45df-ab83-a476af267eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597587986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.3597587986
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.1888547254
Short name T484
Test name
Test status
Simulation time 28272416 ps
CPU time 0.77 seconds
Started Mar 28 03:21:29 PM PDT 24
Finished Mar 28 03:21:30 PM PDT 24
Peak memory 207308 kb
Host smart-d6c3b02d-783d-4d9f-81b3-d3d4129ed03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888547254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.1888547254
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.1893028396
Short name T136
Test name
Test status
Simulation time 12808957310 ps
CPU time 25.01 seconds
Started Mar 28 03:21:46 PM PDT 24
Finished Mar 28 03:22:12 PM PDT 24
Peak memory 251660 kb
Host smart-f4974273-16f9-4fc2-8c49-5cc3ec7acdf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893028396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.1893028396
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.1705258229
Short name T511
Test name
Test status
Simulation time 79610273806 ps
CPU time 102.01 seconds
Started Mar 28 03:21:45 PM PDT 24
Finished Mar 28 03:23:27 PM PDT 24
Peak memory 263100 kb
Host smart-e8ca5edc-6779-4545-a470-b32cef3e70a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705258229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.1705258229
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.2856740929
Short name T615
Test name
Test status
Simulation time 223246275874 ps
CPU time 383.47 seconds
Started Mar 28 03:21:50 PM PDT 24
Finished Mar 28 03:28:14 PM PDT 24
Peak memory 266892 kb
Host smart-c2f2e64c-ad29-4c2c-b1c7-5537141f49a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856740929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.2856740929
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.925433312
Short name T403
Test name
Test status
Simulation time 448047799 ps
CPU time 13.11 seconds
Started Mar 28 03:21:26 PM PDT 24
Finished Mar 28 03:21:40 PM PDT 24
Peak memory 240664 kb
Host smart-6754b0f1-d30f-4037-a0a7-743d4f24e793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925433312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.925433312
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.2570074815
Short name T667
Test name
Test status
Simulation time 1709788262 ps
CPU time 7.71 seconds
Started Mar 28 03:21:31 PM PDT 24
Finished Mar 28 03:21:39 PM PDT 24
Peak memory 233836 kb
Host smart-1e19e48c-5af6-40de-86de-4f9b75f9612c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570074815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.2570074815
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.818975816
Short name T363
Test name
Test status
Simulation time 1179796968 ps
CPU time 11.19 seconds
Started Mar 28 03:21:28 PM PDT 24
Finished Mar 28 03:21:39 PM PDT 24
Peak memory 240712 kb
Host smart-c36a9d51-abdb-49cd-8730-9c7d08ad8458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818975816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.818975816
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.2542256396
Short name T442
Test name
Test status
Simulation time 528649086 ps
CPU time 5.46 seconds
Started Mar 28 03:21:25 PM PDT 24
Finished Mar 28 03:21:30 PM PDT 24
Peak memory 233932 kb
Host smart-fa695f3f-fbc7-4c99-ba72-369b9557b1c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542256396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.2542256396
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.1429622545
Short name T231
Test name
Test status
Simulation time 22451969504 ps
CPU time 16.74 seconds
Started Mar 28 03:21:28 PM PDT 24
Finished Mar 28 03:21:45 PM PDT 24
Peak memory 237080 kb
Host smart-a348a9d1-c39f-42b3-a864-9e9d9a7aa41f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429622545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.1429622545
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_ram_cfg.1798024966
Short name T751
Test name
Test status
Simulation time 19256466 ps
CPU time 0.77 seconds
Started Mar 28 03:21:31 PM PDT 24
Finished Mar 28 03:21:32 PM PDT 24
Peak memory 216540 kb
Host smart-f7b97caa-2c96-49b0-b4b7-d26f8de25272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798024966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_ram_cfg.1798024966
Directory /workspace/5.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.2764978552
Short name T874
Test name
Test status
Simulation time 235416313 ps
CPU time 3.59 seconds
Started Mar 28 03:21:40 PM PDT 24
Finished Mar 28 03:21:44 PM PDT 24
Peak memory 221168 kb
Host smart-d01faa65-9760-476e-93aa-3d8c04f006f8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2764978552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.2764978552
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.2754791939
Short name T128
Test name
Test status
Simulation time 3867430206 ps
CPU time 40.87 seconds
Started Mar 28 03:21:46 PM PDT 24
Finished Mar 28 03:22:28 PM PDT 24
Peak memory 240248 kb
Host smart-9efa5479-54cc-45f9-852e-30e76ddab235
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754791939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.2754791939
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.2072583336
Short name T646
Test name
Test status
Simulation time 9975532031 ps
CPU time 29.89 seconds
Started Mar 28 03:21:32 PM PDT 24
Finished Mar 28 03:22:02 PM PDT 24
Peak memory 216892 kb
Host smart-10c3ea7f-2a40-4245-a2e9-c62da10a2e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072583336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.2072583336
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.3748588161
Short name T367
Test name
Test status
Simulation time 19906777689 ps
CPU time 26.82 seconds
Started Mar 28 03:21:29 PM PDT 24
Finished Mar 28 03:21:56 PM PDT 24
Peak memory 216768 kb
Host smart-2127b792-b456-4ddc-a83c-e69566abeead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748588161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.3748588161
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.600896277
Short name T294
Test name
Test status
Simulation time 32257638 ps
CPU time 1.07 seconds
Started Mar 28 03:21:24 PM PDT 24
Finished Mar 28 03:21:26 PM PDT 24
Peak memory 208236 kb
Host smart-26b49036-827b-4dd5-aeb1-b9361234adc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600896277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.600896277
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.2434832400
Short name T938
Test name
Test status
Simulation time 67882132 ps
CPU time 1.08 seconds
Started Mar 28 03:21:29 PM PDT 24
Finished Mar 28 03:21:30 PM PDT 24
Peak memory 207180 kb
Host smart-988531f1-b086-462d-8c98-a1c15af56a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434832400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.2434832400
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.3168497968
Short name T962
Test name
Test status
Simulation time 6482126622 ps
CPU time 23.99 seconds
Started Mar 28 03:21:27 PM PDT 24
Finished Mar 28 03:21:52 PM PDT 24
Peak memory 232056 kb
Host smart-594a65b4-128c-49c1-8b02-e65852fe1909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168497968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.3168497968
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.1942202318
Short name T430
Test name
Test status
Simulation time 12410500 ps
CPU time 0.72 seconds
Started Mar 28 03:21:46 PM PDT 24
Finished Mar 28 03:21:48 PM PDT 24
Peak memory 205832 kb
Host smart-fd74b425-69f4-4d23-b1d3-c7b79bc8d0bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942202318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.1
942202318
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.3842819334
Short name T890
Test name
Test status
Simulation time 467834846 ps
CPU time 2.85 seconds
Started Mar 28 03:21:51 PM PDT 24
Finished Mar 28 03:21:55 PM PDT 24
Peak memory 218920 kb
Host smart-e7c4667f-9d3e-4cd3-9874-dd3102694173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842819334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.3842819334
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.1905177592
Short name T662
Test name
Test status
Simulation time 19923784 ps
CPU time 0.78 seconds
Started Mar 28 03:21:49 PM PDT 24
Finished Mar 28 03:21:51 PM PDT 24
Peak memory 206324 kb
Host smart-835097c9-8add-4d00-96e0-d33041b47aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905177592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.1905177592
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.4138222562
Short name T238
Test name
Test status
Simulation time 3244639215 ps
CPU time 59.32 seconds
Started Mar 28 03:21:45 PM PDT 24
Finished Mar 28 03:22:46 PM PDT 24
Peak memory 249656 kb
Host smart-fb79fde7-3ec3-42a4-a393-9c66b485fc29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138222562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.4138222562
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.3564623134
Short name T14
Test name
Test status
Simulation time 20148155338 ps
CPU time 165.7 seconds
Started Mar 28 03:21:43 PM PDT 24
Finished Mar 28 03:24:30 PM PDT 24
Peak memory 249620 kb
Host smart-5b71a9ab-c823-41e2-99ea-0500baf3bb05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564623134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.3564623134
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_intercept.3093634326
Short name T629
Test name
Test status
Simulation time 806149192 ps
CPU time 7.06 seconds
Started Mar 28 03:21:49 PM PDT 24
Finished Mar 28 03:21:56 PM PDT 24
Peak memory 233948 kb
Host smart-f55c832a-7ba7-4568-b127-edd2f9fa0537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093634326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.3093634326
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.3180612104
Short name T808
Test name
Test status
Simulation time 17023415349 ps
CPU time 17.7 seconds
Started Mar 28 03:21:52 PM PDT 24
Finished Mar 28 03:22:10 PM PDT 24
Peak memory 227412 kb
Host smart-a5946ece-3871-4540-a300-ac19e88c39ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180612104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.3180612104
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.2540745704
Short name T256
Test name
Test status
Simulation time 6780803862 ps
CPU time 5.23 seconds
Started Mar 28 03:21:46 PM PDT 24
Finished Mar 28 03:21:53 PM PDT 24
Peak memory 234220 kb
Host smart-0c94e390-9463-4e29-bdd4-aca3e39e652e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540745704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.2540745704
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.503700533
Short name T545
Test name
Test status
Simulation time 41302735473 ps
CPU time 29.31 seconds
Started Mar 28 03:21:42 PM PDT 24
Finished Mar 28 03:22:11 PM PDT 24
Peak memory 237328 kb
Host smart-e3808acd-01d2-4107-81be-502e7f99c1cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503700533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.503700533
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_ram_cfg.1528971129
Short name T680
Test name
Test status
Simulation time 19479059 ps
CPU time 0.77 seconds
Started Mar 28 03:21:56 PM PDT 24
Finished Mar 28 03:21:58 PM PDT 24
Peak memory 216568 kb
Host smart-135ae80f-d2ed-4f07-8a39-e14b967dfd63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528971129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_ram_cfg.1528971129
Directory /workspace/6.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.209642087
Short name T690
Test name
Test status
Simulation time 2612826816 ps
CPU time 3.99 seconds
Started Mar 28 03:21:39 PM PDT 24
Finished Mar 28 03:21:43 PM PDT 24
Peak memory 220920 kb
Host smart-c045d4a2-0d1f-459c-8a14-667b69b09ce5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=209642087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_direc
t.209642087
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.2107720181
Short name T937
Test name
Test status
Simulation time 103952405546 ps
CPU time 75.3 seconds
Started Mar 28 03:21:43 PM PDT 24
Finished Mar 28 03:22:59 PM PDT 24
Peak memory 238140 kb
Host smart-f75893f2-dd84-4e86-b680-11400a9995cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107720181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.2107720181
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.730395120
Short name T851
Test name
Test status
Simulation time 4910734806 ps
CPU time 37.94 seconds
Started Mar 28 03:21:40 PM PDT 24
Finished Mar 28 03:22:18 PM PDT 24
Peak memory 216900 kb
Host smart-5ee94655-4360-4fd3-acc8-e36d656d3355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730395120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.730395120
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.1584849240
Short name T801
Test name
Test status
Simulation time 46344377440 ps
CPU time 18.65 seconds
Started Mar 28 03:21:46 PM PDT 24
Finished Mar 28 03:22:06 PM PDT 24
Peak memory 216764 kb
Host smart-2818e8bc-e073-41e7-8c5a-1eb1eff2f2d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584849240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.1584849240
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.265728620
Short name T759
Test name
Test status
Simulation time 114280079 ps
CPU time 0.99 seconds
Started Mar 28 03:21:41 PM PDT 24
Finished Mar 28 03:21:43 PM PDT 24
Peak memory 207592 kb
Host smart-457c5bf3-69dd-4980-ae56-dc1a06fb8ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265728620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.265728620
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.2837568803
Short name T817
Test name
Test status
Simulation time 354191341 ps
CPU time 0.99 seconds
Started Mar 28 03:21:44 PM PDT 24
Finished Mar 28 03:21:46 PM PDT 24
Peak memory 207140 kb
Host smart-64c6c669-88f3-4777-bae2-c12ee25796d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837568803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.2837568803
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.3442254284
Short name T693
Test name
Test status
Simulation time 328800788 ps
CPU time 6.43 seconds
Started Mar 28 03:21:41 PM PDT 24
Finished Mar 28 03:21:48 PM PDT 24
Peak memory 236892 kb
Host smart-05f1ce2b-351f-4ce3-b9ce-2bc9eccd9eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442254284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.3442254284
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.1985530576
Short name T854
Test name
Test status
Simulation time 14389368 ps
CPU time 0.71 seconds
Started Mar 28 03:21:47 PM PDT 24
Finished Mar 28 03:21:49 PM PDT 24
Peak memory 205864 kb
Host smart-59ce83bc-5158-4620-b9fb-dbf379f9c229
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985530576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.1
985530576
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.3958950370
Short name T449
Test name
Test status
Simulation time 624320711 ps
CPU time 3.52 seconds
Started Mar 28 03:21:47 PM PDT 24
Finished Mar 28 03:21:51 PM PDT 24
Peak memory 234156 kb
Host smart-f6029e7b-2e03-42df-8edb-506e0162f228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958950370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.3958950370
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.453505392
Short name T940
Test name
Test status
Simulation time 49601476 ps
CPU time 0.78 seconds
Started Mar 28 03:21:43 PM PDT 24
Finished Mar 28 03:21:45 PM PDT 24
Peak memory 207008 kb
Host smart-9d71f7ab-641e-4eb0-959e-c24f980c4154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453505392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.453505392
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.4138246493
Short name T189
Test name
Test status
Simulation time 80519297695 ps
CPU time 108.67 seconds
Started Mar 28 03:21:42 PM PDT 24
Finished Mar 28 03:23:32 PM PDT 24
Peak memory 241392 kb
Host smart-358d339a-aa55-46a2-9f59-c35a3af8e505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138246493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.4138246493
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.960559078
Short name T153
Test name
Test status
Simulation time 286541635514 ps
CPU time 400.95 seconds
Started Mar 28 03:21:44 PM PDT 24
Finished Mar 28 03:28:26 PM PDT 24
Peak memory 255656 kb
Host smart-4e31389a-0f52-40ba-a896-6bbfec291bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960559078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.960559078
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.98539123
Short name T837
Test name
Test status
Simulation time 16847255455 ps
CPU time 108.65 seconds
Started Mar 28 03:21:53 PM PDT 24
Finished Mar 28 03:23:41 PM PDT 24
Peak memory 238604 kb
Host smart-d847bf04-fada-462e-bccc-5d48bd0e7e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98539123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.98539123
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.2024348673
Short name T475
Test name
Test status
Simulation time 25121949346 ps
CPU time 63.69 seconds
Started Mar 28 03:21:45 PM PDT 24
Finished Mar 28 03:22:49 PM PDT 24
Peak memory 249292 kb
Host smart-8cc12e97-6237-4ab7-96a8-b72077851645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024348673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.2024348673
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.4197725568
Short name T206
Test name
Test status
Simulation time 6080952722 ps
CPU time 7.78 seconds
Started Mar 28 03:21:42 PM PDT 24
Finished Mar 28 03:21:50 PM PDT 24
Peak memory 235188 kb
Host smart-457d6ae9-d82a-49c9-a7b1-0d0e3cc10428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197725568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.4197725568
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.2849446188
Short name T326
Test name
Test status
Simulation time 105051341 ps
CPU time 2.89 seconds
Started Mar 28 03:21:43 PM PDT 24
Finished Mar 28 03:21:47 PM PDT 24
Peak memory 224880 kb
Host smart-4aa804cc-c863-4827-ac49-b0fc4b362c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849446188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.2849446188
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.2369796032
Short name T481
Test name
Test status
Simulation time 5822498420 ps
CPU time 11.88 seconds
Started Mar 28 03:21:37 PM PDT 24
Finished Mar 28 03:21:50 PM PDT 24
Peak memory 219228 kb
Host smart-e571f99c-450f-41f2-802a-622fef47b05d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369796032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.2369796032
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.1500310534
Short name T472
Test name
Test status
Simulation time 3515664904 ps
CPU time 10.38 seconds
Started Mar 28 03:21:47 PM PDT 24
Finished Mar 28 03:21:58 PM PDT 24
Peak memory 236656 kb
Host smart-f9645444-b820-4d87-8c2e-0963c6d63908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500310534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.1500310534
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_ram_cfg.3362692362
Short name T301
Test name
Test status
Simulation time 17865229 ps
CPU time 0.76 seconds
Started Mar 28 03:21:47 PM PDT 24
Finished Mar 28 03:21:48 PM PDT 24
Peak memory 216508 kb
Host smart-0cfacbbf-8227-4868-8b9b-963843ed2e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362692362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_ram_cfg.3362692362
Directory /workspace/7.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.3368300481
Short name T737
Test name
Test status
Simulation time 88512296 ps
CPU time 3.56 seconds
Started Mar 28 03:21:47 PM PDT 24
Finished Mar 28 03:21:51 PM PDT 24
Peak memory 222276 kb
Host smart-f4549771-d839-45ca-8d10-efc6612323b7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3368300481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.3368300481
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.3666211015
Short name T590
Test name
Test status
Simulation time 44212698 ps
CPU time 1.05 seconds
Started Mar 28 03:21:43 PM PDT 24
Finished Mar 28 03:21:45 PM PDT 24
Peak memory 207612 kb
Host smart-322b68a6-6a7f-4a8b-8d74-d2178770c21d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666211015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.3666211015
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.4109268587
Short name T747
Test name
Test status
Simulation time 2490271317 ps
CPU time 17.11 seconds
Started Mar 28 03:21:50 PM PDT 24
Finished Mar 28 03:22:08 PM PDT 24
Peak memory 216752 kb
Host smart-21c6e8fe-50fc-4038-bf4a-a9a62cb91b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109268587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.4109268587
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.634549696
Short name T420
Test name
Test status
Simulation time 3357071839 ps
CPU time 9.1 seconds
Started Mar 28 03:21:47 PM PDT 24
Finished Mar 28 03:21:57 PM PDT 24
Peak memory 216748 kb
Host smart-1be4f0e8-8421-4846-86a8-311310a4aade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634549696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.634549696
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.3566985277
Short name T763
Test name
Test status
Simulation time 524917695 ps
CPU time 6.23 seconds
Started Mar 28 03:21:40 PM PDT 24
Finished Mar 28 03:21:47 PM PDT 24
Peak memory 216744 kb
Host smart-51921bb2-a44c-4509-b8ad-84cfd2d36fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566985277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.3566985277
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.3409255193
Short name T347
Test name
Test status
Simulation time 48249223 ps
CPU time 0.82 seconds
Started Mar 28 03:21:41 PM PDT 24
Finished Mar 28 03:21:43 PM PDT 24
Peak memory 206188 kb
Host smart-90fbc4c4-d393-4dae-9d48-77f1b15bbb26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409255193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.3409255193
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.2895685522
Short name T299
Test name
Test status
Simulation time 1012800415 ps
CPU time 7.93 seconds
Started Mar 28 03:21:56 PM PDT 24
Finished Mar 28 03:22:04 PM PDT 24
Peak memory 234908 kb
Host smart-b764b3ee-0d95-4fc1-9c9c-8672fff5ec72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895685522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.2895685522
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.2273266488
Short name T882
Test name
Test status
Simulation time 11159238 ps
CPU time 0.7 seconds
Started Mar 28 03:21:46 PM PDT 24
Finished Mar 28 03:21:48 PM PDT 24
Peak memory 205264 kb
Host smart-f49e31b4-6b0e-4e97-a94b-834a7bab1db9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273266488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.2
273266488
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.2079426528
Short name T872
Test name
Test status
Simulation time 85696434 ps
CPU time 2.94 seconds
Started Mar 28 03:21:44 PM PDT 24
Finished Mar 28 03:21:48 PM PDT 24
Peak memory 236092 kb
Host smart-9206e14f-d01e-43bf-94c0-9e5b78042f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079426528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.2079426528
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.1735347441
Short name T786
Test name
Test status
Simulation time 22730961 ps
CPU time 0.75 seconds
Started Mar 28 03:21:45 PM PDT 24
Finished Mar 28 03:21:47 PM PDT 24
Peak memory 205980 kb
Host smart-4b3f7578-1da1-48af-bbc9-8075eb85268e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735347441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.1735347441
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.3204758390
Short name T192
Test name
Test status
Simulation time 2153958684 ps
CPU time 33.76 seconds
Started Mar 28 03:21:52 PM PDT 24
Finished Mar 28 03:22:25 PM PDT 24
Peak memory 251704 kb
Host smart-5746a88f-e291-434d-bc35-c2354977d263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204758390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.3204758390
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.848300602
Short name T526
Test name
Test status
Simulation time 791436195 ps
CPU time 8.26 seconds
Started Mar 28 03:21:43 PM PDT 24
Finished Mar 28 03:21:53 PM PDT 24
Peak memory 225012 kb
Host smart-d77ff64c-cc27-44dc-a305-e621670455ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848300602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.848300602
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.2244900362
Short name T815
Test name
Test status
Simulation time 201336106 ps
CPU time 2.87 seconds
Started Mar 28 03:21:50 PM PDT 24
Finished Mar 28 03:21:53 PM PDT 24
Peak memory 234040 kb
Host smart-ed441cab-aa1a-454c-8dc6-5b37a559168f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244900362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.2244900362
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.3694447684
Short name T943
Test name
Test status
Simulation time 717196832 ps
CPU time 7.27 seconds
Started Mar 28 03:21:41 PM PDT 24
Finished Mar 28 03:21:49 PM PDT 24
Peak memory 234112 kb
Host smart-d488fecd-4527-4b24-9d28-c5ec03345c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694447684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.3694447684
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.1027267261
Short name T681
Test name
Test status
Simulation time 7069778208 ps
CPU time 19.99 seconds
Started Mar 28 03:21:46 PM PDT 24
Finished Mar 28 03:22:07 PM PDT 24
Peak memory 234072 kb
Host smart-ccce8a9a-bb12-4068-99d3-8c7c1c7ac085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027267261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.1027267261
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.2192127829
Short name T228
Test name
Test status
Simulation time 19155009415 ps
CPU time 35.07 seconds
Started Mar 28 03:21:50 PM PDT 24
Finished Mar 28 03:22:26 PM PDT 24
Peak memory 242324 kb
Host smart-9ecf214a-cd77-4515-854f-4bf4cffb9a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192127829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.2192127829
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_ram_cfg.2391755670
Short name T591
Test name
Test status
Simulation time 24127357 ps
CPU time 0.75 seconds
Started Mar 28 03:21:45 PM PDT 24
Finished Mar 28 03:21:48 PM PDT 24
Peak memory 216444 kb
Host smart-1e640b31-67ca-4676-9faa-651041d79250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391755670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_ram_cfg.2391755670
Directory /workspace/8.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.3540664177
Short name T117
Test name
Test status
Simulation time 1377664922 ps
CPU time 6.55 seconds
Started Mar 28 03:21:46 PM PDT 24
Finished Mar 28 03:21:53 PM PDT 24
Peak memory 223016 kb
Host smart-957241d0-5c3d-4a18-a56e-54c77270e5ad
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3540664177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.3540664177
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.304474505
Short name T644
Test name
Test status
Simulation time 8112742081 ps
CPU time 53.38 seconds
Started Mar 28 03:21:44 PM PDT 24
Finished Mar 28 03:22:39 PM PDT 24
Peak memory 216760 kb
Host smart-343d9015-ec68-4bcd-a335-d5d3c26e679e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304474505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.304474505
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.2637106962
Short name T939
Test name
Test status
Simulation time 6012518862 ps
CPU time 4.81 seconds
Started Mar 28 03:21:56 PM PDT 24
Finished Mar 28 03:22:02 PM PDT 24
Peak memory 216856 kb
Host smart-fd51ed26-b7b7-4249-95d0-e93732836b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637106962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.2637106962
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.3144355959
Short name T966
Test name
Test status
Simulation time 114819031 ps
CPU time 2.12 seconds
Started Mar 28 03:21:42 PM PDT 24
Finished Mar 28 03:21:45 PM PDT 24
Peak memory 216736 kb
Host smart-f67db5dc-2c74-4b3b-978c-3772ceca053d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144355959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.3144355959
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.1724869641
Short name T282
Test name
Test status
Simulation time 508981516 ps
CPU time 0.83 seconds
Started Mar 28 03:21:50 PM PDT 24
Finished Mar 28 03:21:51 PM PDT 24
Peak memory 206156 kb
Host smart-9fcf6cc8-5ef0-4cbc-8688-94d3925ed085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724869641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.1724869641
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.1743654455
Short name T174
Test name
Test status
Simulation time 47375641834 ps
CPU time 53.84 seconds
Started Mar 28 03:21:45 PM PDT 24
Finished Mar 28 03:22:39 PM PDT 24
Peak memory 233792 kb
Host smart-438e69c0-2abd-4596-b49a-0824d9da1072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743654455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.1743654455
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.3738304049
Short name T819
Test name
Test status
Simulation time 14590262 ps
CPU time 0.74 seconds
Started Mar 28 03:21:53 PM PDT 24
Finished Mar 28 03:21:54 PM PDT 24
Peak memory 205768 kb
Host smart-e9b0e475-0702-4a67-9361-ba608bea7313
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738304049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.3
738304049
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.1316300777
Short name T229
Test name
Test status
Simulation time 222707941 ps
CPU time 2.73 seconds
Started Mar 28 03:21:55 PM PDT 24
Finished Mar 28 03:21:58 PM PDT 24
Peak memory 218800 kb
Host smart-fc5bfb16-9c8d-4158-bf9f-b7ec7869c945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316300777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.1316300777
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.2828752846
Short name T844
Test name
Test status
Simulation time 16175675 ps
CPU time 0.75 seconds
Started Mar 28 03:21:42 PM PDT 24
Finished Mar 28 03:21:43 PM PDT 24
Peak memory 205952 kb
Host smart-c01bdd77-c828-4c3e-bd55-b4120b2bc8fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828752846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.2828752846
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.1884123012
Short name T616
Test name
Test status
Simulation time 131837554938 ps
CPU time 158.13 seconds
Started Mar 28 03:21:56 PM PDT 24
Finished Mar 28 03:24:34 PM PDT 24
Peak memory 257744 kb
Host smart-4f2f648a-dc11-4578-b6d4-0c8214b521eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884123012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.1884123012
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.1728523779
Short name T37
Test name
Test status
Simulation time 52491545534 ps
CPU time 101.34 seconds
Started Mar 28 03:21:50 PM PDT 24
Finished Mar 28 03:23:32 PM PDT 24
Peak memory 237676 kb
Host smart-9454f833-48e5-4842-b394-ae51aa266e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728523779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.1728523779
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.899121053
Short name T149
Test name
Test status
Simulation time 9788760063 ps
CPU time 22.27 seconds
Started Mar 28 03:21:49 PM PDT 24
Finished Mar 28 03:22:12 PM PDT 24
Peak memory 233256 kb
Host smart-b2923c2b-d73b-4551-a8e9-8b27452f889e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899121053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.
899121053
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.980036444
Short name T726
Test name
Test status
Simulation time 44966227662 ps
CPU time 27.97 seconds
Started Mar 28 03:21:55 PM PDT 24
Finished Mar 28 03:22:24 PM PDT 24
Peak memory 236064 kb
Host smart-c8e102f7-60dd-4eb1-b4f4-84acf9e41c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980036444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.980036444
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.727810893
Short name T702
Test name
Test status
Simulation time 483563603 ps
CPU time 4.33 seconds
Started Mar 28 03:21:50 PM PDT 24
Finished Mar 28 03:21:55 PM PDT 24
Peak memory 220560 kb
Host smart-efd997f4-4a36-4bd7-8f0b-2ee7aa5822ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727810893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.727810893
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.1940088284
Short name T190
Test name
Test status
Simulation time 1561672284 ps
CPU time 13.62 seconds
Started Mar 28 03:21:56 PM PDT 24
Finished Mar 28 03:22:10 PM PDT 24
Peak memory 233056 kb
Host smart-e23e763e-5d4f-43ca-801d-bb1c7581565e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940088284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.1940088284
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.3491963495
Short name T694
Test name
Test status
Simulation time 1045983904 ps
CPU time 8.8 seconds
Started Mar 28 03:21:52 PM PDT 24
Finished Mar 28 03:22:01 PM PDT 24
Peak memory 232636 kb
Host smart-3a90f6ed-f060-4113-b8d8-4e146e767afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491963495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.3491963495
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.3049753227
Short name T754
Test name
Test status
Simulation time 6517329638 ps
CPU time 7.89 seconds
Started Mar 28 03:21:45 PM PDT 24
Finished Mar 28 03:21:54 PM PDT 24
Peak memory 217348 kb
Host smart-b2437a66-89a2-4e77-9f59-cd243a9aeee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049753227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.3049753227
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_ram_cfg.923895187
Short name T392
Test name
Test status
Simulation time 17331062 ps
CPU time 0.77 seconds
Started Mar 28 03:21:46 PM PDT 24
Finished Mar 28 03:21:48 PM PDT 24
Peak memory 216536 kb
Host smart-f86b2b94-0568-42b4-a2a9-80257e724d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923895187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_ram_cfg.923895187
Directory /workspace/9.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.1525454536
Short name T753
Test name
Test status
Simulation time 1039797513 ps
CPU time 5.78 seconds
Started Mar 28 03:21:50 PM PDT 24
Finished Mar 28 03:21:56 PM PDT 24
Peak memory 219500 kb
Host smart-cfd740d5-ccc9-4b79-bf1f-22101f7c4e9e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1525454536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.1525454536
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.2752133856
Short name T19
Test name
Test status
Simulation time 102432516900 ps
CPU time 244.11 seconds
Started Mar 28 03:21:56 PM PDT 24
Finished Mar 28 03:26:00 PM PDT 24
Peak memory 266352 kb
Host smart-ec59cd8f-e00e-412c-8e08-f695d4d19bad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752133856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.2752133856
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.378110134
Short name T383
Test name
Test status
Simulation time 1490010470 ps
CPU time 8.51 seconds
Started Mar 28 03:21:57 PM PDT 24
Finished Mar 28 03:22:06 PM PDT 24
Peak memory 216808 kb
Host smart-97efb9d8-9cbc-48b0-a43c-027a1be013f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378110134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.378110134
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.2851776177
Short name T271
Test name
Test status
Simulation time 5057702935 ps
CPU time 3.37 seconds
Started Mar 28 03:21:44 PM PDT 24
Finished Mar 28 03:21:49 PM PDT 24
Peak memory 216668 kb
Host smart-648f40c3-f296-4e86-9eba-bf00ef8286d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851776177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.2851776177
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.336491087
Short name T417
Test name
Test status
Simulation time 151478585 ps
CPU time 1.34 seconds
Started Mar 28 03:21:50 PM PDT 24
Finished Mar 28 03:21:52 PM PDT 24
Peak memory 216720 kb
Host smart-094dad12-7807-4e0e-a989-cdd94f42801e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336491087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.336491087
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.1617657926
Short name T568
Test name
Test status
Simulation time 118621520 ps
CPU time 0.95 seconds
Started Mar 28 03:21:56 PM PDT 24
Finished Mar 28 03:21:57 PM PDT 24
Peak memory 207256 kb
Host smart-0c83a3de-d637-40a6-adda-4fd1ab293b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617657926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1617657926
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.733146404
Short name T830
Test name
Test status
Simulation time 2503011883 ps
CPU time 14.04 seconds
Started Mar 28 03:21:44 PM PDT 24
Finished Mar 28 03:21:58 PM PDT 24
Peak memory 247276 kb
Host smart-ccb461d1-8746-4e8b-8fde-ad0dd89c436a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733146404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.733146404
Directory /workspace/9.spi_device_upload/latest
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