Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1428616	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1586438

1

T1

32

T2

63

T3

906

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2347792	1			T1	1		T2	1		T3	11
values[0x0]	333080	1			T1	17		T2	47		T3	478
values[0x1]	334182	1			T1	23		T2	36		T3	426

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1083173	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1931881

1

T1

33

T2

70

T3

910

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	10422	1			T4	22		T15	5		T16	38
valid_sources[0x01]	10728	1			T3	2		T4	18		T15	14
valid_sources[0x02]	11004	1			T4	24		T15	7		T16	39
valid_sources[0x03]	10938	1			T4	27		T15	2		T16	30
valid_sources[0x04]	11493	1			T3	25		T4	31		T15	10
valid_sources[0x05]	11274	1			T4	17		T16	38		T17	9
valid_sources[0x06]	10178	1			T2	11		T4	30		T16	32
valid_sources[0x07]	10287	1			T1	1		T3	4		T4	30
valid_sources[0x08]	11021	1			T3	6		T4	23		T15	4
valid_sources[0x09]	12194	1			T3	4		T4	29		T15	1
valid_sources[0x0a]	11400	1			T4	29		T15	2		T16	39
valid_sources[0x0b]	10370	1			T3	13		T4	18		T15	2
valid_sources[0x0c]	26118	1			T1	1		T4	33		T15	3
valid_sources[0x0d]	11139	1			T2	4		T4	27		T15	5
valid_sources[0x0e]	11089	1			T4	29		T15	6		T16	39
valid_sources[0x0f]	9923	1			T4	32		T15	5		T16	43
valid_sources[0x10]	12462	1			T4	23		T15	8		T16	32
valid_sources[0x11]	11180	1			T4	26		T15	7		T16	43
valid_sources[0x12]	10310	1			T2	2		T4	28		T15	3
valid_sources[0x13]	10487	1			T4	17		T15	5		T16	29
valid_sources[0x14]	13336	1			T4	24		T15	15		T16	40
valid_sources[0x15]	12597	1			T1	1		T4	28		T15	11
valid_sources[0x16]	12620	1			T1	1		T3	8		T4	20
valid_sources[0x17]	10422	1			T4	18		T15	5		T16	29
valid_sources[0x18]	9884	1			T2	2		T3	7		T4	21
valid_sources[0x19]	10243	1			T4	26		T15	5		T16	30
valid_sources[0x1a]	10460	1			T1	2		T4	25		T15	5
valid_sources[0x1b]	11209	1			T3	7		T4	31		T15	5
valid_sources[0x1c]	10156	1			T2	2		T3	2		T4	23
valid_sources[0x1d]	10312	1			T3	7		T4	29		T16	35
valid_sources[0x1e]	10565	1			T3	2		T4	24		T15	5
valid_sources[0x1f]	11335	1			T4	21		T15	4		T16	35
valid_sources[0x20]	10695	1			T4	28		T15	4		T16	41
valid_sources[0x21]	12959	1			T1	2		T4	26		T15	1
valid_sources[0x22]	10470	1			T4	19		T15	1		T16	30
valid_sources[0x23]	10910	1			T2	2		T3	3		T4	24
valid_sources[0x24]	12218	1			T4	26		T15	1		T16	41
valid_sources[0x25]	10347	1			T4	28		T15	31		T16	46
valid_sources[0x26]	12492	1			T3	14		T4	28		T15	3
valid_sources[0x27]	10202	1			T4	21		T15	20		T16	40
valid_sources[0x28]	12071	1			T3	6		T4	18		T15	14
valid_sources[0x29]	10680	1			T3	4		T4	25		T15	7
valid_sources[0x2a]	12946	1			T3	10		T4	24		T15	9
valid_sources[0x2b]	10006	1			T4	27		T15	6		T16	31
valid_sources[0x2c]	11120	1			T4	20		T15	1		T16	48
valid_sources[0x2d]	14600	1			T4	24		T15	16		T16	33
valid_sources[0x2e]	19299	1			T2	2		T4	20		T15	2
valid_sources[0x2f]	10248	1			T3	10		T4	31		T15	12
valid_sources[0x30]	19165	1			T4	40		T16	52		T17	8
valid_sources[0x31]	10281	1			T3	3		T4	24		T15	7
valid_sources[0x32]	12766	1			T3	14		T4	21		T16	45
valid_sources[0x33]	10875	1			T3	6		T4	15		T15	5
valid_sources[0x34]	10776	1			T3	2		T4	28		T15	6
valid_sources[0x35]	10037	1			T4	24		T15	3		T16	35
valid_sources[0x36]	10014	1			T4	28		T15	6		T16	34
valid_sources[0x37]	11530	1			T2	6		T4	26		T15	9
valid_sources[0x38]	11548	1			T4	25		T15	2		T16	25
valid_sources[0x39]	11662	1			T2	3		T4	31		T16	39
valid_sources[0x3a]	17528	1			T4	30		T15	2		T16	36
valid_sources[0x3b]	11655	1			T4	43		T15	6		T16	46
valid_sources[0x3c]	12571	1			T1	2		T4	26		T15	4
valid_sources[0x3d]	10944	1			T3	15		T4	20		T15	2
valid_sources[0x3e]	11477	1			T4	25		T15	8		T16	36
valid_sources[0x3f]	10124	1			T2	1		T4	25		T15	1
valid_sources[0x40]	14717	1			T4	17		T15	12		T16	39
valid_sources[0x41]	10450	1			T4	19		T15	4		T16	48
valid_sources[0x42]	10222	1			T3	8		T4	23		T15	2
valid_sources[0x43]	10036	1			T4	25		T15	6		T16	39
valid_sources[0x44]	19721	1			T4	20		T15	7		T16	40
valid_sources[0x45]	13590	1			T1	2		T4	28		T15	2
valid_sources[0x46]	10940	1			T3	11		T4	21		T15	1
valid_sources[0x47]	10144	1			T1	2		T4	20		T15	4
valid_sources[0x48]	10608	1			T3	1		T4	33		T15	6
valid_sources[0x49]	10031	1			T3	23		T4	23		T15	9
valid_sources[0x4a]	9928	1			T2	2		T3	2		T4	27
valid_sources[0x4b]	11799	1			T2	5		T3	5		T4	32
valid_sources[0x4c]	14271	1			T1	2		T2	3		T3	4
valid_sources[0x4d]	16749	1			T3	26		T4	28		T15	2
valid_sources[0x4e]	10223	1			T3	10		T4	19		T15	6
valid_sources[0x4f]	10666	1			T1	1		T3	6		T4	36
valid_sources[0x50]	10272	1			T1	1		T3	2		T4	20
valid_sources[0x51]	10707	1			T4	25		T15	3		T16	33
valid_sources[0x52]	11446	1			T3	12		T4	41		T15	1
valid_sources[0x53]	10865	1			T4	23		T15	1		T16	32
valid_sources[0x54]	17723	1			T1	1		T3	12		T4	24
valid_sources[0x55]	14054	1			T4	33		T15	4		T16	40
valid_sources[0x56]	23734	1			T4	23		T15	1		T16	41
valid_sources[0x57]	13291	1			T4	22		T15	8		T16	41
valid_sources[0x58]	31428	1			T1	1		T4	27		T15	1
valid_sources[0x59]	12308	1			T4	18		T15	1		T16	33
valid_sources[0x5a]	11578	1			T4	26		T15	6		T16	43
valid_sources[0x5b]	12055	1			T3	4		T4	27		T15	4
valid_sources[0x5c]	10916	1			T3	2		T4	21		T15	10
valid_sources[0x5d]	10638	1			T3	8		T4	27		T15	2
valid_sources[0x5e]	11371	1			T2	2		T4	24		T16	44
valid_sources[0x5f]	12149	1			T3	1		T4	30		T15	9
valid_sources[0x60]	10320	1			T4	22		T16	33		T17	6
valid_sources[0x61]	11039	1			T1	1		T4	24		T15	11
valid_sources[0x62]	11243	1			T4	20		T15	1		T16	28
valid_sources[0x63]	10151	1			T3	5		T4	32		T15	3
valid_sources[0x64]	11872	1			T4	22		T16	27		T17	1
valid_sources[0x65]	11172	1			T1	1		T4	21		T15	4
valid_sources[0x66]	12040	1			T4	32		T15	1		T16	41
valid_sources[0x67]	14415	1			T3	8		T4	29		T15	2
valid_sources[0x68]	10935	1			T3	5		T4	23		T15	6
valid_sources[0x69]	10682	1			T4	30		T16	39		T17	9
valid_sources[0x6a]	13557	1			T4	30		T15	3		T16	33
valid_sources[0x6b]	11788	1			T3	6		T4	32		T16	33
valid_sources[0x6c]	11048	1			T2	4		T3	18		T4	31
valid_sources[0x6d]	10292	1			T4	23		T15	1		T16	32
valid_sources[0x6e]	10302	1			T3	30		T4	28		T15	2
valid_sources[0x6f]	12926	1			T1	1		T2	1		T3	13
valid_sources[0x70]	11882	1			T4	29		T16	43		T17	3
valid_sources[0x71]	10775	1			T2	1		T4	22		T15	6
valid_sources[0x72]	10599	1			T4	26		T15	11		T16	27
valid_sources[0x73]	9994	1			T4	24		T15	8		T16	37
valid_sources[0x74]	11755	1			T3	18		T4	31		T15	2
valid_sources[0x75]	13445	1			T3	1		T4	27		T16	48
valid_sources[0x76]	12014	1			T2	2		T3	15		T4	23
valid_sources[0x77]	10691	1			T4	27		T16	43		T17	1
valid_sources[0x78]	11779	1			T3	11		T4	36		T15	4
valid_sources[0x79]	11076	1			T3	17		T4	25		T16	38
valid_sources[0x7a]	11028	1			T4	17		T16	40		T17	3
valid_sources[0x7b]	10062	1			T3	7		T4	23		T15	5
valid_sources[0x7c]	10889	1			T1	1		T3	2		T4	23
valid_sources[0x7d]	11020	1			T4	26		T15	1		T16	47
valid_sources[0x7e]	14527	1			T4	39		T15	13		T16	32
valid_sources[0x7f]	10787	1			T3	1		T4	27		T15	4
valid_sources[0x80]	11923	1			T4	23		T15	6		T16	29

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

982575

1

T1

1

T3

4

T4

2186

values[0x0]

all_enables

biggest_size

304916

1

T1

13

T2

37

T3

478

values[0x1]

all_enables

biggest_size

298947

1

T1

18

T2

26

T3

424