Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1448725

1

T1

9

T2

21

T3

9

full_word

1587587

1

T1

32

T2

63

T3

906

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3035892	1			T1	41		T2	84		T3	915
auto[TlIntgErrCmd]	135	1			T122	9		T124	7		T129	3
auto[TlIntgErrData]	142	1			T122	5		T124	3		T129	4
auto[TlIntgErrBoth]	143	1			T122	6		T124	10		T129	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2351322

1

T1

1

T2

1

T3

11

auto[1]

684990

1

T1

40

T2

83

T3

904

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1368287	1			T2	1		T3	7		T4	2229
auto[TlIntgErrNone]	partial	auto[1]	80046	1			T1	9		T2	20		T3	2
auto[TlIntgErrNone]	full_word	auto[0]	982844	1			T1	1		T3	4		T4	2186
auto[TlIntgErrNone]	full_word	auto[1]	604715	1			T1	31		T2	63		T3	902
auto[TlIntgErrCmd]	partial	auto[0]	55	1			T122	3		T124	2		T129	2
auto[TlIntgErrCmd]	partial	auto[1]	71	1			T122	6		T124	5		T129	1
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T370	1		T369	1		T371	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T369	1		T163	1		T371	1
auto[TlIntgErrData]	partial	auto[0]	67	1			T122	4		T124	2		T365	2
auto[TlIntgErrData]	partial	auto[1]	68	1			T124	1		T129	3		T365	2
auto[TlIntgErrData]	full_word	auto[0]	5	1			T129	1		T372	1		T373	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T122	1		T366	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	54	1			T122	3		T124	2		T129	1
auto[TlIntgErrBoth]	partial	auto[1]	77	1			T122	3		T124	8		T129	1
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T365	1		T163	1		T373	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T129	1		T372	1		T370	1