Unified Coverage Report :: Module :: prim_generic_ram_1r1w

Module : prim_generic_ram_1r1w

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T15
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_ram_1r1w

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	164177116	568195	0	0
gen_wmask[1].MaskCheckPortA_A	164177116	568195	0	0
gen_wmask[2].MaskCheckPortA_A	164177116	568195	0	0
gen_wmask[3].MaskCheckPortA_A	164177116	568195	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164177116	568195	0	0
T3	615550	832	0	0
T4	142668	2112	0	0
T5	114656	832	0	0
T8	198722	832	0	0
T9	28340	832	0	0
T15	9504	109	0	0
T16	580642	6013	0	0
T17	31416	147	0	0
T18	6147	122	0	0
T19	228952	0	0	0
T21	119362	4405	0	0
T23	912	41	0	0
T63	0	4201	0	0
T64	0	95	0	0
T65	0	94	0	0
T66	0	1416	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164177116	568195	0	0
T3	615550	832	0	0
T4	142668	2112	0	0
T5	114656	832	0	0
T8	198722	832	0	0
T9	28340	832	0	0
T15	9504	109	0	0
T16	580642	6013	0	0
T17	31416	147	0	0
T18	6147	122	0	0
T19	228952	0	0	0
T21	119362	4405	0	0
T23	912	41	0	0
T63	0	4201	0	0
T64	0	95	0	0
T65	0	94	0	0
T66	0	1416	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164177116	568195	0	0
T3	615550	832	0	0
T4	142668	2112	0	0
T5	114656	832	0	0
T8	198722	832	0	0
T9	28340	832	0	0
T15	9504	109	0	0
T16	580642	6013	0	0
T17	31416	147	0	0
T18	6147	122	0	0
T19	228952	0	0	0
T21	119362	4405	0	0
T23	912	41	0	0
T63	0	4201	0	0
T64	0	95	0	0
T65	0	94	0	0
T66	0	1416	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164177116	568195	0	0
T3	615550	832	0	0
T4	142668	2112	0	0
T5	114656	832	0	0
T8	198722	832	0	0
T9	28340	832	0	0
T15	9504	109	0	0
T16	580642	6013	0	0
T17	31416	147	0	0
T18	6147	122	0	0
T19	228952	0	0	0
T21	119362	4405	0	0
T23	912	41	0	0
T63	0	4201	0	0
T64	0	95	0	0
T65	0	94	0	0
T66	0	1416	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			==> MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T15
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	124220062	416957	0	0
gen_wmask[1].MaskCheckPortA_A	124220062	416957	0	0
gen_wmask[2].MaskCheckPortA_A	124220062	416957	0	0
gen_wmask[3].MaskCheckPortA_A	124220062	416957	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124220062	416957	0	0
T3	615550	832	0	0
T4	142668	2112	0	0
T5	60936	832	0	0
T8	73585	832	0	0
T9	15892	832	0	0
T15	6675	47	0	0
T16	332268	1739	0	0
T17	28001	26	0	0
T18	3739	33	0	0
T19	103549	0	0	0
T21	0	1401	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124220062	416957	0	0
T3	615550	832	0	0
T4	142668	2112	0	0
T5	60936	832	0	0
T8	73585	832	0	0
T9	15892	832	0	0
T15	6675	47	0	0
T16	332268	1739	0	0
T17	28001	26	0	0
T18	3739	33	0	0
T19	103549	0	0	0
T21	0	1401	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124220062	416957	0	0
T3	615550	832	0	0
T4	142668	2112	0	0
T5	60936	832	0	0
T8	73585	832	0	0
T9	15892	832	0	0
T15	6675	47	0	0
T16	332268	1739	0	0
T17	28001	26	0	0
T18	3739	33	0	0
T19	103549	0	0	0
T21	0	1401	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124220062	416957	0	0
T3	615550	832	0	0
T4	142668	2112	0	0
T5	60936	832	0	0
T8	73585	832	0	0
T9	15892	832	0	0
T15	6675	47	0	0
T16	332268	1739	0	0
T17	28001	26	0	0
T18	3739	33	0	0
T19	103549	0	0	0
T21	0	1401	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	39957054	151238	0	0
gen_wmask[1].MaskCheckPortA_A	39957054	151238	0	0
gen_wmask[2].MaskCheckPortA_A	39957054	151238	0	0
gen_wmask[3].MaskCheckPortA_A	39957054	151238	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39957054	151238	0	0
T5	53720	0	0	0
T8	125137	0	0	0
T9	12448	0	0	0
T15	2829	62	0	0
T16	248374	4274	0	0
T17	3415	121	0	0
T18	2408	89	0	0
T19	125403	0	0	0
T21	119362	3004	0	0
T23	912	41	0	0
T63	0	4201	0	0
T64	0	95	0	0
T65	0	94	0	0
T66	0	1416	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39957054	151238	0	0
T5	53720	0	0	0
T8	125137	0	0	0
T9	12448	0	0	0
T15	2829	62	0	0
T16	248374	4274	0	0
T17	3415	121	0	0
T18	2408	89	0	0
T19	125403	0	0	0
T21	119362	3004	0	0
T23	912	41	0	0
T63	0	4201	0	0
T64	0	95	0	0
T65	0	94	0	0
T66	0	1416	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39957054	151238	0	0
T5	53720	0	0	0
T8	125137	0	0	0
T9	12448	0	0	0
T15	2829	62	0	0
T16	248374	4274	0	0
T17	3415	121	0	0
T18	2408	89	0	0
T19	125403	0	0	0
T21	119362	3004	0	0
T23	912	41	0	0
T63	0	4201	0	0
T64	0	95	0	0
T65	0	94	0	0
T66	0	1416	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39957054	151238	0	0
T5	53720	0	0	0
T8	125137	0	0	0
T9	12448	0	0	0
T15	2829	62	0	0
T16	248374	4274	0	0
T17	3415	121	0	0
T18	2408	89	0	0
T19	125403	0	0	0
T21	119362	3004	0	0
T23	912	41	0	0
T63	0	4201	0	0
T64	0	95	0	0
T65	0	94	0	0
T66	0	1416	0	0