Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	126461826	2865122	0	0
DepthKnown_A	126461826	126357728	0	0
RvalidKnown_A	126461826	126357728	0	0
WreadyKnown_A	126461826	126357728	0	0
gen_passthru_fifo.paramCheckPass	850	850	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126461826	2865122	0	0
T1	3269	41	0	0
T2	12049	84	0	0
T3	615550	83	0	0
T4	142668	4544	0	0
T5	60936	1758	0	0
T8	73585	2405	0	0
T15	6675	1184	0	0
T16	332268	8838	0	0
T17	28001	1842	0	0
T18	3739	225	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126461826	126357728	0	0
T1	3269	3178	0	0
T2	12049	11964	0	0
T3	615550	615499	0	0
T4	142668	142580	0	0
T5	60936	60850	0	0
T8	73585	73505	0	0
T15	6675	6612	0	0
T16	332268	332169	0	0
T17	28001	27910	0	0
T18	3739	3682	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126461826	126357728	0	0
T1	3269	3178	0	0
T2	12049	11964	0	0
T3	615550	615499	0	0
T4	142668	142580	0	0
T5	60936	60850	0	0
T8	73585	73505	0	0
T15	6675	6612	0	0
T16	332268	332169	0	0
T17	28001	27910	0	0
T18	3739	3682	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126461826	126357728	0	0
T1	3269	3178	0	0
T2	12049	11964	0	0
T3	615550	615499	0	0
T4	142668	142580	0	0
T5	60936	60850	0	0
T8	73585	73505	0	0
T15	6675	6612	0	0
T16	332268	332169	0	0
T17	28001	27910	0	0
T18	3739	3682	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	850	850	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	126461826	5250520	0	0
DepthKnown_A	126461826	126357728	0	0
RvalidKnown_A	126461826	126357728	0	0
WreadyKnown_A	126461826	126357728	0	0
gen_passthru_fifo.paramCheckPass	850	850	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126461826	5250520	0	0
T1	3269	190	0	0
T2	12049	84	0	0
T3	615550	83	0	0
T4	142668	19487	0	0
T5	60936	1757	0	0
T8	73585	10393	0	0
T15	6675	1184	0	0
T16	332268	8807	0	0
T17	28001	1842	0	0
T18	3739	225	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126461826	126357728	0	0
T1	3269	3178	0	0
T2	12049	11964	0	0
T3	615550	615499	0	0
T4	142668	142580	0	0
T5	60936	60850	0	0
T8	73585	73505	0	0
T15	6675	6612	0	0
T16	332268	332169	0	0
T17	28001	27910	0	0
T18	3739	3682	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126461826	126357728	0	0
T1	3269	3178	0	0
T2	12049	11964	0	0
T3	615550	615499	0	0
T4	142668	142580	0	0
T5	60936	60850	0	0
T8	73585	73505	0	0
T15	6675	6612	0	0
T16	332268	332169	0	0
T17	28001	27910	0	0
T18	3739	3682	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126461826	126357728	0	0
T1	3269	3178	0	0
T2	12049	11964	0	0
T3	615550	615499	0	0
T4	142668	142580	0	0
T5	60936	60850	0	0
T8	73585	73505	0	0
T15	6675	6612	0	0
T16	332268	332169	0	0
T17	28001	27910	0	0
T18	3739	3682	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	850	850	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0