Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126461826 |
3269 |
0 |
0 |
T39 |
9364 |
6 |
0 |
0 |
T40 |
13293 |
211 |
0 |
0 |
T41 |
2601 |
81 |
0 |
0 |
T122 |
19623 |
2 |
0 |
0 |
T123 |
5579 |
225 |
0 |
0 |
T130 |
12257 |
6 |
0 |
0 |
T136 |
4627 |
7 |
0 |
0 |
T140 |
3281 |
5 |
0 |
0 |
T141 |
2228 |
5 |
0 |
0 |
T142 |
4791 |
3 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126461826 |
1931 |
0 |
0 |
T39 |
9364 |
4 |
0 |
0 |
T42 |
4208 |
10 |
0 |
0 |
T149 |
91256 |
189 |
0 |
0 |
T151 |
7336 |
9 |
0 |
0 |
T152 |
269923 |
620 |
0 |
0 |
T159 |
10135 |
22 |
0 |
0 |
T160 |
17360 |
15 |
0 |
0 |
T161 |
5525 |
9 |
0 |
0 |
T162 |
7778 |
44 |
0 |
0 |
T163 |
98728 |
103 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126461826 |
1977 |
0 |
0 |
T39 |
9364 |
11 |
0 |
0 |
T42 |
4208 |
3 |
0 |
0 |
T149 |
91256 |
181 |
0 |
0 |
T151 |
7336 |
12 |
0 |
0 |
T152 |
269923 |
585 |
0 |
0 |
T159 |
10135 |
1 |
0 |
0 |
T160 |
17360 |
71 |
0 |
0 |
T161 |
5525 |
9 |
0 |
0 |
T162 |
7778 |
4 |
0 |
0 |
T163 |
98728 |
111 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126461826 |
2414 |
0 |
0 |
T39 |
9364 |
2 |
0 |
0 |
T42 |
4208 |
7 |
0 |
0 |
T149 |
91256 |
200 |
0 |
0 |
T151 |
7336 |
15 |
0 |
0 |
T152 |
269923 |
657 |
0 |
0 |
T159 |
10135 |
19 |
0 |
0 |
T160 |
17360 |
52 |
0 |
0 |
T161 |
5525 |
16 |
0 |
0 |
T162 |
7778 |
3 |
0 |
0 |
T163 |
98728 |
261 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126461826 |
6532 |
0 |
0 |
T39 |
9364 |
6 |
0 |
0 |
T42 |
4208 |
14 |
0 |
0 |
T149 |
91256 |
228 |
0 |
0 |
T151 |
7336 |
128 |
0 |
0 |
T152 |
269923 |
641 |
0 |
0 |
T159 |
10135 |
114 |
0 |
0 |
T160 |
17360 |
30 |
0 |
0 |
T161 |
5525 |
3 |
0 |
0 |
T162 |
7778 |
14 |
0 |
0 |
T163 |
98728 |
1991 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126461826 |
6844 |
0 |
0 |
T39 |
9364 |
91 |
0 |
0 |
T42 |
4208 |
10 |
0 |
0 |
T149 |
91256 |
230 |
0 |
0 |
T151 |
7336 |
132 |
0 |
0 |
T152 |
269923 |
614 |
0 |
0 |
T159 |
10135 |
6 |
0 |
0 |
T160 |
17360 |
54 |
0 |
0 |
T161 |
5525 |
4 |
0 |
0 |
T162 |
7778 |
19 |
0 |
0 |
T163 |
98728 |
1950 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126461826 |
6822 |
0 |
0 |
T39 |
9364 |
72 |
0 |
0 |
T42 |
4208 |
7 |
0 |
0 |
T132 |
12378 |
5 |
0 |
0 |
T149 |
91256 |
260 |
0 |
0 |
T151 |
7336 |
105 |
0 |
0 |
T159 |
10135 |
114 |
0 |
0 |
T160 |
17360 |
25 |
0 |
0 |
T161 |
5525 |
4 |
0 |
0 |
T162 |
7778 |
12 |
0 |
0 |
T163 |
98728 |
1601 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126461826 |
7196 |
0 |
0 |
T39 |
9364 |
170 |
0 |
0 |
T42 |
4208 |
22 |
0 |
0 |
T149 |
91256 |
235 |
0 |
0 |
T151 |
7336 |
8 |
0 |
0 |
T152 |
269923 |
661 |
0 |
0 |
T159 |
10135 |
132 |
0 |
0 |
T160 |
17360 |
6 |
0 |
0 |
T161 |
5525 |
141 |
0 |
0 |
T162 |
7778 |
36 |
0 |
0 |
T163 |
98728 |
1865 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126461826 |
8032 |
0 |
0 |
T39 |
9364 |
90 |
0 |
0 |
T42 |
4208 |
4 |
0 |
0 |
T132 |
12378 |
2 |
0 |
0 |
T149 |
91256 |
244 |
0 |
0 |
T151 |
7336 |
120 |
0 |
0 |
T159 |
10135 |
242 |
0 |
0 |
T160 |
17360 |
57 |
0 |
0 |
T161 |
5525 |
119 |
0 |
0 |
T162 |
7778 |
34 |
0 |
0 |
T163 |
98728 |
2151 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126461826 |
7567 |
0 |
0 |
T39 |
9364 |
45 |
0 |
0 |
T42 |
4208 |
21 |
0 |
0 |
T149 |
91256 |
231 |
0 |
0 |
T151 |
7336 |
142 |
0 |
0 |
T152 |
269923 |
665 |
0 |
0 |
T159 |
10135 |
147 |
0 |
0 |
T160 |
17360 |
23 |
0 |
0 |
T161 |
5525 |
126 |
0 |
0 |
T162 |
7778 |
51 |
0 |
0 |
T163 |
98728 |
1759 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126461826 |
6965 |
0 |
0 |
T39 |
9364 |
6 |
0 |
0 |
T42 |
4208 |
9 |
0 |
0 |
T149 |
91256 |
220 |
0 |
0 |
T151 |
7336 |
135 |
0 |
0 |
T152 |
269923 |
668 |
0 |
0 |
T159 |
10135 |
112 |
0 |
0 |
T160 |
17360 |
34 |
0 |
0 |
T161 |
5525 |
3 |
0 |
0 |
T162 |
7778 |
23 |
0 |
0 |
T163 |
98728 |
1201 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126461826 |
7295 |
0 |
0 |
T39 |
9364 |
14 |
0 |
0 |
T42 |
4208 |
6 |
0 |
0 |
T131 |
20921 |
1 |
0 |
0 |
T149 |
91256 |
268 |
0 |
0 |
T151 |
7336 |
257 |
0 |
0 |
T159 |
10135 |
234 |
0 |
0 |
T160 |
17360 |
30 |
0 |
0 |
T161 |
5525 |
3 |
0 |
0 |
T162 |
7778 |
5 |
0 |
0 |
T163 |
98728 |
2184 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126461826 |
3908 |
0 |
0 |
T39 |
9364 |
6 |
0 |
0 |
T42 |
4208 |
11 |
0 |
0 |
T149 |
91256 |
242 |
0 |
0 |
T151 |
7336 |
41 |
0 |
0 |
T152 |
269923 |
646 |
0 |
0 |
T159 |
10135 |
50 |
0 |
0 |
T160 |
17360 |
42 |
0 |
0 |
T161 |
5525 |
59 |
0 |
0 |
T162 |
7778 |
2 |
0 |
0 |
T163 |
98728 |
731 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126461826 |
3955 |
0 |
0 |
T39 |
9364 |
36 |
0 |
0 |
T42 |
4208 |
2 |
0 |
0 |
T149 |
91256 |
233 |
0 |
0 |
T151 |
7336 |
120 |
0 |
0 |
T152 |
269923 |
625 |
0 |
0 |
T159 |
10135 |
10 |
0 |
0 |
T160 |
17360 |
14 |
0 |
0 |
T161 |
5525 |
8 |
0 |
0 |
T162 |
7778 |
37 |
0 |
0 |
T163 |
98728 |
800 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126461826 |
3971 |
0 |
0 |
T39 |
9364 |
42 |
0 |
0 |
T40 |
13293 |
7 |
0 |
0 |
T42 |
4208 |
9 |
0 |
0 |
T132 |
12378 |
4 |
0 |
0 |
T149 |
91256 |
260 |
0 |
0 |
T151 |
7336 |
53 |
0 |
0 |
T159 |
10135 |
30 |
0 |
0 |
T160 |
17360 |
36 |
0 |
0 |
T161 |
5525 |
40 |
0 |
0 |
T163 |
98728 |
506 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126461826 |
4131 |
0 |
0 |
T39 |
9364 |
74 |
0 |
0 |
T42 |
4208 |
5 |
0 |
0 |
T149 |
91256 |
307 |
0 |
0 |
T151 |
7336 |
95 |
0 |
0 |
T152 |
269923 |
677 |
0 |
0 |
T159 |
10135 |
46 |
0 |
0 |
T160 |
17360 |
61 |
0 |
0 |
T161 |
5525 |
49 |
0 |
0 |
T162 |
7778 |
30 |
0 |
0 |
T163 |
98728 |
630 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126461826 |
4022 |
0 |
0 |
T39 |
9364 |
32 |
0 |
0 |
T42 |
4208 |
7 |
0 |
0 |
T149 |
91256 |
242 |
0 |
0 |
T151 |
7336 |
39 |
0 |
0 |
T152 |
269923 |
663 |
0 |
0 |
T159 |
10135 |
1 |
0 |
0 |
T160 |
17360 |
45 |
0 |
0 |
T161 |
5525 |
71 |
0 |
0 |
T162 |
7778 |
5 |
0 |
0 |
T163 |
98728 |
815 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126461826 |
3665 |
0 |
0 |
T39 |
9364 |
11 |
0 |
0 |
T132 |
12378 |
1 |
0 |
0 |
T149 |
91256 |
202 |
0 |
0 |
T151 |
7336 |
4 |
0 |
0 |
T152 |
269923 |
627 |
0 |
0 |
T159 |
10135 |
52 |
0 |
0 |
T160 |
17360 |
16 |
0 |
0 |
T161 |
5525 |
9 |
0 |
0 |
T162 |
7778 |
18 |
0 |
0 |
T163 |
98728 |
704 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126461826 |
4183 |
0 |
0 |
T39 |
9364 |
28 |
0 |
0 |
T42 |
4208 |
1 |
0 |
0 |
T149 |
91256 |
229 |
0 |
0 |
T151 |
7336 |
47 |
0 |
0 |
T152 |
269923 |
733 |
0 |
0 |
T159 |
10135 |
72 |
0 |
0 |
T160 |
17360 |
30 |
0 |
0 |
T161 |
5525 |
9 |
0 |
0 |
T162 |
7778 |
6 |
0 |
0 |
T163 |
98728 |
689 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126461826 |
4135 |
0 |
0 |
T39 |
9364 |
47 |
0 |
0 |
T42 |
4208 |
3 |
0 |
0 |
T149 |
91256 |
203 |
0 |
0 |
T151 |
7336 |
1 |
0 |
0 |
T152 |
269923 |
654 |
0 |
0 |
T159 |
10135 |
19 |
0 |
0 |
T160 |
17360 |
18 |
0 |
0 |
T161 |
5525 |
51 |
0 |
0 |
T162 |
7778 |
41 |
0 |
0 |
T163 |
98728 |
956 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126461826 |
4221 |
0 |
0 |
T39 |
9364 |
32 |
0 |
0 |
T42 |
4208 |
6 |
0 |
0 |
T149 |
91256 |
212 |
0 |
0 |
T151 |
7336 |
72 |
0 |
0 |
T152 |
269923 |
716 |
0 |
0 |
T159 |
10135 |
112 |
0 |
0 |
T160 |
17360 |
58 |
0 |
0 |
T161 |
5525 |
54 |
0 |
0 |
T162 |
7778 |
11 |
0 |
0 |
T163 |
98728 |
643 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126461826 |
4135 |
0 |
0 |
T39 |
9364 |
52 |
0 |
0 |
T42 |
4208 |
10 |
0 |
0 |
T149 |
91256 |
198 |
0 |
0 |
T151 |
7336 |
82 |
0 |
0 |
T159 |
10135 |
62 |
0 |
0 |
T160 |
17360 |
22 |
0 |
0 |
T161 |
5525 |
7 |
0 |
0 |
T162 |
7778 |
25 |
0 |
0 |
T163 |
98728 |
918 |
0 |
0 |
T164 |
5633 |
4 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126461826 |
3967 |
0 |
0 |
T39 |
9364 |
30 |
0 |
0 |
T149 |
91256 |
182 |
0 |
0 |
T151 |
7336 |
7 |
0 |
0 |
T152 |
269923 |
711 |
0 |
0 |
T159 |
10135 |
31 |
0 |
0 |
T160 |
17360 |
62 |
0 |
0 |
T161 |
5525 |
49 |
0 |
0 |
T162 |
7778 |
65 |
0 |
0 |
T163 |
98728 |
795 |
0 |
0 |
T165 |
6356 |
35 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126461826 |
3928 |
0 |
0 |
T39 |
9364 |
7 |
0 |
0 |
T42 |
4208 |
13 |
0 |
0 |
T149 |
91256 |
200 |
0 |
0 |
T151 |
7336 |
9 |
0 |
0 |
T152 |
269923 |
650 |
0 |
0 |
T159 |
10135 |
114 |
0 |
0 |
T160 |
17360 |
31 |
0 |
0 |
T161 |
5525 |
2 |
0 |
0 |
T162 |
7778 |
14 |
0 |
0 |
T163 |
98728 |
782 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126461826 |
3693 |
0 |
0 |
T39 |
9364 |
9 |
0 |
0 |
T42 |
4208 |
7 |
0 |
0 |
T149 |
91256 |
217 |
0 |
0 |
T151 |
7336 |
49 |
0 |
0 |
T152 |
269923 |
670 |
0 |
0 |
T159 |
10135 |
63 |
0 |
0 |
T160 |
17360 |
39 |
0 |
0 |
T161 |
5525 |
6 |
0 |
0 |
T162 |
7778 |
41 |
0 |
0 |
T163 |
98728 |
690 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126461826 |
4406 |
0 |
0 |
T39 |
9364 |
33 |
0 |
0 |
T42 |
4208 |
7 |
0 |
0 |
T149 |
91256 |
231 |
0 |
0 |
T151 |
7336 |
51 |
0 |
0 |
T152 |
269923 |
687 |
0 |
0 |
T159 |
10135 |
99 |
0 |
0 |
T160 |
17360 |
34 |
0 |
0 |
T161 |
5525 |
47 |
0 |
0 |
T162 |
7778 |
3 |
0 |
0 |
T163 |
98728 |
896 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126461826 |
3826 |
0 |
0 |
T39 |
9364 |
37 |
0 |
0 |
T42 |
4208 |
2 |
0 |
0 |
T149 |
91256 |
235 |
0 |
0 |
T151 |
7336 |
61 |
0 |
0 |
T152 |
269923 |
621 |
0 |
0 |
T159 |
10135 |
25 |
0 |
0 |
T160 |
17360 |
18 |
0 |
0 |
T161 |
5525 |
5 |
0 |
0 |
T162 |
7778 |
5 |
0 |
0 |
T163 |
98728 |
939 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126461826 |
3784 |
0 |
0 |
T39 |
9364 |
8 |
0 |
0 |
T40 |
13293 |
5 |
0 |
0 |
T42 |
4208 |
5 |
0 |
0 |
T149 |
91256 |
239 |
0 |
0 |
T151 |
7336 |
41 |
0 |
0 |
T159 |
10135 |
71 |
0 |
0 |
T160 |
17360 |
24 |
0 |
0 |
T161 |
5525 |
7 |
0 |
0 |
T162 |
7778 |
19 |
0 |
0 |
T163 |
98728 |
698 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126461826 |
3825 |
0 |
0 |
T39 |
9364 |
14 |
0 |
0 |
T42 |
4208 |
7 |
0 |
0 |
T149 |
91256 |
215 |
0 |
0 |
T151 |
7336 |
46 |
0 |
0 |
T152 |
269923 |
629 |
0 |
0 |
T159 |
10135 |
97 |
0 |
0 |
T160 |
17360 |
66 |
0 |
0 |
T161 |
5525 |
41 |
0 |
0 |
T163 |
98728 |
788 |
0 |
0 |
T165 |
6356 |
12 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126461826 |
4431 |
0 |
0 |
T39 |
9364 |
69 |
0 |
0 |
T137 |
14963 |
1 |
0 |
0 |
T149 |
91256 |
235 |
0 |
0 |
T151 |
7336 |
39 |
0 |
0 |
T152 |
269923 |
627 |
0 |
0 |
T159 |
10135 |
42 |
0 |
0 |
T160 |
17360 |
40 |
0 |
0 |
T161 |
5525 |
82 |
0 |
0 |
T162 |
7778 |
8 |
0 |
0 |
T163 |
98728 |
928 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126461826 |
4449 |
0 |
0 |
T39 |
9364 |
43 |
0 |
0 |
T42 |
4208 |
9 |
0 |
0 |
T149 |
91256 |
233 |
0 |
0 |
T151 |
7336 |
47 |
0 |
0 |
T152 |
269923 |
708 |
0 |
0 |
T159 |
10135 |
111 |
0 |
0 |
T160 |
17360 |
45 |
0 |
0 |
T161 |
5525 |
6 |
0 |
0 |
T162 |
7778 |
29 |
0 |
0 |
T163 |
98728 |
653 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126461826 |
3925 |
0 |
0 |
T39 |
9364 |
38 |
0 |
0 |
T42 |
4208 |
14 |
0 |
0 |
T131 |
20921 |
4 |
0 |
0 |
T132 |
12378 |
7 |
0 |
0 |
T149 |
91256 |
237 |
0 |
0 |
T151 |
7336 |
96 |
0 |
0 |
T159 |
10135 |
21 |
0 |
0 |
T160 |
17360 |
11 |
0 |
0 |
T161 |
5525 |
17 |
0 |
0 |
T162 |
7778 |
32 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126461826 |
4283 |
0 |
0 |
T39 |
9364 |
30 |
0 |
0 |
T42 |
4208 |
4 |
0 |
0 |
T149 |
91256 |
222 |
0 |
0 |
T151 |
7336 |
101 |
0 |
0 |
T152 |
269923 |
612 |
0 |
0 |
T159 |
10135 |
85 |
0 |
0 |
T160 |
17360 |
47 |
0 |
0 |
T161 |
5525 |
12 |
0 |
0 |
T162 |
7778 |
35 |
0 |
0 |
T163 |
98728 |
938 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126461826 |
3637 |
0 |
0 |
T39 |
9364 |
22 |
0 |
0 |
T137 |
14963 |
4 |
0 |
0 |
T149 |
91256 |
244 |
0 |
0 |
T151 |
7336 |
14 |
0 |
0 |
T152 |
269923 |
691 |
0 |
0 |
T159 |
10135 |
15 |
0 |
0 |
T160 |
17360 |
46 |
0 |
0 |
T161 |
5525 |
12 |
0 |
0 |
T162 |
7778 |
17 |
0 |
0 |
T163 |
98728 |
714 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126461826 |
3657 |
0 |
0 |
T39 |
9364 |
25 |
0 |
0 |
T42 |
4208 |
18 |
0 |
0 |
T149 |
91256 |
202 |
0 |
0 |
T151 |
7336 |
15 |
0 |
0 |
T152 |
269923 |
678 |
0 |
0 |
T159 |
10135 |
18 |
0 |
0 |
T160 |
17360 |
24 |
0 |
0 |
T161 |
5525 |
6 |
0 |
0 |
T162 |
7778 |
8 |
0 |
0 |
T163 |
98728 |
636 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126461826 |
4097 |
0 |
0 |
T39 |
9364 |
31 |
0 |
0 |
T42 |
4208 |
5 |
0 |
0 |
T149 |
91256 |
233 |
0 |
0 |
T151 |
7336 |
105 |
0 |
0 |
T152 |
269923 |
698 |
0 |
0 |
T159 |
10135 |
65 |
0 |
0 |
T160 |
17360 |
41 |
0 |
0 |
T161 |
5525 |
65 |
0 |
0 |
T162 |
7778 |
20 |
0 |
0 |
T163 |
98728 |
802 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126461826 |
2266 |
0 |
0 |
T39 |
9364 |
14 |
0 |
0 |
T42 |
4208 |
2 |
0 |
0 |
T149 |
91256 |
230 |
0 |
0 |
T151 |
7336 |
11 |
0 |
0 |
T152 |
269923 |
744 |
0 |
0 |
T159 |
10135 |
31 |
0 |
0 |
T160 |
17360 |
16 |
0 |
0 |
T161 |
5525 |
13 |
0 |
0 |
T162 |
7778 |
21 |
0 |
0 |
T163 |
98728 |
191 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126461826 |
2315 |
0 |
0 |
T39 |
9364 |
9 |
0 |
0 |
T42 |
4208 |
7 |
0 |
0 |
T149 |
91256 |
257 |
0 |
0 |
T151 |
7336 |
11 |
0 |
0 |
T152 |
269923 |
701 |
0 |
0 |
T159 |
10135 |
19 |
0 |
0 |
T160 |
17360 |
3 |
0 |
0 |
T161 |
5525 |
3 |
0 |
0 |
T162 |
7778 |
24 |
0 |
0 |
T163 |
98728 |
177 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126461826 |
2229 |
0 |
0 |
T39 |
9364 |
15 |
0 |
0 |
T42 |
4208 |
11 |
0 |
0 |
T149 |
91256 |
217 |
0 |
0 |
T151 |
7336 |
7 |
0 |
0 |
T152 |
269923 |
695 |
0 |
0 |
T159 |
10135 |
13 |
0 |
0 |
T160 |
17360 |
34 |
0 |
0 |
T161 |
5525 |
6 |
0 |
0 |
T162 |
7778 |
15 |
0 |
0 |
T163 |
98728 |
187 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126461826 |
2275 |
0 |
0 |
T39 |
9364 |
4 |
0 |
0 |
T42 |
4208 |
11 |
0 |
0 |
T149 |
91256 |
212 |
0 |
0 |
T151 |
7336 |
14 |
0 |
0 |
T152 |
269923 |
667 |
0 |
0 |
T159 |
10135 |
16 |
0 |
0 |
T160 |
17360 |
50 |
0 |
0 |
T161 |
5525 |
12 |
0 |
0 |
T162 |
7778 |
62 |
0 |
0 |
T163 |
98728 |
178 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126461826 |
2586 |
0 |
0 |
T39 |
9364 |
16 |
0 |
0 |
T40 |
13293 |
8 |
0 |
0 |
T149 |
91256 |
222 |
0 |
0 |
T151 |
7336 |
16 |
0 |
0 |
T152 |
269923 |
714 |
0 |
0 |
T159 |
10135 |
21 |
0 |
0 |
T160 |
17360 |
36 |
0 |
0 |
T161 |
5525 |
23 |
0 |
0 |
T162 |
7778 |
11 |
0 |
0 |
T163 |
98728 |
223 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126461826 |
3927 |
0 |
0 |
T39 |
0 |
12 |
0 |
0 |
T42 |
0 |
11 |
0 |
0 |
T44 |
4005 |
26 |
0 |
0 |
T114 |
215700 |
0 |
0 |
0 |
T149 |
0 |
199 |
0 |
0 |
T159 |
0 |
50 |
0 |
0 |
T166 |
0 |
12 |
0 |
0 |
T167 |
0 |
23 |
0 |
0 |
T168 |
0 |
22 |
0 |
0 |
T169 |
0 |
8 |
0 |
0 |
T170 |
0 |
13 |
0 |
0 |
T171 |
223303 |
0 |
0 |
0 |
T172 |
85679 |
0 |
0 |
0 |
T173 |
106338 |
0 |
0 |
0 |
T174 |
427565 |
0 |
0 |
0 |
T175 |
1015 |
0 |
0 |
0 |
T176 |
57480 |
0 |
0 |
0 |
T177 |
116573 |
0 |
0 |
0 |
T178 |
175050 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126461826 |
2188 |
0 |
0 |
T39 |
9364 |
12 |
0 |
0 |
T42 |
4208 |
14 |
0 |
0 |
T149 |
91256 |
196 |
0 |
0 |
T151 |
7336 |
2 |
0 |
0 |
T152 |
269923 |
659 |
0 |
0 |
T159 |
10135 |
35 |
0 |
0 |
T160 |
17360 |
27 |
0 |
0 |
T161 |
5525 |
7 |
0 |
0 |
T162 |
7778 |
14 |
0 |
0 |
T163 |
98728 |
171 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126461826 |
2219 |
0 |
0 |
T39 |
9364 |
8 |
0 |
0 |
T149 |
91256 |
218 |
0 |
0 |
T151 |
7336 |
5 |
0 |
0 |
T152 |
269923 |
717 |
0 |
0 |
T159 |
10135 |
36 |
0 |
0 |
T160 |
17360 |
46 |
0 |
0 |
T161 |
5525 |
4 |
0 |
0 |
T162 |
7778 |
20 |
0 |
0 |
T163 |
98728 |
167 |
0 |
0 |
T165 |
6356 |
14 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126461826 |
2019 |
0 |
0 |
T39 |
9364 |
7 |
0 |
0 |
T42 |
4208 |
9 |
0 |
0 |
T149 |
91256 |
200 |
0 |
0 |
T151 |
7336 |
9 |
0 |
0 |
T152 |
269923 |
677 |
0 |
0 |
T159 |
10135 |
12 |
0 |
0 |
T160 |
17360 |
14 |
0 |
0 |
T161 |
5525 |
6 |
0 |
0 |
T162 |
7778 |
36 |
0 |
0 |
T163 |
98728 |
121 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126461826 |
1993 |
0 |
0 |
T149 |
91256 |
221 |
0 |
0 |
T151 |
7336 |
7 |
0 |
0 |
T152 |
269923 |
654 |
0 |
0 |
T159 |
10135 |
6 |
0 |
0 |
T160 |
17360 |
12 |
0 |
0 |
T161 |
5525 |
4 |
0 |
0 |
T162 |
7778 |
10 |
0 |
0 |
T163 |
98728 |
105 |
0 |
0 |
T165 |
6356 |
14 |
0 |
0 |
T179 |
36931 |
154 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126461826 |
2118 |
0 |
0 |
T39 |
9364 |
4 |
0 |
0 |
T42 |
4208 |
7 |
0 |
0 |
T149 |
91256 |
226 |
0 |
0 |
T151 |
7336 |
6 |
0 |
0 |
T152 |
269923 |
720 |
0 |
0 |
T159 |
10135 |
7 |
0 |
0 |
T160 |
17360 |
51 |
0 |
0 |
T161 |
5525 |
8 |
0 |
0 |
T162 |
7778 |
1 |
0 |
0 |
T163 |
98728 |
120 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126461826 |
2138 |
0 |
0 |
T39 |
9364 |
10 |
0 |
0 |
T42 |
4208 |
12 |
0 |
0 |
T149 |
91256 |
218 |
0 |
0 |
T151 |
7336 |
6 |
0 |
0 |
T152 |
269923 |
718 |
0 |
0 |
T159 |
10135 |
15 |
0 |
0 |
T160 |
17360 |
33 |
0 |
0 |
T161 |
5525 |
6 |
0 |
0 |
T162 |
7778 |
43 |
0 |
0 |
T163 |
98728 |
118 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126461826 |
2554 |
0 |
0 |
T39 |
9364 |
9 |
0 |
0 |
T42 |
4208 |
14 |
0 |
0 |
T131 |
20921 |
1 |
0 |
0 |
T149 |
91256 |
211 |
0 |
0 |
T151 |
7336 |
14 |
0 |
0 |
T159 |
10135 |
27 |
0 |
0 |
T160 |
17360 |
41 |
0 |
0 |
T161 |
5525 |
16 |
0 |
0 |
T162 |
7778 |
3 |
0 |
0 |
T163 |
98728 |
300 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126461826 |
2028 |
0 |
0 |
T39 |
9364 |
7 |
0 |
0 |
T42 |
4208 |
5 |
0 |
0 |
T131 |
20921 |
5 |
0 |
0 |
T149 |
91256 |
201 |
0 |
0 |
T151 |
7336 |
10 |
0 |
0 |
T159 |
10135 |
5 |
0 |
0 |
T160 |
17360 |
30 |
0 |
0 |
T161 |
5525 |
15 |
0 |
0 |
T162 |
7778 |
31 |
0 |
0 |
T163 |
98728 |
92 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126461826 |
2744 |
0 |
0 |
T39 |
9364 |
1 |
0 |
0 |
T42 |
4208 |
11 |
0 |
0 |
T149 |
91256 |
252 |
0 |
0 |
T151 |
7336 |
23 |
0 |
0 |
T152 |
269923 |
699 |
0 |
0 |
T159 |
10135 |
33 |
0 |
0 |
T160 |
17360 |
17 |
0 |
0 |
T161 |
5525 |
29 |
0 |
0 |
T162 |
7778 |
41 |
0 |
0 |
T163 |
98728 |
279 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126461826 |
2182 |
0 |
0 |
T39 |
9364 |
13 |
0 |
0 |
T42 |
4208 |
3 |
0 |
0 |
T149 |
91256 |
250 |
0 |
0 |
T151 |
7336 |
6 |
0 |
0 |
T152 |
269923 |
661 |
0 |
0 |
T159 |
10135 |
19 |
0 |
0 |
T160 |
17360 |
20 |
0 |
0 |
T161 |
5525 |
5 |
0 |
0 |
T162 |
7778 |
14 |
0 |
0 |
T163 |
98728 |
145 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126461826 |
1992 |
0 |
0 |
T39 |
9364 |
11 |
0 |
0 |
T149 |
91256 |
232 |
0 |
0 |
T151 |
7336 |
14 |
0 |
0 |
T152 |
269923 |
692 |
0 |
0 |
T159 |
10135 |
5 |
0 |
0 |
T160 |
17360 |
39 |
0 |
0 |
T161 |
5525 |
1 |
0 |
0 |
T162 |
7778 |
3 |
0 |
0 |
T163 |
98728 |
101 |
0 |
0 |
T179 |
36931 |
129 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126461826 |
2293 |
0 |
0 |
T39 |
9364 |
17 |
0 |
0 |
T42 |
4208 |
4 |
0 |
0 |
T149 |
91256 |
279 |
0 |
0 |
T152 |
269923 |
703 |
0 |
0 |
T159 |
10135 |
12 |
0 |
0 |
T160 |
17360 |
29 |
0 |
0 |
T161 |
5525 |
12 |
0 |
0 |
T162 |
7778 |
27 |
0 |
0 |
T163 |
98728 |
140 |
0 |
0 |
T165 |
6356 |
30 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126461826 |
2032 |
0 |
0 |
T39 |
9364 |
12 |
0 |
0 |
T42 |
4208 |
10 |
0 |
0 |
T149 |
91256 |
235 |
0 |
0 |
T152 |
269923 |
602 |
0 |
0 |
T159 |
10135 |
24 |
0 |
0 |
T160 |
17360 |
55 |
0 |
0 |
T161 |
5525 |
3 |
0 |
0 |
T162 |
7778 |
35 |
0 |
0 |
T163 |
98728 |
110 |
0 |
0 |
T165 |
6356 |
24 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126461826 |
2032 |
0 |
0 |
T149 |
91256 |
189 |
0 |
0 |
T151 |
7336 |
11 |
0 |
0 |
T152 |
269923 |
702 |
0 |
0 |
T159 |
10135 |
14 |
0 |
0 |
T160 |
17360 |
25 |
0 |
0 |
T161 |
5525 |
4 |
0 |
0 |
T162 |
7778 |
31 |
0 |
0 |
T163 |
98728 |
122 |
0 |
0 |
T165 |
6356 |
19 |
0 |
0 |
T179 |
36931 |
114 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126461826 |
2064 |
0 |
0 |
T39 |
9364 |
12 |
0 |
0 |
T42 |
4208 |
5 |
0 |
0 |
T137 |
14963 |
4 |
0 |
0 |
T149 |
91256 |
224 |
0 |
0 |
T151 |
7336 |
8 |
0 |
0 |
T159 |
10135 |
23 |
0 |
0 |
T160 |
17360 |
15 |
0 |
0 |
T161 |
5525 |
18 |
0 |
0 |
T162 |
7778 |
7 |
0 |
0 |
T163 |
98728 |
107 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126461826 |
2139 |
0 |
0 |
T39 |
9364 |
17 |
0 |
0 |
T42 |
4208 |
4 |
0 |
0 |
T132 |
12378 |
3 |
0 |
0 |
T149 |
91256 |
230 |
0 |
0 |
T151 |
7336 |
6 |
0 |
0 |
T159 |
10135 |
11 |
0 |
0 |
T160 |
17360 |
4 |
0 |
0 |
T161 |
5525 |
2 |
0 |
0 |
T162 |
7778 |
41 |
0 |
0 |
T163 |
98728 |
87 |
0 |
0 |