| T632 |
/workspace/coverage/default/12.spi_device_ram_cfg.696507048 |
|
|
Mar 31 01:24:20 PM PDT 24 |
Mar 31 01:24:21 PM PDT 24 |
42536669 ps |
| T326 |
/workspace/coverage/default/17.spi_device_pass_cmd_filtering.2050998137 |
|
|
Mar 31 01:24:36 PM PDT 24 |
Mar 31 01:24:54 PM PDT 24 |
8295124351 ps |
| T633 |
/workspace/coverage/default/22.spi_device_tpm_sts_read.3835540385 |
|
|
Mar 31 01:24:47 PM PDT 24 |
Mar 31 01:24:48 PM PDT 24 |
244251543 ps |
| T334 |
/workspace/coverage/default/12.spi_device_upload.4002577024 |
|
|
Mar 31 01:24:21 PM PDT 24 |
Mar 31 01:24:34 PM PDT 24 |
3152864616 ps |
| T634 |
/workspace/coverage/default/37.spi_device_csb_read.471083677 |
|
|
Mar 31 01:25:27 PM PDT 24 |
Mar 31 01:25:28 PM PDT 24 |
42307947 ps |
| T635 |
/workspace/coverage/default/0.spi_device_ram_cfg.1691076150 |
|
|
Mar 31 01:23:29 PM PDT 24 |
Mar 31 01:23:30 PM PDT 24 |
16535906 ps |
| T292 |
/workspace/coverage/default/32.spi_device_pass_addr_payload_swap.2431769478 |
|
|
Mar 31 01:25:21 PM PDT 24 |
Mar 31 01:26:01 PM PDT 24 |
14783533760 ps |
| T230 |
/workspace/coverage/default/9.spi_device_upload.1222778123 |
|
|
Mar 31 01:24:01 PM PDT 24 |
Mar 31 01:24:11 PM PDT 24 |
2373971595 ps |
| T327 |
/workspace/coverage/default/22.spi_device_pass_cmd_filtering.1165952807 |
|
|
Mar 31 01:24:48 PM PDT 24 |
Mar 31 01:24:51 PM PDT 24 |
2867770201 ps |
| T258 |
/workspace/coverage/default/16.spi_device_cfg_cmd.288277947 |
|
|
Mar 31 01:24:36 PM PDT 24 |
Mar 31 01:24:40 PM PDT 24 |
822399546 ps |
| T330 |
/workspace/coverage/default/33.spi_device_pass_cmd_filtering.537305465 |
|
|
Mar 31 01:25:23 PM PDT 24 |
Mar 31 01:26:01 PM PDT 24 |
11644659881 ps |
| T636 |
/workspace/coverage/default/13.spi_device_tpm_read_hw_reg.444008943 |
|
|
Mar 31 01:24:21 PM PDT 24 |
Mar 31 01:24:39 PM PDT 24 |
10189240635 ps |
| T637 |
/workspace/coverage/default/7.spi_device_alert_test.4022354832 |
|
|
Mar 31 01:23:54 PM PDT 24 |
Mar 31 01:23:55 PM PDT 24 |
65551331 ps |
| T127 |
/workspace/coverage/default/45.spi_device_intercept.393206025 |
|
|
Mar 31 01:25:52 PM PDT 24 |
Mar 31 01:26:06 PM PDT 24 |
6565287225 ps |
| T305 |
/workspace/coverage/default/25.spi_device_flash_mode.899054806 |
|
|
Mar 31 01:24:56 PM PDT 24 |
Mar 31 01:26:08 PM PDT 24 |
4760585009 ps |
| T638 |
/workspace/coverage/default/11.spi_device_tpm_all.3979835182 |
|
|
Mar 31 01:24:13 PM PDT 24 |
Mar 31 01:24:52 PM PDT 24 |
21935681981 ps |
| T321 |
/workspace/coverage/default/1.spi_device_intercept.2395590807 |
|
|
Mar 31 01:23:36 PM PDT 24 |
Mar 31 01:23:41 PM PDT 24 |
356319410 ps |
| T251 |
/workspace/coverage/default/22.spi_device_mailbox.1108215577 |
|
|
Mar 31 01:24:44 PM PDT 24 |
Mar 31 01:25:01 PM PDT 24 |
1141951648 ps |
| T328 |
/workspace/coverage/default/40.spi_device_mailbox.2676712148 |
|
|
Mar 31 01:25:38 PM PDT 24 |
Mar 31 01:26:38 PM PDT 24 |
6633879894 ps |
| T639 |
/workspace/coverage/default/0.spi_device_read_buffer_direct.2372214595 |
|
|
Mar 31 01:23:28 PM PDT 24 |
Mar 31 01:23:32 PM PDT 24 |
499351919 ps |
| T289 |
/workspace/coverage/default/3.spi_device_cfg_cmd.1167329688 |
|
|
Mar 31 01:23:47 PM PDT 24 |
Mar 31 01:24:02 PM PDT 24 |
2296935203 ps |
| T233 |
/workspace/coverage/default/3.spi_device_mailbox.1741283415 |
|
|
Mar 31 01:23:44 PM PDT 24 |
Mar 31 01:24:07 PM PDT 24 |
3317890187 ps |
| T280 |
/workspace/coverage/default/26.spi_device_pass_addr_payload_swap.3608194626 |
|
|
Mar 31 01:25:07 PM PDT 24 |
Mar 31 01:25:11 PM PDT 24 |
248389245 ps |
| T281 |
/workspace/coverage/default/8.spi_device_intercept.1918735084 |
|
|
Mar 31 01:24:01 PM PDT 24 |
Mar 31 01:24:12 PM PDT 24 |
4320392517 ps |
| T640 |
/workspace/coverage/default/30.spi_device_tpm_sts_read.1828209480 |
|
|
Mar 31 01:25:03 PM PDT 24 |
Mar 31 01:25:04 PM PDT 24 |
13605699 ps |
| T641 |
/workspace/coverage/default/47.spi_device_pass_cmd_filtering.1405084511 |
|
|
Mar 31 01:26:00 PM PDT 24 |
Mar 31 01:26:04 PM PDT 24 |
270817196 ps |
| T642 |
/workspace/coverage/default/24.spi_device_mailbox.3855828496 |
|
|
Mar 31 01:24:56 PM PDT 24 |
Mar 31 01:25:04 PM PDT 24 |
1117424728 ps |
| T297 |
/workspace/coverage/default/43.spi_device_pass_addr_payload_swap.2372917148 |
|
|
Mar 31 01:25:55 PM PDT 24 |
Mar 31 01:26:04 PM PDT 24 |
5506890519 ps |
| T643 |
/workspace/coverage/default/22.spi_device_csb_read.2900744661 |
|
|
Mar 31 01:24:46 PM PDT 24 |
Mar 31 01:24:47 PM PDT 24 |
49729826 ps |
| T350 |
/workspace/coverage/default/41.spi_device_upload.793545913 |
|
|
Mar 31 01:25:41 PM PDT 24 |
Mar 31 01:26:16 PM PDT 24 |
35284615195 ps |
| T296 |
/workspace/coverage/default/1.spi_device_pass_addr_payload_swap.3740574171 |
|
|
Mar 31 01:23:42 PM PDT 24 |
Mar 31 01:23:52 PM PDT 24 |
3610264159 ps |
| T644 |
/workspace/coverage/default/11.spi_device_csb_read.178575406 |
|
|
Mar 31 01:24:12 PM PDT 24 |
Mar 31 01:24:13 PM PDT 24 |
15320591 ps |
| T343 |
/workspace/coverage/default/8.spi_device_pass_addr_payload_swap.1991557981 |
|
|
Mar 31 01:23:57 PM PDT 24 |
Mar 31 01:24:40 PM PDT 24 |
16659263797 ps |
| T222 |
/workspace/coverage/default/2.spi_device_pass_cmd_filtering.2296585690 |
|
|
Mar 31 01:23:37 PM PDT 24 |
Mar 31 01:23:44 PM PDT 24 |
598373671 ps |
| T645 |
/workspace/coverage/default/45.spi_device_tpm_sts_read.2857954860 |
|
|
Mar 31 01:25:55 PM PDT 24 |
Mar 31 01:25:56 PM PDT 24 |
22619013 ps |
| T646 |
/workspace/coverage/default/3.spi_device_ram_cfg.2405322834 |
|
|
Mar 31 01:23:37 PM PDT 24 |
Mar 31 01:23:37 PM PDT 24 |
40048281 ps |
| T647 |
/workspace/coverage/default/20.spi_device_tpm_all.55682619 |
|
|
Mar 31 01:24:42 PM PDT 24 |
Mar 31 01:25:40 PM PDT 24 |
43902062452 ps |
| T249 |
/workspace/coverage/default/16.spi_device_pass_cmd_filtering.2288811420 |
|
|
Mar 31 01:24:32 PM PDT 24 |
Mar 31 01:25:27 PM PDT 24 |
43065258320 ps |
| T219 |
/workspace/coverage/default/14.spi_device_pass_addr_payload_swap.1600160393 |
|
|
Mar 31 01:24:27 PM PDT 24 |
Mar 31 01:24:33 PM PDT 24 |
938208600 ps |
| T648 |
/workspace/coverage/default/38.spi_device_csb_read.1813114810 |
|
|
Mar 31 01:25:30 PM PDT 24 |
Mar 31 01:25:31 PM PDT 24 |
31705394 ps |
| T649 |
/workspace/coverage/default/6.spi_device_tpm_read_hw_reg.21910 |
|
|
Mar 31 01:23:49 PM PDT 24 |
Mar 31 01:24:03 PM PDT 24 |
12775024921 ps |
| T314 |
/workspace/coverage/default/2.spi_device_cfg_cmd.3028124756 |
|
|
Mar 31 01:23:43 PM PDT 24 |
Mar 31 01:23:48 PM PDT 24 |
811473019 ps |
| T650 |
/workspace/coverage/default/44.spi_device_alert_test.2783062225 |
|
|
Mar 31 01:25:54 PM PDT 24 |
Mar 31 01:25:55 PM PDT 24 |
33855831 ps |
| T651 |
/workspace/coverage/default/15.spi_device_tpm_read_hw_reg.3393252786 |
|
|
Mar 31 01:24:31 PM PDT 24 |
Mar 31 01:24:34 PM PDT 24 |
1624826151 ps |
| T652 |
/workspace/coverage/default/31.spi_device_intercept.3565130256 |
|
|
Mar 31 01:25:23 PM PDT 24 |
Mar 31 01:25:28 PM PDT 24 |
337708245 ps |
| T653 |
/workspace/coverage/default/41.spi_device_tpm_rw.2167805971 |
|
|
Mar 31 01:25:40 PM PDT 24 |
Mar 31 01:25:42 PM PDT 24 |
62476817 ps |
| T654 |
/workspace/coverage/default/16.spi_device_csb_read.3597799134 |
|
|
Mar 31 01:24:25 PM PDT 24 |
Mar 31 01:24:26 PM PDT 24 |
39661151 ps |
| T295 |
/workspace/coverage/default/18.spi_device_pass_addr_payload_swap.2312925038 |
|
|
Mar 31 01:24:34 PM PDT 24 |
Mar 31 01:24:48 PM PDT 24 |
8291908723 ps |
| T298 |
/workspace/coverage/default/3.spi_device_pass_addr_payload_swap.2002898126 |
|
|
Mar 31 01:23:37 PM PDT 24 |
Mar 31 01:23:44 PM PDT 24 |
5332172787 ps |
| T655 |
/workspace/coverage/default/15.spi_device_ram_cfg.2618819960 |
|
|
Mar 31 01:24:27 PM PDT 24 |
Mar 31 01:24:28 PM PDT 24 |
35133638 ps |
| T362 |
/workspace/coverage/default/7.spi_device_stress_all.4250823920 |
|
|
Mar 31 01:24:02 PM PDT 24 |
Mar 31 01:24:03 PM PDT 24 |
54008272 ps |
| T339 |
/workspace/coverage/default/24.spi_device_pass_addr_payload_swap.646829155 |
|
|
Mar 31 01:24:51 PM PDT 24 |
Mar 31 01:24:57 PM PDT 24 |
1110911816 ps |
| T329 |
/workspace/coverage/default/11.spi_device_intercept.3824027760 |
|
|
Mar 31 01:24:13 PM PDT 24 |
Mar 31 01:24:27 PM PDT 24 |
4943148570 ps |
| T267 |
/workspace/coverage/default/27.spi_device_mailbox.2970570914 |
|
|
Mar 31 01:25:10 PM PDT 24 |
Mar 31 01:25:14 PM PDT 24 |
158427543 ps |
| T656 |
/workspace/coverage/default/16.spi_device_read_buffer_direct.197374859 |
|
|
Mar 31 01:24:34 PM PDT 24 |
Mar 31 01:24:39 PM PDT 24 |
531693142 ps |
| T322 |
/workspace/coverage/default/30.spi_device_pass_cmd_filtering.68683409 |
|
|
Mar 31 01:25:07 PM PDT 24 |
Mar 31 01:25:14 PM PDT 24 |
1463881629 ps |
| T657 |
/workspace/coverage/default/25.spi_device_tpm_rw.3534042520 |
|
|
Mar 31 01:24:50 PM PDT 24 |
Mar 31 01:24:52 PM PDT 24 |
170944662 ps |
| T658 |
/workspace/coverage/default/29.spi_device_cfg_cmd.1869351425 |
|
|
Mar 31 01:25:12 PM PDT 24 |
Mar 31 01:25:21 PM PDT 24 |
2184942250 ps |
| T231 |
/workspace/coverage/default/11.spi_device_pass_addr_payload_swap.2304241871 |
|
|
Mar 31 01:24:16 PM PDT 24 |
Mar 31 01:24:41 PM PDT 24 |
15517318299 ps |
| T259 |
/workspace/coverage/default/23.spi_device_pass_cmd_filtering.1196082539 |
|
|
Mar 31 01:24:46 PM PDT 24 |
Mar 31 01:25:10 PM PDT 24 |
27443011652 ps |
| T659 |
/workspace/coverage/default/44.spi_device_tpm_sts_read.203252276 |
|
|
Mar 31 01:25:59 PM PDT 24 |
Mar 31 01:26:00 PM PDT 24 |
114226082 ps |
| T220 |
/workspace/coverage/default/42.spi_device_intercept.3467270139 |
|
|
Mar 31 01:25:40 PM PDT 24 |
Mar 31 01:25:54 PM PDT 24 |
12531190589 ps |
| T246 |
/workspace/coverage/default/12.spi_device_intercept.2872144020 |
|
|
Mar 31 01:24:12 PM PDT 24 |
Mar 31 01:24:15 PM PDT 24 |
116740650 ps |
| T195 |
/workspace/coverage/default/6.spi_device_pass_cmd_filtering.2880761659 |
|
|
Mar 31 01:23:52 PM PDT 24 |
Mar 31 01:24:41 PM PDT 24 |
16739728202 ps |
| T660 |
/workspace/coverage/default/12.spi_device_read_buffer_direct.2724599341 |
|
|
Mar 31 01:24:20 PM PDT 24 |
Mar 31 01:24:27 PM PDT 24 |
627254991 ps |
| T338 |
/workspace/coverage/default/6.spi_device_pass_addr_payload_swap.3998879285 |
|
|
Mar 31 01:23:49 PM PDT 24 |
Mar 31 01:24:01 PM PDT 24 |
7351480913 ps |
| T661 |
/workspace/coverage/default/5.spi_device_alert_test.157506658 |
|
|
Mar 31 01:23:48 PM PDT 24 |
Mar 31 01:23:49 PM PDT 24 |
14158322 ps |
| T662 |
/workspace/coverage/default/20.spi_device_tpm_sts_read.3090932557 |
|
|
Mar 31 01:24:42 PM PDT 24 |
Mar 31 01:24:43 PM PDT 24 |
72178240 ps |
| T374 |
/workspace/coverage/default/41.spi_device_pass_cmd_filtering.2955602529 |
|
|
Mar 31 01:25:51 PM PDT 24 |
Mar 31 01:25:57 PM PDT 24 |
14063338127 ps |
| T663 |
/workspace/coverage/default/23.spi_device_stress_all.1030916934 |
|
|
Mar 31 01:24:54 PM PDT 24 |
Mar 31 01:24:55 PM PDT 24 |
476176257 ps |
| T333 |
/workspace/coverage/default/24.spi_device_pass_cmd_filtering.849535862 |
|
|
Mar 31 01:24:53 PM PDT 24 |
Mar 31 01:25:05 PM PDT 24 |
1063378340 ps |
| T664 |
/workspace/coverage/default/47.spi_device_csb_read.80885165 |
|
|
Mar 31 01:26:01 PM PDT 24 |
Mar 31 01:26:01 PM PDT 24 |
63614875 ps |
| T665 |
/workspace/coverage/default/19.spi_device_tpm_read_hw_reg.4288830515 |
|
|
Mar 31 01:24:45 PM PDT 24 |
Mar 31 01:25:23 PM PDT 24 |
19802341823 ps |
| T666 |
/workspace/coverage/default/40.spi_device_alert_test.2121182761 |
|
|
Mar 31 01:25:42 PM PDT 24 |
Mar 31 01:25:43 PM PDT 24 |
40966098 ps |
| T234 |
/workspace/coverage/default/20.spi_device_mailbox.3473573765 |
|
|
Mar 31 01:24:40 PM PDT 24 |
Mar 31 01:24:45 PM PDT 24 |
443686522 ps |
| T320 |
/workspace/coverage/default/29.spi_device_intercept.3437065673 |
|
|
Mar 31 01:25:18 PM PDT 24 |
Mar 31 01:25:29 PM PDT 24 |
4057442707 ps |
| T667 |
/workspace/coverage/default/9.spi_device_csb_read.2964539603 |
|
|
Mar 31 01:24:05 PM PDT 24 |
Mar 31 01:24:06 PM PDT 24 |
20531120 ps |
| T668 |
/workspace/coverage/default/48.spi_device_alert_test.1828958064 |
|
|
Mar 31 01:26:10 PM PDT 24 |
Mar 31 01:26:11 PM PDT 24 |
13339364 ps |
| T268 |
/workspace/coverage/default/13.spi_device_pass_cmd_filtering.1292270992 |
|
|
Mar 31 01:24:20 PM PDT 24 |
Mar 31 01:24:40 PM PDT 24 |
4471134620 ps |
| T348 |
/workspace/coverage/default/14.spi_device_intercept.953700302 |
|
|
Mar 31 01:24:29 PM PDT 24 |
Mar 31 01:24:36 PM PDT 24 |
291167482 ps |
| T669 |
/workspace/coverage/default/30.spi_device_cfg_cmd.4117017356 |
|
|
Mar 31 01:25:14 PM PDT 24 |
Mar 31 01:25:22 PM PDT 24 |
485850428 ps |
| T670 |
/workspace/coverage/default/49.spi_device_tpm_rw.2457517317 |
|
|
Mar 31 01:26:06 PM PDT 24 |
Mar 31 01:26:10 PM PDT 24 |
221138530 ps |
| T671 |
/workspace/coverage/default/24.spi_device_read_buffer_direct.1688311296 |
|
|
Mar 31 01:24:52 PM PDT 24 |
Mar 31 01:25:12 PM PDT 24 |
5041692348 ps |
| T672 |
/workspace/coverage/default/9.spi_device_read_buffer_direct.3947310537 |
|
|
Mar 31 01:24:01 PM PDT 24 |
Mar 31 01:24:06 PM PDT 24 |
1230413336 ps |
| T347 |
/workspace/coverage/default/48.spi_device_mailbox.608084539 |
|
|
Mar 31 01:26:08 PM PDT 24 |
Mar 31 01:26:22 PM PDT 24 |
3456936808 ps |
| T673 |
/workspace/coverage/default/44.spi_device_pass_cmd_filtering.797696199 |
|
|
Mar 31 01:25:51 PM PDT 24 |
Mar 31 01:25:54 PM PDT 24 |
180923035 ps |
| T674 |
/workspace/coverage/default/18.spi_device_tpm_rw.2837727670 |
|
|
Mar 31 01:24:35 PM PDT 24 |
Mar 31 01:24:37 PM PDT 24 |
1008540067 ps |
| T675 |
/workspace/coverage/default/3.spi_device_stress_all.2839294451 |
|
|
Mar 31 01:23:44 PM PDT 24 |
Mar 31 01:23:45 PM PDT 24 |
75008159 ps |
| T676 |
/workspace/coverage/default/27.spi_device_cfg_cmd.2711977265 |
|
|
Mar 31 01:24:58 PM PDT 24 |
Mar 31 01:25:07 PM PDT 24 |
1568577921 ps |
| T677 |
/workspace/coverage/default/21.spi_device_tpm_read_hw_reg.81154361 |
|
|
Mar 31 01:24:45 PM PDT 24 |
Mar 31 01:24:56 PM PDT 24 |
2350507121 ps |
| T678 |
/workspace/coverage/default/32.spi_device_csb_read.1671969703 |
|
|
Mar 31 01:25:25 PM PDT 24 |
Mar 31 01:25:26 PM PDT 24 |
89576439 ps |
| T679 |
/workspace/coverage/default/18.spi_device_stress_all.4241143435 |
|
|
Mar 31 01:24:38 PM PDT 24 |
Mar 31 01:24:39 PM PDT 24 |
131516515 ps |
| T680 |
/workspace/coverage/default/38.spi_device_tpm_rw.128113601 |
|
|
Mar 31 01:25:32 PM PDT 24 |
Mar 31 01:25:33 PM PDT 24 |
318515633 ps |
| T681 |
/workspace/coverage/default/21.spi_device_stress_all.3092361940 |
|
|
Mar 31 01:24:44 PM PDT 24 |
Mar 31 01:24:45 PM PDT 24 |
39407208 ps |
| T682 |
/workspace/coverage/default/31.spi_device_tpm_rw.1196977900 |
|
|
Mar 31 01:25:16 PM PDT 24 |
Mar 31 01:25:18 PM PDT 24 |
231149173 ps |
| T683 |
/workspace/coverage/default/35.spi_device_tpm_rw.163022574 |
|
|
Mar 31 01:25:23 PM PDT 24 |
Mar 31 01:25:28 PM PDT 24 |
430102267 ps |
| T684 |
/workspace/coverage/default/8.spi_device_tpm_all.1451646050 |
|
|
Mar 31 01:24:08 PM PDT 24 |
Mar 31 01:24:17 PM PDT 24 |
928533721 ps |
| T685 |
/workspace/coverage/default/40.spi_device_tpm_read_hw_reg.3771012566 |
|
|
Mar 31 01:25:33 PM PDT 24 |
Mar 31 01:25:43 PM PDT 24 |
32393986448 ps |
| T686 |
/workspace/coverage/default/26.spi_device_intercept.2549785124 |
|
|
Mar 31 01:24:58 PM PDT 24 |
Mar 31 01:25:24 PM PDT 24 |
2805772881 ps |
| T286 |
/workspace/coverage/default/23.spi_device_upload.1549772224 |
|
|
Mar 31 01:25:03 PM PDT 24 |
Mar 31 01:25:39 PM PDT 24 |
43603624285 ps |
| T687 |
/workspace/coverage/default/49.spi_device_tpm_sts_read.20113795 |
|
|
Mar 31 01:26:10 PM PDT 24 |
Mar 31 01:26:11 PM PDT 24 |
213706349 ps |
| T688 |
/workspace/coverage/default/13.spi_device_ram_cfg.2023095182 |
|
|
Mar 31 01:24:21 PM PDT 24 |
Mar 31 01:24:22 PM PDT 24 |
62340447 ps |
| T689 |
/workspace/coverage/default/10.spi_device_csb_read.3738457396 |
|
|
Mar 31 01:24:03 PM PDT 24 |
Mar 31 01:24:04 PM PDT 24 |
14676533 ps |
| T690 |
/workspace/coverage/default/27.spi_device_tpm_rw.3572829936 |
|
|
Mar 31 01:25:07 PM PDT 24 |
Mar 31 01:25:09 PM PDT 24 |
83835228 ps |
| T691 |
/workspace/coverage/default/45.spi_device_read_buffer_direct.3482114842 |
|
|
Mar 31 01:25:52 PM PDT 24 |
Mar 31 01:25:56 PM PDT 24 |
207094067 ps |
| T692 |
/workspace/coverage/default/28.spi_device_read_buffer_direct.1956838704 |
|
|
Mar 31 01:24:58 PM PDT 24 |
Mar 31 01:25:03 PM PDT 24 |
1080111660 ps |
| T269 |
/workspace/coverage/default/14.spi_device_upload.1572586420 |
|
|
Mar 31 01:24:27 PM PDT 24 |
Mar 31 01:24:36 PM PDT 24 |
3831736600 ps |
| T359 |
/workspace/coverage/default/11.spi_device_pass_cmd_filtering.2576983532 |
|
|
Mar 31 01:24:13 PM PDT 24 |
Mar 31 01:24:23 PM PDT 24 |
10116199237 ps |
| T284 |
/workspace/coverage/default/44.spi_device_upload.872557979 |
|
|
Mar 31 01:25:57 PM PDT 24 |
Mar 31 01:26:04 PM PDT 24 |
2885483572 ps |
| T342 |
/workspace/coverage/default/45.spi_device_pass_addr_payload_swap.3084632784 |
|
|
Mar 31 01:25:52 PM PDT 24 |
Mar 31 01:25:59 PM PDT 24 |
1791667496 ps |
| T693 |
/workspace/coverage/default/15.spi_device_csb_read.2910714583 |
|
|
Mar 31 01:24:32 PM PDT 24 |
Mar 31 01:24:32 PM PDT 24 |
25008165 ps |
| T56 |
/workspace/coverage/default/0.spi_device_sec_cm.867419158 |
|
|
Mar 31 01:23:37 PM PDT 24 |
Mar 31 01:23:39 PM PDT 24 |
34635051 ps |
| T694 |
/workspace/coverage/default/21.spi_device_read_buffer_direct.3827901256 |
|
|
Mar 31 01:24:46 PM PDT 24 |
Mar 31 01:24:50 PM PDT 24 |
178461211 ps |
| T346 |
/workspace/coverage/default/15.spi_device_intercept.594576027 |
|
|
Mar 31 01:24:26 PM PDT 24 |
Mar 31 01:24:29 PM PDT 24 |
484991874 ps |
| T695 |
/workspace/coverage/default/13.spi_device_csb_read.2593562180 |
|
|
Mar 31 01:24:20 PM PDT 24 |
Mar 31 01:24:21 PM PDT 24 |
20988247 ps |
| T696 |
/workspace/coverage/default/3.spi_device_tpm_all.3301003491 |
|
|
Mar 31 01:23:39 PM PDT 24 |
Mar 31 01:23:54 PM PDT 24 |
2193475997 ps |
| T697 |
/workspace/coverage/default/8.spi_device_tpm_read_hw_reg.2934249292 |
|
|
Mar 31 01:24:02 PM PDT 24 |
Mar 31 01:24:09 PM PDT 24 |
1983758464 ps |
| T349 |
/workspace/coverage/default/48.spi_device_intercept.3123591210 |
|
|
Mar 31 01:26:06 PM PDT 24 |
Mar 31 01:26:09 PM PDT 24 |
166795298 ps |
| T698 |
/workspace/coverage/default/31.spi_device_tpm_sts_read.497180823 |
|
|
Mar 31 01:25:13 PM PDT 24 |
Mar 31 01:25:14 PM PDT 24 |
589441110 ps |
| T699 |
/workspace/coverage/default/39.spi_device_alert_test.1820360762 |
|
|
Mar 31 01:25:37 PM PDT 24 |
Mar 31 01:25:38 PM PDT 24 |
16819282 ps |
| T285 |
/workspace/coverage/default/1.spi_device_upload.3164168263 |
|
|
Mar 31 01:23:36 PM PDT 24 |
Mar 31 01:23:52 PM PDT 24 |
44234966425 ps |
| T190 |
/workspace/coverage/default/49.spi_device_mailbox.1483272147 |
|
|
Mar 31 01:26:10 PM PDT 24 |
Mar 31 01:28:06 PM PDT 24 |
14662347656 ps |
| T335 |
/workspace/coverage/default/46.spi_device_pass_addr_payload_swap.3776862971 |
|
|
Mar 31 01:26:00 PM PDT 24 |
Mar 31 01:26:04 PM PDT 24 |
3541317419 ps |
| T700 |
/workspace/coverage/default/14.spi_device_tpm_rw.953541930 |
|
|
Mar 31 01:24:25 PM PDT 24 |
Mar 31 01:24:28 PM PDT 24 |
48708120 ps |
| T701 |
/workspace/coverage/default/7.spi_device_tpm_sts_read.2000800754 |
|
|
Mar 31 01:24:06 PM PDT 24 |
Mar 31 01:24:07 PM PDT 24 |
1041693695 ps |
| T290 |
/workspace/coverage/default/32.spi_device_intercept.107021591 |
|
|
Mar 31 01:25:13 PM PDT 24 |
Mar 31 01:25:46 PM PDT 24 |
15388613402 ps |
| T702 |
/workspace/coverage/default/43.spi_device_csb_read.2526015006 |
|
|
Mar 31 01:25:53 PM PDT 24 |
Mar 31 01:25:54 PM PDT 24 |
57262496 ps |
| T703 |
/workspace/coverage/default/25.spi_device_mailbox.1013724323 |
|
|
Mar 31 01:24:52 PM PDT 24 |
Mar 31 01:26:39 PM PDT 24 |
38767527703 ps |
| T270 |
/workspace/coverage/default/28.spi_device_intercept.3110524723 |
|
|
Mar 31 01:24:56 PM PDT 24 |
Mar 31 01:25:02 PM PDT 24 |
241427153 ps |
| T215 |
/workspace/coverage/default/47.spi_device_pass_addr_payload_swap.677900457 |
|
|
Mar 31 01:25:58 PM PDT 24 |
Mar 31 01:26:11 PM PDT 24 |
16831367415 ps |
| T704 |
/workspace/coverage/default/30.spi_device_csb_read.1294219280 |
|
|
Mar 31 01:25:10 PM PDT 24 |
Mar 31 01:25:11 PM PDT 24 |
37561064 ps |
| T705 |
/workspace/coverage/default/22.spi_device_read_buffer_direct.3726557206 |
|
|
Mar 31 01:24:49 PM PDT 24 |
Mar 31 01:24:53 PM PDT 24 |
353842839 ps |
| T706 |
/workspace/coverage/default/1.spi_device_tpm_all.1590191880 |
|
|
Mar 31 01:23:36 PM PDT 24 |
Mar 31 01:24:06 PM PDT 24 |
11009367700 ps |
| T247 |
/workspace/coverage/default/33.spi_device_mailbox.3480964332 |
|
|
Mar 31 01:25:23 PM PDT 24 |
Mar 31 01:27:08 PM PDT 24 |
30968077628 ps |
| T707 |
/workspace/coverage/default/8.spi_device_upload.3498896533 |
|
|
Mar 31 01:24:04 PM PDT 24 |
Mar 31 01:24:08 PM PDT 24 |
158329292 ps |
| T313 |
/workspace/coverage/default/16.spi_device_flash_mode.1217178243 |
|
|
Mar 31 01:24:37 PM PDT 24 |
Mar 31 01:25:00 PM PDT 24 |
1615326339 ps |
| T708 |
/workspace/coverage/default/29.spi_device_tpm_rw.1343248693 |
|
|
Mar 31 01:25:13 PM PDT 24 |
Mar 31 01:25:16 PM PDT 24 |
162374844 ps |
| T709 |
/workspace/coverage/default/2.spi_device_tpm_all.1017258892 |
|
|
Mar 31 01:23:38 PM PDT 24 |
Mar 31 01:23:43 PM PDT 24 |
777328970 ps |
| T310 |
/workspace/coverage/default/0.spi_device_flash_mode.2152642505 |
|
|
Mar 31 01:23:28 PM PDT 24 |
Mar 31 01:24:22 PM PDT 24 |
3544112691 ps |
| T710 |
/workspace/coverage/default/11.spi_device_cfg_cmd.1598261419 |
|
|
Mar 31 01:24:18 PM PDT 24 |
Mar 31 01:24:31 PM PDT 24 |
1010952174 ps |
| T711 |
/workspace/coverage/default/12.spi_device_csb_read.3712381995 |
|
|
Mar 31 01:24:18 PM PDT 24 |
Mar 31 01:24:19 PM PDT 24 |
17747887 ps |
| T712 |
/workspace/coverage/default/40.spi_device_tpm_all.3412316413 |
|
|
Mar 31 01:25:37 PM PDT 24 |
Mar 31 01:26:03 PM PDT 24 |
34071578325 ps |
| T713 |
/workspace/coverage/default/43.spi_device_intercept.2791769272 |
|
|
Mar 31 01:25:49 PM PDT 24 |
Mar 31 01:26:04 PM PDT 24 |
4830100540 ps |
| T714 |
/workspace/coverage/default/22.spi_device_tpm_read_hw_reg.2419764402 |
|
|
Mar 31 01:24:45 PM PDT 24 |
Mar 31 01:24:48 PM PDT 24 |
4666421433 ps |
| T715 |
/workspace/coverage/default/43.spi_device_read_buffer_direct.710272184 |
|
|
Mar 31 01:25:51 PM PDT 24 |
Mar 31 01:25:55 PM PDT 24 |
152847601 ps |
| T716 |
/workspace/coverage/default/42.spi_device_read_buffer_direct.1174673484 |
|
|
Mar 31 01:25:50 PM PDT 24 |
Mar 31 01:25:58 PM PDT 24 |
1789281360 ps |
| T717 |
/workspace/coverage/default/40.spi_device_tpm_sts_read.4160547201 |
|
|
Mar 31 01:25:34 PM PDT 24 |
Mar 31 01:25:35 PM PDT 24 |
275292300 ps |
| T718 |
/workspace/coverage/default/24.spi_device_intercept.2639760265 |
|
|
Mar 31 01:24:55 PM PDT 24 |
Mar 31 01:25:09 PM PDT 24 |
5347885850 ps |
| T719 |
/workspace/coverage/default/25.spi_device_tpm_read_hw_reg.1369176745 |
|
|
Mar 31 01:24:51 PM PDT 24 |
Mar 31 01:25:01 PM PDT 24 |
21205591284 ps |
| T720 |
/workspace/coverage/default/13.spi_device_read_buffer_direct.2552360420 |
|
|
Mar 31 01:24:21 PM PDT 24 |
Mar 31 01:24:31 PM PDT 24 |
3964455510 ps |
| T721 |
/workspace/coverage/default/15.spi_device_tpm_rw.368881782 |
|
|
Mar 31 01:24:26 PM PDT 24 |
Mar 31 01:24:27 PM PDT 24 |
28416044 ps |
| T722 |
/workspace/coverage/default/39.spi_device_read_buffer_direct.887179555 |
|
|
Mar 31 01:25:37 PM PDT 24 |
Mar 31 01:25:41 PM PDT 24 |
1196255419 ps |
| T57 |
/workspace/coverage/default/4.spi_device_sec_cm.874224634 |
|
|
Mar 31 01:23:49 PM PDT 24 |
Mar 31 01:23:50 PM PDT 24 |
39752948 ps |
| T723 |
/workspace/coverage/default/16.spi_device_tpm_rw.3924222782 |
|
|
Mar 31 01:24:27 PM PDT 24 |
Mar 31 01:24:29 PM PDT 24 |
94435572 ps |
| T336 |
/workspace/coverage/default/49.spi_device_pass_addr_payload_swap.2511408518 |
|
|
Mar 31 01:26:12 PM PDT 24 |
Mar 31 01:26:44 PM PDT 24 |
38367017018 ps |
| T724 |
/workspace/coverage/default/45.spi_device_mailbox.3288645859 |
|
|
Mar 31 01:26:01 PM PDT 24 |
Mar 31 01:26:22 PM PDT 24 |
8222051990 ps |
| T340 |
/workspace/coverage/default/4.spi_device_pass_addr_payload_swap.2838823602 |
|
|
Mar 31 01:23:52 PM PDT 24 |
Mar 31 01:24:06 PM PDT 24 |
3300180983 ps |
| T331 |
/workspace/coverage/default/12.spi_device_cfg_cmd.2738546152 |
|
|
Mar 31 01:24:23 PM PDT 24 |
Mar 31 01:24:31 PM PDT 24 |
2654871170 ps |
| T725 |
/workspace/coverage/default/0.spi_device_tpm_read_hw_reg.3257702068 |
|
|
Mar 31 01:23:28 PM PDT 24 |
Mar 31 01:23:35 PM PDT 24 |
954793783 ps |
| T726 |
/workspace/coverage/default/34.spi_device_flash_mode.3883114619 |
|
|
Mar 31 01:25:26 PM PDT 24 |
Mar 31 01:26:17 PM PDT 24 |
4699774549 ps |
| T727 |
/workspace/coverage/default/4.spi_device_tpm_rw.388320484 |
|
|
Mar 31 01:23:44 PM PDT 24 |
Mar 31 01:23:45 PM PDT 24 |
159399411 ps |
| T728 |
/workspace/coverage/default/27.spi_device_alert_test.3673576278 |
|
|
Mar 31 01:25:19 PM PDT 24 |
Mar 31 01:25:20 PM PDT 24 |
28904154 ps |
| T337 |
/workspace/coverage/default/2.spi_device_pass_addr_payload_swap.2429325764 |
|
|
Mar 31 01:23:38 PM PDT 24 |
Mar 31 01:23:41 PM PDT 24 |
170294169 ps |
| T729 |
/workspace/coverage/default/38.spi_device_read_buffer_direct.1718462094 |
|
|
Mar 31 01:25:36 PM PDT 24 |
Mar 31 01:25:42 PM PDT 24 |
375150505 ps |
| T240 |
/workspace/coverage/default/46.spi_device_pass_cmd_filtering.4202707119 |
|
|
Mar 31 01:25:56 PM PDT 24 |
Mar 31 01:26:04 PM PDT 24 |
530934663 ps |
| T730 |
/workspace/coverage/default/29.spi_device_csb_read.1980834959 |
|
|
Mar 31 01:25:05 PM PDT 24 |
Mar 31 01:25:06 PM PDT 24 |
36528285 ps |
| T731 |
/workspace/coverage/default/1.spi_device_tpm_sts_read.2129417581 |
|
|
Mar 31 01:23:40 PM PDT 24 |
Mar 31 01:23:41 PM PDT 24 |
176482398 ps |
| T732 |
/workspace/coverage/default/28.spi_device_csb_read.3041933100 |
|
|
Mar 31 01:25:01 PM PDT 24 |
Mar 31 01:25:02 PM PDT 24 |
33964385 ps |
| T733 |
/workspace/coverage/default/4.spi_device_tpm_all.3389159820 |
|
|
Mar 31 01:23:47 PM PDT 24 |
Mar 31 01:23:55 PM PDT 24 |
889753910 ps |
| T734 |
/workspace/coverage/default/16.spi_device_tpm_read_hw_reg.365019680 |
|
|
Mar 31 01:24:28 PM PDT 24 |
Mar 31 01:24:33 PM PDT 24 |
848132899 ps |
| T735 |
/workspace/coverage/default/41.spi_device_tpm_sts_read.3124152644 |
|
|
Mar 31 01:25:42 PM PDT 24 |
Mar 31 01:25:43 PM PDT 24 |
45965091 ps |
| T736 |
/workspace/coverage/default/0.spi_device_mailbox.4113923635 |
|
|
Mar 31 01:23:28 PM PDT 24 |
Mar 31 01:23:41 PM PDT 24 |
2415127979 ps |
| T737 |
/workspace/coverage/default/35.spi_device_alert_test.819285355 |
|
|
Mar 31 01:25:25 PM PDT 24 |
Mar 31 01:25:26 PM PDT 24 |
21317068 ps |
| T738 |
/workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1800466634 |
|
|
Mar 31 01:23:38 PM PDT 24 |
Mar 31 01:23:46 PM PDT 24 |
1780375534 ps |
| T739 |
/workspace/coverage/default/26.spi_device_cfg_cmd.469501039 |
|
|
Mar 31 01:24:57 PM PDT 24 |
Mar 31 01:25:03 PM PDT 24 |
795346973 ps |
| T39 |
/workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3881985853 |
|
|
Mar 31 12:27:49 PM PDT 24 |
Mar 31 12:27:52 PM PDT 24 |
97579637 ps |
| T40 |
/workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2415205104 |
|
|
Mar 31 12:27:53 PM PDT 24 |
Mar 31 12:27:58 PM PDT 24 |
553939068 ps |
| T41 |
/workspace/coverage/cover_reg_top/12.spi_device_tl_errors.764740105 |
|
|
Mar 31 12:27:56 PM PDT 24 |
Mar 31 12:27:58 PM PDT 24 |
153155814 ps |
| T740 |
/workspace/coverage/cover_reg_top/46.spi_device_intr_test.2725578088 |
|
|
Mar 31 12:27:55 PM PDT 24 |
Mar 31 12:27:56 PM PDT 24 |
18650957 ps |
| T42 |
/workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.4018860927 |
|
|
Mar 31 12:27:50 PM PDT 24 |
Mar 31 12:27:53 PM PDT 24 |
168395253 ps |
| T741 |
/workspace/coverage/cover_reg_top/6.spi_device_intr_test.445925983 |
|
|
Mar 31 12:27:54 PM PDT 24 |
Mar 31 12:28:00 PM PDT 24 |
202961133 ps |
| T134 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1227585338 |
|
|
Mar 31 12:27:51 PM PDT 24 |
Mar 31 12:27:55 PM PDT 24 |
372560111 ps |
| T140 |
/workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3045589577 |
|
|
Mar 31 12:27:59 PM PDT 24 |
Mar 31 12:28:01 PM PDT 24 |
164147552 ps |
| T43 |
/workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2664097647 |
|
|
Mar 31 12:28:02 PM PDT 24 |
Mar 31 12:28:10 PM PDT 24 |
278773468 ps |
| T742 |
/workspace/coverage/cover_reg_top/23.spi_device_intr_test.3752611319 |
|
|
Mar 31 12:28:06 PM PDT 24 |
Mar 31 12:28:07 PM PDT 24 |
31051546 ps |
| T141 |
/workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.711019404 |
|
|
Mar 31 12:28:02 PM PDT 24 |
Mar 31 12:28:03 PM PDT 24 |
101343740 ps |
| T154 |
/workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.721088693 |
|
|
Mar 31 12:27:57 PM PDT 24 |
Mar 31 12:28:00 PM PDT 24 |
41425022 ps |
| T155 |
/workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3452920159 |
|
|
Mar 31 12:28:07 PM PDT 24 |
Mar 31 12:28:10 PM PDT 24 |
58061527 ps |
| T166 |
/workspace/coverage/cover_reg_top/5.spi_device_intr_test.412779548 |
|
|
Mar 31 12:28:05 PM PDT 24 |
Mar 31 12:28:06 PM PDT 24 |
17185054 ps |
| T156 |
/workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1512036824 |
|
|
Mar 31 12:28:18 PM PDT 24 |
Mar 31 12:28:20 PM PDT 24 |
169370816 ps |
| T743 |
/workspace/coverage/cover_reg_top/27.spi_device_intr_test.260376823 |
|
|
Mar 31 12:27:55 PM PDT 24 |
Mar 31 12:27:56 PM PDT 24 |
40124935 ps |
| T122 |
/workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3553692491 |
|
|
Mar 31 12:27:53 PM PDT 24 |
Mar 31 12:28:06 PM PDT 24 |
206576421 ps |
| T130 |
/workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3389004888 |
|
|
Mar 31 12:27:56 PM PDT 24 |
Mar 31 12:28:00 PM PDT 24 |
490322170 ps |
| T108 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.225327334 |
|
|
Mar 31 12:28:00 PM PDT 24 |
Mar 31 12:28:01 PM PDT 24 |
13949426 ps |
| T157 |
/workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.4137609617 |
|
|
Mar 31 12:28:29 PM PDT 24 |
Mar 31 12:28:32 PM PDT 24 |
89097381 ps |
| T142 |
/workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.149772275 |
|
|
Mar 31 12:27:51 PM PDT 24 |
Mar 31 12:27:53 PM PDT 24 |
122877002 ps |
| T136 |
/workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1801951226 |
|
|
Mar 31 12:28:04 PM PDT 24 |
Mar 31 12:28:07 PM PDT 24 |
192913713 ps |
| T744 |
/workspace/coverage/cover_reg_top/29.spi_device_intr_test.1631447327 |
|
|
Mar 31 12:27:51 PM PDT 24 |
Mar 31 12:27:53 PM PDT 24 |
47811922 ps |
| T143 |
/workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3115989397 |
|
|
Mar 31 12:28:09 PM PDT 24 |
Mar 31 12:28:11 PM PDT 24 |
58571904 ps |
| T123 |
/workspace/coverage/cover_reg_top/0.spi_device_tl_errors.238708190 |
|
|
Mar 31 12:28:28 PM PDT 24 |
Mar 31 12:28:32 PM PDT 24 |
61322956 ps |
| T745 |
/workspace/coverage/cover_reg_top/15.spi_device_intr_test.3997123113 |
|
|
Mar 31 12:27:57 PM PDT 24 |
Mar 31 12:27:58 PM PDT 24 |
17944207 ps |
| T167 |
/workspace/coverage/cover_reg_top/17.spi_device_intr_test.1837389080 |
|
|
Mar 31 12:27:45 PM PDT 24 |
Mar 31 12:27:46 PM PDT 24 |
20343164 ps |
| T168 |
/workspace/coverage/cover_reg_top/34.spi_device_intr_test.1790660516 |
|
|
Mar 31 12:28:05 PM PDT 24 |
Mar 31 12:28:06 PM PDT 24 |
40315414 ps |
| T144 |
/workspace/coverage/cover_reg_top/16.spi_device_csr_rw.3531100152 |
|
|
Mar 31 12:27:50 PM PDT 24 |
Mar 31 12:27:53 PM PDT 24 |
37494105 ps |
| T132 |
/workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3936865951 |
|
|
Mar 31 12:28:29 PM PDT 24 |
Mar 31 12:28:32 PM PDT 24 |
247600751 ps |
| T746 |
/workspace/coverage/cover_reg_top/12.spi_device_intr_test.1289321329 |
|
|
Mar 31 12:28:33 PM PDT 24 |
Mar 31 12:28:34 PM PDT 24 |
14760362 ps |
| T124 |
/workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1851083696 |
|
|
Mar 31 12:28:09 PM PDT 24 |
Mar 31 12:28:22 PM PDT 24 |
209446516 ps |
| T145 |
/workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1614965419 |
|
|
Mar 31 12:28:01 PM PDT 24 |
Mar 31 12:28:03 PM PDT 24 |
190518303 ps |
| T169 |
/workspace/coverage/cover_reg_top/25.spi_device_intr_test.359857236 |
|
|
Mar 31 12:28:18 PM PDT 24 |
Mar 31 12:28:19 PM PDT 24 |
38523938 ps |
| T747 |
/workspace/coverage/cover_reg_top/21.spi_device_intr_test.3025390258 |
|
|
Mar 31 12:28:17 PM PDT 24 |
Mar 31 12:28:18 PM PDT 24 |
14962418 ps |
| T146 |
/workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3575066119 |
|
|
Mar 31 12:27:59 PM PDT 24 |
Mar 31 12:28:01 PM PDT 24 |
497543535 ps |
| T147 |
/workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3398749079 |
|
|
Mar 31 12:27:55 PM PDT 24 |
Mar 31 12:28:03 PM PDT 24 |
345906649 ps |
| T170 |
/workspace/coverage/cover_reg_top/39.spi_device_intr_test.3600208414 |
|
|
Mar 31 12:27:59 PM PDT 24 |
Mar 31 12:28:00 PM PDT 24 |
27794603 ps |
| T748 |
/workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1870409930 |
|
|
Mar 31 12:27:45 PM PDT 24 |
Mar 31 12:27:46 PM PDT 24 |
197594759 ps |
| T749 |
/workspace/coverage/cover_reg_top/13.spi_device_intr_test.655691604 |
|
|
Mar 31 12:27:51 PM PDT 24 |
Mar 31 12:27:52 PM PDT 24 |
12981361 ps |
| T109 |
/workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1161558320 |
|
|
Mar 31 12:27:52 PM PDT 24 |
Mar 31 12:27:55 PM PDT 24 |
45505528 ps |
| T135 |
/workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3264834307 |
|
|
Mar 31 12:27:51 PM PDT 24 |
Mar 31 12:27:55 PM PDT 24 |
125762903 ps |
| T750 |
/workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2704057067 |
|
|
Mar 31 12:28:01 PM PDT 24 |
Mar 31 12:28:02 PM PDT 24 |
80138294 ps |
| T751 |
/workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2809273337 |
|
|
Mar 31 12:28:29 PM PDT 24 |
Mar 31 12:28:32 PM PDT 24 |
523221249 ps |
| T752 |
/workspace/coverage/cover_reg_top/40.spi_device_intr_test.639463321 |
|
|
Mar 31 12:27:57 PM PDT 24 |
Mar 31 12:27:58 PM PDT 24 |
12362584 ps |
| T129 |
/workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2912335497 |
|
|
Mar 31 12:27:59 PM PDT 24 |
Mar 31 12:28:07 PM PDT 24 |
276692283 ps |
| T753 |
/workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.342559324 |
|
|
Mar 31 12:28:21 PM PDT 24 |
Mar 31 12:28:24 PM PDT 24 |
82017037 ps |
| T365 |
/workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2082894153 |
|
|
Mar 31 12:27:44 PM PDT 24 |
Mar 31 12:27:57 PM PDT 24 |
811782706 ps |
| T148 |
/workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1996741454 |
|
|
Mar 31 12:27:53 PM PDT 24 |
Mar 31 12:27:55 PM PDT 24 |
514894818 ps |
| T131 |
/workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2366089699 |
|
|
Mar 31 12:28:00 PM PDT 24 |
Mar 31 12:28:04 PM PDT 24 |
871818820 ps |
| T754 |
/workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3337256754 |
|
|
Mar 31 12:28:35 PM PDT 24 |
Mar 31 12:28:38 PM PDT 24 |
85597976 ps |
| T372 |
/workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2177019354 |
|
|
Mar 31 12:28:04 PM PDT 24 |
Mar 31 12:28:16 PM PDT 24 |
192534605 ps |
| T159 |
/workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3640216576 |
|
|
Mar 31 12:28:02 PM PDT 24 |
Mar 31 12:28:05 PM PDT 24 |
405481657 ps |
| T149 |
/workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.4291242287 |
|
|
Mar 31 12:27:53 PM PDT 24 |
Mar 31 12:28:08 PM PDT 24 |
1862366843 ps |
| T160 |
/workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3225496298 |
|
|
Mar 31 12:28:09 PM PDT 24 |
Mar 31 12:28:13 PM PDT 24 |
1578286078 ps |
| T755 |
/workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2329305033 |
|
|
Mar 31 12:28:00 PM PDT 24 |
Mar 31 12:28:03 PM PDT 24 |
183429323 ps |
| T161 |
/workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3328448189 |
|
|
Mar 31 12:27:56 PM PDT 24 |
Mar 31 12:27:57 PM PDT 24 |
115130782 ps |
| T756 |
/workspace/coverage/cover_reg_top/0.spi_device_intr_test.27803435 |
|
|
Mar 31 12:27:46 PM PDT 24 |
Mar 31 12:27:47 PM PDT 24 |
14051699 ps |
| T757 |
/workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3604587353 |
|
|
Mar 31 12:27:51 PM PDT 24 |
Mar 31 12:27:53 PM PDT 24 |
10694259 ps |
| T370 |
/workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2352294210 |
|
|
Mar 31 12:28:28 PM PDT 24 |
Mar 31 12:28:50 PM PDT 24 |
15803366507 ps |
| T758 |
/workspace/coverage/cover_reg_top/16.spi_device_intr_test.4050454846 |
|
|
Mar 31 12:27:57 PM PDT 24 |
Mar 31 12:27:58 PM PDT 24 |
17391957 ps |
| T759 |
/workspace/coverage/cover_reg_top/19.spi_device_intr_test.2926275590 |
|
|
Mar 31 12:27:59 PM PDT 24 |
Mar 31 12:28:00 PM PDT 24 |
76037779 ps |
| T760 |
/workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1130748380 |
|
|
Mar 31 12:28:07 PM PDT 24 |
Mar 31 12:28:08 PM PDT 24 |
59587467 ps |
| T761 |
/workspace/coverage/cover_reg_top/30.spi_device_intr_test.2466807655 |
|
|
Mar 31 12:27:57 PM PDT 24 |
Mar 31 12:27:58 PM PDT 24 |
22338881 ps |
| T150 |
/workspace/coverage/cover_reg_top/12.spi_device_csr_rw.929453429 |
|
|
Mar 31 12:28:39 PM PDT 24 |
Mar 31 12:28:41 PM PDT 24 |
89036037 ps |
| T762 |
/workspace/coverage/cover_reg_top/8.spi_device_intr_test.1307398110 |
|
|
Mar 31 12:28:07 PM PDT 24 |
Mar 31 12:28:07 PM PDT 24 |
189070971 ps |
| T763 |
/workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3199562810 |
|
|
Mar 31 12:27:53 PM PDT 24 |
Mar 31 12:27:57 PM PDT 24 |
76981939 ps |
| T764 |
/workspace/coverage/cover_reg_top/36.spi_device_intr_test.701875149 |
|
|
Mar 31 12:27:55 PM PDT 24 |
Mar 31 12:28:00 PM PDT 24 |
37120427 ps |
| T765 |
/workspace/coverage/cover_reg_top/45.spi_device_intr_test.1076990407 |
|
|
Mar 31 12:27:51 PM PDT 24 |
Mar 31 12:27:53 PM PDT 24 |
19618729 ps |
| T766 |
/workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2599360587 |
|
|
Mar 31 12:27:52 PM PDT 24 |
Mar 31 12:27:55 PM PDT 24 |
34495998 ps |
| T767 |
/workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3193074169 |
|
|
Mar 31 12:27:56 PM PDT 24 |
Mar 31 12:28:02 PM PDT 24 |
108540032 ps |
| T133 |
/workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3510023005 |
|
|
Mar 31 12:27:57 PM PDT 24 |
Mar 31 12:28:01 PM PDT 24 |
100589303 ps |
| T151 |
/workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2513937632 |
|
|
Mar 31 12:28:20 PM PDT 24 |
Mar 31 12:28:22 PM PDT 24 |
293502349 ps |
| T768 |
/workspace/coverage/cover_reg_top/11.spi_device_intr_test.1374740719 |
|
|
Mar 31 12:27:54 PM PDT 24 |
Mar 31 12:27:55 PM PDT 24 |
14945820 ps |
| T162 |
/workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1428418439 |
|
|
Mar 31 12:27:57 PM PDT 24 |
Mar 31 12:27:59 PM PDT 24 |
141450989 ps |