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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.16 97.62 92.91 98.61 80.85 95.99 90.96 88.18


Total test records in report: 850
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T769 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2032513055 Mar 31 12:27:54 PM PDT 24 Mar 31 12:27:55 PM PDT 24 11292000 ps
T770 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1292495665 Mar 31 12:28:02 PM PDT 24 Mar 31 12:28:03 PM PDT 24 42346835 ps
T137 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.4114811823 Mar 31 12:28:00 PM PDT 24 Mar 31 12:28:03 PM PDT 24 149656373 ps
T369 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1831160196 Mar 31 12:28:14 PM PDT 24 Mar 31 12:28:25 PM PDT 24 2137048657 ps
T771 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.380969125 Mar 31 12:28:00 PM PDT 24 Mar 31 12:28:02 PM PDT 24 59422133 ps
T163 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1935245409 Mar 31 12:28:04 PM PDT 24 Mar 31 12:28:31 PM PDT 24 2056820683 ps
T772 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1596673086 Mar 31 12:28:00 PM PDT 24 Mar 31 12:28:03 PM PDT 24 214435182 ps
T164 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3320684704 Mar 31 12:27:56 PM PDT 24 Mar 31 12:27:57 PM PDT 24 114978443 ps
T152 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1379671852 Mar 31 12:27:49 PM PDT 24 Mar 31 12:28:28 PM PDT 24 3505511170 ps
T363 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1344868294 Mar 31 12:28:30 PM PDT 24 Mar 31 12:28:33 PM PDT 24 33156660 ps
T773 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.4037137864 Mar 31 12:27:56 PM PDT 24 Mar 31 12:27:58 PM PDT 24 21491706 ps
T165 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1875480839 Mar 31 12:28:00 PM PDT 24 Mar 31 12:28:02 PM PDT 24 64880001 ps
T153 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1966407113 Mar 31 12:27:57 PM PDT 24 Mar 31 12:28:05 PM PDT 24 105904102 ps
T774 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2084067576 Mar 31 12:27:59 PM PDT 24 Mar 31 12:28:00 PM PDT 24 34234690 ps
T775 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2637810037 Mar 31 12:27:48 PM PDT 24 Mar 31 12:28:02 PM PDT 24 824982896 ps
T776 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.235689926 Mar 31 12:28:22 PM PDT 24 Mar 31 12:28:25 PM PDT 24 42368831 ps
T138 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1076877193 Mar 31 12:28:04 PM PDT 24 Mar 31 12:28:06 PM PDT 24 62052250 ps
T777 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.409753297 Mar 31 12:28:33 PM PDT 24 Mar 31 12:28:34 PM PDT 24 18699481 ps
T778 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1111394892 Mar 31 12:28:09 PM PDT 24 Mar 31 12:28:10 PM PDT 24 16228760 ps
T373 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2622565192 Mar 31 12:28:29 PM PDT 24 Mar 31 12:28:44 PM PDT 24 807721265 ps
T779 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2965533071 Mar 31 12:27:56 PM PDT 24 Mar 31 12:27:57 PM PDT 24 31127797 ps
T780 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.275358690 Mar 31 12:28:30 PM PDT 24 Mar 31 12:28:31 PM PDT 24 38171836 ps
T781 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.116865588 Mar 31 12:27:49 PM PDT 24 Mar 31 12:28:03 PM PDT 24 925694675 ps
T782 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3470289174 Mar 31 12:28:30 PM PDT 24 Mar 31 12:28:38 PM PDT 24 292141445 ps
T179 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.311996915 Mar 31 12:27:53 PM PDT 24 Mar 31 12:28:03 PM PDT 24 769407338 ps
T783 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3791886198 Mar 31 12:28:22 PM PDT 24 Mar 31 12:28:25 PM PDT 24 454260970 ps
T784 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.485745850 Mar 31 12:28:04 PM PDT 24 Mar 31 12:28:10 PM PDT 24 61807821 ps
T785 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2644648758 Mar 31 12:27:57 PM PDT 24 Mar 31 12:28:00 PM PDT 24 353236246 ps
T786 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3869932214 Mar 31 12:28:01 PM PDT 24 Mar 31 12:28:02 PM PDT 24 17106989 ps
T787 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2784891393 Mar 31 12:28:17 PM PDT 24 Mar 31 12:28:18 PM PDT 24 23298317 ps
T788 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1126610152 Mar 31 12:28:05 PM PDT 24 Mar 31 12:28:20 PM PDT 24 1374761815 ps
T789 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.865571921 Mar 31 12:27:56 PM PDT 24 Mar 31 12:27:56 PM PDT 24 11392942 ps
T790 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.422207372 Mar 31 12:27:56 PM PDT 24 Mar 31 12:27:57 PM PDT 24 57555798 ps
T791 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3587544711 Mar 31 12:27:59 PM PDT 24 Mar 31 12:28:07 PM PDT 24 1099075077 ps
T792 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3099431301 Mar 31 12:28:26 PM PDT 24 Mar 31 12:28:28 PM PDT 24 220489989 ps
T793 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1651710967 Mar 31 12:27:53 PM PDT 24 Mar 31 12:27:58 PM PDT 24 59950390 ps
T794 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.493817328 Mar 31 12:27:49 PM PDT 24 Mar 31 12:27:53 PM PDT 24 98976746 ps
T795 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1436505296 Mar 31 12:27:50 PM PDT 24 Mar 31 12:27:58 PM PDT 24 565402298 ps
T796 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.191542493 Mar 31 12:28:10 PM PDT 24 Mar 31 12:28:18 PM PDT 24 822069525 ps
T797 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3340416607 Mar 31 12:28:13 PM PDT 24 Mar 31 12:28:17 PM PDT 24 257264577 ps
T798 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.976342013 Mar 31 12:28:20 PM PDT 24 Mar 31 12:28:22 PM PDT 24 168023784 ps
T799 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.287850961 Mar 31 12:28:30 PM PDT 24 Mar 31 12:28:31 PM PDT 24 17660360 ps
T800 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2795663127 Mar 31 12:27:58 PM PDT 24 Mar 31 12:27:59 PM PDT 24 306887451 ps
T801 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3927214783 Mar 31 12:27:53 PM PDT 24 Mar 31 12:27:55 PM PDT 24 96330643 ps
T802 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.4062618078 Mar 31 12:28:20 PM PDT 24 Mar 31 12:28:20 PM PDT 24 13014665 ps
T803 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1889017870 Mar 31 12:28:12 PM PDT 24 Mar 31 12:28:14 PM PDT 24 57893718 ps
T804 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3286733187 Mar 31 12:28:16 PM PDT 24 Mar 31 12:28:16 PM PDT 24 26693118 ps
T805 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.816960642 Mar 31 12:27:47 PM PDT 24 Mar 31 12:27:51 PM PDT 24 217663029 ps
T110 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1870605158 Mar 31 12:28:44 PM PDT 24 Mar 31 12:28:45 PM PDT 24 43348434 ps
T139 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1862589117 Mar 31 12:27:49 PM PDT 24 Mar 31 12:27:52 PM PDT 24 133002131 ps
T806 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1053731856 Mar 31 12:27:53 PM PDT 24 Mar 31 12:28:06 PM PDT 24 202768647 ps
T807 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2050841587 Mar 31 12:27:49 PM PDT 24 Mar 31 12:27:52 PM PDT 24 297279748 ps
T808 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2202330475 Mar 31 12:28:00 PM PDT 24 Mar 31 12:28:01 PM PDT 24 47464733 ps
T809 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2139306091 Mar 31 12:27:59 PM PDT 24 Mar 31 12:28:00 PM PDT 24 315659466 ps
T810 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.243306229 Mar 31 12:27:48 PM PDT 24 Mar 31 12:27:50 PM PDT 24 261939545 ps
T371 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2682939762 Mar 31 12:27:59 PM PDT 24 Mar 31 12:28:16 PM PDT 24 1121301851 ps
T811 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1195491267 Mar 31 12:28:05 PM PDT 24 Mar 31 12:28:07 PM PDT 24 25140937 ps
T812 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3108953313 Mar 31 12:28:08 PM PDT 24 Mar 31 12:28:10 PM PDT 24 28300589 ps
T813 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1295631019 Mar 31 12:27:50 PM PDT 24 Mar 31 12:27:52 PM PDT 24 42159456 ps
T814 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3990772009 Mar 31 12:28:17 PM PDT 24 Mar 31 12:28:18 PM PDT 24 47829439 ps
T815 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2206623262 Mar 31 12:28:39 PM PDT 24 Mar 31 12:28:43 PM PDT 24 256282795 ps
T816 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1116988320 Mar 31 12:27:51 PM PDT 24 Mar 31 12:27:59 PM PDT 24 113064707 ps
T817 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2152921170 Mar 31 12:28:24 PM PDT 24 Mar 31 12:28:26 PM PDT 24 98175156 ps
T818 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2071999212 Mar 31 12:27:45 PM PDT 24 Mar 31 12:27:47 PM PDT 24 111861944 ps
T366 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2889382579 Mar 31 12:27:57 PM PDT 24 Mar 31 12:28:18 PM PDT 24 2094522087 ps
T819 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1824006599 Mar 31 12:27:53 PM PDT 24 Mar 31 12:28:13 PM PDT 24 1253164201 ps
T820 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2633137303 Mar 31 12:28:11 PM PDT 24 Mar 31 12:28:13 PM PDT 24 28490595 ps
T821 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3697127042 Mar 31 12:27:45 PM PDT 24 Mar 31 12:27:46 PM PDT 24 14966225 ps
T822 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.37477536 Mar 31 12:28:24 PM PDT 24 Mar 31 12:28:28 PM PDT 24 321681775 ps
T823 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3878483335 Mar 31 12:28:12 PM PDT 24 Mar 31 12:28:13 PM PDT 24 74596942 ps
T824 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1370607773 Mar 31 12:27:43 PM PDT 24 Mar 31 12:27:46 PM PDT 24 534435804 ps
T825 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2178074025 Mar 31 12:27:54 PM PDT 24 Mar 31 12:27:55 PM PDT 24 13421823 ps
T826 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.304985961 Mar 31 12:28:25 PM PDT 24 Mar 31 12:28:26 PM PDT 24 35997870 ps
T827 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.4003604098 Mar 31 12:27:51 PM PDT 24 Mar 31 12:27:53 PM PDT 24 22094406 ps
T364 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1265473390 Mar 31 12:28:00 PM PDT 24 Mar 31 12:28:05 PM PDT 24 237891984 ps
T828 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.229180754 Mar 31 12:28:31 PM PDT 24 Mar 31 12:28:35 PM PDT 24 101646056 ps
T829 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.269866844 Mar 31 12:28:10 PM PDT 24 Mar 31 12:28:11 PM PDT 24 13246237 ps
T830 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3467384825 Mar 31 12:28:09 PM PDT 24 Mar 31 12:28:10 PM PDT 24 263336276 ps
T831 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.837714765 Mar 31 12:27:52 PM PDT 24 Mar 31 12:27:56 PM PDT 24 45343827 ps
T367 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3541334353 Mar 31 12:28:10 PM PDT 24 Mar 31 12:28:30 PM PDT 24 1613626270 ps
T832 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.482180496 Mar 31 12:27:52 PM PDT 24 Mar 31 12:27:53 PM PDT 24 36721881 ps
T833 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2258521442 Mar 31 12:27:58 PM PDT 24 Mar 31 12:28:02 PM PDT 24 182911808 ps
T834 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2435908350 Mar 31 12:28:31 PM PDT 24 Mar 31 12:28:33 PM PDT 24 28878864 ps
T835 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.334749344 Mar 31 12:27:52 PM PDT 24 Mar 31 12:28:14 PM PDT 24 330002023 ps
T836 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1861017048 Mar 31 12:27:54 PM PDT 24 Mar 31 12:27:59 PM PDT 24 221303381 ps
T837 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.1523103628 Mar 31 12:28:19 PM PDT 24 Mar 31 12:28:20 PM PDT 24 18620897 ps
T838 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3683139920 Mar 31 12:27:57 PM PDT 24 Mar 31 12:28:08 PM PDT 24 748850611 ps
T839 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2257274550 Mar 31 12:28:05 PM PDT 24 Mar 31 12:28:32 PM PDT 24 3753689278 ps
T840 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.675408622 Mar 31 12:28:35 PM PDT 24 Mar 31 12:28:37 PM PDT 24 24542028 ps
T841 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.886410056 Mar 31 12:27:55 PM PDT 24 Mar 31 12:27:56 PM PDT 24 32248701 ps
T842 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.96663979 Mar 31 12:28:35 PM PDT 24 Mar 31 12:28:37 PM PDT 24 184400631 ps
T843 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1958864185 Mar 31 12:28:01 PM PDT 24 Mar 31 12:28:04 PM PDT 24 195658459 ps
T368 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1331267154 Mar 31 12:28:25 PM PDT 24 Mar 31 12:28:39 PM PDT 24 7767178157 ps
T844 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2092988647 Mar 31 12:27:51 PM PDT 24 Mar 31 12:27:53 PM PDT 24 53930045 ps
T845 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1198266359 Mar 31 12:28:24 PM PDT 24 Mar 31 12:28:43 PM PDT 24 323974120 ps
T846 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1201058576 Mar 31 12:28:01 PM PDT 24 Mar 31 12:28:07 PM PDT 24 107986214 ps
T847 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.139167371 Mar 31 12:28:24 PM PDT 24 Mar 31 12:28:31 PM PDT 24 95917519 ps
T848 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2386802648 Mar 31 12:27:57 PM PDT 24 Mar 31 12:27:59 PM PDT 24 113049955 ps
T849 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2948376627 Mar 31 12:27:57 PM PDT 24 Mar 31 12:28:00 PM PDT 24 170583283 ps
T850 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3082739629 Mar 31 12:27:56 PM PDT 24 Mar 31 12:27:58 PM PDT 24 40828449 ps

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.13286954
Short name T3
Test name
Test status
Simulation time 24622068279 ps
CPU time 16.98 seconds
Started Mar 31 01:25:52 PM PDT 24
Finished Mar 31 01:26:09 PM PDT 24
Peak memory 223820 kb
Host smart-7c2314fb-18a2-4a0d-ac95-839fa30a3cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13286954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap.13286954
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.321371241
Short name T16
Test name
Test status
Simulation time 3461263900 ps
CPU time 33.07 seconds
Started Mar 31 01:25:20 PM PDT 24
Finished Mar 31 01:25:53 PM PDT 24
Peak memory 217096 kb
Host smart-29ae86fa-b23f-4507-89d0-083e5733677a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321371241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.321371241
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3881985853
Short name T39
Test name
Test status
Simulation time 97579637 ps
CPU time 2.4 seconds
Started Mar 31 12:27:49 PM PDT 24
Finished Mar 31 12:27:52 PM PDT 24
Peak memory 216196 kb
Host smart-58bb6cae-1383-4bc2-a7d4-0209f96e4e33
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881985853 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.3881985853
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.4159420371
Short name T54
Test name
Test status
Simulation time 43031049810 ps
CPU time 132.05 seconds
Started Mar 31 01:23:48 PM PDT 24
Finished Mar 31 01:26:00 PM PDT 24
Peak memory 225012 kb
Host smart-d64d8a52-f10f-4757-84a0-2026ed49d625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159420371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.4159420371
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.1517002859
Short name T63
Test name
Test status
Simulation time 10299215419 ps
CPU time 52.49 seconds
Started Mar 31 01:25:02 PM PDT 24
Finished Mar 31 01:25:54 PM PDT 24
Peak memory 216816 kb
Host smart-d5b3b03d-ab23-4db2-bc57-61af8b244b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517002859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.1517002859
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.1483488621
Short name T26
Test name
Test status
Simulation time 356965225 ps
CPU time 3.36 seconds
Started Mar 31 01:24:40 PM PDT 24
Finished Mar 31 01:24:44 PM PDT 24
Peak memory 219216 kb
Host smart-2882e117-906a-4458-ab4d-a23334f127eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483488621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.1483488621
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.4220387802
Short name T11
Test name
Test status
Simulation time 757434480 ps
CPU time 17.12 seconds
Started Mar 31 01:24:05 PM PDT 24
Finished Mar 31 01:24:23 PM PDT 24
Peak memory 241364 kb
Host smart-176f8084-9c06-4f9b-b662-bb6441b47cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220387802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.4220387802
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.138697549
Short name T45
Test name
Test status
Simulation time 188078732 ps
CPU time 1.12 seconds
Started Mar 31 01:25:09 PM PDT 24
Finished Mar 31 01:25:11 PM PDT 24
Peak memory 207732 kb
Host smart-58c7b95b-2ddb-4f43-8269-49560ee971f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138697549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stres
s_all.138697549
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_upload.3620931800
Short name T51
Test name
Test status
Simulation time 28175689852 ps
CPU time 21.71 seconds
Started Mar 31 01:25:34 PM PDT 24
Finished Mar 31 01:25:55 PM PDT 24
Peak memory 227380 kb
Host smart-57e459e9-72c9-4b32-94cf-f8fb30414357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620931800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.3620931800
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_ram_cfg.3820720078
Short name T48
Test name
Test status
Simulation time 26124420 ps
CPU time 0.71 seconds
Started Mar 31 01:23:36 PM PDT 24
Finished Mar 31 01:23:37 PM PDT 24
Peak memory 216760 kb
Host smart-204bb736-47d4-4329-9feb-1d333f36e8c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820720078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_ram_cfg.3820720078
Directory /workspace/1.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.3545349811
Short name T5
Test name
Test status
Simulation time 2539143468 ps
CPU time 9.52 seconds
Started Mar 31 01:25:58 PM PDT 24
Finished Mar 31 01:26:07 PM PDT 24
Peak memory 220516 kb
Host smart-e24b5e57-2882-41e6-9c5f-d99a0513e406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545349811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.3545349811
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_upload.2067318070
Short name T6
Test name
Test status
Simulation time 9185235325 ps
CPU time 16.15 seconds
Started Mar 31 01:25:19 PM PDT 24
Finished Mar 31 01:25:36 PM PDT 24
Peak memory 241016 kb
Host smart-43e5c0c6-9111-4119-806b-9a1309cb52c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067318070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.2067318070
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.349151098
Short name T178
Test name
Test status
Simulation time 1842591718 ps
CPU time 25.04 seconds
Started Mar 31 01:25:11 PM PDT 24
Finished Mar 31 01:25:36 PM PDT 24
Peak memory 216832 kb
Host smart-e3607682-f962-4a0b-90c0-31315afa47f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349151098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.349151098
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_intercept.1340229717
Short name T53
Test name
Test status
Simulation time 463829672 ps
CPU time 5.1 seconds
Started Mar 31 01:25:28 PM PDT 24
Finished Mar 31 01:25:33 PM PDT 24
Peak memory 222896 kb
Host smart-33f6b9fa-e694-4c03-bab8-e9360dd77e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340229717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.1340229717
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.1164217692
Short name T516
Test name
Test status
Simulation time 8578433952 ps
CPU time 50.72 seconds
Started Mar 31 01:24:08 PM PDT 24
Finished Mar 31 01:24:59 PM PDT 24
Peak memory 216760 kb
Host smart-77286700-fe20-49c7-9f71-4df9bf4db2e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164217692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.1164217692
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.448501647
Short name T36
Test name
Test status
Simulation time 133490214 ps
CPU time 1.01 seconds
Started Mar 31 01:23:37 PM PDT 24
Finished Mar 31 01:23:39 PM PDT 24
Peak memory 235672 kb
Host smart-d41dd10c-a7f3-49b6-aa48-c5170c8a504f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448501647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.448501647
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.2819839526
Short name T76
Test name
Test status
Simulation time 1847638237 ps
CPU time 6.97 seconds
Started Mar 31 01:24:33 PM PDT 24
Finished Mar 31 01:24:41 PM PDT 24
Peak memory 220420 kb
Host smart-d12d0063-793d-43e6-ae15-0bc16f83c6e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819839526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.2819839526
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.2596496142
Short name T12
Test name
Test status
Simulation time 3414387362 ps
CPU time 36.74 seconds
Started Mar 31 01:25:20 PM PDT 24
Finished Mar 31 01:25:57 PM PDT 24
Peak memory 232108 kb
Host smart-75b715b0-ff61-4edc-b80a-888939713d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596496142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.2596496142
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.791686175
Short name T85
Test name
Test status
Simulation time 59805612418 ps
CPU time 37.03 seconds
Started Mar 31 01:24:47 PM PDT 24
Finished Mar 31 01:25:24 PM PDT 24
Peak memory 236468 kb
Host smart-47179fde-629b-491e-b989-3b9e3c70a264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791686175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap
.791686175
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1935245409
Short name T163
Test name
Test status
Simulation time 2056820683 ps
CPU time 21.84 seconds
Started Mar 31 12:28:04 PM PDT 24
Finished Mar 31 12:28:31 PM PDT 24
Peak memory 215476 kb
Host smart-37de0651-5404-4a1c-80a5-96e95bbc2d77
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935245409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.1935245409
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.1536240090
Short name T94
Test name
Test status
Simulation time 851807896 ps
CPU time 6.57 seconds
Started Mar 31 01:25:28 PM PDT 24
Finished Mar 31 01:25:35 PM PDT 24
Peak memory 223988 kb
Host smart-e69b681d-cf15-4321-858a-16fedd0b5c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536240090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.1536240090
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.3766982124
Short name T256
Test name
Test status
Simulation time 1469766861 ps
CPU time 13.48 seconds
Started Mar 31 01:24:51 PM PDT 24
Finished Mar 31 01:25:05 PM PDT 24
Peak memory 228732 kb
Host smart-6d37d75d-fd58-4d3c-a1cb-5fc1d396c1c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766982124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.3766982124
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3575066119
Short name T146
Test name
Test status
Simulation time 497543535 ps
CPU time 1.8 seconds
Started Mar 31 12:27:59 PM PDT 24
Finished Mar 31 12:28:01 PM PDT 24
Peak memory 215076 kb
Host smart-4eaeaa4e-16b6-4165-8216-fe32e327a314
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575066119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
3575066119
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2366089699
Short name T131
Test name
Test status
Simulation time 871818820 ps
CPU time 4.83 seconds
Started Mar 31 12:28:00 PM PDT 24
Finished Mar 31 12:28:04 PM PDT 24
Peak memory 215388 kb
Host smart-52c9e599-75b1-4657-a770-f826d71ecd5a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366089699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2
366089699
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/default/31.spi_device_upload.2911543741
Short name T221
Test name
Test status
Simulation time 1964450706 ps
CPU time 9.84 seconds
Started Mar 31 01:25:14 PM PDT 24
Finished Mar 31 01:25:25 PM PDT 24
Peak memory 222272 kb
Host smart-ccf90952-448d-43c8-9b7e-a3adf554c28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911543741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.2911543741
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.2966669655
Short name T236
Test name
Test status
Simulation time 400338005 ps
CPU time 5.31 seconds
Started Mar 31 01:24:26 PM PDT 24
Finished Mar 31 01:24:32 PM PDT 24
Peak memory 217108 kb
Host smart-2589f921-07c8-40de-87b0-5092c318b686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966669655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.2966669655
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.652369107
Short name T341
Test name
Test status
Simulation time 4114761638 ps
CPU time 15.26 seconds
Started Mar 31 01:24:45 PM PDT 24
Finished Mar 31 01:25:00 PM PDT 24
Peak memory 224064 kb
Host smart-7f8b0fc9-d289-4bb1-8491-b552563d8491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652369107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap
.652369107
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.2997748553
Short name T114
Test name
Test status
Simulation time 26962681581 ps
CPU time 26.03 seconds
Started Mar 31 01:24:48 PM PDT 24
Finished Mar 31 01:25:14 PM PDT 24
Peak memory 216828 kb
Host smart-2f566e9e-f8f6-4d33-ad48-8faf2de463ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997748553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.2997748553
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_upload.949457367
Short name T283
Test name
Test status
Simulation time 6094112772 ps
CPU time 14.76 seconds
Started Mar 31 01:24:31 PM PDT 24
Finished Mar 31 01:24:45 PM PDT 24
Peak memory 232696 kb
Host smart-863ab5e1-34cd-4030-88d4-3e77a15bc432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949457367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.949457367
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_intercept.2084946533
Short name T121
Test name
Test status
Simulation time 4214560268 ps
CPU time 17.78 seconds
Started Mar 31 01:25:37 PM PDT 24
Finished Mar 31 01:25:55 PM PDT 24
Peak memory 233268 kb
Host smart-9af31665-44c6-437b-b8b9-441ccf4b8d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084946533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.2084946533
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.3813341350
Short name T385
Test name
Test status
Simulation time 11946599828 ps
CPU time 70.83 seconds
Started Mar 31 01:25:46 PM PDT 24
Finished Mar 31 01:26:57 PM PDT 24
Peak memory 216736 kb
Host smart-662a9f22-c58b-450e-813c-8c9799bd16b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813341350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.3813341350
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.2576983532
Short name T359
Test name
Test status
Simulation time 10116199237 ps
CPU time 9.16 seconds
Started Mar 31 01:24:13 PM PDT 24
Finished Mar 31 01:24:23 PM PDT 24
Peak memory 220348 kb
Host smart-4569cb33-1609-4e34-a08c-d05642eaab0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576983532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.2576983532
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_intercept.207252959
Short name T102
Test name
Test status
Simulation time 13325249943 ps
CPU time 30.4 seconds
Started Mar 31 01:23:51 PM PDT 24
Finished Mar 31 01:24:22 PM PDT 24
Peak memory 225056 kb
Host smart-d6efb77b-4aa0-4e15-ba55-25807f92fea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207252959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.207252959
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.806469145
Short name T302
Test name
Test status
Simulation time 7945067183 ps
CPU time 119.41 seconds
Started Mar 31 01:25:36 PM PDT 24
Finished Mar 31 01:27:35 PM PDT 24
Peak memory 235512 kb
Host smart-c4278f9c-c4e4-4fdf-990c-e1d4d1236c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806469145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.806469145
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.1451799846
Short name T198
Test name
Test status
Simulation time 887992354 ps
CPU time 7.32 seconds
Started Mar 31 01:24:23 PM PDT 24
Finished Mar 31 01:24:31 PM PDT 24
Peak memory 232844 kb
Host smart-5bf83412-ae01-403e-8e05-8e7cf23b10ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451799846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.1451799846
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.3377827158
Short name T19
Test name
Test status
Simulation time 1078695522 ps
CPU time 7.86 seconds
Started Mar 31 01:24:41 PM PDT 24
Finished Mar 31 01:24:49 PM PDT 24
Peak memory 216676 kb
Host smart-1b5ffae3-e7aa-4bce-8676-4cc5d364b448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377827158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.3377827158
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.3740574171
Short name T296
Test name
Test status
Simulation time 3610264159 ps
CPU time 10.14 seconds
Started Mar 31 01:23:42 PM PDT 24
Finished Mar 31 01:23:52 PM PDT 24
Peak memory 218936 kb
Host smart-4cb26b06-be71-4ef2-aa47-8321476a6207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740574171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.3740574171
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_upload.1572586420
Short name T269
Test name
Test status
Simulation time 3831736600 ps
CPU time 7.77 seconds
Started Mar 31 01:24:27 PM PDT 24
Finished Mar 31 01:24:36 PM PDT 24
Peak memory 221648 kb
Host smart-efd44c20-9a03-4083-b823-4b991f65441a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572586420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.1572586420
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.2850280616
Short name T324
Test name
Test status
Simulation time 2245391133 ps
CPU time 18.53 seconds
Started Mar 31 01:25:46 PM PDT 24
Finished Mar 31 01:26:05 PM PDT 24
Peak memory 224756 kb
Host smart-eb6afbaa-4a04-437a-8439-b3dd7389d774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850280616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.2850280616
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_upload.3318107315
Short name T7
Test name
Test status
Simulation time 1549761986 ps
CPU time 13.01 seconds
Started Mar 31 01:24:30 PM PDT 24
Finished Mar 31 01:24:43 PM PDT 24
Peak memory 237076 kb
Host smart-51832acd-0887-454d-a3b2-e187a7ccd894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318107315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.3318107315
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.4160867077
Short name T194
Test name
Test status
Simulation time 641758395 ps
CPU time 7.55 seconds
Started Mar 31 01:25:09 PM PDT 24
Finished Mar 31 01:25:17 PM PDT 24
Peak memory 224720 kb
Host smart-5ad1085c-89d8-458d-adc6-ff76f7b8faed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160867077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.4160867077
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.2935993580
Short name T204
Test name
Test status
Simulation time 752572642 ps
CPU time 4.24 seconds
Started Mar 31 01:24:57 PM PDT 24
Finished Mar 31 01:25:01 PM PDT 24
Peak memory 218936 kb
Host smart-f6e2e2d3-d09f-451c-9b63-7e265b3d8aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935993580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.2935993580
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.3753195618
Short name T241
Test name
Test status
Simulation time 393845817 ps
CPU time 5.48 seconds
Started Mar 31 01:25:26 PM PDT 24
Finished Mar 31 01:25:32 PM PDT 24
Peak memory 237316 kb
Host smart-39beb9c8-eae6-474d-b77c-fba9b65697e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753195618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.3753195618
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_intercept.107021591
Short name T290
Test name
Test status
Simulation time 15388613402 ps
CPU time 32.18 seconds
Started Mar 31 01:25:13 PM PDT 24
Finished Mar 31 01:25:46 PM PDT 24
Peak memory 217304 kb
Host smart-f1dc5b69-ccfe-4c34-8f15-896b96ecafa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107021591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.107021591
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_upload.2144850842
Short name T254
Test name
Test status
Simulation time 25274391728 ps
CPU time 39.48 seconds
Started Mar 31 01:24:41 PM PDT 24
Finished Mar 31 01:25:21 PM PDT 24
Peak memory 233196 kb
Host smart-ecf29e8e-2309-47e0-a502-99b3b8fc7f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144850842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.2144850842
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_upload.2662202026
Short name T187
Test name
Test status
Simulation time 390765166 ps
CPU time 4.15 seconds
Started Mar 31 01:25:13 PM PDT 24
Finished Mar 31 01:25:17 PM PDT 24
Peak memory 232840 kb
Host smart-06a52bb8-0aca-43e4-a8a1-ad76f78b512a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662202026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.2662202026
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_upload.4287781645
Short name T252
Test name
Test status
Simulation time 358352901 ps
CPU time 6.24 seconds
Started Mar 31 01:26:00 PM PDT 24
Finished Mar 31 01:26:06 PM PDT 24
Peak memory 221948 kb
Host smart-c09f3001-0d3d-4fd4-aa8e-2551bf4a5538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287781645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.4287781645
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.964612229
Short name T95
Test name
Test status
Simulation time 6699741501 ps
CPU time 61.37 seconds
Started Mar 31 01:23:57 PM PDT 24
Finished Mar 31 01:24:58 PM PDT 24
Peak memory 233236 kb
Host smart-440aefba-ca41-4708-a3ae-9492fb37bc99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964612229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.964612229
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.3356826685
Short name T253
Test name
Test status
Simulation time 10644164505 ps
CPU time 16.02 seconds
Started Mar 31 01:24:04 PM PDT 24
Finished Mar 31 01:24:20 PM PDT 24
Peak memory 221252 kb
Host smart-4bd30b23-9823-4e5a-8bd0-86ca92a1e66e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356826685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.3356826685
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.3004159745
Short name T412
Test name
Test status
Simulation time 15711263 ps
CPU time 0.74 seconds
Started Mar 31 01:24:18 PM PDT 24
Finished Mar 31 01:24:18 PM PDT 24
Peak memory 206000 kb
Host smart-3c8a8f87-299f-41f7-99a1-281943400fc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004159745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
3004159745
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.2002898126
Short name T298
Test name
Test status
Simulation time 5332172787 ps
CPU time 7.34 seconds
Started Mar 31 01:23:37 PM PDT 24
Finished Mar 31 01:23:44 PM PDT 24
Peak memory 223092 kb
Host smart-7cd22163-b475-4415-8de0-afa3ff0356e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002898126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.2002898126
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.326070411
Short name T72
Test name
Test status
Simulation time 6838164958 ps
CPU time 10.06 seconds
Started Mar 31 01:25:26 PM PDT 24
Finished Mar 31 01:25:37 PM PDT 24
Peak memory 235228 kb
Host smart-e82ae6de-e0a3-4971-906a-f9e57c359e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326070411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swap
.326070411
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.414842936
Short name T171
Test name
Test status
Simulation time 2233061340 ps
CPU time 20.4 seconds
Started Mar 31 01:25:34 PM PDT 24
Finished Mar 31 01:25:55 PM PDT 24
Peak memory 227308 kb
Host smart-b8f5d9be-bca5-4c93-b2b2-efbe47fe5270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414842936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.414842936
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.4191562221
Short name T58
Test name
Test status
Simulation time 9839284528 ps
CPU time 44.1 seconds
Started Mar 31 01:23:37 PM PDT 24
Finished Mar 31 01:24:22 PM PDT 24
Peak memory 240632 kb
Host smart-20f25807-9058-4768-8141-41d1e34d51b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191562221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.4191562221
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.594576027
Short name T346
Test name
Test status
Simulation time 484991874 ps
CPU time 3.33 seconds
Started Mar 31 01:24:26 PM PDT 24
Finished Mar 31 01:24:29 PM PDT 24
Peak memory 219572 kb
Host smart-6c80c610-5c6d-4011-9783-669386196b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594576027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.594576027
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.3267928213
Short name T261
Test name
Test status
Simulation time 5111645462 ps
CPU time 29.99 seconds
Started Mar 31 01:24:30 PM PDT 24
Finished Mar 31 01:25:00 PM PDT 24
Peak memory 236548 kb
Host smart-4a65726d-ae14-4bb2-abcb-2ce586e65d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267928213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.3267928213
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.2429325764
Short name T337
Test name
Test status
Simulation time 170294169 ps
CPU time 2.56 seconds
Started Mar 31 01:23:38 PM PDT 24
Finished Mar 31 01:23:41 PM PDT 24
Peak memory 223484 kb
Host smart-5a1bb512-6860-4adc-8255-a9430ce623b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429325764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.2429325764
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.646829155
Short name T339
Test name
Test status
Simulation time 1110911816 ps
CPU time 6.18 seconds
Started Mar 31 01:24:51 PM PDT 24
Finished Mar 31 01:24:57 PM PDT 24
Peak memory 224640 kb
Host smart-2aff0268-3924-4137-82d6-ee395b4e1d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646829155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap
.646829155
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_upload.2131293607
Short name T278
Test name
Test status
Simulation time 2420374995 ps
CPU time 13.66 seconds
Started Mar 31 01:25:48 PM PDT 24
Finished Mar 31 01:26:02 PM PDT 24
Peak memory 224976 kb
Host smart-edb8a89c-8107-43da-a2c2-e77c8f465215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131293607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.2131293607
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.2964653737
Short name T71
Test name
Test status
Simulation time 3120003190 ps
CPU time 9.04 seconds
Started Mar 31 01:25:33 PM PDT 24
Finished Mar 31 01:25:42 PM PDT 24
Peak memory 219920 kb
Host smart-027838d9-0acb-43d3-9a11-2a8e21a81bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964653737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.2964653737
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2889382579
Short name T366
Test name
Test status
Simulation time 2094522087 ps
CPU time 21.09 seconds
Started Mar 31 12:27:57 PM PDT 24
Finished Mar 31 12:28:18 PM PDT 24
Peak memory 215036 kb
Host smart-d65fe4cf-fe7c-4907-9e85-e143bfea307b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889382579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.2889382579
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/14.spi_device_intercept.953700302
Short name T348
Test name
Test status
Simulation time 291167482 ps
CPU time 6.41 seconds
Started Mar 31 01:24:29 PM PDT 24
Finished Mar 31 01:24:36 PM PDT 24
Peak memory 234388 kb
Host smart-a9e9d860-79b0-4f81-b977-54bde8ac55bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953700302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.953700302
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.1600160393
Short name T219
Test name
Test status
Simulation time 938208600 ps
CPU time 5.54 seconds
Started Mar 31 01:24:27 PM PDT 24
Finished Mar 31 01:24:33 PM PDT 24
Peak memory 222844 kb
Host smart-ec60c0ce-3f48-40a8-9585-98b7c5731572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600160393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.1600160393
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.2358471892
Short name T87
Test name
Test status
Simulation time 2546077370 ps
CPU time 9.31 seconds
Started Mar 31 01:24:28 PM PDT 24
Finished Mar 31 01:24:37 PM PDT 24
Peak memory 238896 kb
Host smart-8c71361b-079a-43e4-8949-00beaa9465ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358471892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.2358471892
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.129811397
Short name T262
Test name
Test status
Simulation time 434757846 ps
CPU time 9.94 seconds
Started Mar 31 01:24:31 PM PDT 24
Finished Mar 31 01:24:41 PM PDT 24
Peak memory 219152 kb
Host smart-f06719e8-33d9-4af6-add1-ff099d39f286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129811397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.129811397
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.180641763
Short name T197
Test name
Test status
Simulation time 2627059280 ps
CPU time 16.62 seconds
Started Mar 31 01:24:40 PM PDT 24
Finished Mar 31 01:24:57 PM PDT 24
Peak memory 231312 kb
Host smart-131675c4-013c-44b4-bd0d-a6726d3fefd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180641763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.180641763
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.785205550
Short name T376
Test name
Test status
Simulation time 50337669573 ps
CPU time 35.47 seconds
Started Mar 31 01:24:53 PM PDT 24
Finished Mar 31 01:25:29 PM PDT 24
Peak memory 216812 kb
Host smart-0225accb-478b-4273-8699-52ca13140509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785205550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.785205550
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.4177581712
Short name T89
Test name
Test status
Simulation time 74606662441 ps
CPU time 19.28 seconds
Started Mar 31 01:24:55 PM PDT 24
Finished Mar 31 01:25:15 PM PDT 24
Peak memory 227180 kb
Host smart-38873fa8-1fd7-4179-a70e-eb45dc7312be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177581712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.4177581712
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.258824320
Short name T208
Test name
Test status
Simulation time 2011701611 ps
CPU time 11.99 seconds
Started Mar 31 01:25:06 PM PDT 24
Finished Mar 31 01:25:18 PM PDT 24
Peak memory 224396 kb
Host smart-68759e8d-86b7-4273-9ac5-108f15cc59f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258824320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.258824320
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.2908520599
Short name T68
Test name
Test status
Simulation time 2056366280 ps
CPU time 13.88 seconds
Started Mar 31 01:25:24 PM PDT 24
Finished Mar 31 01:25:38 PM PDT 24
Peak memory 235776 kb
Host smart-7c071aaa-eb5b-4dec-9697-41916437b963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908520599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.2908520599
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.3278614739
Short name T119
Test name
Test status
Simulation time 337423449260 ps
CPU time 344.82 seconds
Started Mar 31 01:25:22 PM PDT 24
Finished Mar 31 01:31:07 PM PDT 24
Peak memory 240108 kb
Host smart-1cdb7971-557d-46cc-9453-c8bb0ad06c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278614739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.3278614739
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.3765792967
Short name T113
Test name
Test status
Simulation time 1825756852 ps
CPU time 18.14 seconds
Started Mar 31 01:25:53 PM PDT 24
Finished Mar 31 01:26:12 PM PDT 24
Peak memory 216760 kb
Host smart-c0ad62b8-4084-4104-9114-0b63407ec4e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765792967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3765792967
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.2312925038
Short name T295
Test name
Test status
Simulation time 8291908723 ps
CPU time 14.63 seconds
Started Mar 31 01:24:34 PM PDT 24
Finished Mar 31 01:24:48 PM PDT 24
Peak memory 236528 kb
Host smart-ca6dfa85-dc00-434d-b3bc-e3792a4bdd4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312925038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.2312925038
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1265473390
Short name T364
Test name
Test status
Simulation time 237891984 ps
CPU time 4.32 seconds
Started Mar 31 12:28:00 PM PDT 24
Finished Mar 31 12:28:05 PM PDT 24
Peak memory 216232 kb
Host smart-a67bf4c5-03aa-48c1-a1bc-13781a015e18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265473390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.1
265473390
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2682939762
Short name T371
Test name
Test status
Simulation time 1121301851 ps
CPU time 16.66 seconds
Started Mar 31 12:27:59 PM PDT 24
Finished Mar 31 12:28:16 PM PDT 24
Peak memory 215112 kb
Host smart-c08f7013-81c5-4517-9ada-d6c5151c0165
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682939762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.2682939762
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_intercept.2144021441
Short name T272
Test name
Test status
Simulation time 52056840165 ps
CPU time 35.85 seconds
Started Mar 31 01:23:30 PM PDT 24
Finished Mar 31 01:24:06 PM PDT 24
Peak memory 224372 kb
Host smart-fa614792-d08b-41ce-a7c0-c8544a249211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144021441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.2144021441
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.114269434
Short name T250
Test name
Test status
Simulation time 8006462582 ps
CPU time 23.99 seconds
Started Mar 31 01:23:35 PM PDT 24
Finished Mar 31 01:23:59 PM PDT 24
Peak memory 233356 kb
Host smart-0a386690-9ea0-4096-b883-74b0056de7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114269434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.114269434
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_upload.3164168263
Short name T285
Test name
Test status
Simulation time 44234966425 ps
CPU time 15.48 seconds
Started Mar 31 01:23:36 PM PDT 24
Finished Mar 31 01:23:52 PM PDT 24
Peak memory 220680 kb
Host smart-b51e6238-e930-4556-aaff-78c79db5f48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164168263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.3164168263
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.859425817
Short name T276
Test name
Test status
Simulation time 317549492 ps
CPU time 2.92 seconds
Started Mar 31 01:24:05 PM PDT 24
Finished Mar 31 01:24:09 PM PDT 24
Peak memory 223184 kb
Host smart-eee0acc0-5641-433f-93ea-aa049a3fb957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859425817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.859425817
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.2304241871
Short name T231
Test name
Test status
Simulation time 15517318299 ps
CPU time 24.47 seconds
Started Mar 31 01:24:16 PM PDT 24
Finished Mar 31 01:24:41 PM PDT 24
Peak memory 236560 kb
Host smart-2775ed98-8bd2-472d-b905-67f0406b07f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304241871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.2304241871
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.1858133597
Short name T18
Test name
Test status
Simulation time 79588913 ps
CPU time 1.29 seconds
Started Mar 31 01:24:19 PM PDT 24
Finished Mar 31 01:24:20 PM PDT 24
Peak memory 208580 kb
Host smart-2d665ba0-586a-4f4f-a431-d7c88b6129c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858133597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1858133597
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.1797241586
Short name T186
Test name
Test status
Simulation time 578885799 ps
CPU time 6.56 seconds
Started Mar 31 01:24:14 PM PDT 24
Finished Mar 31 01:24:21 PM PDT 24
Peak memory 223292 kb
Host smart-42499ed2-14d4-4b68-812e-f805ad0e931a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797241586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.1797241586
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_intercept.1521433493
Short name T239
Test name
Test status
Simulation time 946251382 ps
CPU time 9.48 seconds
Started Mar 31 01:24:21 PM PDT 24
Finished Mar 31 01:24:31 PM PDT 24
Peak memory 223532 kb
Host smart-583fa6b9-238e-4ea7-82d1-f591835acf13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521433493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.1521433493
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.3588007952
Short name T275
Test name
Test status
Simulation time 3858158159 ps
CPU time 4.97 seconds
Started Mar 31 01:24:34 PM PDT 24
Finished Mar 31 01:24:39 PM PDT 24
Peak memory 223200 kb
Host smart-fae14b24-83a1-45ed-a84f-6850c8d937c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588007952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.3588007952
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.2050998137
Short name T326
Test name
Test status
Simulation time 8295124351 ps
CPU time 18.26 seconds
Started Mar 31 01:24:36 PM PDT 24
Finished Mar 31 01:24:54 PM PDT 24
Peak memory 238476 kb
Host smart-9ea5e800-6d1b-487d-a6ed-0404bb82fbd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050998137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.2050998137
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_upload.3651032467
Short name T206
Test name
Test status
Simulation time 4704186581 ps
CPU time 16.95 seconds
Started Mar 31 01:24:33 PM PDT 24
Finished Mar 31 01:24:51 PM PDT 24
Peak memory 232812 kb
Host smart-f7ba42d1-1835-484f-9051-83e527d479e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651032467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.3651032467
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.1196082539
Short name T259
Test name
Test status
Simulation time 27443011652 ps
CPU time 24.61 seconds
Started Mar 31 01:24:46 PM PDT 24
Finished Mar 31 01:25:10 PM PDT 24
Peak memory 233204 kb
Host smart-6f59a1a6-ee96-4b3e-b65b-a7b4841138a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196082539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.1196082539
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_upload.1549772224
Short name T286
Test name
Test status
Simulation time 43603624285 ps
CPU time 36.04 seconds
Started Mar 31 01:25:03 PM PDT 24
Finished Mar 31 01:25:39 PM PDT 24
Peak memory 233108 kb
Host smart-32a124df-5a36-4e98-92b5-3dfaa307e303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549772224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.1549772224
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.3608194626
Short name T280
Test name
Test status
Simulation time 248389245 ps
CPU time 3.13 seconds
Started Mar 31 01:25:07 PM PDT 24
Finished Mar 31 01:25:11 PM PDT 24
Peak memory 222692 kb
Host smart-0c6e892e-48d8-40fd-9eb0-4c0606df1d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608194626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.3608194626
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_intercept.3446622937
Short name T211
Test name
Test status
Simulation time 292695692 ps
CPU time 3.74 seconds
Started Mar 31 01:25:04 PM PDT 24
Finished Mar 31 01:25:08 PM PDT 24
Peak memory 221652 kb
Host smart-e788262e-09ce-496e-ab84-ffa29c169378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446622937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.3446622937
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.2315135742
Short name T83
Test name
Test status
Simulation time 7197096983 ps
CPU time 5.59 seconds
Started Mar 31 01:25:22 PM PDT 24
Finished Mar 31 01:25:28 PM PDT 24
Peak memory 232976 kb
Host smart-e7c78fc2-18f0-42e1-9fec-b106e29c791f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315135742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.2315135742
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.134189666
Short name T73
Test name
Test status
Simulation time 12463313681 ps
CPU time 19.59 seconds
Started Mar 31 01:25:25 PM PDT 24
Finished Mar 31 01:25:46 PM PDT 24
Peak memory 237100 kb
Host smart-fd6d4687-0bee-40a6-ba9f-2969cb58547e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134189666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.134189666
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.1418918332
Short name T255
Test name
Test status
Simulation time 29414344276 ps
CPU time 27.5 seconds
Started Mar 31 01:25:38 PM PDT 24
Finished Mar 31 01:26:06 PM PDT 24
Peak memory 236872 kb
Host smart-d4513a6f-cbdc-47e4-b1ca-7ffc19ed4673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418918332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.1418918332
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.1217946091
Short name T265
Test name
Test status
Simulation time 36802865269 ps
CPU time 25.32 seconds
Started Mar 31 01:25:18 PM PDT 24
Finished Mar 31 01:25:44 PM PDT 24
Peak memory 228952 kb
Host smart-9c22f83b-d4c5-4d01-9283-3922eacce221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217946091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.1217946091
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.2128212038
Short name T183
Test name
Test status
Simulation time 416573913 ps
CPU time 2.79 seconds
Started Mar 31 01:25:26 PM PDT 24
Finished Mar 31 01:25:29 PM PDT 24
Peak memory 222856 kb
Host smart-b352ea87-74cd-4453-8dfb-e03165e6d677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128212038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.2128212038
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.463468775
Short name T86
Test name
Test status
Simulation time 443479717 ps
CPU time 2.48 seconds
Started Mar 31 01:25:40 PM PDT 24
Finished Mar 31 01:25:43 PM PDT 24
Peak memory 217140 kb
Host smart-d78b57e0-abc5-4fc1-9b10-81374788906b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463468775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap
.463468775
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.2301156332
Short name T300
Test name
Test status
Simulation time 23519733231 ps
CPU time 81.24 seconds
Started Mar 31 01:25:59 PM PDT 24
Finished Mar 31 01:27:21 PM PDT 24
Peak memory 241248 kb
Host smart-46a4acef-0a8d-4fb5-a3e9-734f2444abc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301156332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.2301156332
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_upload.2074834411
Short name T227
Test name
Test status
Simulation time 13374015572 ps
CPU time 22.71 seconds
Started Mar 31 01:25:57 PM PDT 24
Finished Mar 31 01:26:20 PM PDT 24
Peak memory 237992 kb
Host smart-1d8aae1c-a93a-4a49-bdbd-73eaeea2ba44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074834411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.2074834411
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.677900457
Short name T215
Test name
Test status
Simulation time 16831367415 ps
CPU time 12.87 seconds
Started Mar 31 01:25:58 PM PDT 24
Finished Mar 31 01:26:11 PM PDT 24
Peak memory 223256 kb
Host smart-745c5902-9327-413f-a7de-3f72da96a966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677900457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap
.677900457
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.1483272147
Short name T190
Test name
Test status
Simulation time 14662347656 ps
CPU time 116.46 seconds
Started Mar 31 01:26:10 PM PDT 24
Finished Mar 31 01:28:06 PM PDT 24
Peak memory 235804 kb
Host smart-9171a416-8202-4b99-adcd-1fb8f7ee1cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483272147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.1483272147
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.2152642505
Short name T310
Test name
Test status
Simulation time 3544112691 ps
CPU time 53.93 seconds
Started Mar 31 01:23:28 PM PDT 24
Finished Mar 31 01:24:22 PM PDT 24
Peak memory 253780 kb
Host smart-274becc5-ebb4-44f6-96ed-079ead0c03f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152642505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.2152642505
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.2030809925
Short name T88
Test name
Test status
Simulation time 6735649761 ps
CPU time 12.13 seconds
Started Mar 31 01:23:30 PM PDT 24
Finished Mar 31 01:23:42 PM PDT 24
Peak memory 217180 kb
Host smart-97a4c91a-fe98-4e54-8d50-ffe5ece52c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030809925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.2030809925
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.878207020
Short name T386
Test name
Test status
Simulation time 2594308167 ps
CPU time 25.45 seconds
Started Mar 31 01:23:30 PM PDT 24
Finished Mar 31 01:23:56 PM PDT 24
Peak memory 220296 kb
Host smart-a73a5b1f-bd7a-4111-b8ae-0e540a9032ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878207020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.878207020
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_intercept.2395590807
Short name T321
Test name
Test status
Simulation time 356319410 ps
CPU time 5.33 seconds
Started Mar 31 01:23:36 PM PDT 24
Finished Mar 31 01:23:41 PM PDT 24
Peak memory 219300 kb
Host smart-f7afd044-eee2-4bef-b9d7-a3ce027d2241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395590807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.2395590807
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.554783331
Short name T356
Test name
Test status
Simulation time 281649285 ps
CPU time 9.58 seconds
Started Mar 31 01:24:16 PM PDT 24
Finished Mar 31 01:24:26 PM PDT 24
Peak memory 233188 kb
Host smart-23e2ded9-1ce9-4a2e-8983-7584548e33f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554783331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.554783331
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.3824027760
Short name T329
Test name
Test status
Simulation time 4943148570 ps
CPU time 14.3 seconds
Started Mar 31 01:24:13 PM PDT 24
Finished Mar 31 01:24:27 PM PDT 24
Peak memory 224988 kb
Host smart-fb8117d2-32c1-472d-a005-bd965acc343a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824027760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.3824027760
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.2738546152
Short name T331
Test name
Test status
Simulation time 2654871170 ps
CPU time 7.71 seconds
Started Mar 31 01:24:23 PM PDT 24
Finished Mar 31 01:24:31 PM PDT 24
Peak memory 224888 kb
Host smart-21f45b4c-98da-4ed2-a955-3cde76b39d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738546152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.2738546152
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.3881135331
Short name T351
Test name
Test status
Simulation time 705983175 ps
CPU time 10.89 seconds
Started Mar 31 01:24:22 PM PDT 24
Finished Mar 31 01:24:33 PM PDT 24
Peak memory 233152 kb
Host smart-7b603886-dc87-4ce9-be2f-38b3aaf35c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881135331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.3881135331
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.2872144020
Short name T246
Test name
Test status
Simulation time 116740650 ps
CPU time 2.4 seconds
Started Mar 31 01:24:12 PM PDT 24
Finished Mar 31 01:24:15 PM PDT 24
Peak memory 218836 kb
Host smart-359ced66-35c5-446a-8a6c-d4627f9349a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872144020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.2872144020
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.621593756
Short name T82
Test name
Test status
Simulation time 743517009 ps
CPU time 5.8 seconds
Started Mar 31 01:24:16 PM PDT 24
Finished Mar 31 01:24:23 PM PDT 24
Peak memory 236424 kb
Host smart-06d48f18-bf9f-4cfd-96b1-155b7ca8e630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621593756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap
.621593756
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.351582963
Short name T257
Test name
Test status
Simulation time 8504158643 ps
CPU time 26.72 seconds
Started Mar 31 01:24:22 PM PDT 24
Finished Mar 31 01:24:49 PM PDT 24
Peak memory 234648 kb
Host smart-3b2c7ca1-0adb-4b55-adc7-4cd59b42545c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351582963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap
.351582963
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.1292270992
Short name T268
Test name
Test status
Simulation time 4471134620 ps
CPU time 19.56 seconds
Started Mar 31 01:24:20 PM PDT 24
Finished Mar 31 01:24:40 PM PDT 24
Peak memory 223932 kb
Host smart-18c72bac-de0e-4704-b545-43e7f4db1120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292270992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.1292270992
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.1062348816
Short name T293
Test name
Test status
Simulation time 12496210757 ps
CPU time 12.8 seconds
Started Mar 31 01:24:28 PM PDT 24
Finished Mar 31 01:24:41 PM PDT 24
Peak memory 239336 kb
Host smart-dce9ba99-8748-4c6e-8505-cf85539ee97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062348816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.1062348816
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.3260847534
Short name T84
Test name
Test status
Simulation time 9449514143 ps
CPU time 11.8 seconds
Started Mar 31 01:24:45 PM PDT 24
Finished Mar 31 01:24:56 PM PDT 24
Peak memory 219260 kb
Host smart-b7e1a798-62fa-46e8-9f43-2b282cd33545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260847534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.3260847534
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.2527319620
Short name T287
Test name
Test status
Simulation time 44719297236 ps
CPU time 9.18 seconds
Started Mar 31 01:24:38 PM PDT 24
Finished Mar 31 01:24:47 PM PDT 24
Peak memory 219016 kb
Host smart-401ef40f-c6d0-4f02-a8fb-a3c9760a5ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527319620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.2527319620
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_upload.3778286605
Short name T223
Test name
Test status
Simulation time 2095003907 ps
CPU time 8.57 seconds
Started Mar 31 01:24:44 PM PDT 24
Finished Mar 31 01:24:53 PM PDT 24
Peak memory 240804 kb
Host smart-59fc6f33-d6ca-4fd3-a84a-da198e97bc21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778286605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.3778286605
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.3028124756
Short name T314
Test name
Test status
Simulation time 811473019 ps
CPU time 5.05 seconds
Started Mar 31 01:23:43 PM PDT 24
Finished Mar 31 01:23:48 PM PDT 24
Peak memory 218912 kb
Host smart-fdf942cf-c671-42fb-9edc-5aa180bd9669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028124756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.3028124756
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.2296585690
Short name T222
Test name
Test status
Simulation time 598373671 ps
CPU time 6.28 seconds
Started Mar 31 01:23:37 PM PDT 24
Finished Mar 31 01:23:44 PM PDT 24
Peak memory 224536 kb
Host smart-c7c30461-e558-4e2a-a914-52308b20f39e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296585690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.2296585690
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.3111395558
Short name T75
Test name
Test status
Simulation time 2154322363 ps
CPU time 8.66 seconds
Started Mar 31 01:24:42 PM PDT 24
Finished Mar 31 01:24:51 PM PDT 24
Peak memory 238348 kb
Host smart-24ae05e8-91e4-4eb1-af1a-8b6a1e3792f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111395558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.3111395558
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_upload.59003174
Short name T294
Test name
Test status
Simulation time 7556984697 ps
CPU time 7.83 seconds
Started Mar 31 01:24:40 PM PDT 24
Finished Mar 31 01:24:48 PM PDT 24
Peak memory 223752 kb
Host smart-99e7cbb0-8b1b-4fe2-9af4-005dd3e9ec04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59003174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.59003174
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_intercept.715566176
Short name T226
Test name
Test status
Simulation time 2632997472 ps
CPU time 8.79 seconds
Started Mar 31 01:24:42 PM PDT 24
Finished Mar 31 01:24:51 PM PDT 24
Peak memory 222732 kb
Host smart-985b5539-68ab-4f06-ab94-9fdce50abe37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715566176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.715566176
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.4080710100
Short name T10
Test name
Test status
Simulation time 7486933810 ps
CPU time 19.73 seconds
Started Mar 31 01:24:56 PM PDT 24
Finished Mar 31 01:25:15 PM PDT 24
Peak memory 249524 kb
Host smart-82c8df4d-ad21-4f04-bebb-95657dad095c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080710100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.4080710100
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.197608417
Short name T92
Test name
Test status
Simulation time 3732120583 ps
CPU time 40.56 seconds
Started Mar 31 01:25:06 PM PDT 24
Finished Mar 31 01:25:47 PM PDT 24
Peak memory 232136 kb
Host smart-2e8f99e1-2ee1-483f-941d-f04f545ebb7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197608417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.197608417
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.799234747
Short name T235
Test name
Test status
Simulation time 1036288331 ps
CPU time 6.58 seconds
Started Mar 31 01:24:57 PM PDT 24
Finished Mar 31 01:25:04 PM PDT 24
Peak memory 220656 kb
Host smart-8f4caf76-8c6e-4404-92ae-e93750d04816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799234747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.799234747
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.1741283415
Short name T233
Test name
Test status
Simulation time 3317890187 ps
CPU time 22.6 seconds
Started Mar 31 01:23:44 PM PDT 24
Finished Mar 31 01:24:07 PM PDT 24
Peak memory 236944 kb
Host smart-a1adcfda-639a-467a-8763-c134a6056174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741283415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.1741283415
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.2221374325
Short name T185
Test name
Test status
Simulation time 2580950026 ps
CPU time 11.01 seconds
Started Mar 31 01:23:35 PM PDT 24
Finished Mar 31 01:23:47 PM PDT 24
Peak memory 225048 kb
Host smart-79660a65-0ef8-4ae8-a4c2-96afafb78205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221374325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.2221374325
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.2510355376
Short name T210
Test name
Test status
Simulation time 29150235182 ps
CPU time 21.72 seconds
Started Mar 31 01:25:13 PM PDT 24
Finished Mar 31 01:25:35 PM PDT 24
Peak memory 233156 kb
Host smart-8e5f67fb-4478-4675-bc25-332a588f9165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510355376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.2510355376
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.2431769478
Short name T292
Test name
Test status
Simulation time 14783533760 ps
CPU time 39.71 seconds
Started Mar 31 01:25:21 PM PDT 24
Finished Mar 31 01:26:01 PM PDT 24
Peak memory 236372 kb
Host smart-ef6be53b-83a3-43d4-88b3-011cb16757f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431769478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.2431769478
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.1450153662
Short name T344
Test name
Test status
Simulation time 1652897163 ps
CPU time 3.05 seconds
Started Mar 31 01:25:34 PM PDT 24
Finished Mar 31 01:25:37 PM PDT 24
Peak memory 222872 kb
Host smart-01157516-38fb-4362-b1e2-c0a98c9de100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450153662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.1450153662
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_intercept.1970748963
Short name T105
Test name
Test status
Simulation time 1847813694 ps
CPU time 6.73 seconds
Started Mar 31 01:25:50 PM PDT 24
Finished Mar 31 01:25:57 PM PDT 24
Peak memory 219876 kb
Host smart-2e73a40e-641a-47d1-b53e-77f4257ab355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970748963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.1970748963
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.797160630
Short name T224
Test name
Test status
Simulation time 1371064239 ps
CPU time 10.15 seconds
Started Mar 31 01:25:42 PM PDT 24
Finished Mar 31 01:25:53 PM PDT 24
Peak memory 223196 kb
Host smart-08f06e7f-f412-419d-92bf-ee4de3922dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797160630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap
.797160630
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.2372917148
Short name T297
Test name
Test status
Simulation time 5506890519 ps
CPU time 8.79 seconds
Started Mar 31 01:25:55 PM PDT 24
Finished Mar 31 01:26:04 PM PDT 24
Peak memory 223508 kb
Host smart-574fd7e3-eea5-4852-9cc7-7425c1435041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372917148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.2372917148
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.3812351586
Short name T77
Test name
Test status
Simulation time 882967969 ps
CPU time 7.56 seconds
Started Mar 31 01:26:04 PM PDT 24
Finished Mar 31 01:26:12 PM PDT 24
Peak memory 232760 kb
Host smart-17244ef6-75e0-4a39-b107-e7158c1986c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812351586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.3812351586
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.2511408518
Short name T336
Test name
Test status
Simulation time 38367017018 ps
CPU time 32.23 seconds
Started Mar 31 01:26:12 PM PDT 24
Finished Mar 31 01:26:44 PM PDT 24
Peak memory 233060 kb
Host smart-22f76462-137b-4f39-a923-9b2991aeea56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511408518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.2511408518
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.3149374074
Short name T218
Test name
Test status
Simulation time 6462185366 ps
CPU time 15.54 seconds
Started Mar 31 01:26:06 PM PDT 24
Finished Mar 31 01:26:22 PM PDT 24
Peak memory 224652 kb
Host smart-9ec5850b-7d4d-4a68-8b62-d1a97850beda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149374074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.3149374074
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.1055226374
Short name T228
Test name
Test status
Simulation time 1263458981 ps
CPU time 7.23 seconds
Started Mar 31 01:23:45 PM PDT 24
Finished Mar 31 01:23:52 PM PDT 24
Peak memory 224976 kb
Host smart-b51dd534-3ed3-4d32-8515-77a219f07060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055226374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.1055226374
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_intercept.3880046956
Short name T193
Test name
Test status
Simulation time 210834204 ps
CPU time 4.83 seconds
Started Mar 31 01:23:52 PM PDT 24
Finished Mar 31 01:23:57 PM PDT 24
Peak memory 217096 kb
Host smart-9277b280-a379-4054-bf7c-1b3a9fac3bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880046956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.3880046956
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_intercept.159870132
Short name T189
Test name
Test status
Simulation time 518094129 ps
CPU time 4.09 seconds
Started Mar 31 01:23:57 PM PDT 24
Finished Mar 31 01:24:02 PM PDT 24
Peak memory 223688 kb
Host smart-0703c06e-55bf-4afe-a99f-60b290df869a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159870132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.159870132
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.1991557981
Short name T343
Test name
Test status
Simulation time 16659263797 ps
CPU time 42.33 seconds
Started Mar 31 01:23:57 PM PDT 24
Finished Mar 31 01:24:40 PM PDT 24
Peak memory 237428 kb
Host smart-1f37d738-6069-4e8e-8f22-7e8fe7fbf685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991557981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.1991557981
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.2670583421
Short name T70
Test name
Test status
Simulation time 1161249062 ps
CPU time 8.77 seconds
Started Mar 31 01:24:03 PM PDT 24
Finished Mar 31 01:24:12 PM PDT 24
Peak memory 235876 kb
Host smart-6a491078-cc9e-4cfc-b6ba-132ad164fab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670583421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.2670583421
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.1654010271
Short name T22
Test name
Test status
Simulation time 52410250 ps
CPU time 0.74 seconds
Started Mar 31 01:24:40 PM PDT 24
Finished Mar 31 01:24:41 PM PDT 24
Peak memory 206092 kb
Host smart-84cbf734-dbde-4f68-86f6-d835b7dc333d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654010271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.1654010271
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.238708190
Short name T123
Test name
Test status
Simulation time 61322956 ps
CPU time 4.07 seconds
Started Mar 31 12:28:28 PM PDT 24
Finished Mar 31 12:28:32 PM PDT 24
Peak memory 215328 kb
Host smart-ae77cbfe-11d0-4c00-9849-7ee97690e510
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238708190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.238708190
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.4018860927
Short name T42
Test name
Test status
Simulation time 168395253 ps
CPU time 1.37 seconds
Started Mar 31 12:27:50 PM PDT 24
Finished Mar 31 12:27:53 PM PDT 24
Peak memory 206868 kb
Host smart-b182feba-fcb6-44d3-a7d9-e0673ff1d742
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018860927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.4018860927
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.191542493
Short name T796
Test name
Test status
Simulation time 822069525 ps
CPU time 8.62 seconds
Started Mar 31 12:28:10 PM PDT 24
Finished Mar 31 12:28:18 PM PDT 24
Peak memory 206888 kb
Host smart-b2d520f5-a05c-4807-b52c-90bdcb4ddb41
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191542493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_aliasing.191542493
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2257274550
Short name T839
Test name
Test status
Simulation time 3753689278 ps
CPU time 26.6 seconds
Started Mar 31 12:28:05 PM PDT 24
Finished Mar 31 12:28:32 PM PDT 24
Peak memory 215096 kb
Host smart-544b4842-d940-47df-a277-4f935484e96b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257274550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.2257274550
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.225327334
Short name T108
Test name
Test status
Simulation time 13949426 ps
CPU time 0.87 seconds
Started Mar 31 12:28:00 PM PDT 24
Finished Mar 31 12:28:01 PM PDT 24
Peak memory 206696 kb
Host smart-6ffb9f1a-0e19-4f6d-8974-bb24c4ea2c08
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225327334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_hw_reset.225327334
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1651710967
Short name T793
Test name
Test status
Simulation time 59950390 ps
CPU time 3.85 seconds
Started Mar 31 12:27:53 PM PDT 24
Finished Mar 31 12:27:58 PM PDT 24
Peak memory 216808 kb
Host smart-f101121c-9687-4c05-8b40-514814cc6b6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651710967 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.1651710967
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1227585338
Short name T134
Test name
Test status
Simulation time 372560111 ps
CPU time 2.76 seconds
Started Mar 31 12:27:51 PM PDT 24
Finished Mar 31 12:27:55 PM PDT 24
Peak memory 206916 kb
Host smart-61939d5d-1aa1-4a08-8a40-265bfabd0a97
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227585338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.1
227585338
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.27803435
Short name T756
Test name
Test status
Simulation time 14051699 ps
CPU time 0.68 seconds
Started Mar 31 12:27:46 PM PDT 24
Finished Mar 31 12:27:47 PM PDT 24
Peak memory 203508 kb
Host smart-ece0113d-d2cf-4990-aaa4-00480864f994
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27803435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.27803435
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2386802648
Short name T848
Test name
Test status
Simulation time 113049955 ps
CPU time 1.63 seconds
Started Mar 31 12:27:57 PM PDT 24
Finished Mar 31 12:27:59 PM PDT 24
Peak memory 215196 kb
Host smart-fd408297-4d41-47be-afa8-65e39f8b4ec0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386802648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.2386802648
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3604587353
Short name T757
Test name
Test status
Simulation time 10694259 ps
CPU time 0.63 seconds
Started Mar 31 12:27:51 PM PDT 24
Finished Mar 31 12:27:53 PM PDT 24
Peak memory 203428 kb
Host smart-46fe865b-3f01-4d7a-82ef-d1359c995b38
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604587353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.3604587353
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1870409930
Short name T748
Test name
Test status
Simulation time 197594759 ps
CPU time 1.79 seconds
Started Mar 31 12:27:45 PM PDT 24
Finished Mar 31 12:27:46 PM PDT 24
Peak memory 206888 kb
Host smart-f7b638fc-6537-475f-b626-968670e3f32b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870409930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.1870409930
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2637810037
Short name T775
Test name
Test status
Simulation time 824982896 ps
CPU time 13.4 seconds
Started Mar 31 12:27:48 PM PDT 24
Finished Mar 31 12:28:02 PM PDT 24
Peak memory 206844 kb
Host smart-3ed7b5aa-0e3b-49ea-9f67-6616fba7dd7a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637810037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.2637810037
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3683139920
Short name T838
Test name
Test status
Simulation time 748850611 ps
CPU time 10.69 seconds
Started Mar 31 12:27:57 PM PDT 24
Finished Mar 31 12:28:08 PM PDT 24
Peak memory 207036 kb
Host smart-7466d50f-9049-42c3-b2bd-81cd63bda5f3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683139920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.3683139920
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2139306091
Short name T809
Test name
Test status
Simulation time 315659466 ps
CPU time 1.18 seconds
Started Mar 31 12:27:59 PM PDT 24
Finished Mar 31 12:28:00 PM PDT 24
Peak memory 216128 kb
Host smart-e5129016-cf8f-483f-ae91-b1be55e7a1ce
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139306091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.2139306091
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.243306229
Short name T810
Test name
Test status
Simulation time 261939545 ps
CPU time 2.24 seconds
Started Mar 31 12:27:48 PM PDT 24
Finished Mar 31 12:27:50 PM PDT 24
Peak memory 206932 kb
Host smart-bab56f7b-e85f-41f6-9f80-af813a81f93c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243306229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.243306229
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3697127042
Short name T821
Test name
Test status
Simulation time 14966225 ps
CPU time 0.73 seconds
Started Mar 31 12:27:45 PM PDT 24
Finished Mar 31 12:27:46 PM PDT 24
Peak memory 203572 kb
Host smart-1c392ad7-051f-450a-b60d-f9b89e37e534
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697127042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.3
697127042
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3927214783
Short name T801
Test name
Test status
Simulation time 96330643 ps
CPU time 1.8 seconds
Started Mar 31 12:27:53 PM PDT 24
Finished Mar 31 12:27:55 PM PDT 24
Peak memory 215092 kb
Host smart-fd87c30a-485d-47a7-9325-381999ce7390
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927214783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.3927214783
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2092988647
Short name T844
Test name
Test status
Simulation time 53930045 ps
CPU time 0.63 seconds
Started Mar 31 12:27:51 PM PDT 24
Finished Mar 31 12:27:53 PM PDT 24
Peak memory 203436 kb
Host smart-7ad62269-c563-4a0b-b99f-0fdc2bd18fea
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092988647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.2092988647
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1889017870
Short name T803
Test name
Test status
Simulation time 57893718 ps
CPU time 1.67 seconds
Started Mar 31 12:28:12 PM PDT 24
Finished Mar 31 12:28:14 PM PDT 24
Peak memory 215308 kb
Host smart-17fbd5f3-83d5-43a9-a5fc-d123c8980e49
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889017870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.1889017870
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2258521442
Short name T833
Test name
Test status
Simulation time 182911808 ps
CPU time 3.63 seconds
Started Mar 31 12:27:58 PM PDT 24
Finished Mar 31 12:28:02 PM PDT 24
Peak memory 215292 kb
Host smart-7ad9e489-d1af-4477-9c46-5ef41b6329ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258521442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.2
258521442
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1126610152
Short name T788
Test name
Test status
Simulation time 1374761815 ps
CPU time 15.35 seconds
Started Mar 31 12:28:05 PM PDT 24
Finished Mar 31 12:28:20 PM PDT 24
Peak memory 215060 kb
Host smart-e891bde6-54c8-4eb3-b446-9e3f79270a87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126610152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.1126610152
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1596673086
Short name T772
Test name
Test status
Simulation time 214435182 ps
CPU time 3.43 seconds
Started Mar 31 12:28:00 PM PDT 24
Finished Mar 31 12:28:03 PM PDT 24
Peak memory 216868 kb
Host smart-02f343a7-63c8-415f-af5f-321a394f521b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596673086 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.1596673086
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.235689926
Short name T776
Test name
Test status
Simulation time 42368831 ps
CPU time 2.72 seconds
Started Mar 31 12:28:22 PM PDT 24
Finished Mar 31 12:28:25 PM PDT 24
Peak memory 206844 kb
Host smart-8a24393f-6689-465b-b0d6-2653c8ee1aa0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235689926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.235689926
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2965533071
Short name T779
Test name
Test status
Simulation time 31127797 ps
CPU time 0.72 seconds
Started Mar 31 12:27:56 PM PDT 24
Finished Mar 31 12:27:57 PM PDT 24
Peak memory 203588 kb
Host smart-48cf8661-4982-4d6d-a17e-a80db744fbf8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965533071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
2965533071
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3587544711
Short name T791
Test name
Test status
Simulation time 1099075077 ps
CPU time 3.07 seconds
Started Mar 31 12:27:59 PM PDT 24
Finished Mar 31 12:28:07 PM PDT 24
Peak memory 215088 kb
Host smart-698c8527-3646-4a36-b065-0c1143912dcd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587544711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.3587544711
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.837714765
Short name T831
Test name
Test status
Simulation time 45343827 ps
CPU time 3.13 seconds
Started Mar 31 12:27:52 PM PDT 24
Finished Mar 31 12:27:56 PM PDT 24
Peak memory 215252 kb
Host smart-641206cf-d7aa-4868-92c8-9e6b177c9a40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837714765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.837714765
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.711019404
Short name T141
Test name
Test status
Simulation time 101343740 ps
CPU time 1.74 seconds
Started Mar 31 12:28:02 PM PDT 24
Finished Mar 31 12:28:03 PM PDT 24
Peak memory 215220 kb
Host smart-e30aaf7b-1254-4840-bd18-36d0ab8593f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711019404 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.711019404
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2152921170
Short name T817
Test name
Test status
Simulation time 98175156 ps
CPU time 1.79 seconds
Started Mar 31 12:28:24 PM PDT 24
Finished Mar 31 12:28:26 PM PDT 24
Peak memory 215044 kb
Host smart-5182babb-bc36-4fae-8ade-bf95cc5f1f67
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152921170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
2152921170
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1374740719
Short name T768
Test name
Test status
Simulation time 14945820 ps
CPU time 0.74 seconds
Started Mar 31 12:27:54 PM PDT 24
Finished Mar 31 12:27:55 PM PDT 24
Peak memory 203580 kb
Host smart-5a354425-f882-4c06-8e67-54ee91be2009
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374740719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
1374740719
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3108953313
Short name T812
Test name
Test status
Simulation time 28300589 ps
CPU time 1.84 seconds
Started Mar 31 12:28:08 PM PDT 24
Finished Mar 31 12:28:10 PM PDT 24
Peak memory 206908 kb
Host smart-8f5a7b5e-0ee4-4925-998c-88c273c19493
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108953313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.3108953313
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.4114811823
Short name T137
Test name
Test status
Simulation time 149656373 ps
CPU time 3.51 seconds
Started Mar 31 12:28:00 PM PDT 24
Finished Mar 31 12:28:03 PM PDT 24
Peak memory 215380 kb
Host smart-460dd38f-6efb-4d48-8dbf-e3ed5a8450e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114811823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
4114811823
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3541334353
Short name T367
Test name
Test status
Simulation time 1613626270 ps
CPU time 19.93 seconds
Started Mar 31 12:28:10 PM PDT 24
Finished Mar 31 12:28:30 PM PDT 24
Peak memory 216428 kb
Host smart-e0a1ba1d-fe8e-472f-a2ea-dbaab7454026
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541334353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.3541334353
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3389004888
Short name T130
Test name
Test status
Simulation time 490322170 ps
CPU time 3.6 seconds
Started Mar 31 12:27:56 PM PDT 24
Finished Mar 31 12:28:00 PM PDT 24
Peak memory 217528 kb
Host smart-7116284e-c493-4b7b-aa46-df100a486841
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389004888 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3389004888
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.929453429
Short name T150
Test name
Test status
Simulation time 89036037 ps
CPU time 2.53 seconds
Started Mar 31 12:28:39 PM PDT 24
Finished Mar 31 12:28:41 PM PDT 24
Peak memory 206960 kb
Host smart-0646aaa1-012b-44e3-b086-561386af254a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929453429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.929453429
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1289321329
Short name T746
Test name
Test status
Simulation time 14760362 ps
CPU time 0.74 seconds
Started Mar 31 12:28:33 PM PDT 24
Finished Mar 31 12:28:34 PM PDT 24
Peak memory 203556 kb
Host smart-7d89d543-484d-4cea-a04a-8dc637d9823b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289321329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
1289321329
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1053731856
Short name T806
Test name
Test status
Simulation time 202768647 ps
CPU time 2.79 seconds
Started Mar 31 12:27:53 PM PDT 24
Finished Mar 31 12:28:06 PM PDT 24
Peak memory 215100 kb
Host smart-fa2fe65b-01fc-4a14-865a-6c5a4aaf0629
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053731856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.1053731856
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.764740105
Short name T41
Test name
Test status
Simulation time 153155814 ps
CPU time 1.89 seconds
Started Mar 31 12:27:56 PM PDT 24
Finished Mar 31 12:27:58 PM PDT 24
Peak memory 215264 kb
Host smart-6cfcf418-e5cf-47da-9578-045f1a379041
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764740105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.764740105
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3193074169
Short name T767
Test name
Test status
Simulation time 108540032 ps
CPU time 5.85 seconds
Started Mar 31 12:27:56 PM PDT 24
Finished Mar 31 12:28:02 PM PDT 24
Peak memory 215052 kb
Host smart-86b2ecac-1c36-45a5-ae1f-bcfb0d73da33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193074169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.3193074169
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2644648758
Short name T785
Test name
Test status
Simulation time 353236246 ps
CPU time 2.8 seconds
Started Mar 31 12:27:57 PM PDT 24
Finished Mar 31 12:28:00 PM PDT 24
Peak memory 216688 kb
Host smart-f7e82168-7aee-4fc5-b856-0633720cdc74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644648758 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.2644648758
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.655691604
Short name T749
Test name
Test status
Simulation time 12981361 ps
CPU time 0.74 seconds
Started Mar 31 12:27:51 PM PDT 24
Finished Mar 31 12:27:52 PM PDT 24
Peak memory 203068 kb
Host smart-73705c7e-6a1e-46e6-b9cb-c7efd5a55042
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655691604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.655691604
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1875480839
Short name T165
Test name
Test status
Simulation time 64880001 ps
CPU time 1.67 seconds
Started Mar 31 12:28:00 PM PDT 24
Finished Mar 31 12:28:02 PM PDT 24
Peak memory 215012 kb
Host smart-73456f81-1cef-488a-897b-dc12ee928211
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875480839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.1875480839
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1958864185
Short name T843
Test name
Test status
Simulation time 195658459 ps
CPU time 2.87 seconds
Started Mar 31 12:28:01 PM PDT 24
Finished Mar 31 12:28:04 PM PDT 24
Peak memory 215396 kb
Host smart-df35ccf5-afc9-4472-a045-5ecccbe4de08
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958864185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
1958864185
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1831160196
Short name T369
Test name
Test status
Simulation time 2137048657 ps
CPU time 11.45 seconds
Started Mar 31 12:28:14 PM PDT 24
Finished Mar 31 12:28:25 PM PDT 24
Peak memory 215068 kb
Host smart-a91524f7-58fc-4538-919e-065b818475a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831160196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.1831160196
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3199562810
Short name T763
Test name
Test status
Simulation time 76981939 ps
CPU time 3.7 seconds
Started Mar 31 12:27:53 PM PDT 24
Finished Mar 31 12:27:57 PM PDT 24
Peak memory 217276 kb
Host smart-18b73ebb-d28b-40e2-8c33-ec068dd24d79
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199562810 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.3199562810
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.976342013
Short name T798
Test name
Test status
Simulation time 168023784 ps
CPU time 1.25 seconds
Started Mar 31 12:28:20 PM PDT 24
Finished Mar 31 12:28:22 PM PDT 24
Peak memory 206880 kb
Host smart-a1b893cb-f040-4e28-89e9-c82ff2e6e24c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976342013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.976342013
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.1523103628
Short name T837
Test name
Test status
Simulation time 18620897 ps
CPU time 0.71 seconds
Started Mar 31 12:28:19 PM PDT 24
Finished Mar 31 12:28:20 PM PDT 24
Peak memory 203848 kb
Host smart-94320f7a-948d-478f-879a-135c2bee9c0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523103628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
1523103628
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3225496298
Short name T160
Test name
Test status
Simulation time 1578286078 ps
CPU time 3.76 seconds
Started Mar 31 12:28:09 PM PDT 24
Finished Mar 31 12:28:13 PM PDT 24
Peak memory 215080 kb
Host smart-d8130bfb-e2fd-489e-a082-141b6dc39ea8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225496298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.3225496298
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2415205104
Short name T40
Test name
Test status
Simulation time 553939068 ps
CPU time 3.43 seconds
Started Mar 31 12:27:53 PM PDT 24
Finished Mar 31 12:27:58 PM PDT 24
Peak memory 215160 kb
Host smart-3eff9238-ae36-4bad-b3a4-a16766b26a2c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415205104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
2415205104
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2082894153
Short name T365
Test name
Test status
Simulation time 811782706 ps
CPU time 12.25 seconds
Started Mar 31 12:27:44 PM PDT 24
Finished Mar 31 12:27:57 PM PDT 24
Peak memory 215792 kb
Host smart-d7d3cae7-eb8f-4784-9755-ecc74508271e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082894153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.2082894153
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1801951226
Short name T136
Test name
Test status
Simulation time 192913713 ps
CPU time 2.99 seconds
Started Mar 31 12:28:04 PM PDT 24
Finished Mar 31 12:28:07 PM PDT 24
Peak memory 217092 kb
Host smart-b94b8115-a662-4e77-92e3-f7d3f4ddfc89
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801951226 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.1801951226
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.139167371
Short name T847
Test name
Test status
Simulation time 95917519 ps
CPU time 1.88 seconds
Started Mar 31 12:28:24 PM PDT 24
Finished Mar 31 12:28:31 PM PDT 24
Peak memory 206884 kb
Host smart-4d25cf8a-e8e7-41fc-ae0c-dd2d06fdf1ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139167371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.139167371
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3997123113
Short name T745
Test name
Test status
Simulation time 17944207 ps
CPU time 0.73 seconds
Started Mar 31 12:27:57 PM PDT 24
Finished Mar 31 12:27:58 PM PDT 24
Peak memory 203860 kb
Host smart-6cb3307e-6481-4817-a547-8373ff7058b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997123113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
3997123113
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.342559324
Short name T753
Test name
Test status
Simulation time 82017037 ps
CPU time 2.8 seconds
Started Mar 31 12:28:21 PM PDT 24
Finished Mar 31 12:28:24 PM PDT 24
Peak memory 206804 kb
Host smart-78eebec0-5334-4828-b6bf-449faa3631dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342559324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.s
pi_device_same_csr_outstanding.342559324
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1195491267
Short name T811
Test name
Test status
Simulation time 25140937 ps
CPU time 1.6 seconds
Started Mar 31 12:28:05 PM PDT 24
Finished Mar 31 12:28:07 PM PDT 24
Peak memory 215260 kb
Host smart-b2d7aca8-ef09-44a0-afd1-fa10eba79eea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195491267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
1195491267
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1201058576
Short name T846
Test name
Test status
Simulation time 107986214 ps
CPU time 6.4 seconds
Started Mar 31 12:28:01 PM PDT 24
Finished Mar 31 12:28:07 PM PDT 24
Peak memory 215068 kb
Host smart-48d72859-2735-477c-9a81-d1aeeebf161e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201058576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.1201058576
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3082739629
Short name T850
Test name
Test status
Simulation time 40828449 ps
CPU time 2.65 seconds
Started Mar 31 12:27:56 PM PDT 24
Finished Mar 31 12:27:58 PM PDT 24
Peak memory 217160 kb
Host smart-55634582-7dc8-4917-9c7c-992f6909ea67
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082739629 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.3082739629
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.3531100152
Short name T144
Test name
Test status
Simulation time 37494105 ps
CPU time 2.36 seconds
Started Mar 31 12:27:50 PM PDT 24
Finished Mar 31 12:27:53 PM PDT 24
Peak memory 215104 kb
Host smart-a066edd8-363f-4711-8150-83c9c86bc507
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531100152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
3531100152
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.4050454846
Short name T758
Test name
Test status
Simulation time 17391957 ps
CPU time 0.67 seconds
Started Mar 31 12:27:57 PM PDT 24
Finished Mar 31 12:27:58 PM PDT 24
Peak memory 203864 kb
Host smart-71d4d02a-7955-4637-87ff-f89943565f74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050454846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
4050454846
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3340416607
Short name T797
Test name
Test status
Simulation time 257264577 ps
CPU time 3.78 seconds
Started Mar 31 12:28:13 PM PDT 24
Finished Mar 31 12:28:17 PM PDT 24
Peak memory 215096 kb
Host smart-4341bfb4-a0b8-455e-af18-bd582ed6abc3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340416607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.3340416607
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2948376627
Short name T849
Test name
Test status
Simulation time 170583283 ps
CPU time 2.9 seconds
Started Mar 31 12:27:57 PM PDT 24
Finished Mar 31 12:28:00 PM PDT 24
Peak memory 215260 kb
Host smart-b3845578-b989-4ce4-a05f-f57722566742
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948376627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
2948376627
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3470289174
Short name T782
Test name
Test status
Simulation time 292141445 ps
CPU time 8.34 seconds
Started Mar 31 12:28:30 PM PDT 24
Finished Mar 31 12:28:38 PM PDT 24
Peak memory 215052 kb
Host smart-05cf7572-a65e-4c6c-b11a-3a547178e2c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470289174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.3470289174
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3099431301
Short name T792
Test name
Test status
Simulation time 220489989 ps
CPU time 1.75 seconds
Started Mar 31 12:28:26 PM PDT 24
Finished Mar 31 12:28:28 PM PDT 24
Peak memory 216216 kb
Host smart-237b8990-1bb5-43d6-aa59-fbca20f0cac7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099431301 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.3099431301
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1512036824
Short name T156
Test name
Test status
Simulation time 169370816 ps
CPU time 1.25 seconds
Started Mar 31 12:28:18 PM PDT 24
Finished Mar 31 12:28:20 PM PDT 24
Peak memory 215076 kb
Host smart-7a086c43-f96a-4d87-9ad0-d149b25670fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512036824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
1512036824
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1837389080
Short name T167
Test name
Test status
Simulation time 20343164 ps
CPU time 0.75 seconds
Started Mar 31 12:27:45 PM PDT 24
Finished Mar 31 12:27:46 PM PDT 24
Peak memory 203560 kb
Host smart-78e37529-535e-4788-a547-5b8fd91c85e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837389080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
1837389080
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.380969125
Short name T771
Test name
Test status
Simulation time 59422133 ps
CPU time 1.72 seconds
Started Mar 31 12:28:00 PM PDT 24
Finished Mar 31 12:28:02 PM PDT 24
Peak memory 215076 kb
Host smart-66bf9d2f-86f5-4aea-b554-6bf3458cdddb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380969125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.s
pi_device_same_csr_outstanding.380969125
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3510023005
Short name T133
Test name
Test status
Simulation time 100589303 ps
CPU time 2.96 seconds
Started Mar 31 12:27:57 PM PDT 24
Finished Mar 31 12:28:01 PM PDT 24
Peak memory 215248 kb
Host smart-45f3708c-6635-43e9-a03f-513d0b6f4090
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510023005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
3510023005
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1198266359
Short name T845
Test name
Test status
Simulation time 323974120 ps
CPU time 19.79 seconds
Started Mar 31 12:28:24 PM PDT 24
Finished Mar 31 12:28:43 PM PDT 24
Peak memory 215124 kb
Host smart-b90beb0a-77a8-4406-b245-a4b2ab27214d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198266359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.1198266359
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3328448189
Short name T161
Test name
Test status
Simulation time 115130782 ps
CPU time 1.65 seconds
Started Mar 31 12:27:56 PM PDT 24
Finished Mar 31 12:27:57 PM PDT 24
Peak memory 215180 kb
Host smart-c9f4f7b0-924a-420b-89fa-0ffcfc2ff8fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328448189 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.3328448189
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3791886198
Short name T783
Test name
Test status
Simulation time 454260970 ps
CPU time 2.57 seconds
Started Mar 31 12:28:22 PM PDT 24
Finished Mar 31 12:28:25 PM PDT 24
Peak memory 206896 kb
Host smart-35411936-4f45-4cdb-833f-d1800dca447d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791886198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
3791886198
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1295631019
Short name T813
Test name
Test status
Simulation time 42159456 ps
CPU time 0.71 seconds
Started Mar 31 12:27:50 PM PDT 24
Finished Mar 31 12:27:52 PM PDT 24
Peak memory 203580 kb
Host smart-98127f62-a780-43f4-8675-449288ebb22e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295631019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
1295631019
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3337256754
Short name T754
Test name
Test status
Simulation time 85597976 ps
CPU time 2.72 seconds
Started Mar 31 12:28:35 PM PDT 24
Finished Mar 31 12:28:38 PM PDT 24
Peak memory 215060 kb
Host smart-d08883e9-efa6-4650-9125-f9479eee28fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337256754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.3337256754
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1076877193
Short name T138
Test name
Test status
Simulation time 62052250 ps
CPU time 2.04 seconds
Started Mar 31 12:28:04 PM PDT 24
Finished Mar 31 12:28:06 PM PDT 24
Peak memory 215428 kb
Host smart-3e04e781-19df-4f49-b9f1-c1320108ddbe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076877193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
1076877193
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1851083696
Short name T124
Test name
Test status
Simulation time 209446516 ps
CPU time 12.7 seconds
Started Mar 31 12:28:09 PM PDT 24
Finished Mar 31 12:28:22 PM PDT 24
Peak memory 215048 kb
Host smart-30555486-a0aa-4d07-91fb-5ed63e4dc74d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851083696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.1851083696
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2206623262
Short name T815
Test name
Test status
Simulation time 256282795 ps
CPU time 3.8 seconds
Started Mar 31 12:28:39 PM PDT 24
Finished Mar 31 12:28:43 PM PDT 24
Peak memory 217072 kb
Host smart-e2951145-6afd-42e5-894b-9c1bd7bf35a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206623262 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2206623262
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2513937632
Short name T151
Test name
Test status
Simulation time 293502349 ps
CPU time 2.03 seconds
Started Mar 31 12:28:20 PM PDT 24
Finished Mar 31 12:28:22 PM PDT 24
Peak memory 215088 kb
Host smart-bd1de9ab-2695-4090-b213-d532101ea45e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513937632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
2513937632
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2926275590
Short name T759
Test name
Test status
Simulation time 76037779 ps
CPU time 0.7 seconds
Started Mar 31 12:27:59 PM PDT 24
Finished Mar 31 12:28:00 PM PDT 24
Peak memory 203640 kb
Host smart-c4b58980-18fc-4b52-8d50-5c5e2763fddb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926275590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
2926275590
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.37477536
Short name T822
Test name
Test status
Simulation time 321681775 ps
CPU time 3.97 seconds
Started Mar 31 12:28:24 PM PDT 24
Finished Mar 31 12:28:28 PM PDT 24
Peak memory 215052 kb
Host smart-c2259438-98a2-4158-ab12-8f353c6124bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37477536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sp
i_device_same_csr_outstanding.37477536
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1344868294
Short name T363
Test name
Test status
Simulation time 33156660 ps
CPU time 2.32 seconds
Started Mar 31 12:28:30 PM PDT 24
Finished Mar 31 12:28:33 PM PDT 24
Peak memory 215272 kb
Host smart-b55a0bf6-cc83-49da-8b25-c33da3090df3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344868294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
1344868294
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1331267154
Short name T368
Test name
Test status
Simulation time 7767178157 ps
CPU time 14.29 seconds
Started Mar 31 12:28:25 PM PDT 24
Finished Mar 31 12:28:39 PM PDT 24
Peak memory 215156 kb
Host smart-35d7aacc-ebe5-44f7-8578-4f6fe155627e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331267154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.1331267154
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.334749344
Short name T835
Test name
Test status
Simulation time 330002023 ps
CPU time 21.89 seconds
Started Mar 31 12:27:52 PM PDT 24
Finished Mar 31 12:28:14 PM PDT 24
Peak memory 215064 kb
Host smart-00fd458a-f302-401f-bb8a-0e4ef683e9b5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334749344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_aliasing.334749344
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.116865588
Short name T781
Test name
Test status
Simulation time 925694675 ps
CPU time 12.87 seconds
Started Mar 31 12:27:49 PM PDT 24
Finished Mar 31 12:28:03 PM PDT 24
Peak memory 206904 kb
Host smart-b6a45336-48b0-4f38-aa24-fbfee4c7cf9f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116865588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_bit_bash.116865588
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1161558320
Short name T109
Test name
Test status
Simulation time 45505528 ps
CPU time 1.37 seconds
Started Mar 31 12:27:52 PM PDT 24
Finished Mar 31 12:27:55 PM PDT 24
Peak memory 206788 kb
Host smart-e1083875-3684-4bf6-b5dd-da9026822f1a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161558320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.1161558320
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3264834307
Short name T135
Test name
Test status
Simulation time 125762903 ps
CPU time 3.49 seconds
Started Mar 31 12:27:51 PM PDT 24
Finished Mar 31 12:27:55 PM PDT 24
Peak memory 217972 kb
Host smart-447d09d1-ec0a-4bee-8dcd-d6a2fa3388a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264834307 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.3264834307
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2050841587
Short name T807
Test name
Test status
Simulation time 297279748 ps
CPU time 1.94 seconds
Started Mar 31 12:27:49 PM PDT 24
Finished Mar 31 12:27:52 PM PDT 24
Peak memory 215040 kb
Host smart-be243b02-20f1-418c-93d3-1836514d176a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050841587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.2
050841587
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.482180496
Short name T832
Test name
Test status
Simulation time 36721881 ps
CPU time 0.69 seconds
Started Mar 31 12:27:52 PM PDT 24
Finished Mar 31 12:27:53 PM PDT 24
Peak memory 203512 kb
Host smart-9e264c93-438c-4cd4-a365-8e715fdda823
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482180496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.482180496
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1996741454
Short name T148
Test name
Test status
Simulation time 514894818 ps
CPU time 1.61 seconds
Started Mar 31 12:27:53 PM PDT 24
Finished Mar 31 12:27:55 PM PDT 24
Peak memory 215380 kb
Host smart-0fa92099-392e-40d9-8d54-c62e3bdac227
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996741454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.1996741454
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.865571921
Short name T789
Test name
Test status
Simulation time 11392942 ps
CPU time 0.64 seconds
Started Mar 31 12:27:56 PM PDT 24
Finished Mar 31 12:27:56 PM PDT 24
Peak memory 203412 kb
Host smart-30c1f8f3-5e4f-4447-af14-97efb555e22f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865571921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem
_walk.865571921
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1370607773
Short name T824
Test name
Test status
Simulation time 534435804 ps
CPU time 3.12 seconds
Started Mar 31 12:27:43 PM PDT 24
Finished Mar 31 12:27:46 PM PDT 24
Peak memory 215024 kb
Host smart-e5c40342-1c2c-4141-8d33-abe55aa525c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370607773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.1370607773
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2071999212
Short name T818
Test name
Test status
Simulation time 111861944 ps
CPU time 1.86 seconds
Started Mar 31 12:27:45 PM PDT 24
Finished Mar 31 12:27:47 PM PDT 24
Peak memory 215168 kb
Host smart-c66a3dc2-3dae-4742-b6b4-0e239b7fdd42
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071999212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.2
071999212
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1436505296
Short name T795
Test name
Test status
Simulation time 565402298 ps
CPU time 6.7 seconds
Started Mar 31 12:27:50 PM PDT 24
Finished Mar 31 12:27:58 PM PDT 24
Peak memory 215108 kb
Host smart-8e1cb140-4b3d-4bf7-954e-79456c66bfcf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436505296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.1436505296
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.485745850
Short name T784
Test name
Test status
Simulation time 61807821 ps
CPU time 0.76 seconds
Started Mar 31 12:28:04 PM PDT 24
Finished Mar 31 12:28:10 PM PDT 24
Peak memory 203564 kb
Host smart-56267208-af11-48f9-a6c2-ce816e8438e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485745850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.485745850
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3025390258
Short name T747
Test name
Test status
Simulation time 14962418 ps
CPU time 0.7 seconds
Started Mar 31 12:28:17 PM PDT 24
Finished Mar 31 12:28:18 PM PDT 24
Peak memory 203864 kb
Host smart-14f2b598-8197-44bd-b714-75747ba1c755
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025390258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
3025390258
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2784891393
Short name T787
Test name
Test status
Simulation time 23298317 ps
CPU time 0.72 seconds
Started Mar 31 12:28:17 PM PDT 24
Finished Mar 31 12:28:18 PM PDT 24
Peak memory 203576 kb
Host smart-c8608fdc-e4ca-4088-af54-a03c28430991
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784891393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
2784891393
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.3752611319
Short name T742
Test name
Test status
Simulation time 31051546 ps
CPU time 0.73 seconds
Started Mar 31 12:28:06 PM PDT 24
Finished Mar 31 12:28:07 PM PDT 24
Peak memory 203544 kb
Host smart-aaecd3d6-be63-406f-96f9-0f0108456430
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752611319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
3752611319
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.304985961
Short name T826
Test name
Test status
Simulation time 35997870 ps
CPU time 0.69 seconds
Started Mar 31 12:28:25 PM PDT 24
Finished Mar 31 12:28:26 PM PDT 24
Peak memory 203536 kb
Host smart-415186b8-8d8d-4b14-a1c3-08a86eb80103
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304985961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.304985961
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.359857236
Short name T169
Test name
Test status
Simulation time 38523938 ps
CPU time 0.67 seconds
Started Mar 31 12:28:18 PM PDT 24
Finished Mar 31 12:28:19 PM PDT 24
Peak memory 203540 kb
Host smart-a588f681-dec4-42ef-a30b-69bd6737c3d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359857236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.359857236
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3467384825
Short name T830
Test name
Test status
Simulation time 263336276 ps
CPU time 0.75 seconds
Started Mar 31 12:28:09 PM PDT 24
Finished Mar 31 12:28:10 PM PDT 24
Peak memory 203612 kb
Host smart-2741f723-25a7-4eaf-b58c-b3550d826d4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467384825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
3467384825
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.260376823
Short name T743
Test name
Test status
Simulation time 40124935 ps
CPU time 0.68 seconds
Started Mar 31 12:27:55 PM PDT 24
Finished Mar 31 12:27:56 PM PDT 24
Peak memory 203540 kb
Host smart-f760a68b-2768-4b42-a712-85df07b613b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260376823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.260376823
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.269866844
Short name T829
Test name
Test status
Simulation time 13246237 ps
CPU time 0.73 seconds
Started Mar 31 12:28:10 PM PDT 24
Finished Mar 31 12:28:11 PM PDT 24
Peak memory 203864 kb
Host smart-515b9cd6-dffe-47da-9ee5-8e5e1807084a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269866844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.269866844
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1631447327
Short name T744
Test name
Test status
Simulation time 47811922 ps
CPU time 0.69 seconds
Started Mar 31 12:27:51 PM PDT 24
Finished Mar 31 12:27:53 PM PDT 24
Peak memory 203552 kb
Host smart-a4982e70-8e9b-4ed5-bb95-2442eb4eb867
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631447327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
1631447327
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.311996915
Short name T179
Test name
Test status
Simulation time 769407338 ps
CPU time 8.3 seconds
Started Mar 31 12:27:53 PM PDT 24
Finished Mar 31 12:28:03 PM PDT 24
Peak memory 206880 kb
Host smart-74b99cb1-2782-47f4-a2a0-4314b8c63edf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311996915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_aliasing.311996915
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.4291242287
Short name T149
Test name
Test status
Simulation time 1862366843 ps
CPU time 14.08 seconds
Started Mar 31 12:27:53 PM PDT 24
Finished Mar 31 12:28:08 PM PDT 24
Peak memory 215032 kb
Host smart-20e22eed-81d9-4998-8b8a-500b77abb900
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291242287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.4291242287
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.816960642
Short name T805
Test name
Test status
Simulation time 217663029 ps
CPU time 3.89 seconds
Started Mar 31 12:27:47 PM PDT 24
Finished Mar 31 12:27:51 PM PDT 24
Peak memory 216968 kb
Host smart-3abd6aaa-bd7f-4f45-8d40-d77c4ee14f23
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816960642 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.816960642
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1116988320
Short name T816
Test name
Test status
Simulation time 113064707 ps
CPU time 2.47 seconds
Started Mar 31 12:27:51 PM PDT 24
Finished Mar 31 12:27:59 PM PDT 24
Peak memory 215184 kb
Host smart-6fbe7454-8a6d-4c5d-8610-1e9dd37c8b4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116988320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.1
116988320
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2795663127
Short name T800
Test name
Test status
Simulation time 306887451 ps
CPU time 0.77 seconds
Started Mar 31 12:27:58 PM PDT 24
Finished Mar 31 12:27:59 PM PDT 24
Peak memory 203544 kb
Host smart-f7916d3f-790d-4497-b932-a95956040dac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795663127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.2
795663127
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2599360587
Short name T766
Test name
Test status
Simulation time 34495998 ps
CPU time 1.28 seconds
Started Mar 31 12:27:52 PM PDT 24
Finished Mar 31 12:27:55 PM PDT 24
Peak memory 215140 kb
Host smart-13562c15-9702-430a-b6ab-68b36d39a572
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599360587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.2599360587
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.4003604098
Short name T827
Test name
Test status
Simulation time 22094406 ps
CPU time 0.68 seconds
Started Mar 31 12:27:51 PM PDT 24
Finished Mar 31 12:27:53 PM PDT 24
Peak memory 203412 kb
Host smart-6d382bc4-6e59-4902-b12d-7b7766829175
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003604098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.4003604098
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1861017048
Short name T836
Test name
Test status
Simulation time 221303381 ps
CPU time 4.07 seconds
Started Mar 31 12:27:54 PM PDT 24
Finished Mar 31 12:27:59 PM PDT 24
Peak memory 215096 kb
Host smart-e19ddfb9-e1e6-4ad7-acfd-fc6ab176c5ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861017048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.1861017048
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2633137303
Short name T820
Test name
Test status
Simulation time 28490595 ps
CPU time 1.9 seconds
Started Mar 31 12:28:11 PM PDT 24
Finished Mar 31 12:28:13 PM PDT 24
Peak memory 215212 kb
Host smart-64a3ee26-5a1f-4b0d-b4c0-60e056fc694d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633137303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.2
633137303
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1824006599
Short name T819
Test name
Test status
Simulation time 1253164201 ps
CPU time 18.37 seconds
Started Mar 31 12:27:53 PM PDT 24
Finished Mar 31 12:28:13 PM PDT 24
Peak memory 215484 kb
Host smart-a404bb1c-3eb7-4dc5-a123-f9eee5db2202
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824006599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.1824006599
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2466807655
Short name T761
Test name
Test status
Simulation time 22338881 ps
CPU time 0.67 seconds
Started Mar 31 12:27:57 PM PDT 24
Finished Mar 31 12:27:58 PM PDT 24
Peak memory 203520 kb
Host smart-bc203328-03d1-47be-b113-e1b04bca3407
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466807655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
2466807655
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.275358690
Short name T780
Test name
Test status
Simulation time 38171836 ps
CPU time 0.67 seconds
Started Mar 31 12:28:30 PM PDT 24
Finished Mar 31 12:28:31 PM PDT 24
Peak memory 203880 kb
Host smart-18a80f7a-e5c0-43fb-a69d-e757749a4739
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275358690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.275358690
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3869932214
Short name T786
Test name
Test status
Simulation time 17106989 ps
CPU time 0.73 seconds
Started Mar 31 12:28:01 PM PDT 24
Finished Mar 31 12:28:02 PM PDT 24
Peak memory 203560 kb
Host smart-6d089f62-1d25-4db4-bb33-c0ebc53a1268
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869932214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
3869932214
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.4037137864
Short name T773
Test name
Test status
Simulation time 21491706 ps
CPU time 0.68 seconds
Started Mar 31 12:27:56 PM PDT 24
Finished Mar 31 12:27:58 PM PDT 24
Peak memory 203520 kb
Host smart-e3980fec-9336-46ad-bae0-f1d07de46d8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037137864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
4037137864
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1790660516
Short name T168
Test name
Test status
Simulation time 40315414 ps
CPU time 0.74 seconds
Started Mar 31 12:28:05 PM PDT 24
Finished Mar 31 12:28:06 PM PDT 24
Peak memory 203604 kb
Host smart-248f9d3f-02a7-4fd6-9222-737d988173b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790660516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
1790660516
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.422207372
Short name T790
Test name
Test status
Simulation time 57555798 ps
CPU time 0.68 seconds
Started Mar 31 12:27:56 PM PDT 24
Finished Mar 31 12:27:57 PM PDT 24
Peak memory 203868 kb
Host smart-cfd82c1d-98b2-48a9-a766-0c6104d64ac9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422207372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.422207372
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.701875149
Short name T764
Test name
Test status
Simulation time 37120427 ps
CPU time 0.73 seconds
Started Mar 31 12:27:55 PM PDT 24
Finished Mar 31 12:28:00 PM PDT 24
Peak memory 203912 kb
Host smart-902764b5-1961-40da-ac33-435fd73ab87e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701875149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.701875149
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.287850961
Short name T799
Test name
Test status
Simulation time 17660360 ps
CPU time 0.77 seconds
Started Mar 31 12:28:30 PM PDT 24
Finished Mar 31 12:28:31 PM PDT 24
Peak memory 203568 kb
Host smart-01820085-0453-4d2c-ba48-ba822a5c613c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287850961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.287850961
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3990772009
Short name T814
Test name
Test status
Simulation time 47829439 ps
CPU time 0.72 seconds
Started Mar 31 12:28:17 PM PDT 24
Finished Mar 31 12:28:18 PM PDT 24
Peak memory 203576 kb
Host smart-4371ce60-d111-4906-b6e4-bb5aebd379eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990772009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
3990772009
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3600208414
Short name T170
Test name
Test status
Simulation time 27794603 ps
CPU time 0.68 seconds
Started Mar 31 12:27:59 PM PDT 24
Finished Mar 31 12:28:00 PM PDT 24
Peak memory 203824 kb
Host smart-4bc743e6-056a-4871-a61a-cfc0966a41ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600208414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
3600208414
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1966407113
Short name T153
Test name
Test status
Simulation time 105904102 ps
CPU time 7.47 seconds
Started Mar 31 12:27:57 PM PDT 24
Finished Mar 31 12:28:05 PM PDT 24
Peak memory 215044 kb
Host smart-1e8951d6-f48c-4e17-892d-69dc4ad819f8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966407113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.1966407113
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1379671852
Short name T152
Test name
Test status
Simulation time 3505511170 ps
CPU time 38.13 seconds
Started Mar 31 12:27:49 PM PDT 24
Finished Mar 31 12:28:28 PM PDT 24
Peak memory 206892 kb
Host smart-02fbde63-64d9-407a-a690-cc1b7dac786d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379671852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.1379671852
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1870605158
Short name T110
Test name
Test status
Simulation time 43348434 ps
CPU time 1.3 seconds
Started Mar 31 12:28:44 PM PDT 24
Finished Mar 31 12:28:45 PM PDT 24
Peak memory 216088 kb
Host smart-d69befd4-55cd-4b47-89c0-4c6c84aedd87
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870605158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.1870605158
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3640216576
Short name T159
Test name
Test status
Simulation time 405481657 ps
CPU time 2.82 seconds
Started Mar 31 12:28:02 PM PDT 24
Finished Mar 31 12:28:05 PM PDT 24
Peak memory 216552 kb
Host smart-1f6a597a-15e1-466f-8c99-204b880201ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640216576 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.3640216576
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2435908350
Short name T834
Test name
Test status
Simulation time 28878864 ps
CPU time 1.83 seconds
Started Mar 31 12:28:31 PM PDT 24
Finished Mar 31 12:28:33 PM PDT 24
Peak memory 215072 kb
Host smart-5c75380f-99aa-460d-a86f-5d6468c1242f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435908350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.2
435908350
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2084067576
Short name T774
Test name
Test status
Simulation time 34234690 ps
CPU time 0.66 seconds
Started Mar 31 12:27:59 PM PDT 24
Finished Mar 31 12:28:00 PM PDT 24
Peak memory 203548 kb
Host smart-ffbcab06-5824-4406-b427-bfaeb34854cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084067576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.2
084067576
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1614965419
Short name T145
Test name
Test status
Simulation time 190518303 ps
CPU time 1.55 seconds
Started Mar 31 12:28:01 PM PDT 24
Finished Mar 31 12:28:03 PM PDT 24
Peak memory 215056 kb
Host smart-b5708272-8451-4605-a0a4-b473deac8d8b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614965419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.1614965419
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3286733187
Short name T804
Test name
Test status
Simulation time 26693118 ps
CPU time 0.65 seconds
Started Mar 31 12:28:16 PM PDT 24
Finished Mar 31 12:28:16 PM PDT 24
Peak memory 203392 kb
Host smart-77fd1ac2-462d-4906-80c5-929c4d492b5d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286733187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.3286733187
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.721088693
Short name T154
Test name
Test status
Simulation time 41425022 ps
CPU time 2.54 seconds
Started Mar 31 12:27:57 PM PDT 24
Finished Mar 31 12:28:00 PM PDT 24
Peak memory 215136 kb
Host smart-05280777-2c06-4215-87f8-78c7621db6c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721088693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sp
i_device_same_csr_outstanding.721088693
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3936865951
Short name T132
Test name
Test status
Simulation time 247600751 ps
CPU time 3.15 seconds
Started Mar 31 12:28:29 PM PDT 24
Finished Mar 31 12:28:32 PM PDT 24
Peak memory 215344 kb
Host smart-db65a703-e64d-40b9-a6c9-c35f1524f093
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936865951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.3
936865951
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3553692491
Short name T122
Test name
Test status
Simulation time 206576421 ps
CPU time 12.08 seconds
Started Mar 31 12:27:53 PM PDT 24
Finished Mar 31 12:28:06 PM PDT 24
Peak memory 215048 kb
Host smart-bd9167a8-1708-45a1-98e2-d31fcd9d6a9c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553692491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.3553692491
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.639463321
Short name T752
Test name
Test status
Simulation time 12362584 ps
CPU time 0.67 seconds
Started Mar 31 12:27:57 PM PDT 24
Finished Mar 31 12:27:58 PM PDT 24
Peak memory 203540 kb
Host smart-d0e5d855-a741-47be-9c54-e30eedfb1ff8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639463321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.639463321
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.886410056
Short name T841
Test name
Test status
Simulation time 32248701 ps
CPU time 0.72 seconds
Started Mar 31 12:27:55 PM PDT 24
Finished Mar 31 12:27:56 PM PDT 24
Peak memory 203576 kb
Host smart-6dddb66f-042f-4c22-8ca7-869b54370335
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886410056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.886410056
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1292495665
Short name T770
Test name
Test status
Simulation time 42346835 ps
CPU time 0.65 seconds
Started Mar 31 12:28:02 PM PDT 24
Finished Mar 31 12:28:03 PM PDT 24
Peak memory 203872 kb
Host smart-62a7af63-e0ff-418d-832e-a96d9a38a223
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292495665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
1292495665
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1111394892
Short name T778
Test name
Test status
Simulation time 16228760 ps
CPU time 0.72 seconds
Started Mar 31 12:28:09 PM PDT 24
Finished Mar 31 12:28:10 PM PDT 24
Peak memory 203872 kb
Host smart-9eb7feb3-7deb-4b6e-8b2c-409c1a8e58ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111394892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
1111394892
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3878483335
Short name T823
Test name
Test status
Simulation time 74596942 ps
CPU time 0.73 seconds
Started Mar 31 12:28:12 PM PDT 24
Finished Mar 31 12:28:13 PM PDT 24
Peak memory 203872 kb
Host smart-5bb679c6-d7e0-40b2-9a49-51995050f51a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878483335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
3878483335
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1076990407
Short name T765
Test name
Test status
Simulation time 19618729 ps
CPU time 0.76 seconds
Started Mar 31 12:27:51 PM PDT 24
Finished Mar 31 12:27:53 PM PDT 24
Peak memory 203572 kb
Host smart-d10f3fb5-0e61-4559-a6c8-60c63d737bf0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076990407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
1076990407
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2725578088
Short name T740
Test name
Test status
Simulation time 18650957 ps
CPU time 0.65 seconds
Started Mar 31 12:27:55 PM PDT 24
Finished Mar 31 12:27:56 PM PDT 24
Peak memory 203492 kb
Host smart-c576a0dc-5284-49db-b697-b67d5f13ee55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725578088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
2725578088
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.409753297
Short name T777
Test name
Test status
Simulation time 18699481 ps
CPU time 0.78 seconds
Started Mar 31 12:28:33 PM PDT 24
Finished Mar 31 12:28:34 PM PDT 24
Peak memory 203544 kb
Host smart-b2d2aeab-94dc-4f7b-b962-e117fa15dcae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409753297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.409753297
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2032513055
Short name T769
Test name
Test status
Simulation time 11292000 ps
CPU time 0.69 seconds
Started Mar 31 12:27:54 PM PDT 24
Finished Mar 31 12:27:55 PM PDT 24
Peak memory 203564 kb
Host smart-9525d559-275c-490d-a2a7-88a6ee60cdc3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032513055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2032513055
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2178074025
Short name T825
Test name
Test status
Simulation time 13421823 ps
CPU time 0.69 seconds
Started Mar 31 12:27:54 PM PDT 24
Finished Mar 31 12:27:55 PM PDT 24
Peak memory 203532 kb
Host smart-5f7df287-0cb6-49b1-ba26-868a860c2bb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178074025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
2178074025
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2704057067
Short name T750
Test name
Test status
Simulation time 80138294 ps
CPU time 1.47 seconds
Started Mar 31 12:28:01 PM PDT 24
Finished Mar 31 12:28:02 PM PDT 24
Peak memory 216216 kb
Host smart-3d8a73ab-df85-4ca6-b31f-c09c17d44c7f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704057067 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.2704057067
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.493817328
Short name T794
Test name
Test status
Simulation time 98976746 ps
CPU time 2.76 seconds
Started Mar 31 12:27:49 PM PDT 24
Finished Mar 31 12:27:53 PM PDT 24
Peak memory 215092 kb
Host smart-b1416058-50a0-48d6-b3c7-e82f710d05de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493817328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.493817328
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.412779548
Short name T166
Test name
Test status
Simulation time 17185054 ps
CPU time 0.73 seconds
Started Mar 31 12:28:05 PM PDT 24
Finished Mar 31 12:28:06 PM PDT 24
Peak memory 203484 kb
Host smart-f87dc039-a2bc-4eb6-a0ae-7cbb49268152
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412779548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.412779548
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.675408622
Short name T840
Test name
Test status
Simulation time 24542028 ps
CPU time 1.61 seconds
Started Mar 31 12:28:35 PM PDT 24
Finished Mar 31 12:28:37 PM PDT 24
Peak memory 206812 kb
Host smart-dd4cd1a9-ab9f-4301-98fb-e018a539007d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675408622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sp
i_device_same_csr_outstanding.675408622
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.229180754
Short name T828
Test name
Test status
Simulation time 101646056 ps
CPU time 3.09 seconds
Started Mar 31 12:28:31 PM PDT 24
Finished Mar 31 12:28:35 PM PDT 24
Peak memory 215168 kb
Host smart-1cacbc4f-8e3c-4a88-80b5-e21bd6abfd6a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229180754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.229180754
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2622565192
Short name T373
Test name
Test status
Simulation time 807721265 ps
CPU time 14.96 seconds
Started Mar 31 12:28:29 PM PDT 24
Finished Mar 31 12:28:44 PM PDT 24
Peak memory 215532 kb
Host smart-5e6d1d4b-24ed-4e0f-a17b-41f445add8a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622565192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.2622565192
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3045589577
Short name T140
Test name
Test status
Simulation time 164147552 ps
CPU time 2.39 seconds
Started Mar 31 12:27:59 PM PDT 24
Finished Mar 31 12:28:01 PM PDT 24
Peak memory 217244 kb
Host smart-7b2cbaa2-e4d5-4fcf-b099-e9373d3004bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045589577 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.3045589577
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3115989397
Short name T143
Test name
Test status
Simulation time 58571904 ps
CPU time 1.82 seconds
Started Mar 31 12:28:09 PM PDT 24
Finished Mar 31 12:28:11 PM PDT 24
Peak memory 215060 kb
Host smart-71149ce5-a97a-4ae6-9327-94b771b1764f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115989397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.3
115989397
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.445925983
Short name T741
Test name
Test status
Simulation time 202961133 ps
CPU time 0.73 seconds
Started Mar 31 12:27:54 PM PDT 24
Finished Mar 31 12:28:00 PM PDT 24
Peak memory 203876 kb
Host smart-14b2a9aa-096a-46f0-82d1-7ac0d22a43e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445925983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.445925983
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.4137609617
Short name T157
Test name
Test status
Simulation time 89097381 ps
CPU time 2.62 seconds
Started Mar 31 12:28:29 PM PDT 24
Finished Mar 31 12:28:32 PM PDT 24
Peak memory 215132 kb
Host smart-b26f7c7c-fef8-41d3-92af-dbe53b3d8d92
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137609617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.4137609617
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2329305033
Short name T755
Test name
Test status
Simulation time 183429323 ps
CPU time 3.42 seconds
Started Mar 31 12:28:00 PM PDT 24
Finished Mar 31 12:28:03 PM PDT 24
Peak memory 217800 kb
Host smart-ab7207b6-c358-4d50-8f04-4dc8c5f33a4a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329305033 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.2329305033
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3398749079
Short name T147
Test name
Test status
Simulation time 345906649 ps
CPU time 2.53 seconds
Started Mar 31 12:27:55 PM PDT 24
Finished Mar 31 12:28:03 PM PDT 24
Peak memory 206920 kb
Host smart-f4134c27-581d-445a-9fba-ae87d88838a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398749079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.3
398749079
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.4062618078
Short name T802
Test name
Test status
Simulation time 13014665 ps
CPU time 0.68 seconds
Started Mar 31 12:28:20 PM PDT 24
Finished Mar 31 12:28:20 PM PDT 24
Peak memory 203540 kb
Host smart-7558598b-4d15-4ce4-8b10-08b0c802ce0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062618078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.4
062618078
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1428418439
Short name T162
Test name
Test status
Simulation time 141450989 ps
CPU time 1.87 seconds
Started Mar 31 12:27:57 PM PDT 24
Finished Mar 31 12:27:59 PM PDT 24
Peak memory 215088 kb
Host smart-3bdb936e-126b-45f8-b44e-5ab07f5274ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428418439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.1428418439
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2352294210
Short name T370
Test name
Test status
Simulation time 15803366507 ps
CPU time 22.24 seconds
Started Mar 31 12:28:28 PM PDT 24
Finished Mar 31 12:28:50 PM PDT 24
Peak memory 215176 kb
Host smart-0b4d0a2b-9db7-46cd-8b24-49edf3dbf5be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352294210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.2352294210
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2809273337
Short name T751
Test name
Test status
Simulation time 523221249 ps
CPU time 2.75 seconds
Started Mar 31 12:28:29 PM PDT 24
Finished Mar 31 12:28:32 PM PDT 24
Peak memory 216872 kb
Host smart-2230a6d7-5941-4742-8996-1dca44ab6f03
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809273337 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2809273337
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1130748380
Short name T760
Test name
Test status
Simulation time 59587467 ps
CPU time 1.18 seconds
Started Mar 31 12:28:07 PM PDT 24
Finished Mar 31 12:28:08 PM PDT 24
Peak memory 206856 kb
Host smart-9ea58c2c-ac4e-4050-b0c1-73f9e3e08817
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130748380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.1
130748380
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1307398110
Short name T762
Test name
Test status
Simulation time 189070971 ps
CPU time 0.69 seconds
Started Mar 31 12:28:07 PM PDT 24
Finished Mar 31 12:28:07 PM PDT 24
Peak memory 203508 kb
Host smart-07b13e92-131a-425a-a1b7-ecd2d2e8c2b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307398110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.1
307398110
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2664097647
Short name T43
Test name
Test status
Simulation time 278773468 ps
CPU time 3.6 seconds
Started Mar 31 12:28:02 PM PDT 24
Finished Mar 31 12:28:10 PM PDT 24
Peak memory 215140 kb
Host smart-a738e5ee-d8ed-4163-9d9f-74efe66a83c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664097647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.2664097647
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1862589117
Short name T139
Test name
Test status
Simulation time 133002131 ps
CPU time 1.99 seconds
Started Mar 31 12:27:49 PM PDT 24
Finished Mar 31 12:27:52 PM PDT 24
Peak memory 215184 kb
Host smart-79e85a13-bc3e-4ff6-9547-cd0b24035bb1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862589117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.1
862589117
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2912335497
Short name T129
Test name
Test status
Simulation time 276692283 ps
CPU time 7.47 seconds
Started Mar 31 12:27:59 PM PDT 24
Finished Mar 31 12:28:07 PM PDT 24
Peak memory 215688 kb
Host smart-b5ea8584-4b9b-4765-9d21-00739019db97
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912335497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.2912335497
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.149772275
Short name T142
Test name
Test status
Simulation time 122877002 ps
CPU time 1.79 seconds
Started Mar 31 12:27:51 PM PDT 24
Finished Mar 31 12:27:53 PM PDT 24
Peak memory 214640 kb
Host smart-dd30f91b-ca6c-4b9e-a272-a91965615209
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149772275 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.149772275
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.96663979
Short name T842
Test name
Test status
Simulation time 184400631 ps
CPU time 1.78 seconds
Started Mar 31 12:28:35 PM PDT 24
Finished Mar 31 12:28:37 PM PDT 24
Peak memory 215036 kb
Host smart-22b44b88-0d0c-41b9-90a6-39c994cf6754
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96663979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.96663979
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2202330475
Short name T808
Test name
Test status
Simulation time 47464733 ps
CPU time 0.7 seconds
Started Mar 31 12:28:00 PM PDT 24
Finished Mar 31 12:28:01 PM PDT 24
Peak memory 203564 kb
Host smart-7ae4ece3-72f1-47b2-a4bf-aaa3e2f515c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202330475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.2
202330475
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3452920159
Short name T155
Test name
Test status
Simulation time 58061527 ps
CPU time 3.6 seconds
Started Mar 31 12:28:07 PM PDT 24
Finished Mar 31 12:28:10 PM PDT 24
Peak memory 215028 kb
Host smart-a5a8ff55-ad04-409e-a836-4acfbeb0f9ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452920159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.3452920159
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3320684704
Short name T164
Test name
Test status
Simulation time 114978443 ps
CPU time 1.73 seconds
Started Mar 31 12:27:56 PM PDT 24
Finished Mar 31 12:27:57 PM PDT 24
Peak memory 215252 kb
Host smart-fc3baab6-64cd-47b8-b0d9-16a9839935fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320684704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.3
320684704
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2177019354
Short name T372
Test name
Test status
Simulation time 192534605 ps
CPU time 12.19 seconds
Started Mar 31 12:28:04 PM PDT 24
Finished Mar 31 12:28:16 PM PDT 24
Peak memory 215220 kb
Host smart-47a5c68a-371f-4a27-bed2-a7e4ca10dd79
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177019354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.2177019354
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.639331019
Short name T562
Test name
Test status
Simulation time 19312192 ps
CPU time 0.72 seconds
Started Mar 31 01:23:42 PM PDT 24
Finished Mar 31 01:23:43 PM PDT 24
Peak memory 205892 kb
Host smart-0b63f45d-18d7-489e-9429-245f003442cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639331019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.639331019
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.1975074915
Short name T480
Test name
Test status
Simulation time 79414815 ps
CPU time 0.86 seconds
Started Mar 31 01:23:30 PM PDT 24
Finished Mar 31 01:23:31 PM PDT 24
Peak memory 207196 kb
Host smart-410ece92-4050-4fb0-add3-18c88f1880b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975074915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.1975074915
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.4113923635
Short name T736
Test name
Test status
Simulation time 2415127979 ps
CPU time 12.91 seconds
Started Mar 31 01:23:28 PM PDT 24
Finished Mar 31 01:23:41 PM PDT 24
Peak memory 237376 kb
Host smart-77c0da38-77bc-4124-a4f3-bab576a1a868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113923635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.4113923635
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.1936204021
Short name T260
Test name
Test status
Simulation time 26849447612 ps
CPU time 24.76 seconds
Started Mar 31 01:23:30 PM PDT 24
Finished Mar 31 01:23:55 PM PDT 24
Peak memory 227628 kb
Host smart-c585c6e2-cb32-49e7-ab70-6f11e6606f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936204021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.1936204021
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.1691076150
Short name T635
Test name
Test status
Simulation time 16535906 ps
CPU time 0.74 seconds
Started Mar 31 01:23:29 PM PDT 24
Finished Mar 31 01:23:30 PM PDT 24
Peak memory 216676 kb
Host smart-ddbe0e7f-a63d-4bb6-b5e8-3bbe0af17f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691076150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.1691076150
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.2372214595
Short name T639
Test name
Test status
Simulation time 499351919 ps
CPU time 4.25 seconds
Started Mar 31 01:23:28 PM PDT 24
Finished Mar 31 01:23:32 PM PDT 24
Peak memory 223104 kb
Host smart-1416e53a-5116-4c79-9ce3-63b2b93d5ed2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2372214595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.2372214595
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.867419158
Short name T56
Test name
Test status
Simulation time 34635051 ps
CPU time 1.04 seconds
Started Mar 31 01:23:37 PM PDT 24
Finished Mar 31 01:23:39 PM PDT 24
Peak memory 235408 kb
Host smart-e1f83fca-4f2e-4cdc-917a-4a1079919e0a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867419158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.867419158
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.3257702068
Short name T725
Test name
Test status
Simulation time 954793783 ps
CPU time 6.99 seconds
Started Mar 31 01:23:28 PM PDT 24
Finished Mar 31 01:23:35 PM PDT 24
Peak memory 216708 kb
Host smart-29d25d51-c330-4378-a954-8631a70e5d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257702068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.3257702068
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.3305376531
Short name T610
Test name
Test status
Simulation time 154240846 ps
CPU time 2.9 seconds
Started Mar 31 01:23:27 PM PDT 24
Finished Mar 31 01:23:30 PM PDT 24
Peak memory 216680 kb
Host smart-d357f50d-ba40-4f4d-a6e7-65d0aec44a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305376531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.3305376531
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.444993153
Short name T116
Test name
Test status
Simulation time 103117368 ps
CPU time 1.1 seconds
Started Mar 31 01:23:30 PM PDT 24
Finished Mar 31 01:23:31 PM PDT 24
Peak memory 207244 kb
Host smart-ff31961d-164b-4550-9b51-4276218893cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444993153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.444993153
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.1891533970
Short name T325
Test name
Test status
Simulation time 241893223 ps
CPU time 5.6 seconds
Started Mar 31 01:23:28 PM PDT 24
Finished Mar 31 01:23:33 PM PDT 24
Peak memory 233064 kb
Host smart-1c76b5db-ecd3-4168-8748-2b7e282930a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891533970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.1891533970
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.818632679
Short name T575
Test name
Test status
Simulation time 36702543 ps
CPU time 0.74 seconds
Started Mar 31 01:23:41 PM PDT 24
Finished Mar 31 01:23:42 PM PDT 24
Peak memory 206044 kb
Host smart-555722f4-0f8b-468c-bdc5-5a190aa6eae2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818632679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.818632679
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.3278565127
Short name T598
Test name
Test status
Simulation time 65289536 ps
CPU time 0.76 seconds
Started Mar 31 01:23:38 PM PDT 24
Finished Mar 31 01:23:38 PM PDT 24
Peak memory 207172 kb
Host smart-75f8f04f-b92f-41c8-b606-e92976677b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278565127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.3278565127
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.243316520
Short name T266
Test name
Test status
Simulation time 2157170175 ps
CPU time 10.92 seconds
Started Mar 31 01:23:36 PM PDT 24
Finished Mar 31 01:23:47 PM PDT 24
Peak memory 218972 kb
Host smart-f3bbd882-6501-4beb-8246-3439e314335f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243316520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.243316520
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.833660139
Short name T544
Test name
Test status
Simulation time 1191971620 ps
CPU time 4.94 seconds
Started Mar 31 01:23:34 PM PDT 24
Finished Mar 31 01:23:39 PM PDT 24
Peak memory 223352 kb
Host smart-02114ee8-ce40-4112-a342-01b8e39bc2b5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=833660139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_direc
t.833660139
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.1590191880
Short name T706
Test name
Test status
Simulation time 11009367700 ps
CPU time 29.87 seconds
Started Mar 31 01:23:36 PM PDT 24
Finished Mar 31 01:24:06 PM PDT 24
Peak memory 216776 kb
Host smart-441ad65e-41d8-4482-acf5-d9703e1a55d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590191880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.1590191880
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1800466634
Short name T738
Test name
Test status
Simulation time 1780375534 ps
CPU time 7.45 seconds
Started Mar 31 01:23:38 PM PDT 24
Finished Mar 31 01:23:46 PM PDT 24
Peak memory 216700 kb
Host smart-f2645737-7943-4a83-beb3-6b886ee5a8bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800466634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1800466634
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.934649655
Short name T395
Test name
Test status
Simulation time 451672109 ps
CPU time 1.1 seconds
Started Mar 31 01:23:37 PM PDT 24
Finished Mar 31 01:23:38 PM PDT 24
Peak memory 207568 kb
Host smart-0da47dcb-30ab-4f50-9dc7-e51ae0927438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934649655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.934649655
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.2129417581
Short name T731
Test name
Test status
Simulation time 176482398 ps
CPU time 0.92 seconds
Started Mar 31 01:23:40 PM PDT 24
Finished Mar 31 01:23:41 PM PDT 24
Peak memory 207244 kb
Host smart-1168c12b-6947-492c-ad8d-50f5143ea83f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129417581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.2129417581
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.360659587
Short name T625
Test name
Test status
Simulation time 4901311102 ps
CPU time 20.31 seconds
Started Mar 31 01:24:09 PM PDT 24
Finished Mar 31 01:24:30 PM PDT 24
Peak memory 223860 kb
Host smart-5d928aba-b1b4-42e1-8b93-adce01caca72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360659587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.360659587
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.3738457396
Short name T689
Test name
Test status
Simulation time 14676533 ps
CPU time 0.78 seconds
Started Mar 31 01:24:03 PM PDT 24
Finished Mar 31 01:24:04 PM PDT 24
Peak memory 207088 kb
Host smart-5586fbc0-cdb8-4656-b0c7-51a83b8c1e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738457396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.3738457396
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.2694055624
Short name T301
Test name
Test status
Simulation time 1466747589 ps
CPU time 18.12 seconds
Started Mar 31 01:24:09 PM PDT 24
Finished Mar 31 01:24:27 PM PDT 24
Peak memory 249540 kb
Host smart-cb65ffbf-8624-4591-a244-90335dd5dd3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694055624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.2694055624
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.3894353296
Short name T200
Test name
Test status
Simulation time 20268066496 ps
CPU time 45.23 seconds
Started Mar 31 01:24:08 PM PDT 24
Finished Mar 31 01:24:53 PM PDT 24
Peak memory 235920 kb
Host smart-11a60552-3c8c-494d-a586-2a8070f486b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894353296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.3894353296
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.2116751272
Short name T60
Test name
Test status
Simulation time 14703932897 ps
CPU time 5.96 seconds
Started Mar 31 01:24:07 PM PDT 24
Finished Mar 31 01:24:13 PM PDT 24
Peak memory 224100 kb
Host smart-3b6a838b-cf21-4d30-86ee-7ff1a675d2c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116751272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.2116751272
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_ram_cfg.546229958
Short name T175
Test name
Test status
Simulation time 21166410 ps
CPU time 0.73 seconds
Started Mar 31 01:24:10 PM PDT 24
Finished Mar 31 01:24:11 PM PDT 24
Peak memory 216756 kb
Host smart-9d418544-8a02-4656-b8ba-5a620c318731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546229958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_ram_cfg.546229958
Directory /workspace/10.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.257786398
Short name T477
Test name
Test status
Simulation time 6484751245 ps
CPU time 7.84 seconds
Started Mar 31 01:24:08 PM PDT 24
Finished Mar 31 01:24:16 PM PDT 24
Peak memory 223364 kb
Host smart-b52329b4-f4d5-42a7-860b-02ad84dba5b1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=257786398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dire
ct.257786398
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.2196154894
Short name T117
Test name
Test status
Simulation time 6604879636 ps
CPU time 19.05 seconds
Started Mar 31 01:24:09 PM PDT 24
Finished Mar 31 01:24:28 PM PDT 24
Peak memory 216836 kb
Host smart-bd42c74b-3a57-42ca-8eef-8484aadd46a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196154894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.2196154894
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.1081149369
Short name T469
Test name
Test status
Simulation time 3877035775 ps
CPU time 3.01 seconds
Started Mar 31 01:24:11 PM PDT 24
Finished Mar 31 01:24:15 PM PDT 24
Peak memory 216864 kb
Host smart-81aaf36f-18f1-4600-b28a-f8415db58c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081149369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.1081149369
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.3617784891
Short name T572
Test name
Test status
Simulation time 117747266 ps
CPU time 0.87 seconds
Started Mar 31 01:24:09 PM PDT 24
Finished Mar 31 01:24:10 PM PDT 24
Peak memory 207204 kb
Host smart-9538b0b0-e54a-4505-957a-62b94c4cadca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617784891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.3617784891
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.980496807
Short name T264
Test name
Test status
Simulation time 19664086281 ps
CPU time 17.33 seconds
Started Mar 31 01:24:09 PM PDT 24
Finished Mar 31 01:24:26 PM PDT 24
Peak memory 236492 kb
Host smart-993a0905-44e8-43f1-99e6-22ecc889bf50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980496807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.980496807
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.3583363921
Short name T445
Test name
Test status
Simulation time 43512278 ps
CPU time 0.74 seconds
Started Mar 31 01:24:17 PM PDT 24
Finished Mar 31 01:24:18 PM PDT 24
Peak memory 205472 kb
Host smart-5fe2d3fc-cf5d-4605-8085-5aa3824e7099
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583363921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
3583363921
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.1598261419
Short name T710
Test name
Test status
Simulation time 1010952174 ps
CPU time 12.88 seconds
Started Mar 31 01:24:18 PM PDT 24
Finished Mar 31 01:24:31 PM PDT 24
Peak memory 224056 kb
Host smart-77e7b360-8732-46d4-a382-662431b0fe6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598261419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.1598261419
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.178575406
Short name T644
Test name
Test status
Simulation time 15320591 ps
CPU time 0.83 seconds
Started Mar 31 01:24:12 PM PDT 24
Finished Mar 31 01:24:13 PM PDT 24
Peak memory 207152 kb
Host smart-03af2713-e8ed-4016-bd7e-b624a5fddb3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178575406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.178575406
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_ram_cfg.1731098862
Short name T49
Test name
Test status
Simulation time 31336395 ps
CPU time 0.75 seconds
Started Mar 31 01:24:14 PM PDT 24
Finished Mar 31 01:24:15 PM PDT 24
Peak memory 216716 kb
Host smart-7a8479b1-139a-42e9-a8aa-2164334c4426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731098862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_ram_cfg.1731098862
Directory /workspace/11.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.1869754860
Short name T535
Test name
Test status
Simulation time 406892023 ps
CPU time 4.94 seconds
Started Mar 31 01:24:14 PM PDT 24
Finished Mar 31 01:24:20 PM PDT 24
Peak memory 223444 kb
Host smart-8866f19d-dc31-404e-b32b-74bce43a2ae1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1869754860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.1869754860
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.3979835182
Short name T638
Test name
Test status
Simulation time 21935681981 ps
CPU time 39 seconds
Started Mar 31 01:24:13 PM PDT 24
Finished Mar 31 01:24:52 PM PDT 24
Peak memory 217116 kb
Host smart-d9fd7f10-1257-45e2-b1be-cda08fe8f7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979835182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.3979835182
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.2185059056
Short name T548
Test name
Test status
Simulation time 1505604841 ps
CPU time 7.01 seconds
Started Mar 31 01:24:13 PM PDT 24
Finished Mar 31 01:24:20 PM PDT 24
Peak memory 216688 kb
Host smart-73a5c427-8bf3-429e-b73e-f57c0d3225c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185059056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.2185059056
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.163730790
Short name T504
Test name
Test status
Simulation time 17035633 ps
CPU time 0.75 seconds
Started Mar 31 01:24:15 PM PDT 24
Finished Mar 31 01:24:16 PM PDT 24
Peak memory 206240 kb
Host smart-80383613-98c9-4139-89df-d63510f61843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163730790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.163730790
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.4189584918
Short name T318
Test name
Test status
Simulation time 29058340503 ps
CPU time 25.54 seconds
Started Mar 31 01:24:12 PM PDT 24
Finished Mar 31 01:24:38 PM PDT 24
Peak memory 224712 kb
Host smart-3a569c33-cf00-4f3b-a093-569cc46b4dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189584918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.4189584918
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.3089363185
Short name T34
Test name
Test status
Simulation time 27822861 ps
CPU time 0.7 seconds
Started Mar 31 01:24:24 PM PDT 24
Finished Mar 31 01:24:25 PM PDT 24
Peak memory 206380 kb
Host smart-d6537d7f-f033-471d-9a3d-0723941bdf30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089363185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
3089363185
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.3712381995
Short name T711
Test name
Test status
Simulation time 17747887 ps
CPU time 0.83 seconds
Started Mar 31 01:24:18 PM PDT 24
Finished Mar 31 01:24:19 PM PDT 24
Peak memory 207128 kb
Host smart-53b2b2ed-98bf-45df-9031-cb2f4f394c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712381995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.3712381995
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_ram_cfg.696507048
Short name T632
Test name
Test status
Simulation time 42536669 ps
CPU time 0.76 seconds
Started Mar 31 01:24:20 PM PDT 24
Finished Mar 31 01:24:21 PM PDT 24
Peak memory 216656 kb
Host smart-0f56f19e-8580-400b-82df-de10006d4e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696507048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_ram_cfg.696507048
Directory /workspace/12.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.2724599341
Short name T660
Test name
Test status
Simulation time 627254991 ps
CPU time 6.76 seconds
Started Mar 31 01:24:20 PM PDT 24
Finished Mar 31 01:24:27 PM PDT 24
Peak memory 223288 kb
Host smart-8b56c191-968b-4a37-9566-795b49d8085b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2724599341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.2724599341
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.4115203919
Short name T617
Test name
Test status
Simulation time 2519460315 ps
CPU time 16.8 seconds
Started Mar 31 01:24:15 PM PDT 24
Finished Mar 31 01:24:32 PM PDT 24
Peak memory 216732 kb
Host smart-31525e48-d989-4888-ba63-3d249817d6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115203919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.4115203919
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.4015106629
Short name T594
Test name
Test status
Simulation time 882674544 ps
CPU time 6.29 seconds
Started Mar 31 01:24:17 PM PDT 24
Finished Mar 31 01:24:24 PM PDT 24
Peak memory 216700 kb
Host smart-8f3bd38b-a34e-4c53-a9b6-787cfd23e9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015106629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.4015106629
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.1321649791
Short name T608
Test name
Test status
Simulation time 216347535 ps
CPU time 3.07 seconds
Started Mar 31 01:24:14 PM PDT 24
Finished Mar 31 01:24:18 PM PDT 24
Peak memory 216796 kb
Host smart-ef2184b8-817c-465a-8980-4da61de4dfa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321649791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.1321649791
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.2772044935
Short name T442
Test name
Test status
Simulation time 386778618 ps
CPU time 0.97 seconds
Started Mar 31 01:24:17 PM PDT 24
Finished Mar 31 01:24:19 PM PDT 24
Peak memory 207232 kb
Host smart-1bb8e2cb-07c0-43d7-95bb-eb8387758fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772044935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.2772044935
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.4002577024
Short name T334
Test name
Test status
Simulation time 3152864616 ps
CPU time 13.24 seconds
Started Mar 31 01:24:21 PM PDT 24
Finished Mar 31 01:24:34 PM PDT 24
Peak memory 240264 kb
Host smart-b9d5623c-a77b-4437-99d0-01fad1dd5db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002577024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.4002577024
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.343226549
Short name T431
Test name
Test status
Simulation time 36048177 ps
CPU time 0.72 seconds
Started Mar 31 01:24:23 PM PDT 24
Finished Mar 31 01:24:24 PM PDT 24
Peak memory 205988 kb
Host smart-e888fd81-8f1a-4d11-9fbe-7fda157c22a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343226549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.343226549
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.2593562180
Short name T695
Test name
Test status
Simulation time 20988247 ps
CPU time 0.79 seconds
Started Mar 31 01:24:20 PM PDT 24
Finished Mar 31 01:24:21 PM PDT 24
Peak memory 207468 kb
Host smart-844ac878-e8c1-45e5-8453-1bcdcb065068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593562180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.2593562180
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.2379427020
Short name T125
Test name
Test status
Simulation time 85660525 ps
CPU time 2.6 seconds
Started Mar 31 01:24:24 PM PDT 24
Finished Mar 31 01:24:27 PM PDT 24
Peak memory 223500 kb
Host smart-aef28f66-023d-41dc-bd08-1260a2f52ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379427020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.2379427020
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_ram_cfg.2023095182
Short name T688
Test name
Test status
Simulation time 62340447 ps
CPU time 0.81 seconds
Started Mar 31 01:24:21 PM PDT 24
Finished Mar 31 01:24:22 PM PDT 24
Peak memory 216656 kb
Host smart-49bd8068-ce92-4882-836c-879125ace3a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023095182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_ram_cfg.2023095182
Directory /workspace/13.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.2552360420
Short name T720
Test name
Test status
Simulation time 3964455510 ps
CPU time 9.16 seconds
Started Mar 31 01:24:21 PM PDT 24
Finished Mar 31 01:24:31 PM PDT 24
Peak memory 219440 kb
Host smart-5e53a82f-79aa-4d21-9d52-d1f3f401d3e4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2552360420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.2552360420
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.239499112
Short name T380
Test name
Test status
Simulation time 33443574136 ps
CPU time 18.89 seconds
Started Mar 31 01:24:19 PM PDT 24
Finished Mar 31 01:24:38 PM PDT 24
Peak memory 216888 kb
Host smart-bf3016f0-1709-412c-a47a-5600e49dcc73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239499112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.239499112
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.444008943
Short name T636
Test name
Test status
Simulation time 10189240635 ps
CPU time 17.13 seconds
Started Mar 31 01:24:21 PM PDT 24
Finished Mar 31 01:24:39 PM PDT 24
Peak memory 216828 kb
Host smart-3f22a061-4231-499b-baf3-04e2fb9f1db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444008943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.444008943
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.1550060433
Short name T399
Test name
Test status
Simulation time 114970905 ps
CPU time 1.93 seconds
Started Mar 31 01:24:23 PM PDT 24
Finished Mar 31 01:24:25 PM PDT 24
Peak memory 216752 kb
Host smart-65430c79-bf23-4cf8-af72-710761325900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550060433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.1550060433
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.457660585
Short name T522
Test name
Test status
Simulation time 92378905 ps
CPU time 0.79 seconds
Started Mar 31 01:24:23 PM PDT 24
Finished Mar 31 01:24:24 PM PDT 24
Peak memory 206152 kb
Host smart-92d528a4-a242-40b5-9ba9-9628858f8908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457660585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.457660585
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.3032692069
Short name T199
Test name
Test status
Simulation time 13189701549 ps
CPU time 17.04 seconds
Started Mar 31 01:24:21 PM PDT 24
Finished Mar 31 01:24:38 PM PDT 24
Peak memory 239904 kb
Host smart-a442c456-f6a2-412b-ae66-4b654a065431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032692069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.3032692069
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.128210068
Short name T451
Test name
Test status
Simulation time 63558413 ps
CPU time 0.7 seconds
Started Mar 31 01:24:28 PM PDT 24
Finished Mar 31 01:24:29 PM PDT 24
Peak memory 205980 kb
Host smart-bb92850b-1f38-4ba7-b37b-36e942915a9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128210068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.128210068
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.1420091454
Short name T9
Test name
Test status
Simulation time 160542505 ps
CPU time 4.41 seconds
Started Mar 31 01:24:29 PM PDT 24
Finished Mar 31 01:24:34 PM PDT 24
Peak memory 219212 kb
Host smart-fc582520-f930-46b2-9270-811024f2d4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420091454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.1420091454
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.1967247946
Short name T464
Test name
Test status
Simulation time 33824584 ps
CPU time 0.78 seconds
Started Mar 31 01:24:19 PM PDT 24
Finished Mar 31 01:24:20 PM PDT 24
Peak memory 207448 kb
Host smart-aa973e02-3c24-4c6e-bf6f-d4e5d962f578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967247946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.1967247946
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.1770958092
Short name T101
Test name
Test status
Simulation time 30425197030 ps
CPU time 44.69 seconds
Started Mar 31 01:24:29 PM PDT 24
Finished Mar 31 01:25:13 PM PDT 24
Peak memory 236644 kb
Host smart-61d5a1cd-ab6b-4f67-b420-26fba0b9d63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770958092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.1770958092
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_ram_cfg.2856612541
Short name T484
Test name
Test status
Simulation time 17824310 ps
CPU time 0.75 seconds
Started Mar 31 01:24:22 PM PDT 24
Finished Mar 31 01:24:23 PM PDT 24
Peak memory 216748 kb
Host smart-b9e1b170-db1a-4c87-b730-fca11621d325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856612541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_ram_cfg.2856612541
Directory /workspace/14.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.1593536811
Short name T493
Test name
Test status
Simulation time 378984809 ps
CPU time 4.3 seconds
Started Mar 31 01:24:27 PM PDT 24
Finished Mar 31 01:24:31 PM PDT 24
Peak memory 223428 kb
Host smart-e23f2373-5d6a-4845-8fd4-d816f4248be3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1593536811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.1593536811
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.3811178267
Short name T616
Test name
Test status
Simulation time 2132328123 ps
CPU time 4.68 seconds
Started Mar 31 01:24:22 PM PDT 24
Finished Mar 31 01:24:26 PM PDT 24
Peak memory 219208 kb
Host smart-c50b3b74-fa8f-46ea-b65c-c75ec104274c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811178267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.3811178267
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.675305822
Short name T614
Test name
Test status
Simulation time 2044442582 ps
CPU time 9.81 seconds
Started Mar 31 01:24:26 PM PDT 24
Finished Mar 31 01:24:36 PM PDT 24
Peak memory 216792 kb
Host smart-fab77f5c-0983-4d3c-aa28-96439b835a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675305822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.675305822
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.953541930
Short name T700
Test name
Test status
Simulation time 48708120 ps
CPU time 2.03 seconds
Started Mar 31 01:24:25 PM PDT 24
Finished Mar 31 01:24:28 PM PDT 24
Peak memory 216664 kb
Host smart-ac9c4840-d942-40af-b56f-0cd68d9a40f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953541930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.953541930
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.3878052782
Short name T414
Test name
Test status
Simulation time 63422395 ps
CPU time 0.91 seconds
Started Mar 31 01:24:19 PM PDT 24
Finished Mar 31 01:24:20 PM PDT 24
Peak memory 207224 kb
Host smart-6bd929b2-371b-4cfe-98cb-0e30c01478a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878052782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.3878052782
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.3327328240
Short name T579
Test name
Test status
Simulation time 40548156 ps
CPU time 0.74 seconds
Started Mar 31 01:24:29 PM PDT 24
Finished Mar 31 01:24:29 PM PDT 24
Peak memory 205320 kb
Host smart-b255da5f-28d4-4411-998c-b8e8b6f11625
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327328240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
3327328240
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.3660848344
Short name T27
Test name
Test status
Simulation time 109548152 ps
CPU time 3.31 seconds
Started Mar 31 01:24:25 PM PDT 24
Finished Mar 31 01:24:29 PM PDT 24
Peak memory 224676 kb
Host smart-0e833557-6104-41c3-a815-426642e9c3ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660848344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.3660848344
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.2910714583
Short name T693
Test name
Test status
Simulation time 25008165 ps
CPU time 0.74 seconds
Started Mar 31 01:24:32 PM PDT 24
Finished Mar 31 01:24:32 PM PDT 24
Peak memory 206460 kb
Host smart-c6457d26-8cd5-4f5d-b31b-7f9162fcc9f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910714583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.2910714583
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.3448644318
Short name T511
Test name
Test status
Simulation time 7589727363 ps
CPU time 59.61 seconds
Started Mar 31 01:24:28 PM PDT 24
Finished Mar 31 01:25:28 PM PDT 24
Peak memory 241332 kb
Host smart-5bb41bc4-fd2c-42d6-890c-4a3e4c8a505a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448644318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.3448644318
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.3497113919
Short name T184
Test name
Test status
Simulation time 5811725094 ps
CPU time 20.49 seconds
Started Mar 31 01:24:29 PM PDT 24
Finished Mar 31 01:24:50 PM PDT 24
Peak memory 235832 kb
Host smart-b7a5fba7-c5dc-42d4-aced-742d64896606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497113919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.3497113919
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_ram_cfg.2618819960
Short name T655
Test name
Test status
Simulation time 35133638 ps
CPU time 0.76 seconds
Started Mar 31 01:24:27 PM PDT 24
Finished Mar 31 01:24:28 PM PDT 24
Peak memory 216776 kb
Host smart-9e2aef58-287a-4ba7-87b2-a83d45997920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618819960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_ram_cfg.2618819960
Directory /workspace/15.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.2240211653
Short name T580
Test name
Test status
Simulation time 89389185 ps
CPU time 3.94 seconds
Started Mar 31 01:24:25 PM PDT 24
Finished Mar 31 01:24:30 PM PDT 24
Peak memory 222104 kb
Host smart-e0e52e5d-ede7-4ec6-b913-839ef9843034
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2240211653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.2240211653
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.2564127074
Short name T390
Test name
Test status
Simulation time 44109467184 ps
CPU time 57 seconds
Started Mar 31 01:24:27 PM PDT 24
Finished Mar 31 01:25:24 PM PDT 24
Peak memory 216820 kb
Host smart-b635849d-e14f-4bff-bff2-e2010b169421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564127074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.2564127074
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.3393252786
Short name T651
Test name
Test status
Simulation time 1624826151 ps
CPU time 3.45 seconds
Started Mar 31 01:24:31 PM PDT 24
Finished Mar 31 01:24:34 PM PDT 24
Peak memory 216752 kb
Host smart-11f70345-d124-4052-a48a-5c7568edab55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393252786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.3393252786
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.368881782
Short name T721
Test name
Test status
Simulation time 28416044 ps
CPU time 1.32 seconds
Started Mar 31 01:24:26 PM PDT 24
Finished Mar 31 01:24:27 PM PDT 24
Peak memory 216696 kb
Host smart-c318d1dc-3e4f-47cc-bf1f-42d56c50bab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368881782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.368881782
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.1883195568
Short name T574
Test name
Test status
Simulation time 89528420 ps
CPU time 0.93 seconds
Started Mar 31 01:24:27 PM PDT 24
Finished Mar 31 01:24:28 PM PDT 24
Peak memory 206208 kb
Host smart-80454523-f8b0-4592-98cd-03d510dc520c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883195568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.1883195568
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.953339401
Short name T623
Test name
Test status
Simulation time 44788502 ps
CPU time 0.69 seconds
Started Mar 31 01:24:33 PM PDT 24
Finished Mar 31 01:24:34 PM PDT 24
Peak memory 205940 kb
Host smart-dc758f8f-77ca-41b8-9a96-cdee04fcf59b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953339401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.953339401
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.288277947
Short name T258
Test name
Test status
Simulation time 822399546 ps
CPU time 4.34 seconds
Started Mar 31 01:24:36 PM PDT 24
Finished Mar 31 01:24:40 PM PDT 24
Peak memory 217060 kb
Host smart-ce1ebf4c-f9d4-4a1b-8efa-c8e496c7fba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288277947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.288277947
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.3597799134
Short name T654
Test name
Test status
Simulation time 39661151 ps
CPU time 0.77 seconds
Started Mar 31 01:24:25 PM PDT 24
Finished Mar 31 01:24:26 PM PDT 24
Peak memory 207164 kb
Host smart-30f7e763-5764-4b5a-b508-b1bc628b2194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597799134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.3597799134
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.1217178243
Short name T313
Test name
Test status
Simulation time 1615326339 ps
CPU time 23.4 seconds
Started Mar 31 01:24:37 PM PDT 24
Finished Mar 31 01:25:00 PM PDT 24
Peak memory 239976 kb
Host smart-55fb4bf0-a419-42e6-abc6-9a988821ef69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217178243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.1217178243
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.1633441430
Short name T316
Test name
Test status
Simulation time 575770161 ps
CPU time 3.81 seconds
Started Mar 31 01:24:28 PM PDT 24
Finished Mar 31 01:24:32 PM PDT 24
Peak memory 224460 kb
Host smart-74fd1763-7f53-4a8b-a158-5a801078a908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633441430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.1633441430
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.2288811420
Short name T249
Test name
Test status
Simulation time 43065258320 ps
CPU time 54.72 seconds
Started Mar 31 01:24:32 PM PDT 24
Finished Mar 31 01:25:27 PM PDT 24
Peak memory 223780 kb
Host smart-f7dd9cf5-c74e-4a39-9548-4ab3242fc57f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288811420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.2288811420
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_ram_cfg.196907459
Short name T603
Test name
Test status
Simulation time 24505446 ps
CPU time 0.74 seconds
Started Mar 31 01:24:27 PM PDT 24
Finished Mar 31 01:24:27 PM PDT 24
Peak memory 216740 kb
Host smart-d78c8e17-f816-4efb-89b9-8c62b4e0cf2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196907459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_ram_cfg.196907459
Directory /workspace/16.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.197374859
Short name T656
Test name
Test status
Simulation time 531693142 ps
CPU time 3.98 seconds
Started Mar 31 01:24:34 PM PDT 24
Finished Mar 31 01:24:39 PM PDT 24
Peak memory 221328 kb
Host smart-5690235a-6ff7-4a7b-8d91-e3b4ae427508
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=197374859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dire
ct.197374859
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.4275808096
Short name T384
Test name
Test status
Simulation time 9433453106 ps
CPU time 54.01 seconds
Started Mar 31 01:24:28 PM PDT 24
Finished Mar 31 01:25:23 PM PDT 24
Peak memory 216880 kb
Host smart-c7d30115-912f-4cdd-b77b-744f8687b9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275808096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.4275808096
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.365019680
Short name T734
Test name
Test status
Simulation time 848132899 ps
CPU time 4.55 seconds
Started Mar 31 01:24:28 PM PDT 24
Finished Mar 31 01:24:33 PM PDT 24
Peak memory 216764 kb
Host smart-e0d40465-bf3d-4766-9228-69f0238fceae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365019680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.365019680
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.3924222782
Short name T723
Test name
Test status
Simulation time 94435572 ps
CPU time 1.32 seconds
Started Mar 31 01:24:27 PM PDT 24
Finished Mar 31 01:24:29 PM PDT 24
Peak memory 216148 kb
Host smart-f15f246e-a9b4-4720-8039-8193298928df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924222782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.3924222782
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.1696982035
Short name T607
Test name
Test status
Simulation time 99138111 ps
CPU time 1.02 seconds
Started Mar 31 01:24:29 PM PDT 24
Finished Mar 31 01:24:30 PM PDT 24
Peak memory 206192 kb
Host smart-636201bd-1fc6-434e-bb08-2590520c922e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696982035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.1696982035
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.1618651704
Short name T474
Test name
Test status
Simulation time 42430989 ps
CPU time 0.74 seconds
Started Mar 31 01:24:35 PM PDT 24
Finished Mar 31 01:24:35 PM PDT 24
Peak memory 205376 kb
Host smart-35329364-aedf-47c8-bf55-61122bfcfbcf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618651704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
1618651704
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.2849229068
Short name T459
Test name
Test status
Simulation time 28083534 ps
CPU time 0.76 seconds
Started Mar 31 01:24:33 PM PDT 24
Finished Mar 31 01:24:34 PM PDT 24
Peak memory 206116 kb
Host smart-41d2811e-68a9-4cac-9793-c5a0d6de9338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849229068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.2849229068
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.1358934144
Short name T312
Test name
Test status
Simulation time 4734477941 ps
CPU time 11.51 seconds
Started Mar 31 01:24:35 PM PDT 24
Finished Mar 31 01:24:46 PM PDT 24
Peak memory 249180 kb
Host smart-f22d589f-1e03-453e-89c5-4aa1174a70db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358934144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.1358934144
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.2589052631
Short name T237
Test name
Test status
Simulation time 2228202785 ps
CPU time 16.4 seconds
Started Mar 31 01:24:36 PM PDT 24
Finished Mar 31 01:24:52 PM PDT 24
Peak memory 222996 kb
Host smart-e0495ffe-8511-4a5f-94ca-310bbd5a66ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589052631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.2589052631
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_ram_cfg.3005967936
Short name T519
Test name
Test status
Simulation time 37556194 ps
CPU time 0.71 seconds
Started Mar 31 01:24:36 PM PDT 24
Finished Mar 31 01:24:37 PM PDT 24
Peak memory 216672 kb
Host smart-a1195ef8-fb59-4d34-8fe2-7336f8f17a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005967936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_ram_cfg.3005967936
Directory /workspace/17.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.3767622210
Short name T106
Test name
Test status
Simulation time 1476984522 ps
CPU time 21.02 seconds
Started Mar 31 01:24:35 PM PDT 24
Finished Mar 31 01:24:56 PM PDT 24
Peak memory 219588 kb
Host smart-72d73cca-084f-4c35-bcee-c05ddffcc229
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3767622210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.3767622210
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.1652707444
Short name T393
Test name
Test status
Simulation time 3248589557 ps
CPU time 7.15 seconds
Started Mar 31 01:24:35 PM PDT 24
Finished Mar 31 01:24:42 PM PDT 24
Peak memory 216704 kb
Host smart-c4dee0c8-7c0d-4b33-8502-dbec11b1f7e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652707444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.1652707444
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.3507387494
Short name T517
Test name
Test status
Simulation time 486311432 ps
CPU time 2.94 seconds
Started Mar 31 01:24:34 PM PDT 24
Finished Mar 31 01:24:37 PM PDT 24
Peak memory 216812 kb
Host smart-4eded3f0-d962-4683-a562-13a21602e519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507387494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.3507387494
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.2340760160
Short name T446
Test name
Test status
Simulation time 372952338 ps
CPU time 1.45 seconds
Started Mar 31 01:24:34 PM PDT 24
Finished Mar 31 01:24:36 PM PDT 24
Peak memory 216768 kb
Host smart-2cd14043-7eea-45c7-9ce1-24511eb44ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340760160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.2340760160
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.3788623862
Short name T421
Test name
Test status
Simulation time 48143435 ps
CPU time 0.92 seconds
Started Mar 31 01:24:36 PM PDT 24
Finished Mar 31 01:24:37 PM PDT 24
Peak memory 206156 kb
Host smart-f1c0ff93-e6f6-424b-a658-84962bb63632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788623862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.3788623862
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.4019232915
Short name T518
Test name
Test status
Simulation time 24859692 ps
CPU time 0.71 seconds
Started Mar 31 01:24:41 PM PDT 24
Finished Mar 31 01:24:42 PM PDT 24
Peak memory 205948 kb
Host smart-bd4665ec-95af-4c75-a1b6-a96d16eec888
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019232915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
4019232915
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.3495374523
Short name T360
Test name
Test status
Simulation time 2924350461 ps
CPU time 19.71 seconds
Started Mar 31 01:24:40 PM PDT 24
Finished Mar 31 01:25:00 PM PDT 24
Peak memory 253612 kb
Host smart-c25be1ea-4887-4553-940f-499456315070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495374523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.3495374523
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.2620121060
Short name T50
Test name
Test status
Simulation time 914073376 ps
CPU time 10.28 seconds
Started Mar 31 01:24:41 PM PDT 24
Finished Mar 31 01:24:52 PM PDT 24
Peak memory 224120 kb
Host smart-b353265d-2dc1-4cac-88ba-122adca15278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620121060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.2620121060
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.1842704964
Short name T629
Test name
Test status
Simulation time 160110218146 ps
CPU time 128.89 seconds
Started Mar 31 01:24:41 PM PDT 24
Finished Mar 31 01:26:50 PM PDT 24
Peak memory 239312 kb
Host smart-b7e271bd-7778-45f2-92c3-161fd2573e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842704964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.1842704964
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_ram_cfg.3392256317
Short name T460
Test name
Test status
Simulation time 24538914 ps
CPU time 0.73 seconds
Started Mar 31 01:24:36 PM PDT 24
Finished Mar 31 01:24:37 PM PDT 24
Peak memory 216672 kb
Host smart-2cb2e265-7426-4878-9fbd-3892db2329bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392256317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_ram_cfg.3392256317
Directory /workspace/18.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.2462691975
Short name T107
Test name
Test status
Simulation time 118106184 ps
CPU time 4.38 seconds
Started Mar 31 01:24:38 PM PDT 24
Finished Mar 31 01:24:43 PM PDT 24
Peak memory 223432 kb
Host smart-e061f220-9978-49a6-aa3f-b6081a6c4ef2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2462691975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.2462691975
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.4241143435
Short name T679
Test name
Test status
Simulation time 131516515 ps
CPU time 1.04 seconds
Started Mar 31 01:24:38 PM PDT 24
Finished Mar 31 01:24:39 PM PDT 24
Peak memory 207784 kb
Host smart-39ec3377-1f83-4e54-9011-6b52d2cdfb97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241143435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.4241143435
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.1527749638
Short name T387
Test name
Test status
Simulation time 4623207653 ps
CPU time 13.22 seconds
Started Mar 31 01:24:36 PM PDT 24
Finished Mar 31 01:24:49 PM PDT 24
Peak memory 216852 kb
Host smart-e9efb296-f20b-4f26-ab97-d14209437a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527749638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.1527749638
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.1717963288
Short name T621
Test name
Test status
Simulation time 50287256751 ps
CPU time 8.87 seconds
Started Mar 31 01:24:35 PM PDT 24
Finished Mar 31 01:24:44 PM PDT 24
Peak memory 216744 kb
Host smart-178273b7-b667-4b96-9104-475e7684f2c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717963288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.1717963288
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.2837727670
Short name T674
Test name
Test status
Simulation time 1008540067 ps
CPU time 2.4 seconds
Started Mar 31 01:24:35 PM PDT 24
Finished Mar 31 01:24:37 PM PDT 24
Peak memory 216704 kb
Host smart-47a238a9-bc81-48be-bd4b-4b68f53efb3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837727670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.2837727670
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.1130515399
Short name T406
Test name
Test status
Simulation time 128132845 ps
CPU time 0.86 seconds
Started Mar 31 01:24:37 PM PDT 24
Finished Mar 31 01:24:38 PM PDT 24
Peak memory 206276 kb
Host smart-1a185763-13bf-4847-b9a8-f9b12eab5b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130515399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.1130515399
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.1650521187
Short name T626
Test name
Test status
Simulation time 27387243 ps
CPU time 0.67 seconds
Started Mar 31 01:24:39 PM PDT 24
Finished Mar 31 01:24:40 PM PDT 24
Peak memory 205364 kb
Host smart-3772b3e8-c96e-4c5f-a658-1829d03dc9ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650521187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
1650521187
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.3409481853
Short name T590
Test name
Test status
Simulation time 15662512 ps
CPU time 0.75 seconds
Started Mar 31 01:24:41 PM PDT 24
Finished Mar 31 01:24:42 PM PDT 24
Peak memory 207480 kb
Host smart-4d1bfbe6-8ddd-4fb3-a63b-949e21fd3448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409481853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.3409481853
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.2382223667
Short name T14
Test name
Test status
Simulation time 1668307997 ps
CPU time 16.92 seconds
Started Mar 31 01:24:42 PM PDT 24
Finished Mar 31 01:24:59 PM PDT 24
Peak memory 240744 kb
Host smart-76848c10-0422-4ca8-9000-fd383e599506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382223667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.2382223667
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.1263644157
Short name T128
Test name
Test status
Simulation time 1058660040 ps
CPU time 9.35 seconds
Started Mar 31 01:24:41 PM PDT 24
Finished Mar 31 01:24:50 PM PDT 24
Peak memory 224548 kb
Host smart-b49e3501-4eac-4108-bb7d-bf4246ad41ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263644157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.1263644157
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_ram_cfg.1889846465
Short name T439
Test name
Test status
Simulation time 16307858 ps
CPU time 0.76 seconds
Started Mar 31 01:24:43 PM PDT 24
Finished Mar 31 01:24:43 PM PDT 24
Peak memory 216776 kb
Host smart-ce30d92d-d6a0-4fad-9131-2183c6132280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889846465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_ram_cfg.1889846465
Directory /workspace/19.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.4240226504
Short name T512
Test name
Test status
Simulation time 1023433794 ps
CPU time 4.73 seconds
Started Mar 31 01:24:42 PM PDT 24
Finished Mar 31 01:24:46 PM PDT 24
Peak memory 222344 kb
Host smart-32180def-49ac-490a-b770-5d3a2d2f29a0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4240226504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.4240226504
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.2438756471
Short name T361
Test name
Test status
Simulation time 219039653 ps
CPU time 1.08 seconds
Started Mar 31 01:24:43 PM PDT 24
Finished Mar 31 01:24:44 PM PDT 24
Peak memory 216024 kb
Host smart-d37bbf59-5740-4c70-87fc-ecd8f7f54d6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438756471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.2438756471
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.3539479984
Short name T112
Test name
Test status
Simulation time 6037225503 ps
CPU time 14.74 seconds
Started Mar 31 01:24:39 PM PDT 24
Finished Mar 31 01:24:54 PM PDT 24
Peak memory 220308 kb
Host smart-750f8807-3075-4ea7-8d99-b8f063391e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539479984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.3539479984
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.4288830515
Short name T665
Test name
Test status
Simulation time 19802341823 ps
CPU time 37.93 seconds
Started Mar 31 01:24:45 PM PDT 24
Finished Mar 31 01:25:23 PM PDT 24
Peak memory 216808 kb
Host smart-7e4a6e55-0278-4f45-8fc6-23762815d530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288830515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.4288830515
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.4176650404
Short name T471
Test name
Test status
Simulation time 35861063 ps
CPU time 0.99 seconds
Started Mar 31 01:24:39 PM PDT 24
Finished Mar 31 01:24:40 PM PDT 24
Peak memory 207136 kb
Host smart-7022ff71-9f3c-4c7e-b6be-9ff729cd42af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176650404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.4176650404
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.996585073
Short name T500
Test name
Test status
Simulation time 67132261 ps
CPU time 0.96 seconds
Started Mar 31 01:24:42 PM PDT 24
Finished Mar 31 01:24:43 PM PDT 24
Peak memory 206192 kb
Host smart-8adb63e5-aed8-489d-879e-97fdd6f2e950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996585073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.996585073
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.2760151528
Short name T473
Test name
Test status
Simulation time 71144568 ps
CPU time 0.73 seconds
Started Mar 31 01:23:41 PM PDT 24
Finished Mar 31 01:23:42 PM PDT 24
Peak memory 206052 kb
Host smart-785ef2a3-79c1-4927-bc89-ab9eff705ee7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760151528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.2
760151528
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.4214273325
Short name T489
Test name
Test status
Simulation time 86318564 ps
CPU time 0.81 seconds
Started Mar 31 01:23:35 PM PDT 24
Finished Mar 31 01:23:37 PM PDT 24
Peak memory 206100 kb
Host smart-992c5059-7bdf-445e-8419-2eea039458e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214273325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.4214273325
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.1698707767
Short name T91
Test name
Test status
Simulation time 8017020336 ps
CPU time 57.79 seconds
Started Mar 31 01:23:39 PM PDT 24
Finished Mar 31 01:24:37 PM PDT 24
Peak memory 240524 kb
Host smart-e3b8a511-6baa-4d91-a0e4-a0e9043b76ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698707767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.1698707767
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.1734210105
Short name T332
Test name
Test status
Simulation time 1847672010 ps
CPU time 16.64 seconds
Started Mar 31 01:23:40 PM PDT 24
Finished Mar 31 01:23:57 PM PDT 24
Peak memory 222996 kb
Host smart-14ab93dd-9776-4930-b7e1-1313b98ddf8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734210105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.1734210105
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.3602494050
Short name T214
Test name
Test status
Simulation time 21086873778 ps
CPU time 41.47 seconds
Started Mar 31 01:23:37 PM PDT 24
Finished Mar 31 01:24:18 PM PDT 24
Peak memory 234112 kb
Host smart-b0011e2a-bd13-4e7f-b978-118fd41ba2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602494050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.3602494050
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_ram_cfg.195555867
Short name T605
Test name
Test status
Simulation time 33315706 ps
CPU time 0.74 seconds
Started Mar 31 01:23:42 PM PDT 24
Finished Mar 31 01:23:44 PM PDT 24
Peak memory 216632 kb
Host smart-1fd20d47-583b-4a85-a19c-e134e1460406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195555867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_ram_cfg.195555867
Directory /workspace/2.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.426898498
Short name T525
Test name
Test status
Simulation time 1408757857 ps
CPU time 6.53 seconds
Started Mar 31 01:23:40 PM PDT 24
Finished Mar 31 01:23:47 PM PDT 24
Peak memory 222244 kb
Host smart-60ddd6cf-77d6-4780-b7c5-a6d122d84d3a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=426898498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direc
t.426898498
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.1196607971
Short name T55
Test name
Test status
Simulation time 470990807 ps
CPU time 0.96 seconds
Started Mar 31 01:23:43 PM PDT 24
Finished Mar 31 01:23:44 PM PDT 24
Peak memory 235644 kb
Host smart-a653927a-437c-47a9-a45a-c82eb33b1523
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196607971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.1196607971
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.1017258892
Short name T709
Test name
Test status
Simulation time 777328970 ps
CPU time 4.65 seconds
Started Mar 31 01:23:38 PM PDT 24
Finished Mar 31 01:23:43 PM PDT 24
Peak memory 216816 kb
Host smart-f6fda09d-333b-40ac-afab-6114db8f83df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017258892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.1017258892
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.192599729
Short name T506
Test name
Test status
Simulation time 8040404468 ps
CPU time 22.31 seconds
Started Mar 31 01:23:36 PM PDT 24
Finished Mar 31 01:23:59 PM PDT 24
Peak memory 216828 kb
Host smart-7137c3c8-05f8-4b93-a70f-ad18c7d51d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192599729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.192599729
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.2788794679
Short name T542
Test name
Test status
Simulation time 248683281 ps
CPU time 2.04 seconds
Started Mar 31 01:23:39 PM PDT 24
Finished Mar 31 01:23:42 PM PDT 24
Peak memory 216756 kb
Host smart-2d4a5530-3bec-4dd0-8d72-6ff91fc97dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788794679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.2788794679
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.3265686979
Short name T502
Test name
Test status
Simulation time 506274076 ps
CPU time 0.93 seconds
Started Mar 31 01:23:38 PM PDT 24
Finished Mar 31 01:23:39 PM PDT 24
Peak memory 206292 kb
Host smart-230630ab-e0a9-4ede-9e10-2d7f680a5639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265686979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.3265686979
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.179751383
Short name T531
Test name
Test status
Simulation time 16717325 ps
CPU time 0.7 seconds
Started Mar 31 01:24:47 PM PDT 24
Finished Mar 31 01:24:48 PM PDT 24
Peak memory 206264 kb
Host smart-c5e126b1-babd-4b06-89fc-d32c931bceb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179751383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.179751383
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.171895996
Short name T490
Test name
Test status
Simulation time 15019292 ps
CPU time 0.8 seconds
Started Mar 31 01:24:40 PM PDT 24
Finished Mar 31 01:24:40 PM PDT 24
Peak memory 207460 kb
Host smart-f71d17a4-0f56-4995-bbdb-e4d88db8ba90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171895996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.171895996
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.2310668439
Short name T353
Test name
Test status
Simulation time 11436346257 ps
CPU time 46.46 seconds
Started Mar 31 01:24:41 PM PDT 24
Finished Mar 31 01:25:28 PM PDT 24
Peak memory 233204 kb
Host smart-dbe46730-d574-4fb2-9a74-2d0d123f8e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310668439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.2310668439
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.2524366851
Short name T104
Test name
Test status
Simulation time 1238616703 ps
CPU time 14.92 seconds
Started Mar 31 01:24:38 PM PDT 24
Finished Mar 31 01:24:53 PM PDT 24
Peak memory 223664 kb
Host smart-678397f8-8354-4935-860a-d59b0828cce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524366851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.2524366851
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.3473573765
Short name T234
Test name
Test status
Simulation time 443686522 ps
CPU time 4.64 seconds
Started Mar 31 01:24:40 PM PDT 24
Finished Mar 31 01:24:45 PM PDT 24
Peak memory 219048 kb
Host smart-257dfc84-1696-488b-9c78-705c47844f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473573765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.3473573765
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.253568927
Short name T182
Test name
Test status
Simulation time 1478070657 ps
CPU time 3.83 seconds
Started Mar 31 01:24:42 PM PDT 24
Finished Mar 31 01:24:46 PM PDT 24
Peak memory 217188 kb
Host smart-609b729d-3764-49f0-a371-4c079881c7be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253568927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.253568927
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.2029895179
Short name T496
Test name
Test status
Simulation time 1002484201 ps
CPU time 5.2 seconds
Started Mar 31 01:24:39 PM PDT 24
Finished Mar 31 01:24:44 PM PDT 24
Peak memory 219376 kb
Host smart-a8ebad5b-9005-4887-9388-93d871b3574a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2029895179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.2029895179
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.55682619
Short name T647
Test name
Test status
Simulation time 43902062452 ps
CPU time 58.38 seconds
Started Mar 31 01:24:42 PM PDT 24
Finished Mar 31 01:25:40 PM PDT 24
Peak memory 216812 kb
Host smart-0459b0bb-1b77-4140-b979-ac27e03e6035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55682619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.55682619
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.114747505
Short name T463
Test name
Test status
Simulation time 44184648 ps
CPU time 0.94 seconds
Started Mar 31 01:24:43 PM PDT 24
Finished Mar 31 01:24:44 PM PDT 24
Peak memory 206992 kb
Host smart-d10cde61-fc32-4bd2-a085-2778063153e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114747505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.114747505
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.3090932557
Short name T662
Test name
Test status
Simulation time 72178240 ps
CPU time 0.92 seconds
Started Mar 31 01:24:42 PM PDT 24
Finished Mar 31 01:24:43 PM PDT 24
Peak memory 206296 kb
Host smart-816cce90-c11a-4bcc-8b27-cc452a920765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090932557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.3090932557
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.2347970857
Short name T33
Test name
Test status
Simulation time 37794881 ps
CPU time 0.69 seconds
Started Mar 31 01:24:46 PM PDT 24
Finished Mar 31 01:24:47 PM PDT 24
Peak memory 205408 kb
Host smart-8518134d-0a86-4e93-bf20-c954f354faac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347970857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
2347970857
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.2073723126
Short name T599
Test name
Test status
Simulation time 47077349 ps
CPU time 0.83 seconds
Started Mar 31 01:24:45 PM PDT 24
Finished Mar 31 01:24:46 PM PDT 24
Peak memory 207096 kb
Host smart-1f7d4ca7-ecb5-48ea-9eb4-eb2ffd67bb0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073723126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.2073723126
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.1436598720
Short name T410
Test name
Test status
Simulation time 1755572503 ps
CPU time 19.56 seconds
Started Mar 31 01:24:46 PM PDT 24
Finished Mar 31 01:25:06 PM PDT 24
Peak memory 257376 kb
Host smart-1ba54ea0-2b38-4ba0-aa3e-439907037fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436598720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.1436598720
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.1504565611
Short name T97
Test name
Test status
Simulation time 1292656062 ps
CPU time 18.37 seconds
Started Mar 31 01:24:50 PM PDT 24
Finished Mar 31 01:25:08 PM PDT 24
Peak memory 219520 kb
Host smart-135238d4-357d-49f7-9a30-d95b3ab965c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504565611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.1504565611
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.1150113337
Short name T242
Test name
Test status
Simulation time 9758635089 ps
CPU time 16.41 seconds
Started Mar 31 01:24:44 PM PDT 24
Finished Mar 31 01:25:00 PM PDT 24
Peak memory 224548 kb
Host smart-83cb638b-08be-4e27-a2ca-2c2428c5f8ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150113337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.1150113337
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.3827901256
Short name T694
Test name
Test status
Simulation time 178461211 ps
CPU time 3.72 seconds
Started Mar 31 01:24:46 PM PDT 24
Finished Mar 31 01:24:50 PM PDT 24
Peak memory 222188 kb
Host smart-b62500f9-a35a-4b14-8c8f-d370dec3ea20
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3827901256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.3827901256
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.3092361940
Short name T681
Test name
Test status
Simulation time 39407208 ps
CPU time 0.95 seconds
Started Mar 31 01:24:44 PM PDT 24
Finished Mar 31 01:24:45 PM PDT 24
Peak memory 207152 kb
Host smart-6a7db3e3-baee-420c-8d29-4935187f506b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092361940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.3092361940
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.81154361
Short name T677
Test name
Test status
Simulation time 2350507121 ps
CPU time 10.34 seconds
Started Mar 31 01:24:45 PM PDT 24
Finished Mar 31 01:24:56 PM PDT 24
Peak memory 216824 kb
Host smart-286295c9-588f-49bb-9a82-357cb938fbe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81154361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.81154361
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.204360004
Short name T515
Test name
Test status
Simulation time 379517581 ps
CPU time 2.01 seconds
Started Mar 31 01:24:45 PM PDT 24
Finished Mar 31 01:24:48 PM PDT 24
Peak memory 216724 kb
Host smart-04446423-ad91-4afe-9a65-ad4f8a4dc551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204360004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.204360004
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.3345925640
Short name T437
Test name
Test status
Simulation time 20466528 ps
CPU time 0.76 seconds
Started Mar 31 01:24:45 PM PDT 24
Finished Mar 31 01:24:45 PM PDT 24
Peak memory 206200 kb
Host smart-dc8698c2-0526-4bf7-82a4-5ea69dbd44fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345925640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.3345925640
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.731162141
Short name T212
Test name
Test status
Simulation time 2683594469 ps
CPU time 6.43 seconds
Started Mar 31 01:24:53 PM PDT 24
Finished Mar 31 01:25:00 PM PDT 24
Peak memory 234832 kb
Host smart-6c655a40-6b76-49c7-8b14-c49416a48b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731162141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.731162141
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.80273611
Short name T497
Test name
Test status
Simulation time 70194834 ps
CPU time 0.72 seconds
Started Mar 31 01:24:59 PM PDT 24
Finished Mar 31 01:25:00 PM PDT 24
Peak memory 205404 kb
Host smart-777f8d9d-6864-41a9-9ee4-28a57bc6f81c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80273611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.80273611
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.769184066
Short name T317
Test name
Test status
Simulation time 174317132 ps
CPU time 3.7 seconds
Started Mar 31 01:24:45 PM PDT 24
Finished Mar 31 01:24:49 PM PDT 24
Peak memory 223292 kb
Host smart-3fd530fe-b9f7-4151-a0fb-4acbdf2b618d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769184066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.769184066
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.2900744661
Short name T643
Test name
Test status
Simulation time 49729826 ps
CPU time 0.78 seconds
Started Mar 31 01:24:46 PM PDT 24
Finished Mar 31 01:24:47 PM PDT 24
Peak memory 207104 kb
Host smart-62addf1f-066c-414c-866e-eb8344618aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900744661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.2900744661
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.1390975490
Short name T352
Test name
Test status
Simulation time 2377209945 ps
CPU time 17.29 seconds
Started Mar 31 01:24:59 PM PDT 24
Finished Mar 31 01:25:17 PM PDT 24
Peak memory 233232 kb
Host smart-4c330482-df8f-4547-8d5c-e43cff32eba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390975490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.1390975490
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.1108215577
Short name T251
Test name
Test status
Simulation time 1141951648 ps
CPU time 17.3 seconds
Started Mar 31 01:24:44 PM PDT 24
Finished Mar 31 01:25:01 PM PDT 24
Peak memory 228316 kb
Host smart-3877e39e-0a04-4807-b8ae-913407c41d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108215577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.1108215577
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.401344972
Short name T245
Test name
Test status
Simulation time 525854371 ps
CPU time 3.41 seconds
Started Mar 31 01:24:48 PM PDT 24
Finished Mar 31 01:24:51 PM PDT 24
Peak memory 217264 kb
Host smart-a3afb481-d1af-4ebb-9181-e2ec7423e74b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401344972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap
.401344972
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.1165952807
Short name T327
Test name
Test status
Simulation time 2867770201 ps
CPU time 3.86 seconds
Started Mar 31 01:24:48 PM PDT 24
Finished Mar 31 01:24:51 PM PDT 24
Peak memory 219092 kb
Host smart-6b7c1caf-895d-49a3-b9fd-211880ab1892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165952807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.1165952807
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.3726557206
Short name T705
Test name
Test status
Simulation time 353842839 ps
CPU time 4.16 seconds
Started Mar 31 01:24:49 PM PDT 24
Finished Mar 31 01:24:53 PM PDT 24
Peak memory 223400 kb
Host smart-35007aee-d9f3-4b75-a441-efd6005943a9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3726557206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.3726557206
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.3936279820
Short name T389
Test name
Test status
Simulation time 16301315130 ps
CPU time 31.57 seconds
Started Mar 31 01:24:46 PM PDT 24
Finished Mar 31 01:25:18 PM PDT 24
Peak memory 216884 kb
Host smart-ddb42333-77fc-40da-8b30-b3fdc94fbdd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936279820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.3936279820
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.2419764402
Short name T714
Test name
Test status
Simulation time 4666421433 ps
CPU time 2.72 seconds
Started Mar 31 01:24:45 PM PDT 24
Finished Mar 31 01:24:48 PM PDT 24
Peak memory 208460 kb
Host smart-cb7693a9-eef2-4bf6-8308-5c8c5666ee3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419764402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.2419764402
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.2717358791
Short name T458
Test name
Test status
Simulation time 951354696 ps
CPU time 3.39 seconds
Started Mar 31 01:24:44 PM PDT 24
Finished Mar 31 01:24:47 PM PDT 24
Peak memory 216744 kb
Host smart-705ae1f7-035f-4a1f-a294-f8eeb3bb4ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717358791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.2717358791
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.3835540385
Short name T633
Test name
Test status
Simulation time 244251543 ps
CPU time 0.99 seconds
Started Mar 31 01:24:47 PM PDT 24
Finished Mar 31 01:24:48 PM PDT 24
Peak memory 207260 kb
Host smart-f6220020-5f66-4c06-8017-b92067f98a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835540385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.3835540385
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.1739115973
Short name T627
Test name
Test status
Simulation time 34012004 ps
CPU time 0.72 seconds
Started Mar 31 01:24:51 PM PDT 24
Finished Mar 31 01:24:52 PM PDT 24
Peak memory 205956 kb
Host smart-2e0b498b-44d2-4869-8f29-9836edfc8c8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739115973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
1739115973
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.316967945
Short name T24
Test name
Test status
Simulation time 48796293 ps
CPU time 0.74 seconds
Started Mar 31 01:24:44 PM PDT 24
Finished Mar 31 01:24:45 PM PDT 24
Peak memory 206416 kb
Host smart-6a846ded-656e-449f-8897-1e669f104da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316967945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.316967945
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.4009838744
Short name T526
Test name
Test status
Simulation time 2948675481 ps
CPU time 17.68 seconds
Started Mar 31 01:24:48 PM PDT 24
Finished Mar 31 01:25:05 PM PDT 24
Peak memory 241360 kb
Host smart-e713573f-48a3-4b6f-bb7c-640f23224497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009838744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.4009838744
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.4215696423
Short name T438
Test name
Test status
Simulation time 5333307727 ps
CPU time 13.61 seconds
Started Mar 31 01:24:45 PM PDT 24
Finished Mar 31 01:24:59 PM PDT 24
Peak memory 220548 kb
Host smart-d0a1fad6-432f-4956-9255-c74ca480a855
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4215696423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.4215696423
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.1030916934
Short name T663
Test name
Test status
Simulation time 476176257 ps
CPU time 0.94 seconds
Started Mar 31 01:24:54 PM PDT 24
Finished Mar 31 01:24:55 PM PDT 24
Peak memory 207208 kb
Host smart-88861fb7-95b3-43f6-bb66-0a08ec78b6dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030916934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.1030916934
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.164353949
Short name T581
Test name
Test status
Simulation time 15544953054 ps
CPU time 16.65 seconds
Started Mar 31 01:24:59 PM PDT 24
Finished Mar 31 01:25:16 PM PDT 24
Peak memory 216780 kb
Host smart-12d651e3-6fa0-4cb1-afbd-1e1a711b672f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164353949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.164353949
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.243802129
Short name T64
Test name
Test status
Simulation time 465186400 ps
CPU time 5.4 seconds
Started Mar 31 01:24:44 PM PDT 24
Finished Mar 31 01:24:50 PM PDT 24
Peak memory 216684 kb
Host smart-76ee1944-c24b-4dfe-ae76-3dbfc9a8948e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243802129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.243802129
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.690824903
Short name T565
Test name
Test status
Simulation time 49790249 ps
CPU time 0.77 seconds
Started Mar 31 01:24:47 PM PDT 24
Finished Mar 31 01:24:47 PM PDT 24
Peak memory 206276 kb
Host smart-0c8e1538-e027-45a8-b67e-353952d2a005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690824903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.690824903
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.576890279
Short name T428
Test name
Test status
Simulation time 47396216 ps
CPU time 0.71 seconds
Started Mar 31 01:24:54 PM PDT 24
Finished Mar 31 01:24:55 PM PDT 24
Peak memory 205404 kb
Host smart-80fb3c89-60ce-493e-9b26-2285d4621189
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576890279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.576890279
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.384723008
Short name T401
Test name
Test status
Simulation time 15688071 ps
CPU time 0.76 seconds
Started Mar 31 01:24:53 PM PDT 24
Finished Mar 31 01:24:54 PM PDT 24
Peak memory 207496 kb
Host smart-98b96f6c-23c0-48c7-a959-c63db4508bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384723008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.384723008
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.2605745897
Short name T61
Test name
Test status
Simulation time 11522327815 ps
CPU time 84.63 seconds
Started Mar 31 01:24:51 PM PDT 24
Finished Mar 31 01:26:16 PM PDT 24
Peak memory 249668 kb
Host smart-15dbcbfe-d8ff-4026-8601-8a9d158bb31a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605745897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.2605745897
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.2639760265
Short name T718
Test name
Test status
Simulation time 5347885850 ps
CPU time 13.5 seconds
Started Mar 31 01:24:55 PM PDT 24
Finished Mar 31 01:25:09 PM PDT 24
Peak memory 233324 kb
Host smart-39cab509-30bf-47c1-8c03-d190d8967cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639760265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.2639760265
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.3855828496
Short name T642
Test name
Test status
Simulation time 1117424728 ps
CPU time 8.64 seconds
Started Mar 31 01:24:56 PM PDT 24
Finished Mar 31 01:25:04 PM PDT 24
Peak memory 223844 kb
Host smart-16f74015-fd66-4c39-926e-1d989f88e402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855828496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.3855828496
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.849535862
Short name T333
Test name
Test status
Simulation time 1063378340 ps
CPU time 11.95 seconds
Started Mar 31 01:24:53 PM PDT 24
Finished Mar 31 01:25:05 PM PDT 24
Peak memory 237932 kb
Host smart-83673479-c679-4829-9ad7-f8d3c42ede76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849535862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.849535862
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.1688311296
Short name T671
Test name
Test status
Simulation time 5041692348 ps
CPU time 19.73 seconds
Started Mar 31 01:24:52 PM PDT 24
Finished Mar 31 01:25:12 PM PDT 24
Peak memory 221248 kb
Host smart-1c4bf01c-0939-4fff-bf2a-1a38493d4ca6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1688311296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.1688311296
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.904625639
Short name T486
Test name
Test status
Simulation time 9988706192 ps
CPU time 32.82 seconds
Started Mar 31 01:24:49 PM PDT 24
Finished Mar 31 01:25:22 PM PDT 24
Peak memory 216736 kb
Host smart-5134e60e-b575-47db-9bda-ac6f60c0af66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904625639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.904625639
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.87835813
Short name T481
Test name
Test status
Simulation time 14213687841 ps
CPU time 19.48 seconds
Started Mar 31 01:24:52 PM PDT 24
Finished Mar 31 01:25:12 PM PDT 24
Peak memory 216796 kb
Host smart-93ab11c1-d429-4601-9eb1-23c4690a54ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87835813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.87835813
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.1508123025
Short name T597
Test name
Test status
Simulation time 52339732 ps
CPU time 1.89 seconds
Started Mar 31 01:24:54 PM PDT 24
Finished Mar 31 01:24:56 PM PDT 24
Peak memory 216752 kb
Host smart-c5e854b7-2f05-4fbf-88de-f3d6bc481a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508123025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.1508123025
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.2146984464
Short name T450
Test name
Test status
Simulation time 405199434 ps
CPU time 1.09 seconds
Started Mar 31 01:24:51 PM PDT 24
Finished Mar 31 01:24:52 PM PDT 24
Peak memory 207180 kb
Host smart-74e9c486-917c-4d14-a13e-e4fb8fcaf090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146984464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.2146984464
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.246241440
Short name T98
Test name
Test status
Simulation time 1087050129 ps
CPU time 7.76 seconds
Started Mar 31 01:24:53 PM PDT 24
Finished Mar 31 01:25:00 PM PDT 24
Peak memory 223504 kb
Host smart-1c25e8be-3d15-41ab-870f-d4e7b306e95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246241440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.246241440
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.927625664
Short name T568
Test name
Test status
Simulation time 15006482 ps
CPU time 0.71 seconds
Started Mar 31 01:24:56 PM PDT 24
Finished Mar 31 01:24:57 PM PDT 24
Peak memory 205364 kb
Host smart-dc370eb8-1622-4f5d-a733-0fb02a041d1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927625664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.927625664
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.2009392263
Short name T196
Test name
Test status
Simulation time 31627197032 ps
CPU time 16.49 seconds
Started Mar 31 01:24:55 PM PDT 24
Finished Mar 31 01:25:11 PM PDT 24
Peak memory 219216 kb
Host smart-796c426f-2074-4cb3-9b34-6098cf286036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009392263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.2009392263
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.3897548422
Short name T400
Test name
Test status
Simulation time 19623070 ps
CPU time 0.81 seconds
Started Mar 31 01:24:51 PM PDT 24
Finished Mar 31 01:24:52 PM PDT 24
Peak memory 207040 kb
Host smart-8b61a5b7-1515-4fcc-a4ed-44a9d4f6f835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897548422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.3897548422
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.899054806
Short name T305
Test name
Test status
Simulation time 4760585009 ps
CPU time 72.29 seconds
Started Mar 31 01:24:56 PM PDT 24
Finished Mar 31 01:26:08 PM PDT 24
Peak memory 249608 kb
Host smart-ce0e9192-2ff4-4556-b5dd-2c3ba0a15be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899054806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.899054806
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.1295666414
Short name T323
Test name
Test status
Simulation time 3065954004 ps
CPU time 20.58 seconds
Started Mar 31 01:24:52 PM PDT 24
Finished Mar 31 01:25:13 PM PDT 24
Peak memory 222528 kb
Host smart-ffe711cf-eedf-49aa-aea1-371501c41c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295666414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.1295666414
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.1013724323
Short name T703
Test name
Test status
Simulation time 38767527703 ps
CPU time 107.67 seconds
Started Mar 31 01:24:52 PM PDT 24
Finished Mar 31 01:26:39 PM PDT 24
Peak memory 234160 kb
Host smart-570372c5-0737-49d4-8117-1e689d71d7c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013724323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.1013724323
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.3228168473
Short name T244
Test name
Test status
Simulation time 70343751 ps
CPU time 1.96 seconds
Started Mar 31 01:24:52 PM PDT 24
Finished Mar 31 01:24:54 PM PDT 24
Peak memory 218960 kb
Host smart-c14933e9-bf67-4669-ab3a-56679e3760ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228168473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.3228168473
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.1140971393
Short name T209
Test name
Test status
Simulation time 1000603540 ps
CPU time 7.69 seconds
Started Mar 31 01:24:52 PM PDT 24
Finished Mar 31 01:25:00 PM PDT 24
Peak memory 232996 kb
Host smart-4e8e87de-99e5-4dc0-8de6-d93f5f3ab892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140971393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.1140971393
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.1551152189
Short name T433
Test name
Test status
Simulation time 1277664693 ps
CPU time 15.92 seconds
Started Mar 31 01:24:53 PM PDT 24
Finished Mar 31 01:25:09 PM PDT 24
Peak memory 223568 kb
Host smart-39e80553-6f27-403e-80ba-6c87193adc3f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1551152189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.1551152189
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.1369176745
Short name T719
Test name
Test status
Simulation time 21205591284 ps
CPU time 9.31 seconds
Started Mar 31 01:24:51 PM PDT 24
Finished Mar 31 01:25:01 PM PDT 24
Peak memory 216764 kb
Host smart-7d90a5de-882a-4826-b5ee-b902636064fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369176745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.1369176745
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.3534042520
Short name T657
Test name
Test status
Simulation time 170944662 ps
CPU time 1.24 seconds
Started Mar 31 01:24:50 PM PDT 24
Finished Mar 31 01:24:52 PM PDT 24
Peak memory 216828 kb
Host smart-c97d6ef3-abc1-4b8f-8769-932ca9a8e48c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534042520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3534042520
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.1643912689
Short name T513
Test name
Test status
Simulation time 43285842 ps
CPU time 0.75 seconds
Started Mar 31 01:24:50 PM PDT 24
Finished Mar 31 01:24:51 PM PDT 24
Peak memory 206248 kb
Host smart-c0f3d3c2-b7e0-4c48-bc4d-097a04bf8b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643912689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.1643912689
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.1244901956
Short name T315
Test name
Test status
Simulation time 592602028 ps
CPU time 4.33 seconds
Started Mar 31 01:24:56 PM PDT 24
Finished Mar 31 01:25:00 PM PDT 24
Peak memory 223428 kb
Host smart-16cca733-5b7a-4fc8-af93-199e6bc58c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244901956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.1244901956
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.474264437
Short name T530
Test name
Test status
Simulation time 11814692 ps
CPU time 0.66 seconds
Started Mar 31 01:24:57 PM PDT 24
Finished Mar 31 01:24:58 PM PDT 24
Peak memory 205960 kb
Host smart-94679c41-a30d-4bf4-81b5-05e3a908b86b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474264437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.474264437
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.469501039
Short name T739
Test name
Test status
Simulation time 795346973 ps
CPU time 5.06 seconds
Started Mar 31 01:24:57 PM PDT 24
Finished Mar 31 01:25:03 PM PDT 24
Peak memory 224452 kb
Host smart-63c87feb-a228-45af-873f-3eed115f34f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469501039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.469501039
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.2140944700
Short name T622
Test name
Test status
Simulation time 64732021 ps
CPU time 0.77 seconds
Started Mar 31 01:24:50 PM PDT 24
Finished Mar 31 01:24:51 PM PDT 24
Peak memory 207480 kb
Host smart-d23526a7-1774-4da2-bd6f-64fb83deeb72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140944700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.2140944700
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_intercept.2549785124
Short name T686
Test name
Test status
Simulation time 2805772881 ps
CPU time 25.35 seconds
Started Mar 31 01:24:58 PM PDT 24
Finished Mar 31 01:25:24 PM PDT 24
Peak memory 220856 kb
Host smart-03729519-5f60-4706-ad5b-21264bcabcdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549785124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.2549785124
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.3605433948
Short name T556
Test name
Test status
Simulation time 4411201776 ps
CPU time 11.08 seconds
Started Mar 31 01:25:02 PM PDT 24
Finished Mar 31 01:25:14 PM PDT 24
Peak memory 221920 kb
Host smart-690a3982-a251-4c5c-bbba-3220e10a4876
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3605433948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.3605433948
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.44589142
Short name T555
Test name
Test status
Simulation time 16282264231 ps
CPU time 24.82 seconds
Started Mar 31 01:24:55 PM PDT 24
Finished Mar 31 01:25:20 PM PDT 24
Peak memory 216816 kb
Host smart-cd49880c-3084-401c-8ddc-ba93f78f6277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44589142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.44589142
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.4039045941
Short name T2
Test name
Test status
Simulation time 125542761 ps
CPU time 1.32 seconds
Started Mar 31 01:24:52 PM PDT 24
Finished Mar 31 01:24:53 PM PDT 24
Peak memory 208368 kb
Host smart-96f691a5-2c6e-4dff-a1b9-84e456782782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039045941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.4039045941
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.1440466736
Short name T550
Test name
Test status
Simulation time 382103817 ps
CPU time 4.71 seconds
Started Mar 31 01:25:04 PM PDT 24
Finished Mar 31 01:25:09 PM PDT 24
Peak memory 216772 kb
Host smart-9dba6ee6-8985-41d8-842e-2d4a0cc4c26b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440466736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.1440466736
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.3625522159
Short name T539
Test name
Test status
Simulation time 16730352 ps
CPU time 0.74 seconds
Started Mar 31 01:24:55 PM PDT 24
Finished Mar 31 01:24:56 PM PDT 24
Peak memory 206216 kb
Host smart-b18a1c5f-6a79-4337-b147-c5b025ceb369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625522159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.3625522159
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.4072711606
Short name T192
Test name
Test status
Simulation time 9464201317 ps
CPU time 15.37 seconds
Started Mar 31 01:24:57 PM PDT 24
Finished Mar 31 01:25:13 PM PDT 24
Peak memory 227956 kb
Host smart-0b0866ec-171e-40df-82ac-dae54f3928bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072711606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.4072711606
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.3673576278
Short name T728
Test name
Test status
Simulation time 28904154 ps
CPU time 0.69 seconds
Started Mar 31 01:25:19 PM PDT 24
Finished Mar 31 01:25:20 PM PDT 24
Peak memory 205216 kb
Host smart-7579603e-ebfa-4a28-890a-f5837b699bda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673576278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
3673576278
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.2711977265
Short name T676
Test name
Test status
Simulation time 1568577921 ps
CPU time 9.51 seconds
Started Mar 31 01:24:58 PM PDT 24
Finished Mar 31 01:25:07 PM PDT 24
Peak memory 232796 kb
Host smart-d71c9888-a8a4-42a5-b940-20317c3178f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711977265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.2711977265
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.2494822160
Short name T440
Test name
Test status
Simulation time 13772518 ps
CPU time 0.75 seconds
Started Mar 31 01:25:03 PM PDT 24
Finished Mar 31 01:25:04 PM PDT 24
Peak memory 206124 kb
Host smart-834451b0-25b3-4244-8bd4-cf932766686c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494822160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.2494822160
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.1706475078
Short name T308
Test name
Test status
Simulation time 1071700746 ps
CPU time 17.92 seconds
Started Mar 31 01:24:57 PM PDT 24
Finished Mar 31 01:25:15 PM PDT 24
Peak memory 249556 kb
Host smart-7e17d287-7fc3-476a-b80b-be4b1c0225f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706475078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.1706475078
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2970570914
Short name T267
Test name
Test status
Simulation time 158427543 ps
CPU time 3.92 seconds
Started Mar 31 01:25:10 PM PDT 24
Finished Mar 31 01:25:14 PM PDT 24
Peak memory 224936 kb
Host smart-9049cca3-22bf-4fcc-bc12-311746402701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970570914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2970570914
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.2399444614
Short name T263
Test name
Test status
Simulation time 633571675 ps
CPU time 2.91 seconds
Started Mar 31 01:25:19 PM PDT 24
Finished Mar 31 01:25:23 PM PDT 24
Peak memory 222280 kb
Host smart-228cfa07-9e78-4d42-bcd5-677f1fbf7399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399444614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.2399444614
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.3665751400
Short name T411
Test name
Test status
Simulation time 4142766664 ps
CPU time 11.03 seconds
Started Mar 31 01:24:56 PM PDT 24
Finished Mar 31 01:25:08 PM PDT 24
Peak memory 223580 kb
Host smart-a4390553-c12d-4fe2-92c8-c61ced0707b1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3665751400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.3665751400
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.1713626781
Short name T394
Test name
Test status
Simulation time 24199939156 ps
CPU time 62.88 seconds
Started Mar 31 01:24:55 PM PDT 24
Finished Mar 31 01:25:58 PM PDT 24
Peak memory 216716 kb
Host smart-3b5e55a5-5a79-429a-8242-1f2627c67d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713626781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.1713626781
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.4276281094
Short name T507
Test name
Test status
Simulation time 4129625770 ps
CPU time 13.19 seconds
Started Mar 31 01:24:57 PM PDT 24
Finished Mar 31 01:25:11 PM PDT 24
Peak memory 216800 kb
Host smart-51f66e5e-df79-4272-a75d-22c3f3654837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276281094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.4276281094
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.3572829936
Short name T690
Test name
Test status
Simulation time 83835228 ps
CPU time 1.45 seconds
Started Mar 31 01:25:07 PM PDT 24
Finished Mar 31 01:25:09 PM PDT 24
Peak memory 216624 kb
Host smart-d52483c1-db59-4f72-a99c-7adbf3d73c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572829936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.3572829936
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.816752451
Short name T563
Test name
Test status
Simulation time 68133693 ps
CPU time 0.74 seconds
Started Mar 31 01:25:12 PM PDT 24
Finished Mar 31 01:25:13 PM PDT 24
Peak memory 206256 kb
Host smart-143e5b05-dbd0-461f-8b2e-818680c070c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816752451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.816752451
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.513851856
Short name T595
Test name
Test status
Simulation time 54110931 ps
CPU time 0.69 seconds
Started Mar 31 01:25:18 PM PDT 24
Finished Mar 31 01:25:19 PM PDT 24
Peak memory 206128 kb
Host smart-106b8b3a-89a2-4930-8046-b29582c78fbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513851856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.513851856
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.3041933100
Short name T732
Test name
Test status
Simulation time 33964385 ps
CPU time 0.82 seconds
Started Mar 31 01:25:01 PM PDT 24
Finished Mar 31 01:25:02 PM PDT 24
Peak memory 207140 kb
Host smart-bb4c9ce7-8b9a-4dca-a38e-7997fcc14674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041933100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.3041933100
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.4053985777
Short name T4
Test name
Test status
Simulation time 2911590307 ps
CPU time 29.45 seconds
Started Mar 31 01:24:59 PM PDT 24
Finished Mar 31 01:25:28 PM PDT 24
Peak memory 251732 kb
Host smart-b98a3a0a-4734-4671-a81e-dca46275a85f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053985777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.4053985777
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.3110524723
Short name T270
Test name
Test status
Simulation time 241427153 ps
CPU time 5.73 seconds
Started Mar 31 01:24:56 PM PDT 24
Finished Mar 31 01:25:02 PM PDT 24
Peak memory 233152 kb
Host smart-abb126ce-e12a-4db4-94d2-6e02cb621f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110524723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.3110524723
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.1106020600
Short name T13
Test name
Test status
Simulation time 2685064433 ps
CPU time 32.58 seconds
Started Mar 31 01:24:57 PM PDT 24
Finished Mar 31 01:25:30 PM PDT 24
Peak memory 232164 kb
Host smart-a859b9fb-731b-49fe-bd91-c3e5e8b3158d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106020600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.1106020600
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.1775639082
Short name T202
Test name
Test status
Simulation time 41318655952 ps
CPU time 23.02 seconds
Started Mar 31 01:25:14 PM PDT 24
Finished Mar 31 01:25:37 PM PDT 24
Peak memory 217148 kb
Host smart-e06401d0-6e9c-4b1c-ba67-f6597a3247ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775639082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.1775639082
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.1956838704
Short name T692
Test name
Test status
Simulation time 1080111660 ps
CPU time 4.44 seconds
Started Mar 31 01:24:58 PM PDT 24
Finished Mar 31 01:25:03 PM PDT 24
Peak memory 223360 kb
Host smart-a9512925-c399-4f64-8488-46a35197e912
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1956838704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.1956838704
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.4120962393
Short name T541
Test name
Test status
Simulation time 3702506834 ps
CPU time 6.05 seconds
Started Mar 31 01:24:59 PM PDT 24
Finished Mar 31 01:25:05 PM PDT 24
Peak memory 216720 kb
Host smart-8d01a805-9dee-40f6-bea8-4fa297c03410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120962393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.4120962393
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.3150569618
Short name T527
Test name
Test status
Simulation time 52426324 ps
CPU time 0.75 seconds
Started Mar 31 01:25:19 PM PDT 24
Finished Mar 31 01:25:21 PM PDT 24
Peak memory 206060 kb
Host smart-6c0bbc6f-9911-4bf2-b543-65be2f9a8b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150569618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.3150569618
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.3678512256
Short name T453
Test name
Test status
Simulation time 161466586 ps
CPU time 1.21 seconds
Started Mar 31 01:25:05 PM PDT 24
Finished Mar 31 01:25:06 PM PDT 24
Peak memory 207332 kb
Host smart-3857819f-113f-46bc-a8fb-7e3b5827273e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678512256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.3678512256
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.2446866786
Short name T604
Test name
Test status
Simulation time 12582323 ps
CPU time 0.72 seconds
Started Mar 31 01:25:11 PM PDT 24
Finished Mar 31 01:25:12 PM PDT 24
Peak memory 205968 kb
Host smart-ff34bd50-60d0-4635-8bf7-7291a16ce353
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446866786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
2446866786
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.1869351425
Short name T658
Test name
Test status
Simulation time 2184942250 ps
CPU time 7.88 seconds
Started Mar 31 01:25:12 PM PDT 24
Finished Mar 31 01:25:21 PM PDT 24
Peak memory 219100 kb
Host smart-14077c75-c9f3-470b-922b-b28dd914bc66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869351425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.1869351425
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.1980834959
Short name T730
Test name
Test status
Simulation time 36528285 ps
CPU time 0.78 seconds
Started Mar 31 01:25:05 PM PDT 24
Finished Mar 31 01:25:06 PM PDT 24
Peak memory 207168 kb
Host smart-b2784f25-c5b2-435d-9223-8a253d41be95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980834959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.1980834959
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.1388063926
Short name T120
Test name
Test status
Simulation time 759479290 ps
CPU time 17.44 seconds
Started Mar 31 01:25:18 PM PDT 24
Finished Mar 31 01:25:36 PM PDT 24
Peak memory 233332 kb
Host smart-c898cb40-6cdf-435b-b943-273e1c059641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388063926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.1388063926
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.3437065673
Short name T320
Test name
Test status
Simulation time 4057442707 ps
CPU time 10.92 seconds
Started Mar 31 01:25:18 PM PDT 24
Finished Mar 31 01:25:29 PM PDT 24
Peak memory 224292 kb
Host smart-6f0998b3-9c7c-40f8-b78a-fb977e9074c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437065673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.3437065673
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.4177981764
Short name T538
Test name
Test status
Simulation time 90762173 ps
CPU time 3.95 seconds
Started Mar 31 01:25:05 PM PDT 24
Finished Mar 31 01:25:09 PM PDT 24
Peak memory 222152 kb
Host smart-f6725122-965c-4162-bf48-ec86b324a2d2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4177981764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.4177981764
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.1980727345
Short name T379
Test name
Test status
Simulation time 9779714730 ps
CPU time 57.52 seconds
Started Mar 31 01:25:05 PM PDT 24
Finished Mar 31 01:26:02 PM PDT 24
Peak memory 216812 kb
Host smart-605c6cff-f0c7-407f-b048-7523bc5e3216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980727345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.1980727345
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.1932798896
Short name T559
Test name
Test status
Simulation time 37725533570 ps
CPU time 19.02 seconds
Started Mar 31 01:24:58 PM PDT 24
Finished Mar 31 01:25:17 PM PDT 24
Peak memory 216948 kb
Host smart-a45a7c12-b7dd-4b89-af10-34428e89771f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932798896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.1932798896
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.1343248693
Short name T708
Test name
Test status
Simulation time 162374844 ps
CPU time 2.28 seconds
Started Mar 31 01:25:13 PM PDT 24
Finished Mar 31 01:25:16 PM PDT 24
Peak memory 216776 kb
Host smart-8020974a-a580-4c3c-97a9-db779af3e042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343248693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.1343248693
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.2625324487
Short name T435
Test name
Test status
Simulation time 76156820 ps
CPU time 0.99 seconds
Started Mar 31 01:25:02 PM PDT 24
Finished Mar 31 01:25:04 PM PDT 24
Peak memory 206260 kb
Host smart-7a7fc257-a2c7-4dc1-8cc6-3af9b303d615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625324487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2625324487
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.677507026
Short name T319
Test name
Test status
Simulation time 611907323 ps
CPU time 5.83 seconds
Started Mar 31 01:25:18 PM PDT 24
Finished Mar 31 01:25:24 PM PDT 24
Peak memory 232928 kb
Host smart-1737cf8d-fd4e-44bf-8277-18c5b97eb569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677507026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.677507026
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.1879876868
Short name T528
Test name
Test status
Simulation time 35525809 ps
CPU time 0.7 seconds
Started Mar 31 01:23:45 PM PDT 24
Finished Mar 31 01:23:46 PM PDT 24
Peak memory 205404 kb
Host smart-b65c51c7-ae29-458d-a7cf-9f0b69e76c68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879876868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.1
879876868
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.1167329688
Short name T289
Test name
Test status
Simulation time 2296935203 ps
CPU time 14.01 seconds
Started Mar 31 01:23:47 PM PDT 24
Finished Mar 31 01:24:02 PM PDT 24
Peak memory 217868 kb
Host smart-4a1507b3-9c82-4175-8d72-171c1a59c795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167329688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.1167329688
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.3398166999
Short name T619
Test name
Test status
Simulation time 165201421 ps
CPU time 0.73 seconds
Started Mar 31 01:23:37 PM PDT 24
Finished Mar 31 01:23:38 PM PDT 24
Peak memory 206052 kb
Host smart-28c058d1-5b86-457e-954e-95e708baea35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398166999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.3398166999
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.1588338536
Short name T311
Test name
Test status
Simulation time 31020354307 ps
CPU time 113.3 seconds
Started Mar 31 01:23:43 PM PDT 24
Finished Mar 31 01:25:37 PM PDT 24
Peak memory 249624 kb
Host smart-6464eab3-051c-4939-83b1-0feb8d0a3947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588338536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.1588338536
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_ram_cfg.2405322834
Short name T646
Test name
Test status
Simulation time 40048281 ps
CPU time 0.73 seconds
Started Mar 31 01:23:37 PM PDT 24
Finished Mar 31 01:23:37 PM PDT 24
Peak memory 216780 kb
Host smart-92c0daaa-8922-4bd4-ba84-2c597bdcab27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405322834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_ram_cfg.2405322834
Directory /workspace/3.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.7989941
Short name T620
Test name
Test status
Simulation time 70766653 ps
CPU time 3.54 seconds
Started Mar 31 01:23:47 PM PDT 24
Finished Mar 31 01:23:50 PM PDT 24
Peak memory 219588 kb
Host smart-6ef60640-d73f-44bd-950c-4e3e22514a29
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=7989941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direct.7989941
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.2748021684
Short name T37
Test name
Test status
Simulation time 84098644 ps
CPU time 1.1 seconds
Started Mar 31 01:23:45 PM PDT 24
Finished Mar 31 01:23:47 PM PDT 24
Peak memory 235704 kb
Host smart-ad1bb41a-5d79-44b2-bf8c-5dc23c780569
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748021684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.2748021684
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.2839294451
Short name T675
Test name
Test status
Simulation time 75008159 ps
CPU time 1.11 seconds
Started Mar 31 01:23:44 PM PDT 24
Finished Mar 31 01:23:45 PM PDT 24
Peak memory 207764 kb
Host smart-09bc3725-73ec-4227-b410-889a91debdc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839294451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.2839294451
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.3301003491
Short name T696
Test name
Test status
Simulation time 2193475997 ps
CPU time 14.45 seconds
Started Mar 31 01:23:39 PM PDT 24
Finished Mar 31 01:23:54 PM PDT 24
Peak memory 216812 kb
Host smart-7c5fbcd8-ef89-45bf-87e0-2587cb26bed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301003491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.3301003491
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.2508804791
Short name T468
Test name
Test status
Simulation time 7291363665 ps
CPU time 21.08 seconds
Started Mar 31 01:23:39 PM PDT 24
Finished Mar 31 01:24:00 PM PDT 24
Peak memory 216796 kb
Host smart-35be4a7d-4a72-4605-92b2-de01ee383baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508804791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.2508804791
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.336732242
Short name T472
Test name
Test status
Simulation time 162225206 ps
CPU time 1.72 seconds
Started Mar 31 01:23:36 PM PDT 24
Finished Mar 31 01:23:38 PM PDT 24
Peak memory 216720 kb
Host smart-056ea081-0d06-432e-99f1-37d258ba4e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336732242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.336732242
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.14187786
Short name T403
Test name
Test status
Simulation time 28045617 ps
CPU time 0.75 seconds
Started Mar 31 01:23:35 PM PDT 24
Finished Mar 31 01:23:36 PM PDT 24
Peak memory 206240 kb
Host smart-e225c9a5-8f0c-4811-afdf-f35e3da909d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14187786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.14187786
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.2713396566
Short name T291
Test name
Test status
Simulation time 6166980705 ps
CPU time 17.73 seconds
Started Mar 31 01:23:45 PM PDT 24
Finished Mar 31 01:24:03 PM PDT 24
Peak memory 219728 kb
Host smart-3153c86b-add2-465c-838e-6f36ad79353b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713396566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.2713396566
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.4190139757
Short name T452
Test name
Test status
Simulation time 39950924 ps
CPU time 0.71 seconds
Started Mar 31 01:25:06 PM PDT 24
Finished Mar 31 01:25:07 PM PDT 24
Peak memory 206000 kb
Host smart-9bb7f296-c6b5-4969-96f5-75b887894c83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190139757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
4190139757
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.4117017356
Short name T669
Test name
Test status
Simulation time 485850428 ps
CPU time 8.64 seconds
Started Mar 31 01:25:14 PM PDT 24
Finished Mar 31 01:25:22 PM PDT 24
Peak memory 219388 kb
Host smart-1d12b9c3-a4ce-4c5f-874c-3ab1c1803a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117017356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.4117017356
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.1294219280
Short name T704
Test name
Test status
Simulation time 37561064 ps
CPU time 0.8 seconds
Started Mar 31 01:25:10 PM PDT 24
Finished Mar 31 01:25:11 PM PDT 24
Peak memory 207168 kb
Host smart-da11c1b4-1175-4c9d-8427-c26fe425ce3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294219280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.1294219280
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.808932754
Short name T354
Test name
Test status
Simulation time 15992843386 ps
CPU time 54.36 seconds
Started Mar 31 01:25:06 PM PDT 24
Finished Mar 31 01:26:01 PM PDT 24
Peak memory 233120 kb
Host smart-07829233-f753-479e-8e7c-5d3f496637eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808932754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.808932754
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.1388822514
Short name T8
Test name
Test status
Simulation time 758611265 ps
CPU time 12.62 seconds
Started Mar 31 01:25:04 PM PDT 24
Finished Mar 31 01:25:17 PM PDT 24
Peak memory 224984 kb
Host smart-55bd05ce-0bda-4581-b13c-34027a282f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388822514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.1388822514
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.1843525044
Short name T238
Test name
Test status
Simulation time 62961725937 ps
CPU time 42.1 seconds
Started Mar 31 01:25:16 PM PDT 24
Finished Mar 31 01:25:58 PM PDT 24
Peak memory 217004 kb
Host smart-12db6353-02af-4a0b-8e19-40575b7b734a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843525044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.1843525044
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.68683409
Short name T322
Test name
Test status
Simulation time 1463881629 ps
CPU time 6.77 seconds
Started Mar 31 01:25:07 PM PDT 24
Finished Mar 31 01:25:14 PM PDT 24
Peak memory 238944 kb
Host smart-62bbc047-d762-4fd1-a80f-15a1fd0df0c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68683409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.68683409
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.1805030623
Short name T536
Test name
Test status
Simulation time 11078359894 ps
CPU time 8.05 seconds
Started Mar 31 01:25:07 PM PDT 24
Finished Mar 31 01:25:15 PM PDT 24
Peak memory 220704 kb
Host smart-7f733414-6a11-4a80-a94f-e85ede19353b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1805030623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.1805030623
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.3415231313
Short name T540
Test name
Test status
Simulation time 9586282254 ps
CPU time 39.48 seconds
Started Mar 31 01:25:11 PM PDT 24
Finished Mar 31 01:25:51 PM PDT 24
Peak memory 216912 kb
Host smart-2165af0d-071f-4baf-b697-3c16c0ece5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415231313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.3415231313
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.4134454532
Short name T561
Test name
Test status
Simulation time 2341569472 ps
CPU time 8.85 seconds
Started Mar 31 01:25:07 PM PDT 24
Finished Mar 31 01:25:16 PM PDT 24
Peak memory 216780 kb
Host smart-846ac46d-d80f-4ff8-9ba3-884003fb5456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134454532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.4134454532
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.4283942465
Short name T434
Test name
Test status
Simulation time 305642372 ps
CPU time 1.43 seconds
Started Mar 31 01:25:03 PM PDT 24
Finished Mar 31 01:25:05 PM PDT 24
Peak memory 216580 kb
Host smart-b598d609-c53d-4a29-ab65-e7c333ea8bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283942465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.4283942465
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.1828209480
Short name T640
Test name
Test status
Simulation time 13605699 ps
CPU time 0.73 seconds
Started Mar 31 01:25:03 PM PDT 24
Finished Mar 31 01:25:04 PM PDT 24
Peak memory 206216 kb
Host smart-503e8d1b-9d5e-4a87-be8e-c1b56b932ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828209480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.1828209480
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.2105565150
Short name T485
Test name
Test status
Simulation time 17444601 ps
CPU time 0.75 seconds
Started Mar 31 01:25:13 PM PDT 24
Finished Mar 31 01:25:14 PM PDT 24
Peak memory 205992 kb
Host smart-14f797ce-e2a7-4541-a9e8-49c66c288dc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105565150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
2105565150
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.3243857776
Short name T615
Test name
Test status
Simulation time 58139872 ps
CPU time 0.79 seconds
Started Mar 31 01:25:04 PM PDT 24
Finished Mar 31 01:25:05 PM PDT 24
Peak memory 207464 kb
Host smart-a8248e35-80a0-4fb9-8709-2ec8cb0e831b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243857776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.3243857776
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.1355056075
Short name T304
Test name
Test status
Simulation time 7097669443 ps
CPU time 100.13 seconds
Started Mar 31 01:25:23 PM PDT 24
Finished Mar 31 01:27:03 PM PDT 24
Peak memory 249588 kb
Host smart-2e6815e6-4d48-40e5-b4fc-6076ce2f3c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355056075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1355056075
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.3565130256
Short name T652
Test name
Test status
Simulation time 337708245 ps
CPU time 5.29 seconds
Started Mar 31 01:25:23 PM PDT 24
Finished Mar 31 01:25:28 PM PDT 24
Peak memory 224564 kb
Host smart-bd50785e-d585-4171-a31c-579f3d23d522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565130256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.3565130256
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.2022181267
Short name T491
Test name
Test status
Simulation time 2486960781 ps
CPU time 12.49 seconds
Started Mar 31 01:25:16 PM PDT 24
Finished Mar 31 01:25:29 PM PDT 24
Peak memory 241168 kb
Host smart-9b4a0e50-746b-48d1-ac67-d577f2c2d207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022181267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.2022181267
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.1819248009
Short name T207
Test name
Test status
Simulation time 3823419533 ps
CPU time 14.05 seconds
Started Mar 31 01:25:13 PM PDT 24
Finished Mar 31 01:25:27 PM PDT 24
Peak memory 225048 kb
Host smart-f60ebc4f-2202-46cb-b8a7-19344fb54b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819248009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.1819248009
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.1520674870
Short name T551
Test name
Test status
Simulation time 3127952284 ps
CPU time 7.28 seconds
Started Mar 31 01:25:15 PM PDT 24
Finished Mar 31 01:25:23 PM PDT 24
Peak memory 220704 kb
Host smart-6a389557-9485-4d19-948c-b10653c5f9dc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1520674870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.1520674870
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.3571010058
Short name T392
Test name
Test status
Simulation time 12552408808 ps
CPU time 32.05 seconds
Started Mar 31 01:25:14 PM PDT 24
Finished Mar 31 01:25:47 PM PDT 24
Peak memory 217108 kb
Host smart-6b48ee98-9bf5-4d44-b9e4-34c35e5750a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571010058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.3571010058
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.3206341469
Short name T461
Test name
Test status
Simulation time 6200771526 ps
CPU time 9.62 seconds
Started Mar 31 01:25:18 PM PDT 24
Finished Mar 31 01:25:28 PM PDT 24
Peak memory 216856 kb
Host smart-99ecb043-0715-4b3c-9c3a-95057e8db635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206341469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.3206341469
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.1196977900
Short name T682
Test name
Test status
Simulation time 231149173 ps
CPU time 1.69 seconds
Started Mar 31 01:25:16 PM PDT 24
Finished Mar 31 01:25:18 PM PDT 24
Peak memory 216776 kb
Host smart-b1afa67f-2da3-4519-8eb2-b7585cd9fece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196977900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.1196977900
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.497180823
Short name T698
Test name
Test status
Simulation time 589441110 ps
CPU time 0.83 seconds
Started Mar 31 01:25:13 PM PDT 24
Finished Mar 31 01:25:14 PM PDT 24
Peak memory 206204 kb
Host smart-d7c90f01-ddef-4569-8e03-c7f7421ce525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497180823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.497180823
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.2497510512
Short name T408
Test name
Test status
Simulation time 12424160 ps
CPU time 0.7 seconds
Started Mar 31 01:25:16 PM PDT 24
Finished Mar 31 01:25:17 PM PDT 24
Peak memory 205936 kb
Host smart-b59e6bcc-a718-4609-ad70-465356bae28e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497510512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
2497510512
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.1671969703
Short name T678
Test name
Test status
Simulation time 89576439 ps
CPU time 0.8 seconds
Started Mar 31 01:25:25 PM PDT 24
Finished Mar 31 01:25:26 PM PDT 24
Peak memory 207484 kb
Host smart-7661fbe7-17fd-41a7-8175-5fb5be4347f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671969703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.1671969703
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.1473000669
Short name T358
Test name
Test status
Simulation time 61966390665 ps
CPU time 63.57 seconds
Started Mar 31 01:25:14 PM PDT 24
Finished Mar 31 01:26:18 PM PDT 24
Peak memory 234208 kb
Host smart-c4e31137-c60a-4266-b270-36a46136466b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473000669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.1473000669
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.4266455556
Short name T52
Test name
Test status
Simulation time 8655910421 ps
CPU time 26.94 seconds
Started Mar 31 01:25:22 PM PDT 24
Finished Mar 31 01:25:49 PM PDT 24
Peak memory 223460 kb
Host smart-0e1eedd0-7404-4757-ab78-67e213e7ab49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266455556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.4266455556
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.1446884413
Short name T299
Test name
Test status
Simulation time 11038295351 ps
CPU time 5.63 seconds
Started Mar 31 01:25:12 PM PDT 24
Finished Mar 31 01:25:19 PM PDT 24
Peak memory 220884 kb
Host smart-397db412-ce5e-478d-9ce0-b89d8566f093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446884413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.1446884413
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.3198059911
Short name T630
Test name
Test status
Simulation time 158407553 ps
CPU time 3.32 seconds
Started Mar 31 01:25:14 PM PDT 24
Finished Mar 31 01:25:17 PM PDT 24
Peak memory 220196 kb
Host smart-8ba1a3f6-829f-4c77-94f6-8e59a417b3b2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3198059911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.3198059911
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.1937016269
Short name T21
Test name
Test status
Simulation time 26752102097 ps
CPU time 33.54 seconds
Started Mar 31 01:25:23 PM PDT 24
Finished Mar 31 01:25:57 PM PDT 24
Peak memory 216720 kb
Host smart-aefc05cb-dca4-4dda-b092-7dd953399c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937016269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.1937016269
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.1169220436
Short name T455
Test name
Test status
Simulation time 4065717850 ps
CPU time 18.83 seconds
Started Mar 31 01:25:12 PM PDT 24
Finished Mar 31 01:25:32 PM PDT 24
Peak memory 216812 kb
Host smart-f368843f-34bc-4de2-afd0-2df65bbadc4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169220436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.1169220436
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.2998810635
Short name T65
Test name
Test status
Simulation time 69223062 ps
CPU time 1.82 seconds
Started Mar 31 01:25:14 PM PDT 24
Finished Mar 31 01:25:16 PM PDT 24
Peak memory 216752 kb
Host smart-0ca2c63d-5afb-4bf6-82fe-4abbbab5e593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998810635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.2998810635
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.819760531
Short name T90
Test name
Test status
Simulation time 217240620 ps
CPU time 0.87 seconds
Started Mar 31 01:25:16 PM PDT 24
Finished Mar 31 01:25:17 PM PDT 24
Peak memory 206264 kb
Host smart-e911d2a2-abac-4d4a-98bf-024d1e17c3b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819760531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.819760531
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.3248210014
Short name T409
Test name
Test status
Simulation time 13615856 ps
CPU time 0.68 seconds
Started Mar 31 01:25:21 PM PDT 24
Finished Mar 31 01:25:22 PM PDT 24
Peak memory 205992 kb
Host smart-aee33c76-ea07-4201-94a4-2045e2ead146
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248210014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
3248210014
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.2771874332
Short name T478
Test name
Test status
Simulation time 34248519 ps
CPU time 0.82 seconds
Started Mar 31 01:25:16 PM PDT 24
Finished Mar 31 01:25:17 PM PDT 24
Peak memory 207160 kb
Host smart-526d0c94-48ac-47d5-aeb9-04af4395cf13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771874332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.2771874332
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.1778804551
Short name T307
Test name
Test status
Simulation time 21350512256 ps
CPU time 69.47 seconds
Started Mar 31 01:25:23 PM PDT 24
Finished Mar 31 01:26:33 PM PDT 24
Peak memory 249596 kb
Host smart-7bf26171-88c6-48e9-acfc-ce5c6eeee594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778804551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.1778804551
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.1971463435
Short name T103
Test name
Test status
Simulation time 6384503675 ps
CPU time 14.73 seconds
Started Mar 31 01:25:26 PM PDT 24
Finished Mar 31 01:25:41 PM PDT 24
Peak memory 219440 kb
Host smart-57d1f90d-b683-470e-b6fd-93d60d85f073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971463435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.1971463435
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.3480964332
Short name T247
Test name
Test status
Simulation time 30968077628 ps
CPU time 104.46 seconds
Started Mar 31 01:25:23 PM PDT 24
Finished Mar 31 01:27:08 PM PDT 24
Peak memory 233856 kb
Host smart-29cb3c3e-c45d-4212-bf93-325edc56b71e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480964332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.3480964332
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.537305465
Short name T330
Test name
Test status
Simulation time 11644659881 ps
CPU time 37.33 seconds
Started Mar 31 01:25:23 PM PDT 24
Finished Mar 31 01:26:01 PM PDT 24
Peak memory 239404 kb
Host smart-6d1b62f4-5698-43f2-a8b2-092c1f4510d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537305465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.537305465
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.3563187017
Short name T546
Test name
Test status
Simulation time 1984113692 ps
CPU time 15.75 seconds
Started Mar 31 01:25:23 PM PDT 24
Finished Mar 31 01:25:39 PM PDT 24
Peak memory 219208 kb
Host smart-eb320afb-ab96-45da-ba3b-dd2c29ca198a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3563187017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.3563187017
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.524651912
Short name T115
Test name
Test status
Simulation time 5952745774 ps
CPU time 28.73 seconds
Started Mar 31 01:25:20 PM PDT 24
Finished Mar 31 01:25:49 PM PDT 24
Peak memory 216772 kb
Host smart-3367bfff-7763-4d1a-8a27-396cf26ab6e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524651912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.524651912
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.3365102270
Short name T419
Test name
Test status
Simulation time 8138735971 ps
CPU time 25.99 seconds
Started Mar 31 01:25:38 PM PDT 24
Finished Mar 31 01:26:05 PM PDT 24
Peak memory 216992 kb
Host smart-8128969a-e3ec-4e0e-bae2-21624dc66d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365102270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.3365102270
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.2576279625
Short name T549
Test name
Test status
Simulation time 1132972140 ps
CPU time 4.97 seconds
Started Mar 31 01:25:21 PM PDT 24
Finished Mar 31 01:25:26 PM PDT 24
Peak memory 216736 kb
Host smart-07d13b64-3129-4148-93db-8fa097c19fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576279625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.2576279625
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.2145622755
Short name T413
Test name
Test status
Simulation time 77192881 ps
CPU time 0.91 seconds
Started Mar 31 01:25:38 PM PDT 24
Finished Mar 31 01:25:40 PM PDT 24
Peak memory 206412 kb
Host smart-aa56ec26-bf5f-4917-b8c1-f00164e7946a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145622755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.2145622755
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.710068775
Short name T624
Test name
Test status
Simulation time 20472690 ps
CPU time 0.71 seconds
Started Mar 31 01:25:21 PM PDT 24
Finished Mar 31 01:25:22 PM PDT 24
Peak memory 205440 kb
Host smart-373c7fba-e86d-4dc0-9755-e32a0a81858f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710068775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.710068775
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.447324427
Short name T487
Test name
Test status
Simulation time 20890443 ps
CPU time 0.78 seconds
Started Mar 31 01:25:19 PM PDT 24
Finished Mar 31 01:25:20 PM PDT 24
Peak memory 207144 kb
Host smart-0e99d257-5ca5-482c-af95-869c6d765f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447324427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.447324427
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.3883114619
Short name T726
Test name
Test status
Simulation time 4699774549 ps
CPU time 50.46 seconds
Started Mar 31 01:25:26 PM PDT 24
Finished Mar 31 01:26:17 PM PDT 24
Peak memory 251364 kb
Host smart-09969668-c6ef-4922-beea-85b4c80a6ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883114619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.3883114619
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.834471450
Short name T602
Test name
Test status
Simulation time 1606159072 ps
CPU time 7.44 seconds
Started Mar 31 01:25:23 PM PDT 24
Finished Mar 31 01:25:30 PM PDT 24
Peak memory 222244 kb
Host smart-5863607d-b7cb-4f86-9701-e18dd9b92819
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=834471450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dire
ct.834471450
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.1309777907
Short name T523
Test name
Test status
Simulation time 140325147 ps
CPU time 1.05 seconds
Started Mar 31 01:25:22 PM PDT 24
Finished Mar 31 01:25:23 PM PDT 24
Peak memory 207496 kb
Host smart-f1584054-7435-4cc2-97e6-f3a24c260749
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309777907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.1309777907
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.600100284
Short name T510
Test name
Test status
Simulation time 3427510065 ps
CPU time 4.16 seconds
Started Mar 31 01:25:30 PM PDT 24
Finished Mar 31 01:25:35 PM PDT 24
Peak memory 216996 kb
Host smart-50da007c-68a2-47fa-b665-f098e0e2c60a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600100284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.600100284
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.3818262653
Short name T96
Test name
Test status
Simulation time 747297749 ps
CPU time 4.24 seconds
Started Mar 31 01:25:25 PM PDT 24
Finished Mar 31 01:25:31 PM PDT 24
Peak memory 216832 kb
Host smart-54add34a-f075-412b-aedf-8d9b256e69e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818262653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.3818262653
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.3736079980
Short name T67
Test name
Test status
Simulation time 511962851 ps
CPU time 3.88 seconds
Started Mar 31 01:25:20 PM PDT 24
Finished Mar 31 01:25:24 PM PDT 24
Peak memory 216676 kb
Host smart-00fcde5c-a341-49db-a1f6-f428dc8a91b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736079980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.3736079980
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.432948912
Short name T529
Test name
Test status
Simulation time 347860199 ps
CPU time 1.04 seconds
Started Mar 31 01:25:20 PM PDT 24
Finished Mar 31 01:25:22 PM PDT 24
Peak memory 207280 kb
Host smart-873f85ca-4ec9-4bed-9383-5543fd77e50c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432948912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.432948912
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.819285355
Short name T737
Test name
Test status
Simulation time 21317068 ps
CPU time 0.73 seconds
Started Mar 31 01:25:25 PM PDT 24
Finished Mar 31 01:25:26 PM PDT 24
Peak memory 206348 kb
Host smart-68c7e6ab-5be8-424a-9ac9-42c7e29e52b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819285355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.819285355
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.723997311
Short name T606
Test name
Test status
Simulation time 59742034 ps
CPU time 0.77 seconds
Started Mar 31 01:25:30 PM PDT 24
Finished Mar 31 01:25:31 PM PDT 24
Peak memory 207304 kb
Host smart-f4deb641-436b-4ac0-913e-7c3b09ecff02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723997311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.723997311
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.3041435879
Short name T554
Test name
Test status
Simulation time 3366973653 ps
CPU time 59.04 seconds
Started Mar 31 01:25:21 PM PDT 24
Finished Mar 31 01:26:20 PM PDT 24
Peak memory 249672 kb
Host smart-9d3d9c4e-d76e-4184-9644-ca8863ce7d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041435879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.3041435879
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.2729839246
Short name T288
Test name
Test status
Simulation time 1941531579 ps
CPU time 17.6 seconds
Started Mar 31 01:25:38 PM PDT 24
Finished Mar 31 01:25:56 PM PDT 24
Peak memory 219824 kb
Host smart-55e553c4-f276-4281-82f0-cdc81cac57f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729839246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2729839246
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.3615849913
Short name T592
Test name
Test status
Simulation time 3247020880 ps
CPU time 5.1 seconds
Started Mar 31 01:25:25 PM PDT 24
Finished Mar 31 01:25:31 PM PDT 24
Peak memory 222084 kb
Host smart-bbe415cd-421d-41f0-87ba-ed94e4cc325b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3615849913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.3615849913
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.4223418655
Short name T62
Test name
Test status
Simulation time 35230908500 ps
CPU time 18.66 seconds
Started Mar 31 01:25:20 PM PDT 24
Finished Mar 31 01:25:39 PM PDT 24
Peak memory 216884 kb
Host smart-800f0c3b-debb-4eb2-812a-105e5d496c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223418655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.4223418655
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.163022574
Short name T683
Test name
Test status
Simulation time 430102267 ps
CPU time 5.02 seconds
Started Mar 31 01:25:23 PM PDT 24
Finished Mar 31 01:25:28 PM PDT 24
Peak memory 216692 kb
Host smart-fb2845c9-6d27-4d4d-b465-44cbf8f6e0b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163022574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.163022574
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.2219127516
Short name T425
Test name
Test status
Simulation time 145973465 ps
CPU time 0.8 seconds
Started Mar 31 01:25:22 PM PDT 24
Finished Mar 31 01:25:23 PM PDT 24
Peak memory 206308 kb
Host smart-8fb5498c-9a8d-4792-bc27-be7695663ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219127516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.2219127516
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.2736222018
Short name T274
Test name
Test status
Simulation time 11708374428 ps
CPU time 18.77 seconds
Started Mar 31 01:25:24 PM PDT 24
Finished Mar 31 01:25:43 PM PDT 24
Peak memory 224404 kb
Host smart-1308ace0-7641-43fd-9b86-9856d9799a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736222018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.2736222018
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.4030396047
Short name T501
Test name
Test status
Simulation time 12461700 ps
CPU time 0.71 seconds
Started Mar 31 01:25:28 PM PDT 24
Finished Mar 31 01:25:29 PM PDT 24
Peak memory 206008 kb
Host smart-995c6ea3-29b6-43a6-a725-2230497f49b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030396047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
4030396047
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.3603171512
Short name T586
Test name
Test status
Simulation time 30042456 ps
CPU time 0.78 seconds
Started Mar 31 01:25:25 PM PDT 24
Finished Mar 31 01:25:26 PM PDT 24
Peak memory 206576 kb
Host smart-e8a0184c-f9d0-43ca-afc4-6a9894d9ebb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603171512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.3603171512
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_intercept.2272292285
Short name T243
Test name
Test status
Simulation time 2060464705 ps
CPU time 18.92 seconds
Started Mar 31 01:25:27 PM PDT 24
Finished Mar 31 01:25:47 PM PDT 24
Peak memory 219268 kb
Host smart-29d8fed2-0ea3-41ee-9852-7e2935f16b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272292285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.2272292285
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.1075069263
Short name T74
Test name
Test status
Simulation time 973613810 ps
CPU time 3.73 seconds
Started Mar 31 01:25:30 PM PDT 24
Finished Mar 31 01:25:34 PM PDT 24
Peak memory 219012 kb
Host smart-1550a779-78fa-42aa-8b0e-b27951b374ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075069263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.1075069263
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.4256321122
Short name T514
Test name
Test status
Simulation time 1557480675 ps
CPU time 18.41 seconds
Started Mar 31 01:25:26 PM PDT 24
Finished Mar 31 01:25:45 PM PDT 24
Peak memory 223448 kb
Host smart-ffcd1a0c-0953-464a-92ad-7ae613260f6b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4256321122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.4256321122
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.641522728
Short name T176
Test name
Test status
Simulation time 2299246303 ps
CPU time 4.05 seconds
Started Mar 31 01:25:26 PM PDT 24
Finished Mar 31 01:25:30 PM PDT 24
Peak memory 216876 kb
Host smart-64a125f1-a2c2-4ff9-a5a2-c29a621deb62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641522728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.641522728
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.1338884015
Short name T628
Test name
Test status
Simulation time 1501426099 ps
CPU time 7.67 seconds
Started Mar 31 01:25:27 PM PDT 24
Finished Mar 31 01:25:35 PM PDT 24
Peak memory 216776 kb
Host smart-14cd77b0-bf1b-427c-9b89-4d1210a2321d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338884015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.1338884015
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.2160953250
Short name T388
Test name
Test status
Simulation time 227602958 ps
CPU time 1.74 seconds
Started Mar 31 01:25:28 PM PDT 24
Finished Mar 31 01:25:30 PM PDT 24
Peak memory 216788 kb
Host smart-8b8f87ef-b465-48eb-9240-634e2eb9aed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160953250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.2160953250
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.3445283822
Short name T618
Test name
Test status
Simulation time 49804353 ps
CPU time 0.7 seconds
Started Mar 31 01:25:26 PM PDT 24
Finished Mar 31 01:25:27 PM PDT 24
Peak memory 206216 kb
Host smart-6877cdd4-5f46-4ce9-90c2-75dfd665a835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445283822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.3445283822
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.2095178418
Short name T552
Test name
Test status
Simulation time 19307154 ps
CPU time 0.71 seconds
Started Mar 31 01:25:29 PM PDT 24
Finished Mar 31 01:25:30 PM PDT 24
Peak memory 206000 kb
Host smart-0293178d-c4c2-4796-9193-45173853843f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095178418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
2095178418
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.362248854
Short name T99
Test name
Test status
Simulation time 198732891 ps
CPU time 2.76 seconds
Started Mar 31 01:25:30 PM PDT 24
Finished Mar 31 01:25:33 PM PDT 24
Peak memory 218864 kb
Host smart-5084df4b-24ef-4f92-914d-4a1dad6af524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362248854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.362248854
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.471083677
Short name T634
Test name
Test status
Simulation time 42307947 ps
CPU time 0.79 seconds
Started Mar 31 01:25:27 PM PDT 24
Finished Mar 31 01:25:28 PM PDT 24
Peak memory 207492 kb
Host smart-135d1747-d947-4340-bb3f-390fc169baf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471083677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.471083677
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.3770272254
Short name T443
Test name
Test status
Simulation time 357850130 ps
CPU time 3.56 seconds
Started Mar 31 01:25:27 PM PDT 24
Finished Mar 31 01:25:31 PM PDT 24
Peak memory 223384 kb
Host smart-fe3ba179-b3da-4413-bc0c-3675e6097b04
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3770272254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.3770272254
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.1071136962
Short name T382
Test name
Test status
Simulation time 72045420225 ps
CPU time 27.71 seconds
Started Mar 31 01:25:29 PM PDT 24
Finished Mar 31 01:25:57 PM PDT 24
Peak memory 216444 kb
Host smart-da1bf156-1494-4a34-862e-5ecada4aa93b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071136962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.1071136962
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.334729667
Short name T553
Test name
Test status
Simulation time 19212747604 ps
CPU time 27.9 seconds
Started Mar 31 01:25:26 PM PDT 24
Finished Mar 31 01:25:54 PM PDT 24
Peak memory 216764 kb
Host smart-6c79fed9-853b-42e4-9952-c75d40e6a496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334729667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.334729667
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.482359825
Short name T577
Test name
Test status
Simulation time 90038517 ps
CPU time 1.56 seconds
Started Mar 31 01:25:27 PM PDT 24
Finished Mar 31 01:25:30 PM PDT 24
Peak memory 216740 kb
Host smart-a9ca87c4-d196-43bf-854b-33fc9dd7e545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482359825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.482359825
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.1893948685
Short name T424
Test name
Test status
Simulation time 71217713 ps
CPU time 0.9 seconds
Started Mar 31 01:25:35 PM PDT 24
Finished Mar 31 01:25:36 PM PDT 24
Peak memory 207004 kb
Host smart-88d6e155-11f9-422c-9576-b291d0495753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893948685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.1893948685
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.1765305748
Short name T505
Test name
Test status
Simulation time 62328321 ps
CPU time 0.72 seconds
Started Mar 31 01:25:35 PM PDT 24
Finished Mar 31 01:25:36 PM PDT 24
Peak memory 206288 kb
Host smart-578afa36-64b4-4404-be45-adc31501c28b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765305748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
1765305748
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.1813114810
Short name T648
Test name
Test status
Simulation time 31705394 ps
CPU time 0.73 seconds
Started Mar 31 01:25:30 PM PDT 24
Finished Mar 31 01:25:31 PM PDT 24
Peak memory 207492 kb
Host smart-7f023ec6-4daa-4f04-bf9c-2f5fc6baf579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813114810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.1813114810
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.446631723
Short name T303
Test name
Test status
Simulation time 54921026706 ps
CPU time 98.37 seconds
Started Mar 31 01:25:37 PM PDT 24
Finished Mar 31 01:27:16 PM PDT 24
Peak memory 238052 kb
Host smart-6a431d7d-c17b-462a-8373-8352dadf44a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446631723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.446631723
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.579756781
Short name T279
Test name
Test status
Simulation time 111396992 ps
CPU time 3.69 seconds
Started Mar 31 01:25:32 PM PDT 24
Finished Mar 31 01:25:36 PM PDT 24
Peak memory 223512 kb
Host smart-cdfb471d-3700-4051-98d6-2a73266f11d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579756781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.579756781
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.2655635428
Short name T216
Test name
Test status
Simulation time 20178896240 ps
CPU time 29.88 seconds
Started Mar 31 01:25:34 PM PDT 24
Finished Mar 31 01:26:04 PM PDT 24
Peak memory 238960 kb
Host smart-23a3f903-791b-4973-88b4-d375e3bd754c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655635428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.2655635428
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.1718462094
Short name T729
Test name
Test status
Simulation time 375150505 ps
CPU time 5.95 seconds
Started Mar 31 01:25:36 PM PDT 24
Finished Mar 31 01:25:42 PM PDT 24
Peak memory 220812 kb
Host smart-ee4a5b02-b964-476f-b522-861d726dcacf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1718462094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.1718462094
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.3657467077
Short name T494
Test name
Test status
Simulation time 306265659 ps
CPU time 4.39 seconds
Started Mar 31 01:25:35 PM PDT 24
Finished Mar 31 01:25:39 PM PDT 24
Peak memory 216564 kb
Host smart-a94f1052-11ab-4f5e-8e37-d5036114a591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657467077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.3657467077
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.2839748872
Short name T457
Test name
Test status
Simulation time 13281141843 ps
CPU time 7.42 seconds
Started Mar 31 01:25:25 PM PDT 24
Finished Mar 31 01:25:33 PM PDT 24
Peak memory 216820 kb
Host smart-66f65b5e-e83d-4f18-8c24-0ac6ea578b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839748872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.2839748872
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.128113601
Short name T680
Test name
Test status
Simulation time 318515633 ps
CPU time 1.54 seconds
Started Mar 31 01:25:32 PM PDT 24
Finished Mar 31 01:25:33 PM PDT 24
Peak memory 216788 kb
Host smart-1e20c3fb-c1e8-4311-8f24-9a78db2f2fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128113601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.128113601
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.1350664247
Short name T601
Test name
Test status
Simulation time 215842009 ps
CPU time 1.13 seconds
Started Mar 31 01:25:29 PM PDT 24
Finished Mar 31 01:25:30 PM PDT 24
Peak memory 207224 kb
Host smart-f3191a1b-7274-4805-87ca-6c30584367b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350664247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.1350664247
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.1820360762
Short name T699
Test name
Test status
Simulation time 16819282 ps
CPU time 0.75 seconds
Started Mar 31 01:25:37 PM PDT 24
Finished Mar 31 01:25:38 PM PDT 24
Peak memory 205960 kb
Host smart-1f6ef3f3-671b-4097-8406-b4a25d60e4ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820360762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
1820360762
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.1144607029
Short name T508
Test name
Test status
Simulation time 22051385 ps
CPU time 0.78 seconds
Started Mar 31 01:25:38 PM PDT 24
Finished Mar 31 01:25:39 PM PDT 24
Peak memory 207080 kb
Host smart-5541e4ea-1d41-428c-84ae-82c8522b9cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144607029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.1144607029
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_intercept.55148498
Short name T345
Test name
Test status
Simulation time 2364913400 ps
CPU time 8.03 seconds
Started Mar 31 01:25:33 PM PDT 24
Finished Mar 31 01:25:41 PM PDT 24
Peak memory 233160 kb
Host smart-e3a8ad89-d14f-4b02-a14c-f61e17e201d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55148498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.55148498
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.1728372174
Short name T213
Test name
Test status
Simulation time 63847926294 ps
CPU time 9.88 seconds
Started Mar 31 01:25:33 PM PDT 24
Finished Mar 31 01:25:43 PM PDT 24
Peak memory 219040 kb
Host smart-47b88512-b0fe-486a-9e51-ab7725a0a1d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728372174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.1728372174
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.2724539969
Short name T81
Test name
Test status
Simulation time 3342368449 ps
CPU time 13.48 seconds
Started Mar 31 01:25:36 PM PDT 24
Finished Mar 31 01:25:50 PM PDT 24
Peak memory 224980 kb
Host smart-2b39dc06-7841-4213-97d7-c6ec8a41e55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724539969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.2724539969
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.887179555
Short name T722
Test name
Test status
Simulation time 1196255419 ps
CPU time 4.06 seconds
Started Mar 31 01:25:37 PM PDT 24
Finished Mar 31 01:25:41 PM PDT 24
Peak memory 220424 kb
Host smart-02a9e931-675e-4632-913f-057aec14fc3e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=887179555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dire
ct.887179555
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.1943697499
Short name T44
Test name
Test status
Simulation time 160272764 ps
CPU time 0.89 seconds
Started Mar 31 01:25:32 PM PDT 24
Finished Mar 31 01:25:33 PM PDT 24
Peak memory 207192 kb
Host smart-7af5f950-b837-43b7-9ce2-afe1de5d60e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943697499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.1943697499
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.3894435952
Short name T593
Test name
Test status
Simulation time 4381379595 ps
CPU time 40.86 seconds
Started Mar 31 01:25:34 PM PDT 24
Finished Mar 31 01:26:15 PM PDT 24
Peak memory 216976 kb
Host smart-6da20ca9-b95f-4bf3-baf7-1219e91326d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894435952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.3894435952
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.76765107
Short name T415
Test name
Test status
Simulation time 731174970 ps
CPU time 3.93 seconds
Started Mar 31 01:25:35 PM PDT 24
Finished Mar 31 01:25:39 PM PDT 24
Peak memory 216728 kb
Host smart-23e4bb23-2e42-4948-83e5-af8853b813e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76765107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.76765107
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.4086854065
Short name T15
Test name
Test status
Simulation time 247247416 ps
CPU time 2.5 seconds
Started Mar 31 01:25:41 PM PDT 24
Finished Mar 31 01:25:43 PM PDT 24
Peak memory 216936 kb
Host smart-b0fef473-5a9a-4762-a200-91a2168d982f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086854065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.4086854065
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.1755111583
Short name T558
Test name
Test status
Simulation time 65509009 ps
CPU time 0.91 seconds
Started Mar 31 01:25:34 PM PDT 24
Finished Mar 31 01:25:35 PM PDT 24
Peak memory 206288 kb
Host smart-a8155ecc-cf77-4028-a94d-7608074d3509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755111583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.1755111583
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.3259237529
Short name T416
Test name
Test status
Simulation time 13176935 ps
CPU time 0.72 seconds
Started Mar 31 01:23:44 PM PDT 24
Finished Mar 31 01:23:45 PM PDT 24
Peak memory 205996 kb
Host smart-120ef48b-22e0-44c2-bc38-2a1835b02cea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259237529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.3
259237529
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.601185165
Short name T596
Test name
Test status
Simulation time 16846126 ps
CPU time 0.8 seconds
Started Mar 31 01:23:45 PM PDT 24
Finished Mar 31 01:23:46 PM PDT 24
Peak memory 207488 kb
Host smart-78e4942b-52e7-48d0-bcf3-900f761d39d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601185165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.601185165
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.2762838837
Short name T427
Test name
Test status
Simulation time 1276865846 ps
CPU time 11.82 seconds
Started Mar 31 01:23:44 PM PDT 24
Finished Mar 31 01:23:56 PM PDT 24
Peak memory 240460 kb
Host smart-cb090895-4ed9-494e-a8d9-25040c1f9200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762838837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.2762838837
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.3599428666
Short name T584
Test name
Test status
Simulation time 25997553834 ps
CPU time 40.96 seconds
Started Mar 31 01:23:52 PM PDT 24
Finished Mar 31 01:24:33 PM PDT 24
Peak memory 233716 kb
Host smart-077517c2-5b1c-40ef-88a1-647539882ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599428666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.3599428666
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.2838823602
Short name T340
Test name
Test status
Simulation time 3300180983 ps
CPU time 13.94 seconds
Started Mar 31 01:23:52 PM PDT 24
Finished Mar 31 01:24:06 PM PDT 24
Peak memory 224504 kb
Host smart-f9c3a65f-5e8f-4225-8dd5-2807ab90d330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838823602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.2838823602
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.878797389
Short name T80
Test name
Test status
Simulation time 4107182956 ps
CPU time 13.07 seconds
Started Mar 31 01:23:44 PM PDT 24
Finished Mar 31 01:23:57 PM PDT 24
Peak memory 223540 kb
Host smart-8087aeb3-a50d-442c-bbd7-5104d7214457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878797389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.878797389
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_ram_cfg.2995487092
Short name T492
Test name
Test status
Simulation time 45370834 ps
CPU time 0.74 seconds
Started Mar 31 01:23:45 PM PDT 24
Finished Mar 31 01:23:45 PM PDT 24
Peak memory 216752 kb
Host smart-00af4325-0882-4eee-8e54-4887f06ee88b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995487092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_ram_cfg.2995487092
Directory /workspace/4.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.3019005362
Short name T532
Test name
Test status
Simulation time 315600146 ps
CPU time 4.45 seconds
Started Mar 31 01:23:44 PM PDT 24
Finished Mar 31 01:23:48 PM PDT 24
Peak memory 222756 kb
Host smart-3ff3cfd3-c882-4efa-813b-e68244c94f49
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3019005362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.3019005362
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.874224634
Short name T57
Test name
Test status
Simulation time 39752948 ps
CPU time 0.99 seconds
Started Mar 31 01:23:49 PM PDT 24
Finished Mar 31 01:23:50 PM PDT 24
Peak memory 235692 kb
Host smart-0377dc89-be8b-462b-9e17-9c74c47d8bbb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874224634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.874224634
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.3389159820
Short name T733
Test name
Test status
Simulation time 889753910 ps
CPU time 7.78 seconds
Started Mar 31 01:23:47 PM PDT 24
Finished Mar 31 01:23:55 PM PDT 24
Peak memory 216792 kb
Host smart-f6252bc4-2a84-4c14-8a05-0893f259bd4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389159820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.3389159820
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.4086129049
Short name T444
Test name
Test status
Simulation time 132854046839 ps
CPU time 29.85 seconds
Started Mar 31 01:23:44 PM PDT 24
Finished Mar 31 01:24:14 PM PDT 24
Peak memory 216820 kb
Host smart-c31847ed-0cc6-46b0-a434-c406c2588e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086129049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.4086129049
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.388320484
Short name T727
Test name
Test status
Simulation time 159399411 ps
CPU time 1.6 seconds
Started Mar 31 01:23:44 PM PDT 24
Finished Mar 31 01:23:45 PM PDT 24
Peak memory 216696 kb
Host smart-1ae79853-82b6-4aa0-b332-c08070e7e280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388320484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.388320484
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.2412188301
Short name T1
Test name
Test status
Simulation time 65424038 ps
CPU time 0.86 seconds
Started Mar 31 01:23:45 PM PDT 24
Finished Mar 31 01:23:46 PM PDT 24
Peak memory 207224 kb
Host smart-92119b6e-0525-42d7-95bc-e8d55627324b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412188301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.2412188301
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.2121182761
Short name T666
Test name
Test status
Simulation time 40966098 ps
CPU time 0.76 seconds
Started Mar 31 01:25:42 PM PDT 24
Finished Mar 31 01:25:43 PM PDT 24
Peak memory 205960 kb
Host smart-59715818-802a-4b6a-a15f-ed9f53d7d3f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121182761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
2121182761
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.1847592557
Short name T564
Test name
Test status
Simulation time 48078668 ps
CPU time 0.74 seconds
Started Mar 31 01:25:33 PM PDT 24
Finished Mar 31 01:25:34 PM PDT 24
Peak memory 207412 kb
Host smart-588b4880-8ab7-49c3-b621-f8d677b22294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847592557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.1847592557
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.2676712148
Short name T328
Test name
Test status
Simulation time 6633879894 ps
CPU time 59.27 seconds
Started Mar 31 01:25:38 PM PDT 24
Finished Mar 31 01:26:38 PM PDT 24
Peak memory 223584 kb
Host smart-974c49bd-3775-4836-a025-f85a2a7ab7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676712148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.2676712148
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.2927658561
Short name T583
Test name
Test status
Simulation time 234403538 ps
CPU time 2.97 seconds
Started Mar 31 01:25:36 PM PDT 24
Finished Mar 31 01:25:39 PM PDT 24
Peak memory 218844 kb
Host smart-a61341f7-f671-417c-9419-4a9135dec8a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927658561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2927658561
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.1810563642
Short name T537
Test name
Test status
Simulation time 551825333 ps
CPU time 5.55 seconds
Started Mar 31 01:25:42 PM PDT 24
Finished Mar 31 01:25:47 PM PDT 24
Peak memory 220704 kb
Host smart-438ffbb7-dae3-4cb2-ad95-77fbc10dd0a1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1810563642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.1810563642
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.3412316413
Short name T712
Test name
Test status
Simulation time 34071578325 ps
CPU time 25.8 seconds
Started Mar 31 01:25:37 PM PDT 24
Finished Mar 31 01:26:03 PM PDT 24
Peak memory 217832 kb
Host smart-3df23853-317b-494f-99f4-d2a84e5f144f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412316413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.3412316413
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.3771012566
Short name T685
Test name
Test status
Simulation time 32393986448 ps
CPU time 9.95 seconds
Started Mar 31 01:25:33 PM PDT 24
Finished Mar 31 01:25:43 PM PDT 24
Peak memory 216784 kb
Host smart-de61c447-51ff-4619-b582-b62e877db705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771012566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.3771012566
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.3252549871
Short name T591
Test name
Test status
Simulation time 179737138 ps
CPU time 1.49 seconds
Started Mar 31 01:25:36 PM PDT 24
Finished Mar 31 01:25:38 PM PDT 24
Peak memory 216668 kb
Host smart-4d81fae7-f1cf-430f-9a75-b8db6062f23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252549871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.3252549871
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.4160547201
Short name T717
Test name
Test status
Simulation time 275292300 ps
CPU time 0.9 seconds
Started Mar 31 01:25:34 PM PDT 24
Finished Mar 31 01:25:35 PM PDT 24
Peak memory 206204 kb
Host smart-a55adf39-9590-4860-82ff-8f4c4985dcfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160547201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.4160547201
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.569153074
Short name T566
Test name
Test status
Simulation time 12495215 ps
CPU time 0.73 seconds
Started Mar 31 01:25:41 PM PDT 24
Finished Mar 31 01:25:42 PM PDT 24
Peak memory 205944 kb
Host smart-cc06f1fc-8147-4e94-b693-60b4bdb116dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569153074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.569153074
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.744012253
Short name T534
Test name
Test status
Simulation time 13528759 ps
CPU time 0.77 seconds
Started Mar 31 01:25:40 PM PDT 24
Finished Mar 31 01:25:41 PM PDT 24
Peak memory 207488 kb
Host smart-0284b9ac-319e-471c-8cf6-88c9e5055309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744012253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.744012253
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.523976148
Short name T585
Test name
Test status
Simulation time 25545697777 ps
CPU time 102.09 seconds
Started Mar 31 01:25:39 PM PDT 24
Finished Mar 31 01:27:21 PM PDT 24
Peak memory 252728 kb
Host smart-b1bc0aae-bc06-494c-8000-840734ec5b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523976148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.523976148
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.3719078847
Short name T482
Test name
Test status
Simulation time 283857414 ps
CPU time 4.33 seconds
Started Mar 31 01:25:46 PM PDT 24
Finished Mar 31 01:25:50 PM PDT 24
Peak memory 223608 kb
Host smart-8c9464aa-762b-4cda-ad55-58cf01d1f660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719078847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.3719078847
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.2955602529
Short name T374
Test name
Test status
Simulation time 14063338127 ps
CPU time 6.18 seconds
Started Mar 31 01:25:51 PM PDT 24
Finished Mar 31 01:25:57 PM PDT 24
Peak memory 223032 kb
Host smart-715dcc4c-9f30-4e77-8d55-c088247af961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955602529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.2955602529
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.2339060851
Short name T423
Test name
Test status
Simulation time 1301989526 ps
CPU time 11.12 seconds
Started Mar 31 01:25:41 PM PDT 24
Finished Mar 31 01:25:52 PM PDT 24
Peak memory 220740 kb
Host smart-a5c2a932-6e89-48e1-9d8c-4d0416e3b8de
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2339060851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.2339060851
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.4178558865
Short name T111
Test name
Test status
Simulation time 3591189383 ps
CPU time 19.04 seconds
Started Mar 31 01:25:52 PM PDT 24
Finished Mar 31 01:26:12 PM PDT 24
Peak memory 216824 kb
Host smart-108a2609-b866-4156-b05c-8598a94b9f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178558865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.4178558865
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.3818621187
Short name T476
Test name
Test status
Simulation time 71965504062 ps
CPU time 13.75 seconds
Started Mar 31 01:25:42 PM PDT 24
Finished Mar 31 01:25:56 PM PDT 24
Peak memory 216772 kb
Host smart-36a56da6-09bc-444a-92e0-9a2771ce4afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818621187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.3818621187
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.2167805971
Short name T653
Test name
Test status
Simulation time 62476817 ps
CPU time 1.24 seconds
Started Mar 31 01:25:40 PM PDT 24
Finished Mar 31 01:25:42 PM PDT 24
Peak memory 208604 kb
Host smart-5f46a667-5529-493b-8609-1f911ad99234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167805971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.2167805971
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.3124152644
Short name T735
Test name
Test status
Simulation time 45965091 ps
CPU time 0.84 seconds
Started Mar 31 01:25:42 PM PDT 24
Finished Mar 31 01:25:43 PM PDT 24
Peak memory 206196 kb
Host smart-b447229e-73a2-4dfb-81fc-064472371c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124152644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.3124152644
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.793545913
Short name T350
Test name
Test status
Simulation time 35284615195 ps
CPU time 35 seconds
Started Mar 31 01:25:41 PM PDT 24
Finished Mar 31 01:26:16 PM PDT 24
Peak memory 216840 kb
Host smart-8e410d86-55ad-4ec4-8473-b1dbcd4cc270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793545913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.793545913
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.2326334130
Short name T543
Test name
Test status
Simulation time 35820301 ps
CPU time 0.69 seconds
Started Mar 31 01:25:51 PM PDT 24
Finished Mar 31 01:25:52 PM PDT 24
Peak memory 205432 kb
Host smart-9d781f84-6ce6-464f-95f9-55ff25c9960e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326334130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
2326334130
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.2785580837
Short name T25
Test name
Test status
Simulation time 20164856 ps
CPU time 0.77 seconds
Started Mar 31 01:25:41 PM PDT 24
Finished Mar 31 01:25:42 PM PDT 24
Peak memory 207104 kb
Host smart-3f0928c0-2e5c-417d-b119-9a0217b19354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785580837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2785580837
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_intercept.3467270139
Short name T220
Test name
Test status
Simulation time 12531190589 ps
CPU time 14.15 seconds
Started Mar 31 01:25:40 PM PDT 24
Finished Mar 31 01:25:54 PM PDT 24
Peak memory 223336 kb
Host smart-984a8536-4b78-4bda-9246-4108bea3bfa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467270139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.3467270139
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.1295249888
Short name T282
Test name
Test status
Simulation time 50943235509 ps
CPU time 35.73 seconds
Started Mar 31 01:25:41 PM PDT 24
Finished Mar 31 01:26:17 PM PDT 24
Peak memory 219364 kb
Host smart-5f0452cb-6f8f-49c2-8a19-c6dc8b4d5051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295249888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1295249888
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.1174673484
Short name T716
Test name
Test status
Simulation time 1789281360 ps
CPU time 8.11 seconds
Started Mar 31 01:25:50 PM PDT 24
Finished Mar 31 01:25:58 PM PDT 24
Peak memory 220956 kb
Host smart-c27401bd-aca6-4376-ae9c-441e39695fbd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1174673484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.1174673484
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.1698672005
Short name T173
Test name
Test status
Simulation time 48336347509 ps
CPU time 50.05 seconds
Started Mar 31 01:25:52 PM PDT 24
Finished Mar 31 01:26:42 PM PDT 24
Peak memory 216876 kb
Host smart-91766e78-dfd4-475d-8de4-40de794d6005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698672005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.1698672005
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.333401172
Short name T521
Test name
Test status
Simulation time 2462913281 ps
CPU time 5.95 seconds
Started Mar 31 01:25:39 PM PDT 24
Finished Mar 31 01:25:45 PM PDT 24
Peak memory 216744 kb
Host smart-8b4598d5-fb02-473c-953a-a5ee78c78eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333401172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.333401172
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.3700286401
Short name T570
Test name
Test status
Simulation time 123968139 ps
CPU time 2.73 seconds
Started Mar 31 01:25:42 PM PDT 24
Finished Mar 31 01:25:45 PM PDT 24
Peak memory 216812 kb
Host smart-38346d34-88a6-4964-8899-7b6367cff79b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700286401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.3700286401
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.1633200895
Short name T405
Test name
Test status
Simulation time 47280032 ps
CPU time 0.77 seconds
Started Mar 31 01:25:46 PM PDT 24
Finished Mar 31 01:25:47 PM PDT 24
Peak memory 206180 kb
Host smart-ace8a749-a51b-4616-900f-7050a16f4fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633200895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.1633200895
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.1323636818
Short name T191
Test name
Test status
Simulation time 828256443 ps
CPU time 7.93 seconds
Started Mar 31 01:25:50 PM PDT 24
Finished Mar 31 01:25:58 PM PDT 24
Peak memory 222964 kb
Host smart-2d8e9206-77aa-4181-ae39-8c235a867f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323636818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.1323636818
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.2665121926
Short name T567
Test name
Test status
Simulation time 15378005 ps
CPU time 0.77 seconds
Started Mar 31 01:25:50 PM PDT 24
Finished Mar 31 01:25:51 PM PDT 24
Peak memory 205980 kb
Host smart-6f5fcead-5bca-42b4-971e-cf2c8526cf9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665121926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
2665121926
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.3211163222
Short name T576
Test name
Test status
Simulation time 1570242587 ps
CPU time 3.77 seconds
Started Mar 31 01:25:52 PM PDT 24
Finished Mar 31 01:25:56 PM PDT 24
Peak memory 222028 kb
Host smart-cca5f0a0-b3eb-4113-863f-285af7815ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211163222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.3211163222
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.2526015006
Short name T702
Test name
Test status
Simulation time 57262496 ps
CPU time 0.82 seconds
Started Mar 31 01:25:53 PM PDT 24
Finished Mar 31 01:25:54 PM PDT 24
Peak memory 207504 kb
Host smart-a141a897-7af6-4324-b79f-60c29faefd23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526015006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.2526015006
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_intercept.2791769272
Short name T713
Test name
Test status
Simulation time 4830100540 ps
CPU time 14.38 seconds
Started Mar 31 01:25:49 PM PDT 24
Finished Mar 31 01:26:04 PM PDT 24
Peak memory 219500 kb
Host smart-578d55c5-8fc2-408d-ab6b-570906fb8581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791769272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.2791769272
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.3942225061
Short name T229
Test name
Test status
Simulation time 2065354168 ps
CPU time 7.4 seconds
Started Mar 31 01:25:56 PM PDT 24
Finished Mar 31 01:26:04 PM PDT 24
Peak memory 221988 kb
Host smart-73a15f54-574c-4009-807a-d02c5f462346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942225061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.3942225061
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.710272184
Short name T715
Test name
Test status
Simulation time 152847601 ps
CPU time 3.74 seconds
Started Mar 31 01:25:51 PM PDT 24
Finished Mar 31 01:25:55 PM PDT 24
Peak memory 223364 kb
Host smart-4f674f48-0190-4097-a871-b367d76cd855
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=710272184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dire
ct.710272184
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.771263929
Short name T613
Test name
Test status
Simulation time 1871560380 ps
CPU time 3.36 seconds
Started Mar 31 01:25:50 PM PDT 24
Finished Mar 31 01:25:53 PM PDT 24
Peak memory 216720 kb
Host smart-03375f9f-905b-4acb-b37a-c7bb2dac6081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771263929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.771263929
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.3333902472
Short name T396
Test name
Test status
Simulation time 188499600 ps
CPU time 2.47 seconds
Started Mar 31 01:25:49 PM PDT 24
Finished Mar 31 01:25:52 PM PDT 24
Peak memory 216540 kb
Host smart-b0410196-67a8-4355-adea-2bbf6b181681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333902472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.3333902472
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.3353908111
Short name T417
Test name
Test status
Simulation time 263439331 ps
CPU time 0.94 seconds
Started Mar 31 01:25:53 PM PDT 24
Finished Mar 31 01:25:54 PM PDT 24
Peak memory 207280 kb
Host smart-deaa410f-0c4b-459c-90e3-d07b67b5fef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353908111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.3353908111
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.3488130028
Short name T375
Test name
Test status
Simulation time 637439998 ps
CPU time 4.99 seconds
Started Mar 31 01:25:56 PM PDT 24
Finished Mar 31 01:26:01 PM PDT 24
Peak memory 218000 kb
Host smart-064117d8-ef22-4832-8512-ffe779f84370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488130028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3488130028
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.2783062225
Short name T650
Test name
Test status
Simulation time 33855831 ps
CPU time 0.7 seconds
Started Mar 31 01:25:54 PM PDT 24
Finished Mar 31 01:25:55 PM PDT 24
Peak memory 205376 kb
Host smart-5b44f831-423e-4376-9c5a-e350e31310f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783062225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
2783062225
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.2802059957
Short name T29
Test name
Test status
Simulation time 9221104523 ps
CPU time 25.02 seconds
Started Mar 31 01:25:59 PM PDT 24
Finished Mar 31 01:26:24 PM PDT 24
Peak memory 219296 kb
Host smart-149b382a-d663-4ca3-881f-5133f24b9855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802059957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.2802059957
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.494318873
Short name T454
Test name
Test status
Simulation time 20293086 ps
CPU time 0.78 seconds
Started Mar 31 01:25:50 PM PDT 24
Finished Mar 31 01:25:51 PM PDT 24
Peak memory 207496 kb
Host smart-e2c70233-d979-4878-8329-7bb841576d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494318873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.494318873
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_intercept.4144911553
Short name T271
Test name
Test status
Simulation time 4627067537 ps
CPU time 20 seconds
Started Mar 31 01:25:49 PM PDT 24
Finished Mar 31 01:26:10 PM PDT 24
Peak memory 222768 kb
Host smart-c001b6cd-3d73-4cf8-93a1-1834f1f18baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144911553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.4144911553
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.153413784
Short name T180
Test name
Test status
Simulation time 24660512013 ps
CPU time 213.93 seconds
Started Mar 31 01:25:53 PM PDT 24
Finished Mar 31 01:29:27 PM PDT 24
Peak memory 232556 kb
Host smart-f546e8d8-50bf-4c46-ade7-b5dfd03eda7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153413784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.153413784
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.797696199
Short name T673
Test name
Test status
Simulation time 180923035 ps
CPU time 3.2 seconds
Started Mar 31 01:25:51 PM PDT 24
Finished Mar 31 01:25:54 PM PDT 24
Peak memory 218992 kb
Host smart-147b038f-d4f0-40ad-933c-199417f54213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797696199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.797696199
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.3039830916
Short name T547
Test name
Test status
Simulation time 4315471767 ps
CPU time 13.38 seconds
Started Mar 31 01:25:56 PM PDT 24
Finished Mar 31 01:26:10 PM PDT 24
Peak memory 222916 kb
Host smart-fa8e4887-85c5-4879-a550-aa2eec170b96
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3039830916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.3039830916
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.282014019
Short name T560
Test name
Test status
Simulation time 4317369958 ps
CPU time 15.86 seconds
Started Mar 31 01:26:00 PM PDT 24
Finished Mar 31 01:26:16 PM PDT 24
Peak memory 216848 kb
Host smart-3f4ceb45-2c8e-4c1b-ba19-4ff04638aba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282014019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.282014019
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.3076331799
Short name T118
Test name
Test status
Simulation time 10870340678 ps
CPU time 10.77 seconds
Started Mar 31 01:25:49 PM PDT 24
Finished Mar 31 01:26:00 PM PDT 24
Peak memory 216784 kb
Host smart-711b3bc2-60b5-4297-9cf8-abd383f067fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076331799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.3076331799
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.1081325757
Short name T391
Test name
Test status
Simulation time 469877931 ps
CPU time 2 seconds
Started Mar 31 01:25:53 PM PDT 24
Finished Mar 31 01:25:55 PM PDT 24
Peak memory 216724 kb
Host smart-39623e31-02a3-4387-a313-3bfeb18e6e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081325757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.1081325757
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.203252276
Short name T659
Test name
Test status
Simulation time 114226082 ps
CPU time 0.79 seconds
Started Mar 31 01:25:59 PM PDT 24
Finished Mar 31 01:26:00 PM PDT 24
Peak memory 206192 kb
Host smart-1e769f9c-0c37-419f-aeaf-cc8c92b1fe78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203252276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.203252276
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.872557979
Short name T284
Test name
Test status
Simulation time 2885483572 ps
CPU time 6.58 seconds
Started Mar 31 01:25:57 PM PDT 24
Finished Mar 31 01:26:04 PM PDT 24
Peak memory 222020 kb
Host smart-164d5d12-6c3c-43a5-a4be-944ba40a2036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872557979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.872557979
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.2395711868
Short name T407
Test name
Test status
Simulation time 43956301 ps
CPU time 0.7 seconds
Started Mar 31 01:25:53 PM PDT 24
Finished Mar 31 01:25:54 PM PDT 24
Peak memory 206012 kb
Host smart-e99b0c3c-72d8-4827-87dd-cbc97e6b7ed1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395711868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
2395711868
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.1816917306
Short name T589
Test name
Test status
Simulation time 45415325 ps
CPU time 0.79 seconds
Started Mar 31 01:25:58 PM PDT 24
Finished Mar 31 01:25:59 PM PDT 24
Peak memory 207516 kb
Host smart-421ed472-1f8f-43dd-bd46-d803bcf15ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816917306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.1816917306
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.514545411
Short name T158
Test name
Test status
Simulation time 33979176797 ps
CPU time 59.94 seconds
Started Mar 31 01:25:51 PM PDT 24
Finished Mar 31 01:26:51 PM PDT 24
Peak memory 253524 kb
Host smart-03f1796c-ae2c-4c54-bb22-25b5a5d3e1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514545411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.514545411
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.393206025
Short name T127
Test name
Test status
Simulation time 6565287225 ps
CPU time 14.07 seconds
Started Mar 31 01:25:52 PM PDT 24
Finished Mar 31 01:26:06 PM PDT 24
Peak memory 225064 kb
Host smart-6bcdda9d-544c-4c03-9b33-ffcc80d2bfc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393206025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.393206025
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.3288645859
Short name T724
Test name
Test status
Simulation time 8222051990 ps
CPU time 21.05 seconds
Started Mar 31 01:26:01 PM PDT 24
Finished Mar 31 01:26:22 PM PDT 24
Peak memory 225024 kb
Host smart-8eee93f9-b8bc-4a48-894e-db502b14b67c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288645859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.3288645859
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.3084632784
Short name T342
Test name
Test status
Simulation time 1791667496 ps
CPU time 6.71 seconds
Started Mar 31 01:25:52 PM PDT 24
Finished Mar 31 01:25:59 PM PDT 24
Peak memory 217208 kb
Host smart-26f2ba94-ad07-473a-9dbf-ac4032bc0257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084632784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.3084632784
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.3304721165
Short name T201
Test name
Test status
Simulation time 870083178 ps
CPU time 3.04 seconds
Started Mar 31 01:25:56 PM PDT 24
Finished Mar 31 01:25:59 PM PDT 24
Peak memory 220456 kb
Host smart-5039e612-9f17-4efd-8277-e54b1ced861a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304721165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.3304721165
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.3482114842
Short name T691
Test name
Test status
Simulation time 207094067 ps
CPU time 3.93 seconds
Started Mar 31 01:25:52 PM PDT 24
Finished Mar 31 01:25:56 PM PDT 24
Peak memory 223452 kb
Host smart-95d4c753-7459-45ea-8f72-4e2d136d1c60
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3482114842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.3482114842
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.805307124
Short name T467
Test name
Test status
Simulation time 6242046049 ps
CPU time 21.61 seconds
Started Mar 31 01:25:59 PM PDT 24
Finished Mar 31 01:26:20 PM PDT 24
Peak memory 216844 kb
Host smart-e23a9be2-b051-4ab9-b6cb-7ad5049755f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805307124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.805307124
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.2748844712
Short name T397
Test name
Test status
Simulation time 438021592 ps
CPU time 4.79 seconds
Started Mar 31 01:25:59 PM PDT 24
Finished Mar 31 01:26:03 PM PDT 24
Peak memory 216728 kb
Host smart-5aee3cc0-bb52-4193-a7ed-dc909f13c17c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748844712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.2748844712
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.2857954860
Short name T645
Test name
Test status
Simulation time 22619013 ps
CPU time 0.82 seconds
Started Mar 31 01:25:55 PM PDT 24
Finished Mar 31 01:25:56 PM PDT 24
Peak memory 206180 kb
Host smart-f9e21f82-492f-45cd-b5f2-30d1c9b387c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857954860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.2857954860
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.4051347949
Short name T404
Test name
Test status
Simulation time 14944361 ps
CPU time 0.7 seconds
Started Mar 31 01:25:58 PM PDT 24
Finished Mar 31 01:25:59 PM PDT 24
Peak memory 205984 kb
Host smart-d024d143-68c8-40a5-9921-d63fd4c482a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051347949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
4051347949
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.3513236696
Short name T217
Test name
Test status
Simulation time 735148145 ps
CPU time 4.22 seconds
Started Mar 31 01:26:01 PM PDT 24
Finished Mar 31 01:26:06 PM PDT 24
Peak memory 218968 kb
Host smart-7de7196c-2137-4e3c-8bc1-888b5e3100cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513236696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.3513236696
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.545380897
Short name T600
Test name
Test status
Simulation time 63238026 ps
CPU time 0.77 seconds
Started Mar 31 01:26:00 PM PDT 24
Finished Mar 31 01:26:01 PM PDT 24
Peak memory 206440 kb
Host smart-1f04bfde-8aec-45ac-987e-4b65bfa483a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545380897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.545380897
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.3930064793
Short name T355
Test name
Test status
Simulation time 5524830724 ps
CPU time 12.32 seconds
Started Mar 31 01:26:00 PM PDT 24
Finished Mar 31 01:26:12 PM PDT 24
Peak memory 241392 kb
Host smart-1cf10322-1739-49ba-96d5-c8fac51904c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930064793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.3930064793
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.3776862971
Short name T335
Test name
Test status
Simulation time 3541317419 ps
CPU time 4.79 seconds
Started Mar 31 01:26:00 PM PDT 24
Finished Mar 31 01:26:04 PM PDT 24
Peak memory 217204 kb
Host smart-36318f7b-10ce-4b6f-b355-b29cc9657885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776862971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.3776862971
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.4202707119
Short name T240
Test name
Test status
Simulation time 530934663 ps
CPU time 7.49 seconds
Started Mar 31 01:25:56 PM PDT 24
Finished Mar 31 01:26:04 PM PDT 24
Peak memory 223180 kb
Host smart-dc0b3435-8bba-4540-825c-a3c8c41e3898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202707119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.4202707119
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.3983609908
Short name T456
Test name
Test status
Simulation time 433271515 ps
CPU time 6.13 seconds
Started Mar 31 01:26:03 PM PDT 24
Finished Mar 31 01:26:09 PM PDT 24
Peak memory 220444 kb
Host smart-6e0cc433-eec0-4661-9004-7521bcbfd0ee
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3983609908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.3983609908
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.3623075122
Short name T66
Test name
Test status
Simulation time 11773616620 ps
CPU time 19 seconds
Started Mar 31 01:25:58 PM PDT 24
Finished Mar 31 01:26:17 PM PDT 24
Peak memory 216808 kb
Host smart-72f7aba7-3d86-44a3-bfe4-38c027cfd88d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623075122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.3623075122
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.3712168807
Short name T495
Test name
Test status
Simulation time 6640387520 ps
CPU time 11.12 seconds
Started Mar 31 01:26:01 PM PDT 24
Finished Mar 31 01:26:12 PM PDT 24
Peak memory 217692 kb
Host smart-8bef4d24-2492-4283-af2f-f2cd66afbb46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712168807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.3712168807
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.970082099
Short name T17
Test name
Test status
Simulation time 280044550 ps
CPU time 3.76 seconds
Started Mar 31 01:26:02 PM PDT 24
Finished Mar 31 01:26:06 PM PDT 24
Peak memory 216836 kb
Host smart-ddc783a6-879f-41c6-9fa9-b3594084511d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970082099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.970082099
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.514700484
Short name T466
Test name
Test status
Simulation time 145954526 ps
CPU time 1.04 seconds
Started Mar 31 01:25:59 PM PDT 24
Finished Mar 31 01:26:00 PM PDT 24
Peak memory 207284 kb
Host smart-f008b5a9-cd6f-4743-9025-cdd8d0a0b166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514700484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.514700484
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.3948394748
Short name T557
Test name
Test status
Simulation time 41036490 ps
CPU time 0.72 seconds
Started Mar 31 01:26:03 PM PDT 24
Finished Mar 31 01:26:04 PM PDT 24
Peak memory 205444 kb
Host smart-8f3d34c3-780c-487f-b9a2-aecee2a01f07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948394748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
3948394748
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.1438596280
Short name T30
Test name
Test status
Simulation time 370091266 ps
CPU time 5.9 seconds
Started Mar 31 01:26:10 PM PDT 24
Finished Mar 31 01:26:16 PM PDT 24
Peak memory 233200 kb
Host smart-c6f9bf73-8a58-48fc-a2e2-29b44180f74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438596280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.1438596280
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.80885165
Short name T664
Test name
Test status
Simulation time 63614875 ps
CPU time 0.81 seconds
Started Mar 31 01:26:01 PM PDT 24
Finished Mar 31 01:26:01 PM PDT 24
Peak memory 207076 kb
Host smart-caf34b95-a996-41a4-adaf-3bd25bfd1683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80885165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.80885165
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.1889870799
Short name T578
Test name
Test status
Simulation time 14316248222 ps
CPU time 106.54 seconds
Started Mar 31 01:26:05 PM PDT 24
Finished Mar 31 01:27:52 PM PDT 24
Peak memory 249668 kb
Host smart-941d6c5c-33d7-4452-927c-0d7f8e3634d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889870799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.1889870799
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.3524985862
Short name T20
Test name
Test status
Simulation time 3158626043 ps
CPU time 7.9 seconds
Started Mar 31 01:26:02 PM PDT 24
Finished Mar 31 01:26:10 PM PDT 24
Peak memory 222672 kb
Host smart-5be56933-f3ec-4d31-a651-97fe00810e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524985862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.3524985862
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.736747421
Short name T181
Test name
Test status
Simulation time 1718725685 ps
CPU time 13.28 seconds
Started Mar 31 01:26:00 PM PDT 24
Finished Mar 31 01:26:13 PM PDT 24
Peak memory 224004 kb
Host smart-f4393a33-9ebe-4472-a437-df70259515b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736747421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.736747421
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.1405084511
Short name T641
Test name
Test status
Simulation time 270817196 ps
CPU time 3.6 seconds
Started Mar 31 01:26:00 PM PDT 24
Finished Mar 31 01:26:04 PM PDT 24
Peak memory 224492 kb
Host smart-9de3ca54-f9be-4ae6-86ab-7ace3650c23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405084511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.1405084511
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.1570420103
Short name T509
Test name
Test status
Simulation time 275855153 ps
CPU time 4.01 seconds
Started Mar 31 01:26:13 PM PDT 24
Finished Mar 31 01:26:17 PM PDT 24
Peak memory 219676 kb
Host smart-c23595d8-51d4-4823-859d-169b9e6256e0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1570420103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.1570420103
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.2382304733
Short name T378
Test name
Test status
Simulation time 2302960571 ps
CPU time 23.3 seconds
Started Mar 31 01:25:58 PM PDT 24
Finished Mar 31 01:26:21 PM PDT 24
Peak memory 217128 kb
Host smart-2cac4557-6c48-4277-b7a9-3a368b559bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382304733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.2382304733
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.4191426107
Short name T582
Test name
Test status
Simulation time 6653944267 ps
CPU time 19.62 seconds
Started Mar 31 01:26:02 PM PDT 24
Finished Mar 31 01:26:22 PM PDT 24
Peak memory 216640 kb
Host smart-3fb7faca-d917-4691-817a-e37b69a18fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191426107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.4191426107
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.1367125485
Short name T571
Test name
Test status
Simulation time 62848492 ps
CPU time 1.18 seconds
Started Mar 31 01:26:03 PM PDT 24
Finished Mar 31 01:26:04 PM PDT 24
Peak memory 216604 kb
Host smart-fbf95905-11c5-4fe8-84fd-d27cc34c29f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367125485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.1367125485
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.4218804241
Short name T503
Test name
Test status
Simulation time 100283479 ps
CPU time 0.92 seconds
Started Mar 31 01:25:59 PM PDT 24
Finished Mar 31 01:25:59 PM PDT 24
Peak memory 206200 kb
Host smart-de332428-4f65-49e6-8076-72a296187d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218804241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.4218804241
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.1828958064
Short name T668
Test name
Test status
Simulation time 13339364 ps
CPU time 0.74 seconds
Started Mar 31 01:26:10 PM PDT 24
Finished Mar 31 01:26:11 PM PDT 24
Peak memory 205996 kb
Host smart-a91ef62b-3d32-4ac4-b495-4e678d19ef37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828958064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
1828958064
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.3208635675
Short name T418
Test name
Test status
Simulation time 17470371 ps
CPU time 0.81 seconds
Started Mar 31 01:26:05 PM PDT 24
Finished Mar 31 01:26:06 PM PDT 24
Peak memory 207420 kb
Host smart-c65a746f-8168-4ab5-9aeb-e54f0fbf9371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208635675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.3208635675
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.2843361432
Short name T309
Test name
Test status
Simulation time 42345546991 ps
CPU time 101.43 seconds
Started Mar 31 01:26:03 PM PDT 24
Finished Mar 31 01:27:45 PM PDT 24
Peak memory 249628 kb
Host smart-4f1fa5e3-1808-4940-b31d-75886f92e025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843361432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.2843361432
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.3123591210
Short name T349
Test name
Test status
Simulation time 166795298 ps
CPU time 2.45 seconds
Started Mar 31 01:26:06 PM PDT 24
Finished Mar 31 01:26:09 PM PDT 24
Peak memory 222584 kb
Host smart-ea1ad639-4ae8-4f2b-9a76-5eca594ecce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123591210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.3123591210
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.608084539
Short name T347
Test name
Test status
Simulation time 3456936808 ps
CPU time 13.91 seconds
Started Mar 31 01:26:08 PM PDT 24
Finished Mar 31 01:26:22 PM PDT 24
Peak memory 230264 kb
Host smart-55da088d-8a56-4b3d-9ebd-67ddf2198d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608084539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.608084539
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.1382153621
Short name T69
Test name
Test status
Simulation time 5629022045 ps
CPU time 15.13 seconds
Started Mar 31 01:26:04 PM PDT 24
Finished Mar 31 01:26:19 PM PDT 24
Peak memory 232896 kb
Host smart-de477623-0ae5-47cf-83cb-bc3b836c4de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382153621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.1382153621
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.1818361491
Short name T545
Test name
Test status
Simulation time 3142461848 ps
CPU time 6.09 seconds
Started Mar 31 01:26:07 PM PDT 24
Finished Mar 31 01:26:14 PM PDT 24
Peak memory 223804 kb
Host smart-e40fd35e-9be7-4158-b1d1-4ba8ad9d3172
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1818361491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.1818361491
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.350654343
Short name T38
Test name
Test status
Simulation time 208578203 ps
CPU time 0.92 seconds
Started Mar 31 01:26:06 PM PDT 24
Finished Mar 31 01:26:07 PM PDT 24
Peak memory 207144 kb
Host smart-270fa63b-c1fd-4b33-bbef-0ddcec9c2636
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350654343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stres
s_all.350654343
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.1465872168
Short name T383
Test name
Test status
Simulation time 9930433951 ps
CPU time 27.05 seconds
Started Mar 31 01:26:12 PM PDT 24
Finished Mar 31 01:26:39 PM PDT 24
Peak memory 216880 kb
Host smart-284f1d4f-2f13-4e42-88ab-c88f069d7fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465872168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.1465872168
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.3702073878
Short name T462
Test name
Test status
Simulation time 53185609260 ps
CPU time 9.99 seconds
Started Mar 31 01:26:04 PM PDT 24
Finished Mar 31 01:26:14 PM PDT 24
Peak memory 216800 kb
Host smart-5a04cdd4-7cda-4b87-92f1-c90e3bd663ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702073878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.3702073878
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.2620519221
Short name T398
Test name
Test status
Simulation time 63834964 ps
CPU time 0.93 seconds
Started Mar 31 01:26:04 PM PDT 24
Finished Mar 31 01:26:05 PM PDT 24
Peak memory 208324 kb
Host smart-cced2b41-cd5e-46aa-be8f-d8dba6f3822d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620519221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.2620519221
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.3214885445
Short name T59
Test name
Test status
Simulation time 127069482 ps
CPU time 0.79 seconds
Started Mar 31 01:26:05 PM PDT 24
Finished Mar 31 01:26:06 PM PDT 24
Peak memory 206212 kb
Host smart-25266df0-4062-4df5-a824-1711130b01f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214885445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.3214885445
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.2626485126
Short name T35
Test name
Test status
Simulation time 32219897 ps
CPU time 0.72 seconds
Started Mar 31 01:26:11 PM PDT 24
Finished Mar 31 01:26:12 PM PDT 24
Peak memory 206272 kb
Host smart-4300b86e-aae5-488a-aa55-f6c1c5153438
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626485126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
2626485126
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.3160499229
Short name T28
Test name
Test status
Simulation time 40623817 ps
CPU time 2.68 seconds
Started Mar 31 01:26:14 PM PDT 24
Finished Mar 31 01:26:17 PM PDT 24
Peak memory 223332 kb
Host smart-e57c03cc-5211-47ac-8527-132c4b4b8336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160499229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.3160499229
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.1151250860
Short name T432
Test name
Test status
Simulation time 109989978 ps
CPU time 0.79 seconds
Started Mar 31 01:26:13 PM PDT 24
Finished Mar 31 01:26:14 PM PDT 24
Peak memory 206064 kb
Host smart-bde194ad-1b85-43f6-b509-7a807630bd2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151250860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.1151250860
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.2271368479
Short name T609
Test name
Test status
Simulation time 3681403715 ps
CPU time 51.63 seconds
Started Mar 31 01:26:14 PM PDT 24
Finished Mar 31 01:27:06 PM PDT 24
Peak memory 249608 kb
Host smart-d0652585-364b-4d02-9cf7-da43fbf4e5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271368479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.2271368479
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.2631414955
Short name T205
Test name
Test status
Simulation time 755824800 ps
CPU time 9.11 seconds
Started Mar 31 01:26:13 PM PDT 24
Finished Mar 31 01:26:22 PM PDT 24
Peak memory 219248 kb
Host smart-2d76233e-47ad-4b62-b81d-26730178d493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631414955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.2631414955
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.3839123299
Short name T441
Test name
Test status
Simulation time 1387406866 ps
CPU time 5.64 seconds
Started Mar 31 01:26:11 PM PDT 24
Finished Mar 31 01:26:17 PM PDT 24
Peak memory 219612 kb
Host smart-1dbe3007-db8f-4ecc-bda5-b069e786c50d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3839123299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.3839123299
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.2925215998
Short name T483
Test name
Test status
Simulation time 839020738 ps
CPU time 6.76 seconds
Started Mar 31 01:26:07 PM PDT 24
Finished Mar 31 01:26:14 PM PDT 24
Peak memory 216748 kb
Host smart-bd629df6-ed38-4542-b7fb-030b516e832b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925215998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.2925215998
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.901270011
Short name T611
Test name
Test status
Simulation time 3989396195 ps
CPU time 12.31 seconds
Started Mar 31 01:26:08 PM PDT 24
Finished Mar 31 01:26:21 PM PDT 24
Peak memory 216804 kb
Host smart-13d3f111-9596-43cc-b43b-63baa3e61f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901270011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.901270011
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.2457517317
Short name T670
Test name
Test status
Simulation time 221138530 ps
CPU time 3.6 seconds
Started Mar 31 01:26:06 PM PDT 24
Finished Mar 31 01:26:10 PM PDT 24
Peak memory 216628 kb
Host smart-e646c47d-9b15-468a-9898-91dc40d45747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457517317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.2457517317
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.20113795
Short name T687
Test name
Test status
Simulation time 213706349 ps
CPU time 0.78 seconds
Started Mar 31 01:26:10 PM PDT 24
Finished Mar 31 01:26:11 PM PDT 24
Peak memory 206256 kb
Host smart-8304dfe4-9588-40dc-8559-62f5aadb57e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20113795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.20113795
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.2726257632
Short name T32
Test name
Test status
Simulation time 999677092 ps
CPU time 9.48 seconds
Started Mar 31 01:26:11 PM PDT 24
Finished Mar 31 01:26:21 PM PDT 24
Peak memory 221028 kb
Host smart-c92f20f4-17f9-4878-a3f9-9b8f54b2628c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726257632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.2726257632
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.157506658
Short name T661
Test name
Test status
Simulation time 14158322 ps
CPU time 0.71 seconds
Started Mar 31 01:23:48 PM PDT 24
Finished Mar 31 01:23:49 PM PDT 24
Peak memory 205948 kb
Host smart-08adc7ad-6798-4d00-a459-eb2b36ae2969
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157506658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.157506658
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.578139807
Short name T426
Test name
Test status
Simulation time 81956155 ps
CPU time 0.79 seconds
Started Mar 31 01:23:49 PM PDT 24
Finished Mar 31 01:23:50 PM PDT 24
Peak memory 207172 kb
Host smart-d0746ae0-f561-43f6-b8bc-aa3a3841a906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578139807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.578139807
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.2405045221
Short name T357
Test name
Test status
Simulation time 8800787643 ps
CPU time 24.09 seconds
Started Mar 31 01:23:47 PM PDT 24
Finished Mar 31 01:24:11 PM PDT 24
Peak memory 236276 kb
Host smart-4fb878fd-a802-4055-8fef-a93244927e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405045221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.2405045221
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.677155526
Short name T225
Test name
Test status
Simulation time 774987385 ps
CPU time 6.75 seconds
Started Mar 31 01:23:46 PM PDT 24
Finished Mar 31 01:23:54 PM PDT 24
Peak memory 218972 kb
Host smart-c893b37b-2514-49b6-b0b3-6efb81683663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677155526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.677155526
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.105697406
Short name T273
Test name
Test status
Simulation time 2498226557 ps
CPU time 6.32 seconds
Started Mar 31 01:23:44 PM PDT 24
Finished Mar 31 01:23:50 PM PDT 24
Peak memory 217204 kb
Host smart-548ba055-7d88-43ab-ae6a-2a85bc9180d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105697406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.105697406
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_ram_cfg.3275884652
Short name T420
Test name
Test status
Simulation time 16782573 ps
CPU time 0.78 seconds
Started Mar 31 01:23:46 PM PDT 24
Finished Mar 31 01:23:48 PM PDT 24
Peak memory 216672 kb
Host smart-2b76ef53-bc5a-4a33-ade8-6e427b9cc3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275884652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_ram_cfg.3275884652
Directory /workspace/5.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.3931583002
Short name T479
Test name
Test status
Simulation time 75921642 ps
CPU time 3.48 seconds
Started Mar 31 01:23:52 PM PDT 24
Finished Mar 31 01:23:55 PM PDT 24
Peak memory 220812 kb
Host smart-67445ddd-9f15-4978-9a57-ab113b0c1698
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3931583002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.3931583002
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.891421052
Short name T533
Test name
Test status
Simulation time 21037658933 ps
CPU time 34.84 seconds
Started Mar 31 01:23:43 PM PDT 24
Finished Mar 31 01:24:18 PM PDT 24
Peak memory 221336 kb
Host smart-7485f5d8-b2d2-4bf1-b2aa-e79c95044cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891421052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.891421052
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.952812097
Short name T177
Test name
Test status
Simulation time 1494614137 ps
CPU time 7.51 seconds
Started Mar 31 01:23:49 PM PDT 24
Finished Mar 31 01:23:57 PM PDT 24
Peak memory 216712 kb
Host smart-ba572214-cf3b-4722-ba31-b277982e06a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952812097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.952812097
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.599059510
Short name T498
Test name
Test status
Simulation time 1813170911 ps
CPU time 21.33 seconds
Started Mar 31 01:23:40 PM PDT 24
Finished Mar 31 01:24:01 PM PDT 24
Peak memory 216756 kb
Host smart-e747a9a5-ac89-4204-ad5d-a11a15a910fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599059510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.599059510
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.2780108673
Short name T422
Test name
Test status
Simulation time 141601218 ps
CPU time 0.91 seconds
Started Mar 31 01:23:45 PM PDT 24
Finished Mar 31 01:23:46 PM PDT 24
Peak memory 207288 kb
Host smart-cb43f2eb-5fdb-4b60-b3e1-8dfaed9c1cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780108673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.2780108673
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.2417766249
Short name T203
Test name
Test status
Simulation time 525170683 ps
CPU time 3.72 seconds
Started Mar 31 01:23:52 PM PDT 24
Finished Mar 31 01:23:56 PM PDT 24
Peak memory 223716 kb
Host smart-5cb3b4d8-796f-45fc-82a9-3ff73d7e369d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417766249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.2417766249
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.3880123586
Short name T449
Test name
Test status
Simulation time 11702296 ps
CPU time 0.76 seconds
Started Mar 31 01:23:51 PM PDT 24
Finished Mar 31 01:23:52 PM PDT 24
Peak memory 205964 kb
Host smart-21571cd3-59c0-45cb-be30-6202d65e6152
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880123586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.3
880123586
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.3201016099
Short name T448
Test name
Test status
Simulation time 18140401 ps
CPU time 0.8 seconds
Started Mar 31 01:23:49 PM PDT 24
Finished Mar 31 01:23:50 PM PDT 24
Peak memory 207424 kb
Host smart-27107c13-9b49-4287-8f35-c55038107e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201016099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.3201016099
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.2125786805
Short name T306
Test name
Test status
Simulation time 12552957788 ps
CPU time 60.91 seconds
Started Mar 31 01:23:49 PM PDT 24
Finished Mar 31 01:24:50 PM PDT 24
Peak memory 233284 kb
Host smart-53b38d58-916b-44d3-9f86-9f0b7d5cbf39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125786805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.2125786805
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.3998879285
Short name T338
Test name
Test status
Simulation time 7351480913 ps
CPU time 12.41 seconds
Started Mar 31 01:23:49 PM PDT 24
Finished Mar 31 01:24:01 PM PDT 24
Peak memory 224960 kb
Host smart-3ad086cf-40d7-483a-96af-bc42d92d678a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998879285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.3998879285
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.2880761659
Short name T195
Test name
Test status
Simulation time 16739728202 ps
CPU time 49.54 seconds
Started Mar 31 01:23:52 PM PDT 24
Finished Mar 31 01:24:41 PM PDT 24
Peak memory 238608 kb
Host smart-087930f0-0427-4482-bae0-c93a20cb146e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880761659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.2880761659
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_ram_cfg.3542570903
Short name T430
Test name
Test status
Simulation time 32036644 ps
CPU time 0.78 seconds
Started Mar 31 01:23:49 PM PDT 24
Finished Mar 31 01:23:50 PM PDT 24
Peak memory 216768 kb
Host smart-642cebf2-ff73-4d8e-a1f3-6d7853f158b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542570903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_ram_cfg.3542570903
Directory /workspace/6.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.1966940827
Short name T93
Test name
Test status
Simulation time 1730564320 ps
CPU time 9.43 seconds
Started Mar 31 01:23:52 PM PDT 24
Finished Mar 31 01:24:01 PM PDT 24
Peak memory 219208 kb
Host smart-97d2d752-4c04-48ca-9de5-e419fae8c9b6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1966940827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.1966940827
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.2913886385
Short name T520
Test name
Test status
Simulation time 109542299 ps
CPU time 1.12 seconds
Started Mar 31 01:23:50 PM PDT 24
Finished Mar 31 01:23:51 PM PDT 24
Peak memory 207436 kb
Host smart-458c3522-54d7-43f4-a176-020a6a084aaf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913886385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.2913886385
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.914464533
Short name T377
Test name
Test status
Simulation time 3336635005 ps
CPU time 22.79 seconds
Started Mar 31 01:23:49 PM PDT 24
Finished Mar 31 01:24:11 PM PDT 24
Peak memory 216684 kb
Host smart-5c4cc021-15ae-47cd-a2a0-2493b723a7d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914464533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.914464533
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.21910
Short name T649
Test name
Test status
Simulation time 12775024921 ps
CPU time 14.27 seconds
Started Mar 31 01:23:49 PM PDT 24
Finished Mar 31 01:24:03 PM PDT 24
Peak memory 216804 kb
Host smart-3420b5e9-b090-4f33-bf54-2e3b8bb89885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.21910
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.2374166430
Short name T465
Test name
Test status
Simulation time 63750281 ps
CPU time 1.12 seconds
Started Mar 31 01:23:59 PM PDT 24
Finished Mar 31 01:24:00 PM PDT 24
Peak memory 208300 kb
Host smart-fe8374dc-68e0-422a-87ee-4829fdf2d8d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374166430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.2374166430
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.3795136476
Short name T588
Test name
Test status
Simulation time 76562587 ps
CPU time 1.03 seconds
Started Mar 31 01:23:47 PM PDT 24
Finished Mar 31 01:23:49 PM PDT 24
Peak memory 207204 kb
Host smart-02c08ae0-9d58-4862-ac71-f1630b35217c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795136476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.3795136476
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.1294183511
Short name T248
Test name
Test status
Simulation time 14786528334 ps
CPU time 12.65 seconds
Started Mar 31 01:23:47 PM PDT 24
Finished Mar 31 01:24:00 PM PDT 24
Peak memory 219160 kb
Host smart-f8524704-dd2c-40f4-bff8-e3d0982c9f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294183511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.1294183511
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.4022354832
Short name T637
Test name
Test status
Simulation time 65551331 ps
CPU time 0.79 seconds
Started Mar 31 01:23:54 PM PDT 24
Finished Mar 31 01:23:55 PM PDT 24
Peak memory 205968 kb
Host smart-58f7096c-7556-45e5-9e2d-cc4ce67ac9cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022354832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.4
022354832
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.3372684974
Short name T429
Test name
Test status
Simulation time 39038037 ps
CPU time 0.74 seconds
Started Mar 31 01:23:58 PM PDT 24
Finished Mar 31 01:23:59 PM PDT 24
Peak memory 206392 kb
Host smart-830643f9-a98c-4a71-85a6-948dbb3ce5db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372684974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.3372684974
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.933006430
Short name T126
Test name
Test status
Simulation time 71807838718 ps
CPU time 161.51 seconds
Started Mar 31 01:24:01 PM PDT 24
Finished Mar 31 01:26:43 PM PDT 24
Peak memory 236288 kb
Host smart-d6197a32-c86f-4c8a-8192-968d08537542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933006430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.933006430
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.2604265270
Short name T78
Test name
Test status
Simulation time 2280300668 ps
CPU time 3.96 seconds
Started Mar 31 01:24:00 PM PDT 24
Finished Mar 31 01:24:04 PM PDT 24
Peak memory 223392 kb
Host smart-5f3adefa-282c-4e40-8e14-545eef83ee9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604265270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.2604265270
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.759942543
Short name T232
Test name
Test status
Simulation time 4649661229 ps
CPU time 9.02 seconds
Started Mar 31 01:23:59 PM PDT 24
Finished Mar 31 01:24:08 PM PDT 24
Peak memory 240728 kb
Host smart-4a396503-b072-4433-9bf8-37ae113761d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759942543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.759942543
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_ram_cfg.52969526
Short name T631
Test name
Test status
Simulation time 18720784 ps
CPU time 0.77 seconds
Started Mar 31 01:23:47 PM PDT 24
Finished Mar 31 01:23:48 PM PDT 24
Peak memory 216724 kb
Host smart-c46f915a-e45e-4d7d-a945-23dd373ae5a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52969526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_ram_cfg.52969526
Directory /workspace/7.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.1003284088
Short name T447
Test name
Test status
Simulation time 1677251473 ps
CPU time 8.53 seconds
Started Mar 31 01:24:08 PM PDT 24
Finished Mar 31 01:24:17 PM PDT 24
Peak memory 223400 kb
Host smart-4fc7f3a8-af08-4da9-9da4-8094cc8f4007
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1003284088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.1003284088
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.4250823920
Short name T362
Test name
Test status
Simulation time 54008272 ps
CPU time 1.24 seconds
Started Mar 31 01:24:02 PM PDT 24
Finished Mar 31 01:24:03 PM PDT 24
Peak memory 207768 kb
Host smart-11fa6e19-2569-4b45-b49d-0947fc533859
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250823920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.4250823920
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.1634474963
Short name T381
Test name
Test status
Simulation time 3174314832 ps
CPU time 16.31 seconds
Started Mar 31 01:24:04 PM PDT 24
Finished Mar 31 01:24:21 PM PDT 24
Peak memory 216952 kb
Host smart-60539733-f3cf-4978-95d6-c4f97ad5d915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634474963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.1634474963
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.4017106338
Short name T402
Test name
Test status
Simulation time 15826983833 ps
CPU time 16.52 seconds
Started Mar 31 01:23:55 PM PDT 24
Finished Mar 31 01:24:11 PM PDT 24
Peak memory 216796 kb
Host smart-782a2699-9e75-4b53-96c8-9165bfe594c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017106338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.4017106338
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.3289938188
Short name T524
Test name
Test status
Simulation time 483705995 ps
CPU time 7.74 seconds
Started Mar 31 01:23:57 PM PDT 24
Finished Mar 31 01:24:05 PM PDT 24
Peak memory 216876 kb
Host smart-6ed457f4-9d15-4f53-8644-58e3ab6f32b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289938188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.3289938188
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.2000800754
Short name T701
Test name
Test status
Simulation time 1041693695 ps
CPU time 0.89 seconds
Started Mar 31 01:24:06 PM PDT 24
Finished Mar 31 01:24:07 PM PDT 24
Peak memory 206152 kb
Host smart-40f32b06-cddb-4ea8-887f-2f743274b987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000800754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.2000800754
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.840434964
Short name T277
Test name
Test status
Simulation time 4574255601 ps
CPU time 4.69 seconds
Started Mar 31 01:24:06 PM PDT 24
Finished Mar 31 01:24:11 PM PDT 24
Peak memory 225012 kb
Host smart-02881f4c-5773-4878-bd7e-febbc4908aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840434964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.840434964
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.3871121100
Short name T587
Test name
Test status
Simulation time 17276047 ps
CPU time 0.76 seconds
Started Mar 31 01:24:04 PM PDT 24
Finished Mar 31 01:24:05 PM PDT 24
Peak memory 205436 kb
Host smart-900b0ba7-68d0-495d-b88a-491b07cadf3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871121100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.3
871121100
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.198158815
Short name T470
Test name
Test status
Simulation time 62477126 ps
CPU time 0.83 seconds
Started Mar 31 01:24:04 PM PDT 24
Finished Mar 31 01:24:05 PM PDT 24
Peak memory 207460 kb
Host smart-7695de1f-4cfe-492f-93de-ab92cb948c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198158815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.198158815
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_intercept.1918735084
Short name T281
Test name
Test status
Simulation time 4320392517 ps
CPU time 11.24 seconds
Started Mar 31 01:24:01 PM PDT 24
Finished Mar 31 01:24:12 PM PDT 24
Peak memory 225076 kb
Host smart-fcd68dfe-ec70-4839-8505-d89425990f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918735084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.1918735084
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_ram_cfg.624274103
Short name T47
Test name
Test status
Simulation time 62591830 ps
CPU time 0.74 seconds
Started Mar 31 01:24:04 PM PDT 24
Finished Mar 31 01:24:06 PM PDT 24
Peak memory 216768 kb
Host smart-37921694-abb0-452a-9d97-b889561390d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624274103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_ram_cfg.624274103
Directory /workspace/8.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.534664881
Short name T172
Test name
Test status
Simulation time 874292191 ps
CPU time 11.49 seconds
Started Mar 31 01:24:04 PM PDT 24
Finished Mar 31 01:24:16 PM PDT 24
Peak memory 219744 kb
Host smart-89d3cf9c-e875-47d7-8fe4-d38809678402
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=534664881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direc
t.534664881
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.3453173932
Short name T46
Test name
Test status
Simulation time 78414745 ps
CPU time 0.92 seconds
Started Mar 31 01:24:05 PM PDT 24
Finished Mar 31 01:24:07 PM PDT 24
Peak memory 206332 kb
Host smart-ded4fd3a-e76c-4738-bc4a-6fadbc0ddf55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453173932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.3453173932
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.1451646050
Short name T684
Test name
Test status
Simulation time 928533721 ps
CPU time 8.05 seconds
Started Mar 31 01:24:08 PM PDT 24
Finished Mar 31 01:24:17 PM PDT 24
Peak memory 216832 kb
Host smart-f5d75a4e-75a6-41a6-ba8c-1bcc7398012a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451646050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.1451646050
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.2934249292
Short name T697
Test name
Test status
Simulation time 1983758464 ps
CPU time 7.15 seconds
Started Mar 31 01:24:02 PM PDT 24
Finished Mar 31 01:24:09 PM PDT 24
Peak memory 216696 kb
Host smart-359cba12-6d1d-46f1-adb8-3ca2d38a856e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934249292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.2934249292
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.177087230
Short name T23
Test name
Test status
Simulation time 15267449 ps
CPU time 0.93 seconds
Started Mar 31 01:24:01 PM PDT 24
Finished Mar 31 01:24:03 PM PDT 24
Peak memory 207584 kb
Host smart-5f88fab8-56c1-43c4-b7d5-e72a19ae3d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177087230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.177087230
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.652089384
Short name T573
Test name
Test status
Simulation time 136295463 ps
CPU time 1.12 seconds
Started Mar 31 01:24:00 PM PDT 24
Finished Mar 31 01:24:02 PM PDT 24
Peak memory 207224 kb
Host smart-2c41c218-f044-4958-b048-7be50a130bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652089384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.652089384
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.3498896533
Short name T707
Test name
Test status
Simulation time 158329292 ps
CPU time 3.2 seconds
Started Mar 31 01:24:04 PM PDT 24
Finished Mar 31 01:24:08 PM PDT 24
Peak memory 223696 kb
Host smart-f10ed3ce-123f-44a5-8acf-b042cf6216c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498896533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.3498896533
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.1151464358
Short name T499
Test name
Test status
Simulation time 12882514 ps
CPU time 0.76 seconds
Started Mar 31 01:24:05 PM PDT 24
Finished Mar 31 01:24:07 PM PDT 24
Peak memory 205400 kb
Host smart-f4b85cc8-95d0-480c-a9b9-04b120754ef5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151464358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.1
151464358
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.322548439
Short name T31
Test name
Test status
Simulation time 1530395552 ps
CPU time 7.34 seconds
Started Mar 31 01:24:03 PM PDT 24
Finished Mar 31 01:24:11 PM PDT 24
Peak memory 219192 kb
Host smart-cd214a31-7c0b-49ba-9194-d2180d956817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322548439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.322548439
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.2964539603
Short name T667
Test name
Test status
Simulation time 20531120 ps
CPU time 0.78 seconds
Started Mar 31 01:24:05 PM PDT 24
Finished Mar 31 01:24:06 PM PDT 24
Peak memory 206092 kb
Host smart-43df7076-da72-4be4-bc5f-0fc336e60613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964539603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.2964539603
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.3700524327
Short name T174
Test name
Test status
Simulation time 8383739927 ps
CPU time 55.12 seconds
Started Mar 31 01:24:01 PM PDT 24
Finished Mar 31 01:24:57 PM PDT 24
Peak memory 249608 kb
Host smart-8a824811-b2a2-4900-aadd-5248f2b6a2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700524327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.3700524327
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.3380455086
Short name T188
Test name
Test status
Simulation time 438251340 ps
CPU time 6.51 seconds
Started Mar 31 01:24:08 PM PDT 24
Finished Mar 31 01:24:15 PM PDT 24
Peak memory 220536 kb
Host smart-7e28ba3e-7403-4911-b24a-c42d158eb212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380455086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.3380455086
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.58836004
Short name T100
Test name
Test status
Simulation time 2590714411 ps
CPU time 37.62 seconds
Started Mar 31 01:24:08 PM PDT 24
Finished Mar 31 01:24:46 PM PDT 24
Peak memory 233032 kb
Host smart-87411af4-3eba-4be9-911a-615d9d701823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58836004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.58836004
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.2958707045
Short name T79
Test name
Test status
Simulation time 94382417 ps
CPU time 2.94 seconds
Started Mar 31 01:24:08 PM PDT 24
Finished Mar 31 01:24:11 PM PDT 24
Peak memory 223192 kb
Host smart-929d4b95-e530-4599-acaf-f82b53c2fbed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958707045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.2958707045
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_ram_cfg.2425160164
Short name T436
Test name
Test status
Simulation time 33211128 ps
CPU time 0.78 seconds
Started Mar 31 01:24:04 PM PDT 24
Finished Mar 31 01:24:05 PM PDT 24
Peak memory 216696 kb
Host smart-c9048690-9fb9-4110-8745-461ec8e048bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425160164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_ram_cfg.2425160164
Directory /workspace/9.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.3947310537
Short name T672
Test name
Test status
Simulation time 1230413336 ps
CPU time 4.39 seconds
Started Mar 31 01:24:01 PM PDT 24
Finished Mar 31 01:24:06 PM PDT 24
Peak memory 220884 kb
Host smart-a85ad3d0-abc8-4101-ac74-c9c01895febf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3947310537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.3947310537
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.2474531636
Short name T612
Test name
Test status
Simulation time 9087951748 ps
CPU time 30.73 seconds
Started Mar 31 01:24:08 PM PDT 24
Finished Mar 31 01:24:39 PM PDT 24
Peak memory 216796 kb
Host smart-9d01edf2-36b7-4346-a273-2c89bd555b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474531636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.2474531636
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.1892294987
Short name T488
Test name
Test status
Simulation time 8607607841 ps
CPU time 23.01 seconds
Started Mar 31 01:24:02 PM PDT 24
Finished Mar 31 01:24:26 PM PDT 24
Peak memory 216788 kb
Host smart-43f15356-1a74-4636-b471-968c5716f80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892294987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.1892294987
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.781192623
Short name T569
Test name
Test status
Simulation time 85786022 ps
CPU time 3.73 seconds
Started Mar 31 01:24:06 PM PDT 24
Finished Mar 31 01:24:10 PM PDT 24
Peak memory 216688 kb
Host smart-69249fa5-9f40-4d8c-8d9e-e4797c765824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781192623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.781192623
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.3421057525
Short name T475
Test name
Test status
Simulation time 102389791 ps
CPU time 0.85 seconds
Started Mar 31 01:24:04 PM PDT 24
Finished Mar 31 01:24:05 PM PDT 24
Peak memory 206228 kb
Host smart-e4a012dd-4e0d-4bf9-9406-6c351d37e717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421057525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.3421057525
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.1222778123
Short name T230
Test name
Test status
Simulation time 2373971595 ps
CPU time 9.88 seconds
Started Mar 31 01:24:01 PM PDT 24
Finished Mar 31 01:24:11 PM PDT 24
Peak memory 219132 kb
Host smart-52937a3e-d9d5-4d10-8a92-d71ca4d5c9fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222778123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.1222778123
Directory /workspace/9.spi_device_upload/latest
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