Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1544963	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1704180

1

T1

27

T3

1

T7

13384

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2552338	1			T1	77		T2	1		T3	55
values[0x0]	347165	1			T1	17		T7	466		T8	95
values[0x1]	349640	1			T1	14		T7	455		T8	104

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1173519	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2075624

1

T1

50

T2

1

T3

21

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9914	1			T1	1		T7	135		T4	27
valid_sources[0x01]	10460	1			T7	145		T4	24		T5	10
valid_sources[0x02]	10594	1			T3	3		T7	89		T8	7
valid_sources[0x03]	10448	1			T7	112		T4	22		T16	2
valid_sources[0x04]	10093	1			T7	71		T4	30		T16	1
valid_sources[0x05]	10560	1			T7	148		T4	30		T16	2
valid_sources[0x06]	10901	1			T1	2		T7	107		T4	20
valid_sources[0x07]	11964	1			T7	81		T4	20		T16	3
valid_sources[0x08]	9946	1			T7	100		T8	24		T4	21
valid_sources[0x09]	12711	1			T7	104		T8	1		T4	23
valid_sources[0x0a]	10250	1			T7	73		T4	26		T16	2
valid_sources[0x0b]	10356	1			T7	88		T4	25		T16	2
valid_sources[0x0c]	20162	1			T1	3		T3	2		T7	85
valid_sources[0x0d]	11882	1			T7	119		T8	53		T4	21
valid_sources[0x0e]	11498	1			T3	1		T7	87		T4	25
valid_sources[0x0f]	19745	1			T1	1		T7	103		T8	5
valid_sources[0x10]	11362	1			T7	126		T4	19		T5	2
valid_sources[0x11]	11355	1			T7	161		T8	4		T4	23
valid_sources[0x12]	10533	1			T7	47		T4	28		T16	2
valid_sources[0x13]	9670	1			T7	66		T8	10		T4	29
valid_sources[0x14]	22864	1			T7	69		T4	17		T16	3
valid_sources[0x15]	12915	1			T1	3		T7	112		T8	1
valid_sources[0x16]	12643	1			T3	2		T7	86		T4	19
valid_sources[0x17]	11364	1			T1	3		T7	99		T4	23
valid_sources[0x18]	11673	1			T7	130		T4	25		T16	2
valid_sources[0x19]	14153	1			T7	131		T4	10		T9	1
valid_sources[0x1a]	11679	1			T7	81		T4	22		T16	2
valid_sources[0x1b]	10421	1			T1	1		T7	85		T4	37
valid_sources[0x1c]	9808	1			T1	1		T3	1		T7	84
valid_sources[0x1d]	11355	1			T7	106		T4	19		T16	2
valid_sources[0x1e]	16559	1			T1	2		T7	107		T4	26
valid_sources[0x1f]	13284	1			T7	79		T4	20		T16	2
valid_sources[0x20]	9824	1			T1	5		T7	174		T4	21
valid_sources[0x21]	10711	1			T1	1		T7	76		T4	25
valid_sources[0x22]	12908	1			T7	106		T4	38		T16	3
valid_sources[0x23]	12113	1			T7	79		T4	23		T5	5
valid_sources[0x24]	9971	1			T7	81		T4	27		T16	4
valid_sources[0x25]	11577	1			T1	4		T7	122		T4	19
valid_sources[0x26]	10021	1			T7	112		T4	36		T16	6
valid_sources[0x27]	10900	1			T7	124		T4	29		T16	1
valid_sources[0x28]	10127	1			T1	1		T7	90		T4	12
valid_sources[0x29]	12107	1			T7	119		T4	33		T16	1
valid_sources[0x2a]	11176	1			T7	119		T4	40		T16	4
valid_sources[0x2b]	10933	1			T7	98		T4	29		T5	10
valid_sources[0x2c]	9619	1			T7	99		T4	13		T16	4
valid_sources[0x2d]	10477	1			T7	83		T4	27		T16	2
valid_sources[0x2e]	12881	1			T7	149		T8	51		T4	30
valid_sources[0x2f]	16551	1			T7	87		T4	34		T16	2
valid_sources[0x30]	12764	1			T3	3		T7	70		T4	29
valid_sources[0x31]	19447	1			T7	82		T4	23		T16	1
valid_sources[0x32]	12321	1			T7	90		T4	27		T16	2
valid_sources[0x33]	10555	1			T1	3		T7	88		T4	23
valid_sources[0x34]	10701	1			T7	104		T4	26		T16	7
valid_sources[0x35]	9879	1			T3	2		T7	56		T4	14
valid_sources[0x36]	13779	1			T7	96		T4	19		T9	7
valid_sources[0x37]	12154	1			T1	2		T7	92		T4	29
valid_sources[0x38]	9762	1			T7	79		T4	24		T5	1
valid_sources[0x39]	10304	1			T7	100		T4	32		T16	3
valid_sources[0x3a]	11046	1			T7	89		T8	2		T4	26
valid_sources[0x3b]	10661	1			T7	79		T4	21		T16	1
valid_sources[0x3c]	10415	1			T1	1		T7	104		T4	19
valid_sources[0x3d]	13466	1			T3	2		T7	109		T4	29
valid_sources[0x3e]	13622	1			T1	1		T7	82		T4	16
valid_sources[0x3f]	11681	1			T7	89		T4	19		T15	868
valid_sources[0x40]	9587	1			T7	84		T4	21		T16	2
valid_sources[0x41]	10857	1			T1	1		T7	70		T4	18
valid_sources[0x42]	10724	1			T1	1		T7	77		T4	19
valid_sources[0x43]	10903	1			T7	126		T4	30		T16	3
valid_sources[0x44]	11121	1			T1	1		T7	76		T4	21
valid_sources[0x45]	9879	1			T1	2		T7	88		T4	23
valid_sources[0x46]	10858	1			T7	93		T4	26		T16	1
valid_sources[0x47]	11599	1			T7	90		T4	25		T16	1
valid_sources[0x48]	11390	1			T7	142		T4	28		T16	1
valid_sources[0x49]	13100	1			T7	65		T4	26		T16	3
valid_sources[0x4a]	10188	1			T1	2		T7	123		T8	11
valid_sources[0x4b]	10737	1			T7	141		T4	23		T16	1
valid_sources[0x4c]	10586	1			T3	2		T7	103		T4	17
valid_sources[0x4d]	9729	1			T1	1		T3	2		T7	81
valid_sources[0x4e]	9445	1			T7	79		T4	30		T16	1
valid_sources[0x4f]	9164	1			T7	96		T4	22		T16	1
valid_sources[0x50]	11751	1			T7	70		T4	18		T5	3
valid_sources[0x51]	11529	1			T7	110		T4	24		T16	1
valid_sources[0x52]	14175	1			T1	4		T7	116		T4	14
valid_sources[0x53]	10339	1			T7	99		T8	11		T4	34
valid_sources[0x54]	12687	1			T7	116		T8	5		T4	30
valid_sources[0x55]	10675	1			T7	99		T4	30		T5	3
valid_sources[0x56]	11111	1			T7	120		T4	13		T16	3
valid_sources[0x57]	10266	1			T3	2		T7	86		T4	28
valid_sources[0x58]	17776	1			T7	122		T8	86		T4	24
valid_sources[0x59]	36766	1			T7	90		T8	36		T4	18
valid_sources[0x5a]	27226	1			T7	144		T4	18		T16	5
valid_sources[0x5b]	13011	1			T1	1		T7	67		T4	27
valid_sources[0x5c]	11433	1			T7	65		T4	23		T16	1
valid_sources[0x5d]	10267	1			T7	97		T4	39		T16	5
valid_sources[0x5e]	9991	1			T1	1		T7	93		T4	24
valid_sources[0x5f]	12560	1			T7	91		T4	28		T16	1
valid_sources[0x60]	9675	1			T7	91		T4	12		T5	3
valid_sources[0x61]	10555	1			T7	146		T4	27		T16	1
valid_sources[0x62]	10327	1			T1	3		T7	96		T4	26
valid_sources[0x63]	9621	1			T1	1		T7	169		T4	19
valid_sources[0x64]	9430	1			T7	94		T4	17		T16	2
valid_sources[0x65]	11706	1			T7	129		T8	5		T4	29
valid_sources[0x66]	10002	1			T7	161		T4	16		T16	1
valid_sources[0x67]	10626	1			T1	1		T7	148		T4	28
valid_sources[0x68]	22889	1			T7	118		T4	30		T16	3
valid_sources[0x69]	10516	1			T7	68		T4	21		T16	1
valid_sources[0x6a]	12402	1			T7	106		T4	28		T16	6
valid_sources[0x6b]	11953	1			T1	3		T7	66		T4	33
valid_sources[0x6c]	12140	1			T1	1		T7	69		T4	25
valid_sources[0x6d]	10407	1			T7	78		T4	29		T16	1
valid_sources[0x6e]	19614	1			T7	116		T4	22		T16	2
valid_sources[0x6f]	12630	1			T7	124		T4	32		T16	3
valid_sources[0x70]	10847	1			T7	95		T4	16		T16	3
valid_sources[0x71]	10401	1			T7	111		T4	19		T16	2
valid_sources[0x72]	11013	1			T7	94		T4	34		T16	1
valid_sources[0x73]	10322	1			T7	98		T4	25		T16	3
valid_sources[0x74]	22747	1			T7	89		T4	23		T5	2
valid_sources[0x75]	9347	1			T3	2		T7	88		T4	29
valid_sources[0x76]	11374	1			T1	3		T7	77		T8	14
valid_sources[0x77]	11017	1			T7	96		T4	28		T16	1
valid_sources[0x78]	10766	1			T1	2		T7	99		T4	23
valid_sources[0x79]	10796	1			T7	102		T4	26		T16	3
valid_sources[0x7a]	9722	1			T1	1		T7	78		T4	25
valid_sources[0x7b]	11090	1			T7	106		T8	17		T4	27
valid_sources[0x7c]	11571	1			T7	97		T4	17		T5	8
valid_sources[0x7d]	11245	1			T7	153		T4	25		T5	9
valid_sources[0x7e]	10252	1			T1	3		T7	93		T4	25
valid_sources[0x7f]	9693	1			T7	81		T4	23		T16	2
valid_sources[0x80]	13576	1			T1	1		T7	80		T4	28

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1077510

1

T1

16

T3

1

T7

12472

values[0x0]

all_enables

biggest_size

315988

1

T1

8

T7

466

T8

48

values[0x1]

all_enables

biggest_size

310682

1

T1

3

T7

446

T8

41