Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1567385

1

T1

81

T2

1

T3

54

full_word

1705455

1

T1

27

T3

1

T7

13384

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3272430	1			T1	108		T2	1		T3	55
auto[TlIntgErrCmd]	142	1			T35	8		T36	8		T37	10
auto[TlIntgErrData]	137	1			T35	6		T36	6		T37	10
auto[TlIntgErrBoth]	131	1			T35	6		T36	6		T37	10

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2555755

1

T1

77

T2

1

T3

55

auto[1]

717085

1

T1

31

T7

921

T8

199

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1477789	1			T1	61		T2	1		T3	54
auto[TlIntgErrNone]	partial	auto[1]	89226	1			T1	20		T7	9		T8	110
auto[TlIntgErrNone]	full_word	auto[0]	1077782	1			T1	16		T3	1		T7	12472
auto[TlIntgErrNone]	full_word	auto[1]	627633	1			T1	11		T7	912		T8	89
auto[TlIntgErrCmd]	partial	auto[0]	54	1			T35	4		T36	3		T37	4
auto[TlIntgErrCmd]	partial	auto[1]	77	1			T35	4		T36	4		T37	6
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T133	1		T364	1		T365	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T36	1		T135	1		T362	1
auto[TlIntgErrData]	partial	auto[0]	61	1			T35	2		T36	4		T37	4
auto[TlIntgErrData]	partial	auto[1]	62	1			T35	4		T36	2		T37	5
auto[TlIntgErrData]	full_word	auto[0]	8	1			T37	1		T132	1		T362	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T366	1		T363	1		T367	1
auto[TlIntgErrBoth]	partial	auto[0]	53	1			T35	2		T36	1		T37	3
auto[TlIntgErrBoth]	partial	auto[1]	63	1			T35	3		T36	5		T37	6
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T35	1		T162	1		T365	1
auto[TlIntgErrBoth]	full_word	auto[1]	11	1			T37	1		T132	2		T133	1