Unified Coverage Report :: Module :: prim_generic_ram_1r1w

Module : prim_generic_ram_1r1w

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T8,T4,T15
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_ram_1r1w

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	164632580	593525	0	0
gen_wmask[1].MaskCheckPortA_A	164632580	593525	0	0
gen_wmask[2].MaskCheckPortA_A	164632580	593525	0	0
gen_wmask[3].MaskCheckPortA_A	164632580	593525	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164632580	593525	0	0
T4	137467	832	0	0
T5	26290	832	0	0
T6	304239	832	0	0
T7	592315	832	0	0
T8	13710	558	0	0
T9	37122	832	0	0
T10	10406	832	0	0
T11	0	832	0	0
T15	17890	149	0	0
T16	165515	0	0	0
T17	221469	0	0	0
T18	832506	7980	0	0
T19	0	139	0	0
T59	0	125	0	0
T60	0	4	0	0
T61	0	1987	0	0
T62	0	295	0	0
T63	0	2257	0	0
T64	0	2627	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164632580	593525	0	0
T4	137467	832	0	0
T5	26290	832	0	0
T6	304239	832	0	0
T7	592315	832	0	0
T8	13710	558	0	0
T9	37122	832	0	0
T10	10406	832	0	0
T11	0	832	0	0
T15	17890	149	0	0
T16	165515	0	0	0
T17	221469	0	0	0
T18	832506	7980	0	0
T19	0	139	0	0
T59	0	125	0	0
T60	0	4	0	0
T61	0	1987	0	0
T62	0	295	0	0
T63	0	2257	0	0
T64	0	2627	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164632580	593525	0	0
T4	137467	832	0	0
T5	26290	832	0	0
T6	304239	832	0	0
T7	592315	832	0	0
T8	13710	558	0	0
T9	37122	832	0	0
T10	10406	832	0	0
T11	0	832	0	0
T15	17890	149	0	0
T16	165515	0	0	0
T17	221469	0	0	0
T18	832506	7980	0	0
T19	0	139	0	0
T59	0	125	0	0
T60	0	4	0	0
T61	0	1987	0	0
T62	0	295	0	0
T63	0	2257	0	0
T64	0	2627	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164632580	593525	0	0
T4	137467	832	0	0
T5	26290	832	0	0
T6	304239	832	0	0
T7	592315	832	0	0
T8	13710	558	0	0
T9	37122	832	0	0
T10	10406	832	0	0
T11	0	832	0	0
T15	17890	149	0	0
T16	165515	0	0	0
T17	221469	0	0	0
T18	832506	7980	0	0
T19	0	139	0	0
T59	0	125	0	0
T60	0	4	0	0
T61	0	1987	0	0
T62	0	295	0	0
T63	0	2257	0	0
T64	0	2627	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			==> MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T8,T4,T15
0	Covered	T7,T8,T4

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	124652365	422770	0	0
gen_wmask[1].MaskCheckPortA_A	124652365	422770	0	0
gen_wmask[2].MaskCheckPortA_A	124652365	422770	0	0
gen_wmask[3].MaskCheckPortA_A	124652365	422770	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124652365	422770	0	0
T4	115090	832	0	0
T5	11391	832	0	0
T6	135429	832	0	0
T7	592315	832	0	0
T8	5750	47	0	0
T9	14615	832	0	0
T10	0	832	0	0
T11	0	832	0	0
T15	15570	29	0	0
T16	78587	0	0	0
T17	120712	0	0	0
T18	623955	2650	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124652365	422770	0	0
T4	115090	832	0	0
T5	11391	832	0	0
T6	135429	832	0	0
T7	592315	832	0	0
T8	5750	47	0	0
T9	14615	832	0	0
T10	0	832	0	0
T11	0	832	0	0
T15	15570	29	0	0
T16	78587	0	0	0
T17	120712	0	0	0
T18	623955	2650	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124652365	422770	0	0
T4	115090	832	0	0
T5	11391	832	0	0
T6	135429	832	0	0
T7	592315	832	0	0
T8	5750	47	0	0
T9	14615	832	0	0
T10	0	832	0	0
T11	0	832	0	0
T15	15570	29	0	0
T16	78587	0	0	0
T17	120712	0	0	0
T18	623955	2650	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124652365	422770	0	0
T4	115090	832	0	0
T5	11391	832	0	0
T6	135429	832	0	0
T7	592315	832	0	0
T8	5750	47	0	0
T9	14615	832	0	0
T10	0	832	0	0
T11	0	832	0	0
T15	15570	29	0	0
T16	78587	0	0	0
T17	120712	0	0	0
T18	623955	2650	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T8,T15,T18
0	Covered	T7,T8,T4

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T8,T15,T18
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	39980215	170755	0	0
gen_wmask[1].MaskCheckPortA_A	39980215	170755	0	0
gen_wmask[2].MaskCheckPortA_A	39980215	170755	0	0
gen_wmask[3].MaskCheckPortA_A	39980215	170755	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39980215	170755	0	0
T4	22377	0	0	0
T5	14899	0	0	0
T6	168810	0	0	0
T8	7960	511	0	0
T9	22507	0	0	0
T10	10406	0	0	0
T15	2320	120	0	0
T16	86928	0	0	0
T17	100757	0	0	0
T18	208551	5330	0	0
T19	0	139	0	0
T59	0	125	0	0
T60	0	4	0	0
T61	0	1987	0	0
T62	0	295	0	0
T63	0	2257	0	0
T64	0	2627	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39980215	170755	0	0
T4	22377	0	0	0
T5	14899	0	0	0
T6	168810	0	0	0
T8	7960	511	0	0
T9	22507	0	0	0
T10	10406	0	0	0
T15	2320	120	0	0
T16	86928	0	0	0
T17	100757	0	0	0
T18	208551	5330	0	0
T19	0	139	0	0
T59	0	125	0	0
T60	0	4	0	0
T61	0	1987	0	0
T62	0	295	0	0
T63	0	2257	0	0
T64	0	2627	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39980215	170755	0	0
T4	22377	0	0	0
T5	14899	0	0	0
T6	168810	0	0	0
T8	7960	511	0	0
T9	22507	0	0	0
T10	10406	0	0	0
T15	2320	120	0	0
T16	86928	0	0	0
T17	100757	0	0	0
T18	208551	5330	0	0
T19	0	139	0	0
T59	0	125	0	0
T60	0	4	0	0
T61	0	1987	0	0
T62	0	295	0	0
T63	0	2257	0	0
T64	0	2627	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39980215	170755	0	0
T4	22377	0	0	0
T5	14899	0	0	0
T6	168810	0	0	0
T8	7960	511	0	0
T9	22507	0	0	0
T10	10406	0	0	0
T15	2320	120	0	0
T16	86928	0	0	0
T17	100757	0	0	0
T18	208551	5330	0	0
T19	0	139	0	0
T59	0	125	0	0
T60	0	4	0	0
T61	0	1987	0	0
T62	0	295	0	0
T63	0	2257	0	0
T64	0	2627	0	0