Unified Coverage Report :: Module Instance :: tb.dut.u_tlul2sram_ingress.u_sramreqfifo

Module Instance : tb.dut.u_tlul2sram_ingress.u_sramreqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.62	100.00	62.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.64	95.00	72.22			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.01	94.03	70.69			83.33	100.00	u_tlul2sram_ingress

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Module Instance : tb.dut.u_tlul2sram_ingress.u_rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.32	95.00	77.27			85.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.01	94.03	70.69			83.33	100.00	u_tlul2sram_ingress

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Module Instance : tb.dut.u_sys_sram_arbiter.u_req_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.06	100.00	56.25			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.36	100.00	75.00			94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	93.64	100.00	90.00			90.91

Module Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_sramreqfifo

	Total	Covered	Percent
Conditions	16	10	62.50
Logical	16	10	62.50
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T15,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T8,T15,T18

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T8,T15,T18

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T8,T15,T18

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T8,T15,T18
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T8,T15,T18

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T8,T15,T18
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	124652365	44215	0	0
DepthKnown_A	124652365	124593879	0	0
RvalidKnown_A	124652365	124593879	0	0
WreadyKnown_A	124652365	124593879	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	124652365	44215	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124652365	44215	0	0
T4	115090	0	0	0
T5	11391	0	0	0
T6	135429	0	0	0
T8	5750	130	0	0
T9	14615	0	0	0
T10	79752	0	0	0
T15	15570	32	0	0
T16	78587	0	0	0
T17	120712	0	0	0
T18	623955	1376	0	0
T19	0	36	0	0
T59	0	32	0	0
T60	0	1	0	0
T61	0	515	0	0
T62	0	75	0	0
T63	0	585	0	0
T64	0	677	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124652365	124593879	0	0
T1	3596	3309	0	0
T2	1340	1265	0	0
T3	1627	1576	0	0
T4	115090	115008	0	0
T5	11391	11304	0	0
T7	592315	592226	0	0
T8	5750	5652	0	0
T9	14615	14548	0	0
T15	15570	15488	0	0
T16	78587	78487	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124652365	124593879	0	0
T1	3596	3309	0	0
T2	1340	1265	0	0
T3	1627	1576	0	0
T4	115090	115008	0	0
T5	11391	11304	0	0
T7	592315	592226	0	0
T8	5750	5652	0	0
T9	14615	14548	0	0
T15	15570	15488	0	0
T16	78587	78487	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124652365	124593879	0	0
T1	3596	3309	0	0
T2	1340	1265	0	0
T3	1627	1576	0	0
T4	115090	115008	0	0
T5	11391	11304	0	0
T7	592315	592226	0	0
T8	5750	5652	0	0
T9	14615	14548	0	0
T15	15570	15488	0	0
T16	78587	78487	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	124652365	44215	0	0
T4	115090	0	0	0
T5	11391	0	0	0
T6	135429	0	0	0
T8	5750	130	0	0
T9	14615	0	0	0
T10	79752	0	0	0
T15	15570	32	0	0
T16	78587	0	0	0
T17	120712	0	0	0
T18	623955	1376	0	0
T19	0	36	0	0
T59	0	32	0	0
T60	0	1	0	0
T61	0	515	0	0
T62	0	75	0	0
T63	0	585	0	0
T64	0	677	0	0

Line Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_rspfifo

	Total	Covered	Percent
Conditions	24	18	75.00
Logical	24	18	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T70,T71
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T8,T15,T18

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T8,T15,T18

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T15,T59,T60
1	1	0	Not Covered
1	1	1	Covered	T8,T15,T18

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T15,T18

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T15,T18

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T15,T70,T71
1	0	Covered	T8,T15,T18
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T8,T15,T18
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T15,T18
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T8,T15,T18

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T8,T15,T18
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	124652365	83575	0	0
DepthKnown_A	124652365	124593879	0	0
RvalidKnown_A	124652365	124593879	0	0
WreadyKnown_A	124652365	124593879	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	124652365	83575	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124652365	83575	0	0
T4	115090	0	0	0
T5	11391	0	0	0
T6	135429	0	0	0
T8	5750	130	0	0
T9	14615	0	0	0
T10	79752	0	0	0
T15	15570	151	0	0
T16	78587	0	0	0
T17	120712	0	0	0
T18	623955	1376	0	0
T19	0	36	0	0
T59	0	32	0	0
T60	0	1	0	0
T61	0	515	0	0
T62	0	75	0	0
T63	0	585	0	0
T64	0	677	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124652365	124593879	0	0
T1	3596	3309	0	0
T2	1340	1265	0	0
T3	1627	1576	0	0
T4	115090	115008	0	0
T5	11391	11304	0	0
T7	592315	592226	0	0
T8	5750	5652	0	0
T9	14615	14548	0	0
T15	15570	15488	0	0
T16	78587	78487	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124652365	124593879	0	0
T1	3596	3309	0	0
T2	1340	1265	0	0
T3	1627	1576	0	0
T4	115090	115008	0	0
T5	11391	11304	0	0
T7	592315	592226	0	0
T8	5750	5652	0	0
T9	14615	14548	0	0
T15	15570	15488	0	0
T16	78587	78487	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124652365	124593879	0	0
T1	3596	3309	0	0
T2	1340	1265	0	0
T3	1627	1576	0	0
T4	115090	115008	0	0
T5	11391	11304	0	0
T7	592315	592226	0	0
T8	5750	5652	0	0
T9	14615	14548	0	0
T15	15570	15488	0	0
T16	78587	78487	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	124652365	83575	0	0
T4	115090	0	0	0
T5	11391	0	0	0
T6	135429	0	0	0
T8	5750	130	0	0
T9	14615	0	0	0
T10	79752	0	0	0
T15	15570	151	0	0
T16	78587	0	0	0
T17	120712	0	0	0
T18	623955	1376	0	0
T19	0	36	0	0
T59	0	32	0	0
T60	0	1	0	0
T61	0	515	0	0
T62	0	75	0	0
T63	0	585	0	0
T64	0	677	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.u_req_fifo

	Total	Covered	Percent
Conditions	16	9	56.25
Logical	16	9	56.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T8,T15,T18

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T8,T15,T18

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T8,T15,T18

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T8,T15,T18
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T8,T15,T18

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T8,T15,T18
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.u_req_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	124652365	44215	0	0
DepthKnown_A	124652365	124593879	0	0
RvalidKnown_A	124652365	124593879	0	0
WreadyKnown_A	124652365	124593879	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	124652365	44215	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124652365	44215	0	0
T4	115090	0	0	0
T5	11391	0	0	0
T6	135429	0	0	0
T8	5750	130	0	0
T9	14615	0	0	0
T10	79752	0	0	0
T15	15570	32	0	0
T16	78587	0	0	0
T17	120712	0	0	0
T18	623955	1376	0	0
T19	0	36	0	0
T59	0	32	0	0
T60	0	1	0	0
T61	0	515	0	0
T62	0	75	0	0
T63	0	585	0	0
T64	0	677	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124652365	124593879	0	0
T1	3596	3309	0	0
T2	1340	1265	0	0
T3	1627	1576	0	0
T4	115090	115008	0	0
T5	11391	11304	0	0
T7	592315	592226	0	0
T8	5750	5652	0	0
T9	14615	14548	0	0
T15	15570	15488	0	0
T16	78587	78487	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124652365	124593879	0	0
T1	3596	3309	0	0
T2	1340	1265	0	0
T3	1627	1576	0	0
T4	115090	115008	0	0
T5	11391	11304	0	0
T7	592315	592226	0	0
T8	5750	5652	0	0
T9	14615	14548	0	0
T15	15570	15488	0	0
T16	78587	78487	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124652365	124593879	0	0
T1	3596	3309	0	0
T2	1340	1265	0	0
T3	1627	1576	0	0
T4	115090	115008	0	0
T5	11391	11304	0	0
T7	592315	592226	0	0
T8	5750	5652	0	0
T9	14615	14548	0	0
T15	15570	15488	0	0
T16	78587	78487	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	124652365	44215	0	0
T4	115090	0	0	0
T5	11391	0	0	0
T6	135429	0	0	0
T8	5750	130	0	0
T9	14615	0	0	0
T10	79752	0	0	0
T15	15570	32	0	0
T16	78587	0	0	0
T17	120712	0	0	0
T18	623955	1376	0	0
T19	0	36	0	0
T59	0	32	0	0
T60	0	1	0	0
T61	0	515	0	0
T62	0	75	0	0
T63	0	585	0	0
T64	0	677	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	127013807	3650233	0	0
DepthKnown_A	127013807	126909757	0	0
RvalidKnown_A	127013807	126909757	0	0
WreadyKnown_A	127013807	126909757	0	0
gen_passthru_fifo.paramCheckPass	854	854	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127013807	3650233	0	0
T1	3596	108	0	0
T2	1340	1	0	0
T3	1627	55	0	0
T4	115090	6266	0	0
T5	11391	1724	0	0
T7	592315	25932	0	0
T8	5750	610	0	0
T9	14615	1331	0	0
T15	15570	868	0	0
T16	78587	456	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127013807	126909757	0	0
T1	3596	3309	0	0
T2	1340	1265	0	0
T3	1627	1576	0	0
T4	115090	115008	0	0
T5	11391	11304	0	0
T7	592315	592226	0	0
T8	5750	5652	0	0
T9	14615	14548	0	0
T15	15570	15488	0	0
T16	78587	78487	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127013807	126909757	0	0
T1	3596	3309	0	0
T2	1340	1265	0	0
T3	1627	1576	0	0
T4	115090	115008	0	0
T5	11391	11304	0	0
T7	592315	592226	0	0
T8	5750	5652	0	0
T9	14615	14548	0	0
T15	15570	15488	0	0
T16	78587	78487	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127013807	126909757	0	0
T1	3596	3309	0	0
T2	1340	1265	0	0
T3	1627	1576	0	0
T4	115090	115008	0	0
T5	11391	11304	0	0
T7	592315	592226	0	0
T8	5750	5652	0	0
T9	14615	14548	0	0
T15	15570	15488	0	0
T16	78587	78487	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	854	854	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	127013807	5646678	0	0
DepthKnown_A	127013807	126909757	0	0
RvalidKnown_A	127013807	126909757	0	0
WreadyKnown_A	127013807	126909757	0	0
gen_passthru_fifo.paramCheckPass	854	854	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127013807	5646678	0	0
T1	3596	108	0	0
T2	1340	1	0	0
T3	1627	55	0	0
T4	115090	6265	0	0
T5	11391	892	0	0
T7	592315	25932	0	0
T8	5750	610	0	0
T9	14615	1329	0	0
T15	15570	3798	0	0
T16	78587	456	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127013807	126909757	0	0
T1	3596	3309	0	0
T2	1340	1265	0	0
T3	1627	1576	0	0
T4	115090	115008	0	0
T5	11391	11304	0	0
T7	592315	592226	0	0
T8	5750	5652	0	0
T9	14615	14548	0	0
T15	15570	15488	0	0
T16	78587	78487	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127013807	126909757	0	0
T1	3596	3309	0	0
T2	1340	1265	0	0
T3	1627	1576	0	0
T4	115090	115008	0	0
T5	11391	11304	0	0
T7	592315	592226	0	0
T8	5750	5652	0	0
T9	14615	14548	0	0
T15	15570	15488	0	0
T16	78587	78487	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127013807	126909757	0	0
T1	3596	3309	0	0
T2	1340	1265	0	0
T3	1627	1576	0	0
T4	115090	115008	0	0
T5	11391	11304	0	0
T7	592315	592226	0	0
T8	5750	5652	0	0
T9	14615	14548	0	0
T15	15570	15488	0	0
T16	78587	78487	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	854	854	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	127013807	567344	0	0
DepthKnown_A	127013807	126909757	0	0
RvalidKnown_A	127013807	126909757	0	0
WreadyKnown_A	127013807	126909757	0	0
gen_passthru_fifo.paramCheckPass	854	854	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127013807	567344	0	0
T4	115090	832	0	0
T5	11391	1663	0	0
T6	135429	1663	0	0
T7	592315	832	0	0
T8	5750	0	0	0
T9	14615	832	0	0
T10	0	832	0	0
T11	0	832	0	0
T12	0	1663	0	0
T13	0	832	0	0
T14	0	832	0	0
T15	15570	0	0	0
T16	78587	0	0	0
T17	120712	0	0	0
T18	623955	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127013807	126909757	0	0
T1	3596	3309	0	0
T2	1340	1265	0	0
T3	1627	1576	0	0
T4	115090	115008	0	0
T5	11391	11304	0	0
T7	592315	592226	0	0
T8	5750	5652	0	0
T9	14615	14548	0	0
T15	15570	15488	0	0
T16	78587	78487	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127013807	126909757	0	0
T1	3596	3309	0	0
T2	1340	1265	0	0
T3	1627	1576	0	0
T4	115090	115008	0	0
T5	11391	11304	0	0
T7	592315	592226	0	0
T8	5750	5652	0	0
T9	14615	14548	0	0
T15	15570	15488	0	0
T16	78587	78487	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127013807	126909757	0	0
T1	3596	3309	0	0
T2	1340	1265	0	0
T3	1627	1576	0	0
T4	115090	115008	0	0
T5	11391	11304	0	0
T7	592315	592226	0	0
T8	5750	5652	0	0
T9	14615	14548	0	0
T15	15570	15488	0	0
T16	78587	78487	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	854	854	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	127013807	489501	0	0
DepthKnown_A	127013807	126909757	0	0
RvalidKnown_A	127013807	126909757	0	0
WreadyKnown_A	127013807	126909757	0	0
gen_passthru_fifo.paramCheckPass	854	854	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127013807	489501	0	0
T4	115090	832	0	0
T5	11391	832	0	0
T6	135429	832	0	0
T7	592315	832	0	0
T8	5750	0	0	0
T9	14615	832	0	0
T10	0	832	0	0
T11	0	832	0	0
T12	0	832	0	0
T13	0	2521	0	0
T14	0	832	0	0
T15	15570	0	0	0
T16	78587	0	0	0
T17	120712	0	0	0
T18	623955	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127013807	126909757	0	0
T1	3596	3309	0	0
T2	1340	1265	0	0
T3	1627	1576	0	0
T4	115090	115008	0	0
T5	11391	11304	0	0
T7	592315	592226	0	0
T8	5750	5652	0	0
T9	14615	14548	0	0
T15	15570	15488	0	0
T16	78587	78487	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127013807	126909757	0	0
T1	3596	3309	0	0
T2	1340	1265	0	0
T3	1627	1576	0	0
T4	115090	115008	0	0
T5	11391	11304	0	0
T7	592315	592226	0	0
T8	5750	5652	0	0
T9	14615	14548	0	0
T15	15570	15488	0	0
T16	78587	78487	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127013807	126909757	0	0
T1	3596	3309	0	0
T2	1340	1265	0	0
T3	1627	1576	0	0
T4	115090	115008	0	0
T5	11391	11304	0	0
T7	592315	592226	0	0
T8	5750	5652	0	0
T9	14615	14548	0	0
T15	15570	15488	0	0
T16	78587	78487	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	854	854	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	127013807	49979	0	0
DepthKnown_A	127013807	126909757	0	0
RvalidKnown_A	127013807	126909757	0	0
WreadyKnown_A	127013807	126909757	0	0
gen_passthru_fifo.paramCheckPass	854	854	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127013807	49979	0	0
T4	115090	0	0	0
T5	11391	0	0	0
T6	135429	0	0	0
T8	5750	130	0	0
T9	14615	0	0	0
T10	79752	0	0	0
T15	15570	32	0	0
T16	78587	0	0	0
T17	120712	0	0	0
T18	623955	1376	0	0
T19	0	36	0	0
T59	0	32	0	0
T60	0	1	0	0
T61	0	515	0	0
T62	0	75	0	0
T63	0	585	0	0
T64	0	677	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127013807	126909757	0	0
T1	3596	3309	0	0
T2	1340	1265	0	0
T3	1627	1576	0	0
T4	115090	115008	0	0
T5	11391	11304	0	0
T7	592315	592226	0	0
T8	5750	5652	0	0
T9	14615	14548	0	0
T15	15570	15488	0	0
T16	78587	78487	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127013807	126909757	0	0
T1	3596	3309	0	0
T2	1340	1265	0	0
T3	1627	1576	0	0
T4	115090	115008	0	0
T5	11391	11304	0	0
T7	592315	592226	0	0
T8	5750	5652	0	0
T9	14615	14548	0	0
T15	15570	15488	0	0
T16	78587	78487	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127013807	126909757	0	0
T1	3596	3309	0	0
T2	1340	1265	0	0
T3	1627	1576	0	0
T4	115090	115008	0	0
T5	11391	11304	0	0
T7	592315	592226	0	0
T8	5750	5652	0	0
T9	14615	14548	0	0
T15	15570	15488	0	0
T16	78587	78487	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	854	854	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	127013807	92330	0	0
DepthKnown_A	127013807	126909757	0	0
RvalidKnown_A	127013807	126909757	0	0
WreadyKnown_A	127013807	126909757	0	0
gen_passthru_fifo.paramCheckPass	854	854	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127013807	92330	0	0
T4	115090	0	0	0
T5	11391	0	0	0
T6	135429	0	0	0
T8	5750	130	0	0
T9	14615	0	0	0
T10	79752	0	0	0
T15	15570	151	0	0
T16	78587	0	0	0
T17	120712	0	0	0
T18	623955	1376	0	0
T19	0	36	0	0
T59	0	32	0	0
T60	0	1	0	0
T61	0	515	0	0
T62	0	75	0	0
T63	0	585	0	0
T64	0	677	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127013807	126909757	0	0
T1	3596	3309	0	0
T2	1340	1265	0	0
T3	1627	1576	0	0
T4	115090	115008	0	0
T5	11391	11304	0	0
T7	592315	592226	0	0
T8	5750	5652	0	0
T9	14615	14548	0	0
T15	15570	15488	0	0
T16	78587	78487	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127013807	126909757	0	0
T1	3596	3309	0	0
T2	1340	1265	0	0
T3	1627	1576	0	0
T4	115090	115008	0	0
T5	11391	11304	0	0
T7	592315	592226	0	0
T8	5750	5652	0	0
T9	14615	14548	0	0
T15	15570	15488	0	0
T16	78587	78487	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127013807	126909757	0	0
T1	3596	3309	0	0
T2	1340	1265	0	0
T3	1627	1576	0	0
T4	115090	115008	0	0
T5	11391	11304	0	0
T7	592315	592226	0	0
T8	5750	5652	0	0
T9	14615	14548	0	0
T15	15570	15488	0	0
T16	78587	78487	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	854	854	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0