Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	127013807	3020000	0	0
DepthKnown_A	127013807	126909757	0	0
RvalidKnown_A	127013807	126909757	0	0
WreadyKnown_A	127013807	126909757	0	0
gen_passthru_fifo.paramCheckPass	854	854	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127013807	3020000	0	0
T1	3596	108	0	0
T2	1340	1	0	0
T3	1627	55	0	0
T4	115090	5434	0	0
T5	11391	60	0	0
T7	592315	25100	0	0
T8	5750	480	0	0
T9	14615	499	0	0
T15	15570	836	0	0
T16	78587	456	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127013807	126909757	0	0
T1	3596	3309	0	0
T2	1340	1265	0	0
T3	1627	1576	0	0
T4	115090	115008	0	0
T5	11391	11304	0	0
T7	592315	592226	0	0
T8	5750	5652	0	0
T9	14615	14548	0	0
T15	15570	15488	0	0
T16	78587	78487	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127013807	126909757	0	0
T1	3596	3309	0	0
T2	1340	1265	0	0
T3	1627	1576	0	0
T4	115090	115008	0	0
T5	11391	11304	0	0
T7	592315	592226	0	0
T8	5750	5652	0	0
T9	14615	14548	0	0
T15	15570	15488	0	0
T16	78587	78487	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127013807	126909757	0	0
T1	3596	3309	0	0
T2	1340	1265	0	0
T3	1627	1576	0	0
T4	115090	115008	0	0
T5	11391	11304	0	0
T7	592315	592226	0	0
T8	5750	5652	0	0
T9	14615	14548	0	0
T15	15570	15488	0	0
T16	78587	78487	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	854	854	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	127013807	5064847	0	0
DepthKnown_A	127013807	126909757	0	0
RvalidKnown_A	127013807	126909757	0	0
WreadyKnown_A	127013807	126909757	0	0
gen_passthru_fifo.paramCheckPass	854	854	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127013807	5064847	0	0
T1	3596	108	0	0
T2	1340	1	0	0
T3	1627	55	0	0
T4	115090	5433	0	0
T5	11391	60	0	0
T7	592315	25100	0	0
T8	5750	480	0	0
T9	14615	497	0	0
T15	15570	3647	0	0
T16	78587	456	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127013807	126909757	0	0
T1	3596	3309	0	0
T2	1340	1265	0	0
T3	1627	1576	0	0
T4	115090	115008	0	0
T5	11391	11304	0	0
T7	592315	592226	0	0
T8	5750	5652	0	0
T9	14615	14548	0	0
T15	15570	15488	0	0
T16	78587	78487	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127013807	126909757	0	0
T1	3596	3309	0	0
T2	1340	1265	0	0
T3	1627	1576	0	0
T4	115090	115008	0	0
T5	11391	11304	0	0
T7	592315	592226	0	0
T8	5750	5652	0	0
T9	14615	14548	0	0
T15	15570	15488	0	0
T16	78587	78487	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127013807	126909757	0	0
T1	3596	3309	0	0
T2	1340	1265	0	0
T3	1627	1576	0	0
T4	115090	115008	0	0
T5	11391	11304	0	0
T7	592315	592226	0	0
T8	5750	5652	0	0
T9	14615	14548	0	0
T15	15570	15488	0	0
T16	78587	78487	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	854	854	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0