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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.00 97.49 92.77 98.61 80.85 95.83 90.96 87.49


Total test records in report: 854
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html
T142 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2443662374 Apr 02 12:28:21 PM PDT 24 Apr 02 12:28:23 PM PDT 24 217268774 ps
T766 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1275825976 Apr 02 12:28:00 PM PDT 24 Apr 02 12:28:01 PM PDT 24 53227876 ps
T767 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1593560418 Apr 02 12:28:19 PM PDT 24 Apr 02 12:28:27 PM PDT 24 1216443131 ps
T768 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2075085050 Apr 02 12:27:56 PM PDT 24 Apr 02 12:27:57 PM PDT 24 50921482 ps
T143 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1479479550 Apr 02 12:27:56 PM PDT 24 Apr 02 12:27:58 PM PDT 24 70428203 ps
T769 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1336325402 Apr 02 12:28:00 PM PDT 24 Apr 02 12:28:01 PM PDT 24 18273999 ps
T770 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1848959661 Apr 02 12:28:00 PM PDT 24 Apr 02 12:28:01 PM PDT 24 16523102 ps
T771 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3557539965 Apr 02 12:27:58 PM PDT 24 Apr 02 12:28:01 PM PDT 24 594551553 ps
T772 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2087042181 Apr 02 12:27:56 PM PDT 24 Apr 02 12:27:56 PM PDT 24 36209163 ps
T129 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3618653561 Apr 02 12:28:28 PM PDT 24 Apr 02 12:28:33 PM PDT 24 165609198 ps
T773 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3384693813 Apr 02 12:27:55 PM PDT 24 Apr 02 12:27:55 PM PDT 24 13887634 ps
T774 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3394367924 Apr 02 12:28:01 PM PDT 24 Apr 02 12:28:03 PM PDT 24 540678159 ps
T125 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.847119241 Apr 02 12:27:57 PM PDT 24 Apr 02 12:28:02 PM PDT 24 158835866 ps
T775 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.868210377 Apr 02 12:28:22 PM PDT 24 Apr 02 12:28:23 PM PDT 24 20456045 ps
T776 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.954259103 Apr 02 12:27:59 PM PDT 24 Apr 02 12:28:00 PM PDT 24 103655646 ps
T777 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.343358520 Apr 02 12:27:54 PM PDT 24 Apr 02 12:27:55 PM PDT 24 39266576 ps
T144 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3836721520 Apr 02 12:27:58 PM PDT 24 Apr 02 12:28:33 PM PDT 24 772979127 ps
T127 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1092620488 Apr 02 12:28:44 PM PDT 24 Apr 02 12:28:48 PM PDT 24 704555876 ps
T778 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.92254351 Apr 02 12:28:22 PM PDT 24 Apr 02 12:28:23 PM PDT 24 34163819 ps
T779 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3112653809 Apr 02 12:27:57 PM PDT 24 Apr 02 12:27:58 PM PDT 24 31555411 ps
T780 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2309081630 Apr 02 12:27:54 PM PDT 24 Apr 02 12:27:56 PM PDT 24 212078763 ps
T781 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.463905979 Apr 02 12:27:57 PM PDT 24 Apr 02 12:27:58 PM PDT 24 33103055 ps
T782 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3071430266 Apr 02 12:27:53 PM PDT 24 Apr 02 12:27:54 PM PDT 24 42750668 ps
T145 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.4157367080 Apr 02 12:27:54 PM PDT 24 Apr 02 12:27:56 PM PDT 24 112863288 ps
T783 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3895155656 Apr 02 12:27:57 PM PDT 24 Apr 02 12:27:58 PM PDT 24 15663618 ps
T784 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.3287066085 Apr 02 12:27:57 PM PDT 24 Apr 02 12:27:58 PM PDT 24 54085717 ps
T785 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.510051225 Apr 02 12:28:26 PM PDT 24 Apr 02 12:28:30 PM PDT 24 832231112 ps
T786 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1319922965 Apr 02 12:28:20 PM PDT 24 Apr 02 12:28:24 PM PDT 24 58685084 ps
T126 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1105023458 Apr 02 12:27:54 PM PDT 24 Apr 02 12:27:57 PM PDT 24 94986688 ps
T787 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2554577061 Apr 02 12:27:52 PM PDT 24 Apr 02 12:27:56 PM PDT 24 251376128 ps
T788 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2346647512 Apr 02 12:28:18 PM PDT 24 Apr 02 12:28:22 PM PDT 24 353728627 ps
T789 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.4133859130 Apr 02 12:27:56 PM PDT 24 Apr 02 12:27:57 PM PDT 24 14005061 ps
T790 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3507044993 Apr 02 12:28:06 PM PDT 24 Apr 02 12:28:08 PM PDT 24 50187812 ps
T791 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2139196124 Apr 02 12:27:57 PM PDT 24 Apr 02 12:27:59 PM PDT 24 59722508 ps
T792 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1802077427 Apr 02 12:27:55 PM PDT 24 Apr 02 12:28:00 PM PDT 24 165437906 ps
T793 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1881525084 Apr 02 12:28:30 PM PDT 24 Apr 02 12:28:32 PM PDT 24 55348498 ps
T794 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3413647446 Apr 02 12:27:54 PM PDT 24 Apr 02 12:27:56 PM PDT 24 23392791 ps
T795 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1574141267 Apr 02 12:28:00 PM PDT 24 Apr 02 12:28:03 PM PDT 24 45205394 ps
T796 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.880027429 Apr 02 12:28:01 PM PDT 24 Apr 02 12:28:05 PM PDT 24 112000304 ps
T797 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.856230544 Apr 02 12:27:53 PM PDT 24 Apr 02 12:28:15 PM PDT 24 370305137 ps
T798 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2713095379 Apr 02 12:27:58 PM PDT 24 Apr 02 12:27:59 PM PDT 24 23526124 ps
T799 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.831963966 Apr 02 12:27:52 PM PDT 24 Apr 02 12:27:53 PM PDT 24 11198765 ps
T800 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.4192346570 Apr 02 12:28:17 PM PDT 24 Apr 02 12:28:19 PM PDT 24 29169175 ps
T801 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.638644501 Apr 02 12:28:17 PM PDT 24 Apr 02 12:28:33 PM PDT 24 577515158 ps
T146 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2519494752 Apr 02 12:28:19 PM PDT 24 Apr 02 12:28:21 PM PDT 24 18794579 ps
T147 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3488735003 Apr 02 12:27:57 PM PDT 24 Apr 02 12:27:59 PM PDT 24 148599176 ps
T802 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1015422057 Apr 02 12:27:56 PM PDT 24 Apr 02 12:28:28 PM PDT 24 9940913795 ps
T803 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1798806238 Apr 02 12:27:55 PM PDT 24 Apr 02 12:27:57 PM PDT 24 132960887 ps
T365 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2254552235 Apr 02 12:27:53 PM PDT 24 Apr 02 12:28:15 PM PDT 24 829027206 ps
T804 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.990528193 Apr 02 12:27:51 PM PDT 24 Apr 02 12:27:53 PM PDT 24 213347015 ps
T805 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1879213622 Apr 02 12:27:53 PM PDT 24 Apr 02 12:27:56 PM PDT 24 420159129 ps
T806 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2496094248 Apr 02 12:28:26 PM PDT 24 Apr 02 12:28:29 PM PDT 24 242056667 ps
T807 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2398204205 Apr 02 12:27:56 PM PDT 24 Apr 02 12:27:59 PM PDT 24 89232032 ps
T808 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2682558658 Apr 02 12:27:55 PM PDT 24 Apr 02 12:27:57 PM PDT 24 146513174 ps
T809 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3128274799 Apr 02 12:27:54 PM PDT 24 Apr 02 12:27:56 PM PDT 24 35526154 ps
T810 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1162794486 Apr 02 12:27:55 PM PDT 24 Apr 02 12:27:56 PM PDT 24 70619269 ps
T811 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.694141253 Apr 02 12:27:55 PM PDT 24 Apr 02 12:28:10 PM PDT 24 934174074 ps
T812 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1364517659 Apr 02 12:27:57 PM PDT 24 Apr 02 12:27:58 PM PDT 24 19727886 ps
T361 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2863959221 Apr 02 12:27:53 PM PDT 24 Apr 02 12:27:56 PM PDT 24 358458855 ps
T813 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2519850288 Apr 02 12:27:58 PM PDT 24 Apr 02 12:28:01 PM PDT 24 552126893 ps
T814 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3538274137 Apr 02 12:27:54 PM PDT 24 Apr 02 12:27:55 PM PDT 24 81332212 ps
T815 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3718880803 Apr 02 12:27:50 PM PDT 24 Apr 02 12:28:04 PM PDT 24 835214576 ps
T363 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3795236790 Apr 02 12:28:20 PM PDT 24 Apr 02 12:28:42 PM PDT 24 835371268 ps
T816 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.264694600 Apr 02 12:27:52 PM PDT 24 Apr 02 12:27:52 PM PDT 24 33195401 ps
T817 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3351972453 Apr 02 12:27:57 PM PDT 24 Apr 02 12:27:58 PM PDT 24 21991426 ps
T818 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1163861612 Apr 02 12:27:53 PM PDT 24 Apr 02 12:27:53 PM PDT 24 14450100 ps
T819 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.749833333 Apr 02 12:28:17 PM PDT 24 Apr 02 12:28:19 PM PDT 24 28486394 ps
T820 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2683197005 Apr 02 12:28:01 PM PDT 24 Apr 02 12:28:02 PM PDT 24 49361447 ps
T821 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3476818945 Apr 02 12:28:00 PM PDT 24 Apr 02 12:28:06 PM PDT 24 47065874 ps
T822 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1578629465 Apr 02 12:28:27 PM PDT 24 Apr 02 12:28:28 PM PDT 24 23128562 ps
T823 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.4033015891 Apr 02 12:27:54 PM PDT 24 Apr 02 12:27:58 PM PDT 24 931070281 ps
T824 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3401344522 Apr 02 12:27:58 PM PDT 24 Apr 02 12:28:00 PM PDT 24 42372712 ps
T825 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2110855790 Apr 02 12:27:59 PM PDT 24 Apr 02 12:28:01 PM PDT 24 111800821 ps
T826 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1156594823 Apr 02 12:28:06 PM PDT 24 Apr 02 12:28:07 PM PDT 24 20941105 ps
T827 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1515532325 Apr 02 12:27:54 PM PDT 24 Apr 02 12:28:00 PM PDT 24 100553310 ps
T828 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.478671896 Apr 02 12:28:30 PM PDT 24 Apr 02 12:28:33 PM PDT 24 106946643 ps
T829 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.628850937 Apr 02 12:27:54 PM PDT 24 Apr 02 12:27:55 PM PDT 24 21504096 ps
T830 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.152263666 Apr 02 12:27:56 PM PDT 24 Apr 02 12:27:56 PM PDT 24 35408325 ps
T831 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3689065039 Apr 02 12:27:55 PM PDT 24 Apr 02 12:27:56 PM PDT 24 47143723 ps
T832 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1172740501 Apr 02 12:28:28 PM PDT 24 Apr 02 12:28:28 PM PDT 24 26062743 ps
T833 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3413599153 Apr 02 12:27:55 PM PDT 24 Apr 02 12:27:59 PM PDT 24 271643663 ps
T834 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1573678674 Apr 02 12:27:53 PM PDT 24 Apr 02 12:27:54 PM PDT 24 43480500 ps
T835 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3681314318 Apr 02 12:28:26 PM PDT 24 Apr 02 12:28:27 PM PDT 24 50053833 ps
T836 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.73423205 Apr 02 12:28:33 PM PDT 24 Apr 02 12:28:35 PM PDT 24 137774824 ps
T837 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.825641559 Apr 02 12:27:56 PM PDT 24 Apr 02 12:27:57 PM PDT 24 302178281 ps
T838 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1594677994 Apr 02 12:28:00 PM PDT 24 Apr 02 12:28:02 PM PDT 24 135513101 ps
T839 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2567895121 Apr 02 12:28:01 PM PDT 24 Apr 02 12:28:02 PM PDT 24 41252474 ps
T840 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.84299614 Apr 02 12:28:33 PM PDT 24 Apr 02 12:28:36 PM PDT 24 101044909 ps
T841 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3320344335 Apr 02 12:27:53 PM PDT 24 Apr 02 12:28:00 PM PDT 24 753892873 ps
T842 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1182234728 Apr 02 12:27:59 PM PDT 24 Apr 02 12:28:01 PM PDT 24 88332134 ps
T843 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2867371458 Apr 02 12:28:20 PM PDT 24 Apr 02 12:28:22 PM PDT 24 66798653 ps
T844 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.790573482 Apr 02 12:27:54 PM PDT 24 Apr 02 12:27:57 PM PDT 24 274305977 ps
T845 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1576074495 Apr 02 12:27:53 PM PDT 24 Apr 02 12:27:54 PM PDT 24 22320227 ps
T367 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1299712289 Apr 02 12:27:56 PM PDT 24 Apr 02 12:28:04 PM PDT 24 584961576 ps
T846 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3813938544 Apr 02 12:27:56 PM PDT 24 Apr 02 12:27:58 PM PDT 24 82577089 ps
T847 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2523848374 Apr 02 12:27:54 PM PDT 24 Apr 02 12:28:01 PM PDT 24 433107277 ps
T848 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2246776860 Apr 02 12:28:01 PM PDT 24 Apr 02 12:28:17 PM PDT 24 613611984 ps
T849 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3183564508 Apr 02 12:27:53 PM PDT 24 Apr 02 12:28:01 PM PDT 24 466834075 ps
T850 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1806097935 Apr 02 12:28:01 PM PDT 24 Apr 02 12:28:06 PM PDT 24 413258873 ps
T107 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1924972356 Apr 02 12:28:12 PM PDT 24 Apr 02 12:28:13 PM PDT 24 78553843 ps
T851 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3082769374 Apr 02 12:28:15 PM PDT 24 Apr 02 12:28:16 PM PDT 24 31521934 ps
T852 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2548052906 Apr 02 12:27:52 PM PDT 24 Apr 02 12:27:53 PM PDT 24 25324761 ps
T853 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2867984258 Apr 02 12:28:04 PM PDT 24 Apr 02 12:28:08 PM PDT 24 133951959 ps
T854 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2907754908 Apr 02 12:27:57 PM PDT 24 Apr 02 12:28:20 PM PDT 24 16214873117 ps

Test location /workspace/coverage/default/2.spi_device_upload.1483383928
Short name T5
Test name
Test status
Simulation time 116256379 ps
CPU time 3.46 seconds
Started Apr 02 01:39:03 PM PDT 24
Finished Apr 02 01:39:08 PM PDT 24
Peak memory 223524 kb
Host smart-505187c6-cc28-455e-8ec9-a6da39ec669b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483383928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.1483383928
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.3984939817
Short name T18
Test name
Test status
Simulation time 47996595351 ps
CPU time 43.6 seconds
Started Apr 02 01:44:13 PM PDT 24
Finished Apr 02 01:44:57 PM PDT 24
Peak memory 216736 kb
Host smart-60560a14-8d04-4c89-a68a-51ec7af1d8fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984939817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.3984939817
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_intercept.1237746516
Short name T45
Test name
Test status
Simulation time 8891955091 ps
CPU time 18.62 seconds
Started Apr 02 01:39:52 PM PDT 24
Finished Apr 02 01:40:11 PM PDT 24
Peak memory 219384 kb
Host smart-ef194fe0-94d2-40c2-9f46-3b2945f1b83d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237746516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.1237746516
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.1222023592
Short name T64
Test name
Test status
Simulation time 3849894847 ps
CPU time 21.89 seconds
Started Apr 02 01:39:04 PM PDT 24
Finished Apr 02 01:39:27 PM PDT 24
Peak memory 216880 kb
Host smart-7b6f8b54-975c-4576-9afc-c3c9bd280b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222023592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.1222023592
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_upload.2373258415
Short name T26
Test name
Test status
Simulation time 1129277942 ps
CPU time 9.27 seconds
Started Apr 02 01:40:48 PM PDT 24
Finished Apr 02 01:40:57 PM PDT 24
Peak memory 220636 kb
Host smart-00a89f37-b65f-4d81-b38a-6ca90e297359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373258415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.2373258415
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.615655410
Short name T1
Test name
Test status
Simulation time 37486301 ps
CPU time 0.93 seconds
Started Apr 02 01:43:32 PM PDT 24
Finished Apr 02 01:43:33 PM PDT 24
Peak memory 207148 kb
Host smart-b9426861-038f-4bfb-a81f-7bdc60c94be6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615655410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stres
s_all.615655410
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1959574767
Short name T135
Test name
Test status
Simulation time 1050649219 ps
CPU time 21.21 seconds
Started Apr 02 12:28:07 PM PDT 24
Finished Apr 02 12:28:28 PM PDT 24
Peak memory 215220 kb
Host smart-2864edcd-cfaa-4ec3-9b5e-fa5ca346fddd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959574767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.1959574767
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/16.spi_device_upload.3474626378
Short name T72
Test name
Test status
Simulation time 17103803158 ps
CPU time 21.6 seconds
Started Apr 02 01:40:20 PM PDT 24
Finished Apr 02 01:40:42 PM PDT 24
Peak memory 240700 kb
Host smart-de4bf691-62be-4d7d-b18c-e0ad5b518f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474626378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.3474626378
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.3152391366
Short name T380
Test name
Test status
Simulation time 16196623087 ps
CPU time 51.48 seconds
Started Apr 02 01:44:02 PM PDT 24
Finished Apr 02 01:44:54 PM PDT 24
Peak memory 216780 kb
Host smart-cc31c4a0-8aae-4e8f-8597-07fe737ed53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152391366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.3152391366
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.184992071
Short name T13
Test name
Test status
Simulation time 4653506781 ps
CPU time 9.11 seconds
Started Apr 02 01:40:33 PM PDT 24
Finished Apr 02 01:40:42 PM PDT 24
Peak memory 224876 kb
Host smart-4d9e07e3-656b-4476-9c4b-d3a31cb6bb15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184992071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.184992071
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_ram_cfg.3590124940
Short name T426
Test name
Test status
Simulation time 18396179 ps
CPU time 0.73 seconds
Started Apr 02 01:39:45 PM PDT 24
Finished Apr 02 01:39:46 PM PDT 24
Peak memory 216716 kb
Host smart-f8304863-5363-464d-992d-42eb5fbfb2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590124940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_ram_cfg.3590124940
Directory /workspace/11.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.1119234111
Short name T23
Test name
Test status
Simulation time 184743358 ps
CPU time 2.9 seconds
Started Apr 02 01:40:53 PM PDT 24
Finished Apr 02 01:40:57 PM PDT 24
Peak memory 223440 kb
Host smart-63123247-f17a-4dde-826c-f7e70bb4c64f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119234111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.1119234111
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1574316982
Short name T122
Test name
Test status
Simulation time 307002857 ps
CPU time 4.19 seconds
Started Apr 02 12:27:56 PM PDT 24
Finished Apr 02 12:28:00 PM PDT 24
Peak memory 216276 kb
Host smart-c6cb0fae-ed6c-4bad-a2b9-2d69517ba280
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574316982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
1574316982
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.279416348
Short name T393
Test name
Test status
Simulation time 2586333322 ps
CPU time 38.01 seconds
Started Apr 02 01:38:49 PM PDT 24
Finished Apr 02 01:39:27 PM PDT 24
Peak memory 216780 kb
Host smart-7ffa29ce-60db-4f07-b552-1133a0460945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279416348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.279416348
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.1574058093
Short name T65
Test name
Test status
Simulation time 7083124651 ps
CPU time 95.37 seconds
Started Apr 02 01:40:29 PM PDT 24
Finished Apr 02 01:42:05 PM PDT 24
Peak memory 249656 kb
Host smart-1e946487-eab1-4a66-90da-9c87f474c79a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574058093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.1574058093
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.2720760498
Short name T82
Test name
Test status
Simulation time 460048393 ps
CPU time 7.36 seconds
Started Apr 02 01:39:17 PM PDT 24
Finished Apr 02 01:39:24 PM PDT 24
Peak memory 224336 kb
Host smart-48e58a90-c36e-4879-9bdd-a232c6075b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720760498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.2720760498
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.2734216860
Short name T46
Test name
Test status
Simulation time 5441020748 ps
CPU time 17.84 seconds
Started Apr 02 01:40:37 PM PDT 24
Finished Apr 02 01:40:55 PM PDT 24
Peak memory 221944 kb
Host smart-ba8fee4e-1d69-4c3d-99d0-9e039dad0f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734216860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.2734216860
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.2232498607
Short name T33
Test name
Test status
Simulation time 97102524 ps
CPU time 1.13 seconds
Started Apr 02 01:38:55 PM PDT 24
Finished Apr 02 01:38:57 PM PDT 24
Peak memory 235740 kb
Host smart-d979617f-98a7-4004-acdd-27598ff76095
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232498607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.2232498607
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.1318546956
Short name T101
Test name
Test status
Simulation time 1974033280 ps
CPU time 5.98 seconds
Started Apr 02 01:43:30 PM PDT 24
Finished Apr 02 01:43:36 PM PDT 24
Peak memory 217184 kb
Host smart-9983cc6f-1db4-4376-815b-8259cb3fb895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318546956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.1318546956
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.847521545
Short name T6
Test name
Test status
Simulation time 56429539274 ps
CPU time 146.31 seconds
Started Apr 02 01:39:34 PM PDT 24
Finished Apr 02 01:42:01 PM PDT 24
Peak memory 234208 kb
Host smart-64b3c363-704d-4c39-be24-3099179bf0af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847521545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.847521545
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.2628643517
Short name T85
Test name
Test status
Simulation time 1924052331 ps
CPU time 12.28 seconds
Started Apr 02 01:39:45 PM PDT 24
Finished Apr 02 01:39:57 PM PDT 24
Peak memory 225228 kb
Host smart-32a97d9f-09c5-4930-ad9a-69ced7edf22d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628643517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.2628643517
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.952392821
Short name T104
Test name
Test status
Simulation time 42075020 ps
CPU time 0.98 seconds
Started Apr 02 12:27:56 PM PDT 24
Finished Apr 02 12:28:03 PM PDT 24
Peak memory 206696 kb
Host smart-b4664b18-e5cd-452d-b1e8-f904ebc4722e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952392821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_hw_reset.952392821
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.113051766
Short name T371
Test name
Test status
Simulation time 10686557290 ps
CPU time 31.23 seconds
Started Apr 02 01:41:04 PM PDT 24
Finished Apr 02 01:41:35 PM PDT 24
Peak memory 216724 kb
Host smart-bafb7c66-bd6e-4cf8-8139-79aca448c9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113051766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.113051766
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.4242271517
Short name T318
Test name
Test status
Simulation time 23907073058 ps
CPU time 53.97 seconds
Started Apr 02 01:43:19 PM PDT 24
Finished Apr 02 01:44:13 PM PDT 24
Peak memory 236336 kb
Host smart-c22de2fd-36a0-4394-a10b-720ea624577e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242271517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.4242271517
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.1659229001
Short name T216
Test name
Test status
Simulation time 15156599118 ps
CPU time 9.59 seconds
Started Apr 02 01:42:45 PM PDT 24
Finished Apr 02 01:42:55 PM PDT 24
Peak memory 223728 kb
Host smart-754003ec-e132-4d3c-a8e1-b4cc24193b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659229001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.1659229001
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.3121043519
Short name T220
Test name
Test status
Simulation time 1890825974 ps
CPU time 10.19 seconds
Started Apr 02 01:39:44 PM PDT 24
Finished Apr 02 01:39:54 PM PDT 24
Peak memory 239276 kb
Host smart-effdecf6-e334-4a77-a7c8-50fa39ca9bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121043519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.3121043519
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_upload.1345065868
Short name T27
Test name
Test status
Simulation time 8282629229 ps
CPU time 11.42 seconds
Started Apr 02 01:46:26 PM PDT 24
Finished Apr 02 01:46:38 PM PDT 24
Peak memory 240008 kb
Host smart-437a26ae-60a4-44ef-8251-22d7d1acdc5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345065868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.1345065868
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.1699966797
Short name T301
Test name
Test status
Simulation time 4676853226 ps
CPU time 39.75 seconds
Started Apr 02 01:39:21 PM PDT 24
Finished Apr 02 01:40:01 PM PDT 24
Peak memory 220600 kb
Host smart-ceeff639-b2c0-4cac-afb7-409c75e765a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699966797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.1699966797
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.604294765
Short name T389
Test name
Test status
Simulation time 4057619236 ps
CPU time 34.68 seconds
Started Apr 02 01:45:30 PM PDT 24
Finished Apr 02 01:46:05 PM PDT 24
Peak memory 218392 kb
Host smart-080bb497-643a-4d5f-99f2-70cec13e676c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604294765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.604294765
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.2910028483
Short name T347
Test name
Test status
Simulation time 58465247 ps
CPU time 1.22 seconds
Started Apr 02 01:39:44 PM PDT 24
Finished Apr 02 01:39:45 PM PDT 24
Peak memory 207832 kb
Host smart-f4728164-1c8e-460e-90b1-edf957f2f530
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910028483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.2910028483
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.1399371021
Short name T16
Test name
Test status
Simulation time 982366328 ps
CPU time 6.32 seconds
Started Apr 02 01:42:41 PM PDT 24
Finished Apr 02 01:42:47 PM PDT 24
Peak memory 216732 kb
Host smart-fd2a5669-bcb9-4e38-a9dd-1c0ef51f1483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399371021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.1399371021
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.3008964940
Short name T178
Test name
Test status
Simulation time 15566689918 ps
CPU time 13.29 seconds
Started Apr 02 01:44:16 PM PDT 24
Finished Apr 02 01:44:29 PM PDT 24
Peak memory 217352 kb
Host smart-0025ca9b-4ba3-4cd7-a207-d9ae7668cc6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008964940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.3008964940
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_upload.2246758708
Short name T331
Test name
Test status
Simulation time 1918002070 ps
CPU time 10.65 seconds
Started Apr 02 01:38:57 PM PDT 24
Finished Apr 02 01:39:09 PM PDT 24
Peak memory 235100 kb
Host smart-833828f1-d888-4bc0-a561-f535f2428006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246758708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.2246758708
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.641921101
Short name T79
Test name
Test status
Simulation time 16846627893 ps
CPU time 42.35 seconds
Started Apr 02 01:42:46 PM PDT 24
Finished Apr 02 01:43:28 PM PDT 24
Peak memory 224900 kb
Host smart-e3afd05b-2c73-40ba-b234-4794fc614fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641921101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap
.641921101
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_intercept.922715048
Short name T170
Test name
Test status
Simulation time 970823785 ps
CPU time 10.02 seconds
Started Apr 02 01:42:17 PM PDT 24
Finished Apr 02 01:42:27 PM PDT 24
Peak memory 223188 kb
Host smart-3d314264-6f9e-46fc-ab58-23cbe6609654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922715048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.922715048
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.1867801306
Short name T272
Test name
Test status
Simulation time 337325882 ps
CPU time 5.09 seconds
Started Apr 02 01:45:36 PM PDT 24
Finished Apr 02 01:45:42 PM PDT 24
Peak memory 218872 kb
Host smart-a062faaf-2429-4758-8c9b-8de353082c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867801306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.1867801306
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.916433241
Short name T251
Test name
Test status
Simulation time 11778303533 ps
CPU time 10.48 seconds
Started Apr 02 01:39:43 PM PDT 24
Finished Apr 02 01:39:54 PM PDT 24
Peak memory 217408 kb
Host smart-aea7af13-7fa5-49a3-ad6e-10dbe60817a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916433241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.916433241
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_upload.1469640021
Short name T189
Test name
Test status
Simulation time 26177750115 ps
CPU time 9.57 seconds
Started Apr 02 01:40:11 PM PDT 24
Finished Apr 02 01:40:21 PM PDT 24
Peak memory 236952 kb
Host smart-e9f13ea5-db63-4d69-b21c-6a839b122f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469640021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.1469640021
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.2601205778
Short name T67
Test name
Test status
Simulation time 17623285028 ps
CPU time 55.06 seconds
Started Apr 02 01:39:02 PM PDT 24
Finished Apr 02 01:39:59 PM PDT 24
Peak memory 237128 kb
Host smart-3dce341a-5c9f-45b2-8fd6-6d5bae5c690e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601205778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.2601205778
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.3988942866
Short name T304
Test name
Test status
Simulation time 3097473587 ps
CPU time 6.65 seconds
Started Apr 02 01:43:14 PM PDT 24
Finished Apr 02 01:43:21 PM PDT 24
Peak memory 233148 kb
Host smart-2af2c3df-fd14-49b4-b530-679d2196f426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988942866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.3988942866
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.2187980713
Short name T267
Test name
Test status
Simulation time 1782021114 ps
CPU time 32.33 seconds
Started Apr 02 01:40:13 PM PDT 24
Finished Apr 02 01:40:45 PM PDT 24
Peak memory 218332 kb
Host smart-b9e22202-74d2-417f-a135-5f30c4b2dd0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187980713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.2187980713
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.3469850173
Short name T191
Test name
Test status
Simulation time 16838439178 ps
CPU time 22.88 seconds
Started Apr 02 01:40:34 PM PDT 24
Finished Apr 02 01:40:57 PM PDT 24
Peak memory 222960 kb
Host smart-de26acb1-1b8c-441e-8241-b5f7e3d8b572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469850173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.3469850173
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.482947700
Short name T247
Test name
Test status
Simulation time 1871109179 ps
CPU time 11.68 seconds
Started Apr 02 01:42:04 PM PDT 24
Finished Apr 02 01:42:15 PM PDT 24
Peak memory 237940 kb
Host smart-e1c19054-f6cf-44d9-b6cd-9fa4237921d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482947700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.482947700
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.4143132593
Short name T219
Test name
Test status
Simulation time 22153070887 ps
CPU time 29.89 seconds
Started Apr 02 01:43:25 PM PDT 24
Finished Apr 02 01:43:56 PM PDT 24
Peak memory 233136 kb
Host smart-e6faf0c2-9948-4560-8b94-84ead5f0df47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143132593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.4143132593
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_intercept.2729577865
Short name T42
Test name
Test status
Simulation time 4318600000 ps
CPU time 10.45 seconds
Started Apr 02 01:43:41 PM PDT 24
Finished Apr 02 01:43:52 PM PDT 24
Peak memory 219016 kb
Host smart-09de0055-49f6-46ec-adc2-1b9b84db7ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729577865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.2729577865
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2993205942
Short name T37
Test name
Test status
Simulation time 1900236372 ps
CPU time 19.87 seconds
Started Apr 02 12:28:11 PM PDT 24
Finished Apr 02 12:28:31 PM PDT 24
Peak memory 215176 kb
Host smart-ed357d04-b2b8-469a-a5a6-fbe6330f9f17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993205942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.2993205942
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/10.spi_device_intercept.4036821031
Short name T99
Test name
Test status
Simulation time 5355502086 ps
CPU time 12.51 seconds
Started Apr 02 01:39:43 PM PDT 24
Finished Apr 02 01:39:56 PM PDT 24
Peak memory 224156 kb
Host smart-b2187661-9ea9-4b06-b988-9c3103e54213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036821031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.4036821031
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.4022725547
Short name T224
Test name
Test status
Simulation time 4118197578 ps
CPU time 14.45 seconds
Started Apr 02 01:41:09 PM PDT 24
Finished Apr 02 01:41:24 PM PDT 24
Peak memory 223564 kb
Host smart-78874fdd-8ee4-45b4-8b51-55f72fde0799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022725547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.4022725547
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_upload.3690679715
Short name T29
Test name
Test status
Simulation time 4374569473 ps
CPU time 9.07 seconds
Started Apr 02 01:43:29 PM PDT 24
Finished Apr 02 01:43:38 PM PDT 24
Peak memory 225624 kb
Host smart-ee072308-1684-4190-9fc3-b682f054a131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690679715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.3690679715
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.181753042
Short name T83
Test name
Test status
Simulation time 131677777841 ps
CPU time 37.77 seconds
Started Apr 02 01:46:12 PM PDT 24
Finished Apr 02 01:46:50 PM PDT 24
Peak memory 241280 kb
Host smart-2cfa8775-d70c-492e-96ed-d9d72d80df02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181753042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap
.181753042
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_intercept.767238651
Short name T276
Test name
Test status
Simulation time 11442785239 ps
CPU time 30.8 seconds
Started Apr 02 01:44:07 PM PDT 24
Finished Apr 02 01:44:38 PM PDT 24
Peak memory 233036 kb
Host smart-a14a108f-7a5e-4c11-8299-4fa52ba769e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767238651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.767238651
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.1324429343
Short name T413
Test name
Test status
Simulation time 48562415 ps
CPU time 0.71 seconds
Started Apr 02 01:38:51 PM PDT 24
Finished Apr 02 01:38:52 PM PDT 24
Peak memory 205356 kb
Host smart-f89011e3-a499-4226-afa7-20421561e846
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324429343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.1
324429343
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.2755301642
Short name T400
Test name
Test status
Simulation time 34503061865 ps
CPU time 38.78 seconds
Started Apr 02 01:40:36 PM PDT 24
Finished Apr 02 01:41:15 PM PDT 24
Peak memory 216952 kb
Host smart-ff89c8e3-a4bf-4ec1-a5cb-e31c6c99ebc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755301642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.2755301642
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.793710437
Short name T78
Test name
Test status
Simulation time 3401160307 ps
CPU time 11.71 seconds
Started Apr 02 01:41:16 PM PDT 24
Finished Apr 02 01:41:28 PM PDT 24
Peak memory 219324 kb
Host smart-b245acd2-b597-4573-91f5-468542213012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793710437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap
.793710437
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_intercept.1708220184
Short name T259
Test name
Test status
Simulation time 7285211455 ps
CPU time 39.56 seconds
Started Apr 02 01:39:14 PM PDT 24
Finished Apr 02 01:39:54 PM PDT 24
Peak memory 233248 kb
Host smart-72ecdcdd-f6bb-40a8-8b93-8b81a11802c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708220184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.1708220184
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.4249246992
Short name T298
Test name
Test status
Simulation time 34969854151 ps
CPU time 106.2 seconds
Started Apr 02 01:43:03 PM PDT 24
Finished Apr 02 01:44:50 PM PDT 24
Peak memory 241120 kb
Host smart-01b8c482-d1da-41c8-bcae-b660a03504fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249246992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.4249246992
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.2932966361
Short name T213
Test name
Test status
Simulation time 74320787509 ps
CPU time 124.98 seconds
Started Apr 02 01:38:57 PM PDT 24
Finished Apr 02 01:41:03 PM PDT 24
Peak memory 233064 kb
Host smart-7817ecfe-59fc-4ec0-acff-ed60b11e9051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932966361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.2932966361
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.3342622989
Short name T240
Test name
Test status
Simulation time 524448849 ps
CPU time 4.3 seconds
Started Apr 02 01:41:16 PM PDT 24
Finished Apr 02 01:41:20 PM PDT 24
Peak memory 219100 kb
Host smart-fb8e7af2-bd25-40e2-9d48-412b0c65b27a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342622989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.3342622989
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_intercept.2303795027
Short name T181
Test name
Test status
Simulation time 13632327437 ps
CPU time 37.5 seconds
Started Apr 02 01:42:04 PM PDT 24
Finished Apr 02 01:42:42 PM PDT 24
Peak memory 221096 kb
Host smart-1b947d9a-99e0-4f1d-9a2a-de10773e3127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303795027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.2303795027
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_upload.18876069
Short name T282
Test name
Test status
Simulation time 1698919825 ps
CPU time 9.35 seconds
Started Apr 02 01:44:34 PM PDT 24
Finished Apr 02 01:44:44 PM PDT 24
Peak memory 216792 kb
Host smart-0ca865f6-c476-4a95-88d2-115d29d6ec6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18876069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.18876069
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.1772487270
Short name T194
Test name
Test status
Simulation time 10611492194 ps
CPU time 8.92 seconds
Started Apr 02 01:45:01 PM PDT 24
Finished Apr 02 01:45:11 PM PDT 24
Peak memory 220272 kb
Host smart-e03598ca-3bb4-43f1-9b87-444e5050f5b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772487270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.1772487270
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.3541224258
Short name T343
Test name
Test status
Simulation time 9523191419 ps
CPU time 27.09 seconds
Started Apr 02 01:46:25 PM PDT 24
Finished Apr 02 01:46:52 PM PDT 24
Peak memory 225068 kb
Host smart-7866fee5-861c-4069-be1e-5619b901dfd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541224258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.3541224258
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.2510671652
Short name T186
Test name
Test status
Simulation time 13917061523 ps
CPU time 35.8 seconds
Started Apr 02 01:46:25 PM PDT 24
Finished Apr 02 01:47:01 PM PDT 24
Peak memory 237784 kb
Host smart-720ef693-a823-44aa-affd-661af987cf67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510671652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.2510671652
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.1192680167
Short name T71
Test name
Test status
Simulation time 2722526774 ps
CPU time 26.41 seconds
Started Apr 02 01:42:42 PM PDT 24
Finished Apr 02 01:43:09 PM PDT 24
Peak memory 220512 kb
Host smart-963b5f25-0266-4f90-bccf-4fdf6e236152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192680167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.1192680167
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3795236790
Short name T363
Test name
Test status
Simulation time 835371268 ps
CPU time 21.22 seconds
Started Apr 02 12:28:20 PM PDT 24
Finished Apr 02 12:28:42 PM PDT 24
Peak memory 215680 kb
Host smart-94eca35f-4cb1-45c7-920b-94195f3e9d98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795236790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.3795236790
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/17.spi_device_intercept.3317617601
Short name T169
Test name
Test status
Simulation time 3980990557 ps
CPU time 21.3 seconds
Started Apr 02 01:40:26 PM PDT 24
Finished Apr 02 01:40:48 PM PDT 24
Peak memory 219392 kb
Host smart-8a7af8c7-71dd-4918-94cc-3b4e64a03247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317617601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.3317617601
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.468856787
Short name T76
Test name
Test status
Simulation time 3244116669 ps
CPU time 5.11 seconds
Started Apr 02 01:40:37 PM PDT 24
Finished Apr 02 01:40:43 PM PDT 24
Peak memory 224260 kb
Host smart-7b82cfb7-6ce0-41e4-8ff3-c1a570ff6758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468856787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap
.468856787
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.2506182615
Short name T340
Test name
Test status
Simulation time 2725159167 ps
CPU time 8.34 seconds
Started Apr 02 01:39:04 PM PDT 24
Finished Apr 02 01:39:13 PM PDT 24
Peak memory 223312 kb
Host smart-b571ad3e-b408-4b53-9d1c-f988ef409175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506182615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.2506182615
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.1512054604
Short name T86
Test name
Test status
Simulation time 6081653125 ps
CPU time 11.59 seconds
Started Apr 02 01:40:42 PM PDT 24
Finished Apr 02 01:40:54 PM PDT 24
Peak memory 233252 kb
Host smart-664f31c5-9734-4db9-9672-42fbf0483888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512054604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.1512054604
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_upload.1829354121
Short name T81
Test name
Test status
Simulation time 9277157586 ps
CPU time 11.77 seconds
Started Apr 02 01:42:20 PM PDT 24
Finished Apr 02 01:42:31 PM PDT 24
Peak memory 233200 kb
Host smart-8b8fe4ad-ad6a-4dac-98eb-bded621bd2d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829354121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.1829354121
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.377072990
Short name T202
Test name
Test status
Simulation time 12395095463 ps
CPU time 32.37 seconds
Started Apr 02 01:43:56 PM PDT 24
Finished Apr 02 01:44:29 PM PDT 24
Peak memory 220648 kb
Host smart-a0be6b8b-1ec6-4666-bd34-ab3c0925f37e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377072990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.377072990
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.2995805070
Short name T218
Test name
Test status
Simulation time 9446417365 ps
CPU time 13.56 seconds
Started Apr 02 01:44:03 PM PDT 24
Finished Apr 02 01:44:16 PM PDT 24
Peak memory 227304 kb
Host smart-f1da5b3a-c56a-432b-8c08-f143719f5f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995805070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.2995805070
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_upload.1332755772
Short name T43
Test name
Test status
Simulation time 2993484314 ps
CPU time 9.66 seconds
Started Apr 02 01:44:09 PM PDT 24
Finished Apr 02 01:44:19 PM PDT 24
Peak memory 233164 kb
Host smart-8f771eae-06ae-4849-b26d-5044e92e6f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332755772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.1332755772
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3331616411
Short name T155
Test name
Test status
Simulation time 70602818 ps
CPU time 3.78 seconds
Started Apr 02 12:28:22 PM PDT 24
Finished Apr 02 12:28:26 PM PDT 24
Peak memory 215100 kb
Host smart-2ed84ec2-5c49-4cec-8681-7f924cc2a3a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331616411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.3331616411
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3618653561
Short name T129
Test name
Test status
Simulation time 165609198 ps
CPU time 4.45 seconds
Started Apr 02 12:28:28 PM PDT 24
Finished Apr 02 12:28:33 PM PDT 24
Peak memory 215188 kb
Host smart-19511960-85ce-4687-912e-6a313cbbf280
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618653561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
3618653561
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.7523837
Short name T239
Test name
Test status
Simulation time 74429138 ps
CPU time 2.14 seconds
Started Apr 02 01:38:52 PM PDT 24
Finished Apr 02 01:38:55 PM PDT 24
Peak memory 216700 kb
Host smart-d30dbcbc-d341-443e-97b4-d08fb57573f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7523837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.7523837
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.3959145583
Short name T211
Test name
Test status
Simulation time 21755729407 ps
CPU time 30.58 seconds
Started Apr 02 01:38:57 PM PDT 24
Finished Apr 02 01:39:29 PM PDT 24
Peak memory 233072 kb
Host smart-3b89bbbb-cb95-45d8-b55d-7f5dba9778a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959145583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.3959145583
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.3474165112
Short name T232
Test name
Test status
Simulation time 2935839006 ps
CPU time 7.16 seconds
Started Apr 02 01:39:44 PM PDT 24
Finished Apr 02 01:39:52 PM PDT 24
Peak memory 225076 kb
Host smart-922f4faf-42f2-45cf-b893-76d0bdddd892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474165112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.3474165112
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.274451453
Short name T242
Test name
Test status
Simulation time 1159133403 ps
CPU time 7.68 seconds
Started Apr 02 01:39:52 PM PDT 24
Finished Apr 02 01:40:00 PM PDT 24
Peak memory 233908 kb
Host smart-b77d6704-fd61-4000-ad56-77e645f39dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274451453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.274451453
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_intercept.1713254026
Short name T269
Test name
Test status
Simulation time 479134115 ps
CPU time 8.42 seconds
Started Apr 02 01:39:58 PM PDT 24
Finished Apr 02 01:40:06 PM PDT 24
Peak memory 233120 kb
Host smart-8165e755-bc71-4af3-a279-a72ae280d239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713254026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.1713254026
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_upload.3215395231
Short name T270
Test name
Test status
Simulation time 48197717 ps
CPU time 2.31 seconds
Started Apr 02 01:40:07 PM PDT 24
Finished Apr 02 01:40:09 PM PDT 24
Peak memory 222108 kb
Host smart-1db785b6-fbd8-440c-8951-9e6d31c1bb0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215395231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.3215395231
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.1107838132
Short name T193
Test name
Test status
Simulation time 5590843151 ps
CPU time 22.27 seconds
Started Apr 02 01:40:16 PM PDT 24
Finished Apr 02 01:40:38 PM PDT 24
Peak memory 233188 kb
Host smart-887cfc2d-b999-494e-8555-4a93916beb98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107838132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.1107838132
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.223219186
Short name T279
Test name
Test status
Simulation time 538715130 ps
CPU time 4.39 seconds
Started Apr 02 01:40:27 PM PDT 24
Finished Apr 02 01:40:31 PM PDT 24
Peak memory 233064 kb
Host smart-31de7fd9-0c76-43ef-bc0a-5d5365c5124e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223219186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.223219186
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.1660214150
Short name T268
Test name
Test status
Simulation time 455456842 ps
CPU time 5.5 seconds
Started Apr 02 01:40:38 PM PDT 24
Finished Apr 02 01:40:44 PM PDT 24
Peak memory 224880 kb
Host smart-98af4e8d-0dcc-44fc-83b1-892e931322ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660214150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.1660214150
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.2775322077
Short name T295
Test name
Test status
Simulation time 3070072446 ps
CPU time 36.1 seconds
Started Apr 02 01:40:56 PM PDT 24
Finished Apr 02 01:41:32 PM PDT 24
Peak memory 241008 kb
Host smart-8c0fd307-1199-40bd-9396-9e6734908b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775322077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.2775322077
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.1469255108
Short name T256
Test name
Test status
Simulation time 11151606111 ps
CPU time 34.36 seconds
Started Apr 02 01:41:13 PM PDT 24
Finished Apr 02 01:41:47 PM PDT 24
Peak memory 233724 kb
Host smart-6bd53b1b-35e0-465f-9707-d9c623f6f1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469255108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.1469255108
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_intercept.533039952
Short name T208
Test name
Test status
Simulation time 3220677079 ps
CPU time 16.72 seconds
Started Apr 02 01:41:25 PM PDT 24
Finished Apr 02 01:41:42 PM PDT 24
Peak memory 224072 kb
Host smart-77ed43df-53d7-43d1-95f6-3f7bc19c980f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533039952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.533039952
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.3993968222
Short name T263
Test name
Test status
Simulation time 94385050 ps
CPU time 3.02 seconds
Started Apr 02 01:41:25 PM PDT 24
Finished Apr 02 01:41:28 PM PDT 24
Peak memory 222424 kb
Host smart-6bf318ed-703b-4d09-9432-5c483865a005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993968222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.3993968222
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.1531249106
Short name T84
Test name
Test status
Simulation time 5796680729 ps
CPU time 18.93 seconds
Started Apr 02 01:43:40 PM PDT 24
Finished Apr 02 01:43:59 PM PDT 24
Peak memory 234996 kb
Host smart-a88e5e4e-d587-41ea-864a-9fc1d4e843cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531249106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.1531249106
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.154533458
Short name T87
Test name
Test status
Simulation time 297357612 ps
CPU time 4.95 seconds
Started Apr 02 01:43:54 PM PDT 24
Finished Apr 02 01:43:59 PM PDT 24
Peak memory 218860 kb
Host smart-e131bb1c-df1d-4c33-a377-ee62333eb61b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154533458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swap
.154533458
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.3330382393
Short name T285
Test name
Test status
Simulation time 2688161550 ps
CPU time 10.92 seconds
Started Apr 02 01:43:56 PM PDT 24
Finished Apr 02 01:44:07 PM PDT 24
Peak memory 222636 kb
Host smart-c91803ad-b769-4f71-9599-a67b19801b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330382393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.3330382393
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.1748578465
Short name T74
Test name
Test status
Simulation time 367881270 ps
CPU time 2.5 seconds
Started Apr 02 01:45:25 PM PDT 24
Finished Apr 02 01:45:27 PM PDT 24
Peak memory 223420 kb
Host smart-184567fa-9204-498a-8060-237d2ad78d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748578465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.1748578465
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.1841598255
Short name T241
Test name
Test status
Simulation time 3360828208 ps
CPU time 12.54 seconds
Started Apr 02 01:46:11 PM PDT 24
Finished Apr 02 01:46:23 PM PDT 24
Peak memory 233008 kb
Host smart-d6669c8a-e207-4d1f-9b22-a9d9402704c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841598255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.1841598255
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.2410832389
Short name T77
Test name
Test status
Simulation time 8747169615 ps
CPU time 11.9 seconds
Started Apr 02 01:39:35 PM PDT 24
Finished Apr 02 01:39:47 PM PDT 24
Peak memory 233264 kb
Host smart-85eca169-7968-4a2c-b675-b180ef026119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410832389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.2410832389
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_upload.2150612547
Short name T330
Test name
Test status
Simulation time 6077538003 ps
CPU time 11.84 seconds
Started Apr 02 01:39:34 PM PDT 24
Finished Apr 02 01:39:46 PM PDT 24
Peak memory 233156 kb
Host smart-e5a01080-0689-42da-9416-4c0f65bb5616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150612547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.2150612547
Directory /workspace/9.spi_device_upload/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1806097935
Short name T850
Test name
Test status
Simulation time 413258873 ps
CPU time 4.82 seconds
Started Apr 02 12:28:01 PM PDT 24
Finished Apr 02 12:28:06 PM PDT 24
Peak memory 215376 kb
Host smart-76b2b9a5-68c1-40de-96f7-0ab8c8aba25f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806097935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
1806097935
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2907754908
Short name T854
Test name
Test status
Simulation time 16214873117 ps
CPU time 22.23 seconds
Started Apr 02 12:27:57 PM PDT 24
Finished Apr 02 12:28:20 PM PDT 24
Peak memory 215124 kb
Host smart-9facf124-ed36-4e8c-8224-dcc2cddeb4e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907754908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.2907754908
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.2987035667
Short name T10
Test name
Test status
Simulation time 3323149512 ps
CPU time 4.22 seconds
Started Apr 02 01:38:50 PM PDT 24
Finished Apr 02 01:38:55 PM PDT 24
Peak memory 221292 kb
Host smart-04352ca6-cfd4-4517-99c4-007a1c1b49ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987035667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.2987035667
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.2111132952
Short name T287
Test name
Test status
Simulation time 19612884174 ps
CPU time 21.33 seconds
Started Apr 02 01:38:58 PM PDT 24
Finished Apr 02 01:39:19 PM PDT 24
Peak memory 233124 kb
Host smart-fe7a77a0-c845-44a7-9b5e-c16d13c90097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111132952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.2111132952
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.545181249
Short name T258
Test name
Test status
Simulation time 7200408124 ps
CPU time 7.22 seconds
Started Apr 02 01:39:02 PM PDT 24
Finished Apr 02 01:39:12 PM PDT 24
Peak memory 223392 kb
Host smart-3f7aa22e-f37c-4384-a8c0-1dd6b8cf65f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545181249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap.
545181249
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.2058122124
Short name T342
Test name
Test status
Simulation time 4663416783 ps
CPU time 16.67 seconds
Started Apr 02 01:39:44 PM PDT 24
Finished Apr 02 01:40:01 PM PDT 24
Peak memory 235188 kb
Host smart-ae2a1384-7aac-4172-b3aa-b881bb9e5ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058122124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.2058122124
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.128060133
Short name T689
Test name
Test status
Simulation time 19918613580 ps
CPU time 53.13 seconds
Started Apr 02 01:39:42 PM PDT 24
Finished Apr 02 01:40:35 PM PDT 24
Peak memory 217008 kb
Host smart-bf556ef6-e87f-4e0f-af2d-cb8f80ff23e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128060133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.128060133
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_upload.3016029314
Short name T329
Test name
Test status
Simulation time 19390023293 ps
CPU time 16.91 seconds
Started Apr 02 01:39:54 PM PDT 24
Finished Apr 02 01:40:11 PM PDT 24
Peak memory 235816 kb
Host smart-eddb067f-1850-44b9-b26a-ec739e3d41a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016029314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.3016029314
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.4003253539
Short name T237
Test name
Test status
Simulation time 213053961 ps
CPU time 3.06 seconds
Started Apr 02 01:39:56 PM PDT 24
Finished Apr 02 01:39:59 PM PDT 24
Peak memory 222988 kb
Host smart-8dbe619f-e7b0-49d3-96b8-81bc4b77a3f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003253539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.4003253539
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.3225649315
Short name T228
Test name
Test status
Simulation time 4389938765 ps
CPU time 11 seconds
Started Apr 02 01:39:57 PM PDT 24
Finished Apr 02 01:40:09 PM PDT 24
Peak memory 234076 kb
Host smart-74ac1d34-ae3b-4f19-b6cb-5e37bcc9ed30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225649315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.3225649315
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.3813320404
Short name T172
Test name
Test status
Simulation time 19399221508 ps
CPU time 110.2 seconds
Started Apr 02 01:40:06 PM PDT 24
Finished Apr 02 01:41:57 PM PDT 24
Peak memory 239616 kb
Host smart-568d731b-0966-4071-8518-62c6bb948e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813320404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.3813320404
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.1208765480
Short name T235
Test name
Test status
Simulation time 6645545610 ps
CPU time 17.95 seconds
Started Apr 02 01:40:07 PM PDT 24
Finished Apr 02 01:40:25 PM PDT 24
Peak memory 223900 kb
Host smart-0c8b8f2d-7f2b-48f3-bed8-111f8e47bca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208765480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.1208765480
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.3751791418
Short name T260
Test name
Test status
Simulation time 1057293897 ps
CPU time 2.76 seconds
Started Apr 02 01:40:28 PM PDT 24
Finished Apr 02 01:40:31 PM PDT 24
Peak memory 222572 kb
Host smart-3fa2f063-de1d-40ee-8514-0701424c362f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751791418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.3751791418
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_intercept.617890655
Short name T315
Test name
Test status
Simulation time 1075268883 ps
CPU time 10.14 seconds
Started Apr 02 01:40:32 PM PDT 24
Finished Apr 02 01:40:42 PM PDT 24
Peak memory 222348 kb
Host smart-82b31b42-0324-4ad5-8682-5aa93d1688d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617890655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.617890655
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.1108409326
Short name T11
Test name
Test status
Simulation time 888189050 ps
CPU time 6.83 seconds
Started Apr 02 01:39:01 PM PDT 24
Finished Apr 02 01:39:11 PM PDT 24
Peak memory 224848 kb
Host smart-64865011-9c43-4483-a361-8d88a5268422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108409326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.1108409326
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_intercept.2181385287
Short name T115
Test name
Test status
Simulation time 10346941950 ps
CPU time 18.86 seconds
Started Apr 02 01:40:45 PM PDT 24
Finished Apr 02 01:41:04 PM PDT 24
Peak memory 233192 kb
Host smart-04b75d6e-b752-45c3-8064-5446a8a0ff38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181385287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.2181385287
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.1119920865
Short name T312
Test name
Test status
Simulation time 13575791104 ps
CPU time 21.7 seconds
Started Apr 02 01:40:41 PM PDT 24
Finished Apr 02 01:41:03 PM PDT 24
Peak memory 222452 kb
Host smart-4cf43582-6a73-4a11-8497-092f9e787ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119920865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.1119920865
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.2906079519
Short name T292
Test name
Test status
Simulation time 7664843655 ps
CPU time 128.65 seconds
Started Apr 02 01:40:46 PM PDT 24
Finished Apr 02 01:42:55 PM PDT 24
Peak memory 240156 kb
Host smart-9d67a7ea-15b8-467a-be15-69feac0d23e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906079519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.2906079519
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.2097290907
Short name T300
Test name
Test status
Simulation time 1217940772 ps
CPU time 3.2 seconds
Started Apr 02 01:40:44 PM PDT 24
Finished Apr 02 01:40:47 PM PDT 24
Peak memory 218964 kb
Host smart-b6bb5e26-85a9-4ff9-8874-5243d0a74d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097290907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.2097290907
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.1244327760
Short name T334
Test name
Test status
Simulation time 17725899876 ps
CPU time 23.18 seconds
Started Apr 02 01:40:53 PM PDT 24
Finished Apr 02 01:41:16 PM PDT 24
Peak memory 222964 kb
Host smart-8fb18fdb-6b18-4fa6-8b98-94aadc9f10fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244327760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.1244327760
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.435090608
Short name T88
Test name
Test status
Simulation time 13634792842 ps
CPU time 18.94 seconds
Started Apr 02 01:41:01 PM PDT 24
Finished Apr 02 01:41:20 PM PDT 24
Peak memory 224472 kb
Host smart-a6c5e520-2602-4fe7-8fe4-8873e298c3ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435090608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap
.435090608
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.460999738
Short name T280
Test name
Test status
Simulation time 12287925302 ps
CPU time 29.38 seconds
Started Apr 02 01:40:57 PM PDT 24
Finished Apr 02 01:41:27 PM PDT 24
Peak memory 219464 kb
Host smart-cf62666f-c5be-420d-b220-4f3fafe38571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460999738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.460999738
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_upload.3820803130
Short name T188
Test name
Test status
Simulation time 999150130 ps
CPU time 9.93 seconds
Started Apr 02 01:41:05 PM PDT 24
Finished Apr 02 01:41:15 PM PDT 24
Peak memory 227648 kb
Host smart-c88da050-8c00-4e19-b495-3bfc41e661e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820803130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.3820803130
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.2768987211
Short name T179
Test name
Test status
Simulation time 10363178723 ps
CPU time 10.45 seconds
Started Apr 02 01:41:13 PM PDT 24
Finished Apr 02 01:41:24 PM PDT 24
Peak memory 222768 kb
Host smart-7a2c4e2b-940f-48ad-a00c-29dadc12bb1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768987211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.2768987211
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_upload.2828807397
Short name T245
Test name
Test status
Simulation time 459283148 ps
CPU time 2.24 seconds
Started Apr 02 01:41:13 PM PDT 24
Finished Apr 02 01:41:15 PM PDT 24
Peak memory 219144 kb
Host smart-c1e9c2d3-21d5-41e5-9205-8aa27f926e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828807397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.2828807397
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.255575797
Short name T210
Test name
Test status
Simulation time 126172753 ps
CPU time 2.18 seconds
Started Apr 02 01:41:24 PM PDT 24
Finished Apr 02 01:41:26 PM PDT 24
Peak memory 223256 kb
Host smart-d71c9711-e980-4966-bc80-cb9d74c37d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255575797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap
.255575797
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.2948024958
Short name T289
Test name
Test status
Simulation time 8796266046 ps
CPU time 132.75 seconds
Started Apr 02 01:41:48 PM PDT 24
Finished Apr 02 01:44:02 PM PDT 24
Peak memory 251936 kb
Host smart-ccfe7875-c68d-4874-a572-e7efb5a2722a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948024958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.2948024958
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.3204068665
Short name T100
Test name
Test status
Simulation time 207977004 ps
CPU time 5.14 seconds
Started Apr 02 01:41:44 PM PDT 24
Finished Apr 02 01:41:50 PM PDT 24
Peak memory 224624 kb
Host smart-e7a5fbb6-b910-401a-b060-58d037e6debc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204068665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.3204068665
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.745549191
Short name T338
Test name
Test status
Simulation time 16914109867 ps
CPU time 17.6 seconds
Started Apr 02 01:42:03 PM PDT 24
Finished Apr 02 01:42:20 PM PDT 24
Peak memory 232928 kb
Host smart-3461025e-d363-4da9-87c8-b8023006a661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745549191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap
.745549191
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.3086199949
Short name T305
Test name
Test status
Simulation time 7197279423 ps
CPU time 11.63 seconds
Started Apr 02 01:42:03 PM PDT 24
Finished Apr 02 01:42:15 PM PDT 24
Peak memory 241404 kb
Host smart-c3f5c292-7a5d-4335-a64f-aa1e8bb7b569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086199949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3086199949
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.1454841875
Short name T222
Test name
Test status
Simulation time 8439477962 ps
CPU time 8.4 seconds
Started Apr 02 01:42:16 PM PDT 24
Finished Apr 02 01:42:25 PM PDT 24
Peak memory 233160 kb
Host smart-ec64fdbf-757b-4cdd-b8ab-03a2cd6e7d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454841875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.1454841875
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.2641663849
Short name T252
Test name
Test status
Simulation time 17651646316 ps
CPU time 27.44 seconds
Started Apr 02 01:42:39 PM PDT 24
Finished Apr 02 01:43:07 PM PDT 24
Peak memory 233192 kb
Host smart-bc59970d-13f8-48b0-b8fc-2ce70d4d8031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641663849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.2641663849
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.3844854798
Short name T217
Test name
Test status
Simulation time 687555253 ps
CPU time 7.2 seconds
Started Apr 02 01:39:10 PM PDT 24
Finished Apr 02 01:39:17 PM PDT 24
Peak memory 223364 kb
Host smart-0967a879-bddc-4886-a956-6aff5ee095cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844854798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.3844854798
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.1842769035
Short name T286
Test name
Test status
Simulation time 47206650609 ps
CPU time 30.58 seconds
Started Apr 02 01:44:30 PM PDT 24
Finished Apr 02 01:45:01 PM PDT 24
Peak memory 219508 kb
Host smart-a2530b05-7996-4c85-9ebd-beb4ef216d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842769035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.1842769035
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.314669047
Short name T24
Test name
Test status
Simulation time 964205081 ps
CPU time 6.81 seconds
Started Apr 02 01:44:48 PM PDT 24
Finished Apr 02 01:44:55 PM PDT 24
Peak memory 218828 kb
Host smart-91064abc-8611-4c80-a65c-c3955dca6ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314669047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.314669047
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_intercept.2149814565
Short name T227
Test name
Test status
Simulation time 680434476 ps
CPU time 3.01 seconds
Started Apr 02 01:45:25 PM PDT 24
Finished Apr 02 01:45:28 PM PDT 24
Peak memory 219420 kb
Host smart-45485c0d-a928-4eb0-9adc-be748c0c11ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149814565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.2149814565
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_upload.3808524603
Short name T273
Test name
Test status
Simulation time 490507448 ps
CPU time 8.17 seconds
Started Apr 02 01:45:38 PM PDT 24
Finished Apr 02 01:45:47 PM PDT 24
Peak memory 232928 kb
Host smart-68d1e359-f263-452e-8d80-1c3a6d3d48fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808524603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.3808524603
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.1345436625
Short name T310
Test name
Test status
Simulation time 43711534 ps
CPU time 2.45 seconds
Started Apr 02 01:45:51 PM PDT 24
Finished Apr 02 01:45:54 PM PDT 24
Peak memory 223452 kb
Host smart-e3e6521f-fdcb-4f27-8198-c0379f48ce72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345436625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.1345436625
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.2095721667
Short name T333
Test name
Test status
Simulation time 571595311 ps
CPU time 6.38 seconds
Started Apr 02 01:39:14 PM PDT 24
Finished Apr 02 01:39:20 PM PDT 24
Peak memory 239108 kb
Host smart-a348e155-299b-4100-8bee-4747a5c16371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095721667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.2095721667
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.3849257037
Short name T290
Test name
Test status
Simulation time 5144811385 ps
CPU time 49.83 seconds
Started Apr 02 01:39:23 PM PDT 24
Finished Apr 02 01:40:13 PM PDT 24
Peak memory 233268 kb
Host smart-8c4f0004-e1ea-42a1-8a47-340e27b51eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849257037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.3849257037
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.2959722494
Short name T246
Test name
Test status
Simulation time 6292372673 ps
CPU time 10.58 seconds
Started Apr 02 01:39:34 PM PDT 24
Finished Apr 02 01:39:45 PM PDT 24
Peak memory 233164 kb
Host smart-c5028220-9a0c-49c9-8775-73256d84029e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959722494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.2959722494
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.1468992510
Short name T98
Test name
Test status
Simulation time 334001346 ps
CPU time 5.58 seconds
Started Apr 02 01:38:51 PM PDT 24
Finished Apr 02 01:38:56 PM PDT 24
Peak memory 222144 kb
Host smart-eb47cbf3-128a-4667-b2e6-a2347c74d21f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468992510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.1468992510
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1529310869
Short name T136
Test name
Test status
Simulation time 1302282932 ps
CPU time 20.34 seconds
Started Apr 02 12:28:00 PM PDT 24
Finished Apr 02 12:28:20 PM PDT 24
Peak memory 206848 kb
Host smart-15ec172d-de94-4131-bd26-1b770e7de01e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529310869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.1529310869
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.298323859
Short name T137
Test name
Test status
Simulation time 526733340 ps
CPU time 31.63 seconds
Started Apr 02 12:28:01 PM PDT 24
Finished Apr 02 12:28:33 PM PDT 24
Peak memory 206792 kb
Host smart-29e1f5b5-8bbc-4120-b7e0-275d4c32fe23
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298323859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_bit_bash.298323859
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2801500144
Short name T106
Test name
Test status
Simulation time 41701752 ps
CPU time 1.42 seconds
Started Apr 02 12:28:25 PM PDT 24
Finished Apr 02 12:28:26 PM PDT 24
Peak memory 206784 kb
Host smart-4cb3f25f-2107-45d7-8c6c-e2457513274f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801500144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.2801500144
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.730777554
Short name T750
Test name
Test status
Simulation time 457641474 ps
CPU time 1.63 seconds
Started Apr 02 12:27:53 PM PDT 24
Finished Apr 02 12:27:54 PM PDT 24
Peak memory 215300 kb
Host smart-c55e97d8-49e6-431e-a4ac-5f64ed40399d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730777554 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.730777554
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3507044993
Short name T790
Test name
Test status
Simulation time 50187812 ps
CPU time 1.72 seconds
Started Apr 02 12:28:06 PM PDT 24
Finished Apr 02 12:28:08 PM PDT 24
Peak memory 215112 kb
Host smart-2c95515e-bf06-4819-9d5c-cfc3d9268225
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507044993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.3
507044993
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1154008026
Short name T755
Test name
Test status
Simulation time 40325488 ps
CPU time 0.69 seconds
Started Apr 02 12:27:56 PM PDT 24
Finished Apr 02 12:27:57 PM PDT 24
Peak memory 203836 kb
Host smart-2377a2c7-e9a5-4eaf-bb12-055ac8a1b5d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154008026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.1
154008026
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1479479550
Short name T143
Test name
Test status
Simulation time 70428203 ps
CPU time 2.26 seconds
Started Apr 02 12:27:56 PM PDT 24
Finished Apr 02 12:27:58 PM PDT 24
Peak memory 215244 kb
Host smart-8766eb50-73f2-49d3-9c36-71cd1b5c6b79
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479479550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.1479479550
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3042719405
Short name T739
Test name
Test status
Simulation time 139998768 ps
CPU time 0.65 seconds
Started Apr 02 12:27:58 PM PDT 24
Finished Apr 02 12:27:59 PM PDT 24
Peak memory 203436 kb
Host smart-ac5dfdb1-268e-4809-b97c-385353b02110
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042719405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.3042719405
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2863959221
Short name T361
Test name
Test status
Simulation time 358458855 ps
CPU time 3.03 seconds
Started Apr 02 12:27:53 PM PDT 24
Finished Apr 02 12:27:56 PM PDT 24
Peak memory 215268 kb
Host smart-a84f90ba-a4d0-4662-aadf-00287126dddc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863959221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.2
863959221
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3320344335
Short name T841
Test name
Test status
Simulation time 753892873 ps
CPU time 6.56 seconds
Started Apr 02 12:27:53 PM PDT 24
Finished Apr 02 12:28:00 PM PDT 24
Peak memory 216020 kb
Host smart-a3e4dbb7-d091-400a-bbed-3a402dc46a6b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320344335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.3320344335
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3183564508
Short name T849
Test name
Test status
Simulation time 466834075 ps
CPU time 8.1 seconds
Started Apr 02 12:27:53 PM PDT 24
Finished Apr 02 12:28:01 PM PDT 24
Peak memory 206872 kb
Host smart-d13d70ab-cf5e-45d7-8a21-24cc864972b7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183564508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.3183564508
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.856230544
Short name T797
Test name
Test status
Simulation time 370305137 ps
CPU time 21.1 seconds
Started Apr 02 12:27:53 PM PDT 24
Finished Apr 02 12:28:15 PM PDT 24
Peak memory 215064 kb
Host smart-3c2db638-a6da-4707-8619-3cf1d396d8fa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856230544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_bit_bash.856230544
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2309081630
Short name T780
Test name
Test status
Simulation time 212078763 ps
CPU time 1.69 seconds
Started Apr 02 12:27:54 PM PDT 24
Finished Apr 02 12:27:56 PM PDT 24
Peak memory 215172 kb
Host smart-259bc94f-0a3e-4e3f-88be-fd5f515e5436
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309081630 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.2309081630
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.990528193
Short name T804
Test name
Test status
Simulation time 213347015 ps
CPU time 1.81 seconds
Started Apr 02 12:27:51 PM PDT 24
Finished Apr 02 12:27:53 PM PDT 24
Peak memory 206868 kb
Host smart-b74a614a-4910-40bb-862b-f1c82fb680e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990528193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.990528193
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1576074495
Short name T845
Test name
Test status
Simulation time 22320227 ps
CPU time 0.73 seconds
Started Apr 02 12:27:53 PM PDT 24
Finished Apr 02 12:27:54 PM PDT 24
Peak memory 203560 kb
Host smart-a8d5a217-5876-4e1b-b8c8-0e865d45e439
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576074495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.1
576074495
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1594677994
Short name T838
Test name
Test status
Simulation time 135513101 ps
CPU time 1.99 seconds
Started Apr 02 12:28:00 PM PDT 24
Finished Apr 02 12:28:02 PM PDT 24
Peak memory 215064 kb
Host smart-59ca7954-0ee4-40c2-ad1e-731d3ba44d04
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594677994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.1594677994
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3943968578
Short name T762
Test name
Test status
Simulation time 11058936 ps
CPU time 0.66 seconds
Started Apr 02 12:28:09 PM PDT 24
Finished Apr 02 12:28:10 PM PDT 24
Peak memory 203400 kb
Host smart-27bdc934-cedd-46df-b757-ae433ab7fd0f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943968578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.3943968578
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.4289784108
Short name T763
Test name
Test status
Simulation time 261620015 ps
CPU time 2.02 seconds
Started Apr 02 12:28:02 PM PDT 24
Finished Apr 02 12:28:05 PM PDT 24
Peak memory 215108 kb
Host smart-706f58af-68af-4e5b-980c-2149f93faccf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289784108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.4289784108
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1105023458
Short name T126
Test name
Test status
Simulation time 94986688 ps
CPU time 2.17 seconds
Started Apr 02 12:27:54 PM PDT 24
Finished Apr 02 12:27:57 PM PDT 24
Peak memory 218632 kb
Host smart-e579e40c-752a-4ec4-ace0-689040201e86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105023458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.1
105023458
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1326841343
Short name T362
Test name
Test status
Simulation time 2032610533 ps
CPU time 21.94 seconds
Started Apr 02 12:28:00 PM PDT 24
Finished Apr 02 12:28:22 PM PDT 24
Peak memory 215356 kb
Host smart-b249ade0-8e78-4da9-8937-d5a115b6f10c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326841343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.1326841343
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3398433136
Short name T747
Test name
Test status
Simulation time 493622603 ps
CPU time 3.75 seconds
Started Apr 02 12:28:36 PM PDT 24
Finished Apr 02 12:28:41 PM PDT 24
Peak memory 217344 kb
Host smart-aa5ec039-bead-4807-9265-b3f5d4e4d889
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398433136 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.3398433136
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.4157367080
Short name T145
Test name
Test status
Simulation time 112863288 ps
CPU time 1.23 seconds
Started Apr 02 12:27:54 PM PDT 24
Finished Apr 02 12:27:56 PM PDT 24
Peak memory 206860 kb
Host smart-0c01d1d8-67ab-4e68-8110-c73b434a33ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157367080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
4157367080
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1184037341
Short name T746
Test name
Test status
Simulation time 19819783 ps
CPU time 0.76 seconds
Started Apr 02 12:28:32 PM PDT 24
Finished Apr 02 12:28:33 PM PDT 24
Peak memory 203600 kb
Host smart-be5f99fd-2cb9-462b-ab73-66634741bf2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184037341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
1184037341
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.971699815
Short name T148
Test name
Test status
Simulation time 156909868 ps
CPU time 3.25 seconds
Started Apr 02 12:27:55 PM PDT 24
Finished Apr 02 12:27:58 PM PDT 24
Peak memory 215008 kb
Host smart-b765bb50-ddc8-4f99-a4e1-6106333db209
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971699815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.s
pi_device_same_csr_outstanding.971699815
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3026491351
Short name T131
Test name
Test status
Simulation time 68361673 ps
CPU time 2.58 seconds
Started Apr 02 12:27:59 PM PDT 24
Finished Apr 02 12:28:02 PM PDT 24
Peak memory 215300 kb
Host smart-560d4361-7879-4c3a-af7a-2ab2d1276549
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026491351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
3026491351
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1319922965
Short name T786
Test name
Test status
Simulation time 58685084 ps
CPU time 3.98 seconds
Started Apr 02 12:28:20 PM PDT 24
Finished Apr 02 12:28:24 PM PDT 24
Peak memory 216924 kb
Host smart-2b5e4035-1e7e-48e8-825e-8bc60a0aef22
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319922965 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.1319922965
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.4043364938
Short name T140
Test name
Test status
Simulation time 93787968 ps
CPU time 2.75 seconds
Started Apr 02 12:28:26 PM PDT 24
Finished Apr 02 12:28:29 PM PDT 24
Peak memory 215140 kb
Host smart-6cd6d55a-8ed7-46c2-9996-34a9a91a2c24
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043364938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
4043364938
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1547354966
Short name T752
Test name
Test status
Simulation time 23634578 ps
CPU time 0.72 seconds
Started Apr 02 12:27:54 PM PDT 24
Finished Apr 02 12:27:55 PM PDT 24
Peak memory 203796 kb
Host smart-ceb317ae-1661-4aea-9fe8-4611901f045a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547354966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
1547354966
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.790573482
Short name T844
Test name
Test status
Simulation time 274305977 ps
CPU time 3.11 seconds
Started Apr 02 12:27:54 PM PDT 24
Finished Apr 02 12:27:57 PM PDT 24
Peak memory 214960 kb
Host smart-103cf55a-7d7e-4cd8-9815-312078459da5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790573482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.s
pi_device_same_csr_outstanding.790573482
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2554577061
Short name T787
Test name
Test status
Simulation time 251376128 ps
CPU time 4.55 seconds
Started Apr 02 12:27:52 PM PDT 24
Finished Apr 02 12:27:56 PM PDT 24
Peak memory 216184 kb
Host smart-c9818e29-653f-47c4-9bb0-3d2addaa687e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554577061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
2554577061
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2523848374
Short name T847
Test name
Test status
Simulation time 433107277 ps
CPU time 6.85 seconds
Started Apr 02 12:27:54 PM PDT 24
Finished Apr 02 12:28:01 PM PDT 24
Peak memory 215428 kb
Host smart-6cd6c499-0fef-4e34-9170-67196294df22
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523848374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.2523848374
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.4033015891
Short name T823
Test name
Test status
Simulation time 931070281 ps
CPU time 3.75 seconds
Started Apr 02 12:27:54 PM PDT 24
Finished Apr 02 12:27:58 PM PDT 24
Peak memory 216756 kb
Host smart-8541d180-7115-4f9d-88b0-c71261cfe971
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033015891 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.4033015891
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3681314318
Short name T835
Test name
Test status
Simulation time 50053833 ps
CPU time 1.81 seconds
Started Apr 02 12:28:26 PM PDT 24
Finished Apr 02 12:28:27 PM PDT 24
Peak memory 206928 kb
Host smart-fe118496-2e4c-4d6f-97c9-1b846514a7ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681314318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
3681314318
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2280521886
Short name T753
Test name
Test status
Simulation time 15555889 ps
CPU time 0.76 seconds
Started Apr 02 12:28:22 PM PDT 24
Finished Apr 02 12:28:23 PM PDT 24
Peak memory 203876 kb
Host smart-bbb57bd3-81de-439e-9848-4c73ef527960
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280521886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
2280521886
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.775883179
Short name T149
Test name
Test status
Simulation time 1098180478 ps
CPU time 3.77 seconds
Started Apr 02 12:27:58 PM PDT 24
Finished Apr 02 12:28:02 PM PDT 24
Peak memory 215052 kb
Host smart-4851fb53-7d45-482b-bafd-611fa2cf3ce9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775883179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.s
pi_device_same_csr_outstanding.775883179
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1593560418
Short name T767
Test name
Test status
Simulation time 1216443131 ps
CPU time 7.73 seconds
Started Apr 02 12:28:19 PM PDT 24
Finished Apr 02 12:28:27 PM PDT 24
Peak memory 215240 kb
Host smart-141e5a95-08df-488b-80df-5611e035ac42
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593560418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.1593560418
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2398204205
Short name T807
Test name
Test status
Simulation time 89232032 ps
CPU time 2.64 seconds
Started Apr 02 12:27:56 PM PDT 24
Finished Apr 02 12:27:59 PM PDT 24
Peak memory 216888 kb
Host smart-01c3a232-872b-4458-bb08-003a8e56a654
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398204205 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.2398204205
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1578629465
Short name T822
Test name
Test status
Simulation time 23128562 ps
CPU time 1.37 seconds
Started Apr 02 12:28:27 PM PDT 24
Finished Apr 02 12:28:28 PM PDT 24
Peak memory 219360 kb
Host smart-4bf533fd-80c3-4de1-85fb-8bf39146ea5d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578629465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
1578629465
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.92254351
Short name T778
Test name
Test status
Simulation time 34163819 ps
CPU time 0.72 seconds
Started Apr 02 12:28:22 PM PDT 24
Finished Apr 02 12:28:23 PM PDT 24
Peak memory 203544 kb
Host smart-a05e4ae2-e24d-4486-86a2-d6990565c7b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92254351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.92254351
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3813938544
Short name T846
Test name
Test status
Simulation time 82577089 ps
CPU time 1.95 seconds
Started Apr 02 12:27:56 PM PDT 24
Finished Apr 02 12:27:58 PM PDT 24
Peak memory 215040 kb
Host smart-27904410-4bef-4687-9a68-1e74863ac034
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813938544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.3813938544
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2093315281
Short name T132
Test name
Test status
Simulation time 1742388590 ps
CPU time 21.93 seconds
Started Apr 02 12:28:24 PM PDT 24
Finished Apr 02 12:28:46 PM PDT 24
Peak memory 223200 kb
Host smart-267ef6d1-a0c6-48b6-8d84-0275e8dd0fb6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093315281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.2093315281
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.510051225
Short name T785
Test name
Test status
Simulation time 832231112 ps
CPU time 3.63 seconds
Started Apr 02 12:28:26 PM PDT 24
Finished Apr 02 12:28:30 PM PDT 24
Peak memory 217008 kb
Host smart-cdb2b2bd-504f-4a56-a9b5-7b45d611a007
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510051225 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.510051225
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2152161765
Short name T138
Test name
Test status
Simulation time 279102225 ps
CPU time 2.2 seconds
Started Apr 02 12:28:31 PM PDT 24
Finished Apr 02 12:28:33 PM PDT 24
Peak memory 206888 kb
Host smart-c76dfda4-3361-4786-8180-cdf7e64cf2a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152161765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
2152161765
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.4077205631
Short name T759
Test name
Test status
Simulation time 22485846 ps
CPU time 0.77 seconds
Started Apr 02 12:28:31 PM PDT 24
Finished Apr 02 12:28:32 PM PDT 24
Peak memory 203576 kb
Host smart-1c903b94-b6ee-4d1d-8002-043d4191a03e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077205631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
4077205631
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3869921225
Short name T152
Test name
Test status
Simulation time 147771799 ps
CPU time 2.93 seconds
Started Apr 02 12:27:54 PM PDT 24
Finished Apr 02 12:27:57 PM PDT 24
Peak memory 215080 kb
Host smart-931cc3e1-755b-4d2a-ada1-042069d1f5bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869921225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.3869921225
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.954259103
Short name T776
Test name
Test status
Simulation time 103655646 ps
CPU time 1.79 seconds
Started Apr 02 12:27:59 PM PDT 24
Finished Apr 02 12:28:00 PM PDT 24
Peak memory 216052 kb
Host smart-5744dc8c-0901-450d-99e3-5cfce3231d70
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954259103 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.954259103
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3488735003
Short name T147
Test name
Test status
Simulation time 148599176 ps
CPU time 1.76 seconds
Started Apr 02 12:27:57 PM PDT 24
Finished Apr 02 12:27:59 PM PDT 24
Peak memory 215040 kb
Host smart-bab81530-a77a-4775-be40-06c54e61c450
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488735003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
3488735003
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.344798553
Short name T761
Test name
Test status
Simulation time 29025809 ps
CPU time 0.66 seconds
Started Apr 02 12:27:57 PM PDT 24
Finished Apr 02 12:27:58 PM PDT 24
Peak memory 203636 kb
Host smart-a25025f2-f0b0-40c7-9541-62da35fef2a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344798553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.344798553
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1460235697
Short name T760
Test name
Test status
Simulation time 106125887 ps
CPU time 1.75 seconds
Started Apr 02 12:28:01 PM PDT 24
Finished Apr 02 12:28:03 PM PDT 24
Peak memory 215040 kb
Host smart-a869d638-fe28-4af1-8de3-0a9138605876
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460235697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.1460235697
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3401344522
Short name T824
Test name
Test status
Simulation time 42372712 ps
CPU time 2.55 seconds
Started Apr 02 12:27:58 PM PDT 24
Finished Apr 02 12:28:00 PM PDT 24
Peak memory 216284 kb
Host smart-f8770e86-e50d-4603-ad55-400ab826cd53
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401344522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
3401344522
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3557539965
Short name T771
Test name
Test status
Simulation time 594551553 ps
CPU time 3.44 seconds
Started Apr 02 12:27:58 PM PDT 24
Finished Apr 02 12:28:01 PM PDT 24
Peak memory 216576 kb
Host smart-f7f8256f-b823-4ce7-8cea-a51f24ceca52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557539965 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.3557539965
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.3302259147
Short name T157
Test name
Test status
Simulation time 36499437 ps
CPU time 1.2 seconds
Started Apr 02 12:27:51 PM PDT 24
Finished Apr 02 12:27:52 PM PDT 24
Peak memory 215080 kb
Host smart-6bc9a842-1aae-45f2-b78b-e49117b97927
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302259147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
3302259147
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.720027522
Short name T741
Test name
Test status
Simulation time 11408990 ps
CPU time 0.77 seconds
Started Apr 02 12:27:49 PM PDT 24
Finished Apr 02 12:27:50 PM PDT 24
Peak memory 203508 kb
Host smart-b74674e8-e673-4c43-87d3-24054d76a7d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720027522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.720027522
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2110855790
Short name T825
Test name
Test status
Simulation time 111800821 ps
CPU time 1.8 seconds
Started Apr 02 12:27:59 PM PDT 24
Finished Apr 02 12:28:01 PM PDT 24
Peak memory 215088 kb
Host smart-820b2938-c72e-4364-9f46-1adb572ae224
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110855790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.2110855790
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.847119241
Short name T125
Test name
Test status
Simulation time 158835866 ps
CPU time 4.42 seconds
Started Apr 02 12:27:57 PM PDT 24
Finished Apr 02 12:28:02 PM PDT 24
Peak memory 215208 kb
Host smart-937ab0c5-5e28-460f-91b9-70e764b79a36
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847119241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.847119241
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3957844535
Short name T133
Test name
Test status
Simulation time 573192217 ps
CPU time 13.44 seconds
Started Apr 02 12:27:53 PM PDT 24
Finished Apr 02 12:28:06 PM PDT 24
Peak memory 215104 kb
Host smart-2e0d471c-6160-46d5-903d-d05d1e8c73c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957844535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.3957844535
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2519850288
Short name T813
Test name
Test status
Simulation time 552126893 ps
CPU time 3.37 seconds
Started Apr 02 12:27:58 PM PDT 24
Finished Apr 02 12:28:01 PM PDT 24
Peak memory 216756 kb
Host smart-c07c0899-cc27-4562-a277-b75c4a88f03b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519850288 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.2519850288
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.4182204402
Short name T141
Test name
Test status
Simulation time 469751382 ps
CPU time 2.27 seconds
Started Apr 02 12:28:00 PM PDT 24
Finished Apr 02 12:28:02 PM PDT 24
Peak memory 206856 kb
Host smart-5a31463a-e9fa-46cf-9435-0a31f6525b47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182204402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
4182204402
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1163861612
Short name T818
Test name
Test status
Simulation time 14450100 ps
CPU time 0.7 seconds
Started Apr 02 12:27:53 PM PDT 24
Finished Apr 02 12:27:53 PM PDT 24
Peak memory 203500 kb
Host smart-33bc86cd-0a30-4396-82f7-3fa730b7626a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163861612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
1163861612
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.317860040
Short name T154
Test name
Test status
Simulation time 796044900 ps
CPU time 4.11 seconds
Started Apr 02 12:28:00 PM PDT 24
Finished Apr 02 12:28:04 PM PDT 24
Peak memory 215132 kb
Host smart-f9120b7a-7745-4944-a2e6-471326167f73
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317860040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.s
pi_device_same_csr_outstanding.317860040
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2199414635
Short name T124
Test name
Test status
Simulation time 38059115 ps
CPU time 1.4 seconds
Started Apr 02 12:27:54 PM PDT 24
Finished Apr 02 12:27:56 PM PDT 24
Peak memory 215168 kb
Host smart-d89d06c9-c46b-485c-8c28-555d83da3a9a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199414635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
2199414635
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1375713974
Short name T162
Test name
Test status
Simulation time 710610723 ps
CPU time 15.2 seconds
Started Apr 02 12:27:54 PM PDT 24
Finished Apr 02 12:28:09 PM PDT 24
Peak memory 215188 kb
Host smart-cc8df385-baf4-4701-8da3-87a20a9ab384
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375713974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.1375713974
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2867984258
Short name T853
Test name
Test status
Simulation time 133951959 ps
CPU time 3.77 seconds
Started Apr 02 12:28:04 PM PDT 24
Finished Apr 02 12:28:08 PM PDT 24
Peak memory 217872 kb
Host smart-720c1f7b-d57c-46fd-8dfd-38ba745be083
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867984258 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.2867984258
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.73423205
Short name T836
Test name
Test status
Simulation time 137774824 ps
CPU time 2.39 seconds
Started Apr 02 12:28:33 PM PDT 24
Finished Apr 02 12:28:35 PM PDT 24
Peak memory 215012 kb
Host smart-58f05e51-c790-4e27-9d6a-65526d7b30dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73423205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.73423205
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2548052906
Short name T852
Test name
Test status
Simulation time 25324761 ps
CPU time 0.71 seconds
Started Apr 02 12:27:52 PM PDT 24
Finished Apr 02 12:27:53 PM PDT 24
Peak memory 203620 kb
Host smart-443c6fbe-29ef-478b-b71c-8f90d428eeba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548052906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
2548052906
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3803160883
Short name T156
Test name
Test status
Simulation time 100291717 ps
CPU time 1.82 seconds
Started Apr 02 12:28:01 PM PDT 24
Finished Apr 02 12:28:04 PM PDT 24
Peak memory 215104 kb
Host smart-3e4d895d-e6bb-4bb8-b3b8-9ba8d9be2184
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803160883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.3803160883
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1092620488
Short name T127
Test name
Test status
Simulation time 704555876 ps
CPU time 3.9 seconds
Started Apr 02 12:28:44 PM PDT 24
Finished Apr 02 12:28:48 PM PDT 24
Peak memory 215240 kb
Host smart-989c0c33-a82e-4c98-934f-9bdbcadb2e0b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092620488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
1092620488
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3670774807
Short name T36
Test name
Test status
Simulation time 580802485 ps
CPU time 14.16 seconds
Started Apr 02 12:28:30 PM PDT 24
Finished Apr 02 12:28:44 PM PDT 24
Peak memory 215352 kb
Host smart-8316336e-a7ed-47e1-8717-9d3218fd430a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670774807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.3670774807
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1881525084
Short name T793
Test name
Test status
Simulation time 55348498 ps
CPU time 1.84 seconds
Started Apr 02 12:28:30 PM PDT 24
Finished Apr 02 12:28:32 PM PDT 24
Peak memory 216152 kb
Host smart-f558d661-1867-4401-98e7-c0ce51277759
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881525084 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.1881525084
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3665952069
Short name T139
Test name
Test status
Simulation time 100240073 ps
CPU time 2.5 seconds
Started Apr 02 12:28:32 PM PDT 24
Finished Apr 02 12:28:34 PM PDT 24
Peak memory 215112 kb
Host smart-39bf8c8e-f34d-4930-9d9d-f5c2422dcc29
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665952069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
3665952069
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.3684016013
Short name T165
Test name
Test status
Simulation time 18981618 ps
CPU time 0.8 seconds
Started Apr 02 12:28:28 PM PDT 24
Finished Apr 02 12:28:29 PM PDT 24
Peak memory 203576 kb
Host smart-e5149540-53ea-424e-8553-e1304bf5ea0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684016013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
3684016013
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.478671896
Short name T828
Test name
Test status
Simulation time 106946643 ps
CPU time 2.81 seconds
Started Apr 02 12:28:30 PM PDT 24
Finished Apr 02 12:28:33 PM PDT 24
Peak memory 215048 kb
Host smart-97c87e53-46b3-40e0-b154-f61e548cddad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478671896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.s
pi_device_same_csr_outstanding.478671896
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.880027429
Short name T796
Test name
Test status
Simulation time 112000304 ps
CPU time 3.33 seconds
Started Apr 02 12:28:01 PM PDT 24
Finished Apr 02 12:28:05 PM PDT 24
Peak memory 215208 kb
Host smart-d43c9245-e6d8-46c0-8a8f-b39e8408e147
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880027429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.880027429
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1495639630
Short name T128
Test name
Test status
Simulation time 236897452 ps
CPU time 7.52 seconds
Started Apr 02 12:28:23 PM PDT 24
Finished Apr 02 12:28:30 PM PDT 24
Peak memory 206924 kb
Host smart-e87491d9-7688-402e-98a0-e7185cb6730a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495639630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.1495639630
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3836721520
Short name T144
Test name
Test status
Simulation time 772979127 ps
CPU time 30.4 seconds
Started Apr 02 12:27:58 PM PDT 24
Finished Apr 02 12:28:33 PM PDT 24
Peak memory 206904 kb
Host smart-fbb7124b-ab36-4da4-8de2-e737f546c4d7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836721520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.3836721520
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1924972356
Short name T107
Test name
Test status
Simulation time 78553843 ps
CPU time 1.36 seconds
Started Apr 02 12:28:12 PM PDT 24
Finished Apr 02 12:28:13 PM PDT 24
Peak memory 206880 kb
Host smart-9fdddbac-0a97-4acf-a10e-2fc10074dd4f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924972356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.1924972356
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.728896491
Short name T118
Test name
Test status
Simulation time 53355004 ps
CPU time 1.88 seconds
Started Apr 02 12:27:53 PM PDT 24
Finished Apr 02 12:27:55 PM PDT 24
Peak memory 215156 kb
Host smart-1bae04de-aa3f-46d8-9a47-5724368acb79
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728896491 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.728896491
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3128274799
Short name T809
Test name
Test status
Simulation time 35526154 ps
CPU time 1.32 seconds
Started Apr 02 12:27:54 PM PDT 24
Finished Apr 02 12:27:56 PM PDT 24
Peak memory 215052 kb
Host smart-36ff0cab-149d-421a-9711-4354d1b81c97
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128274799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.3
128274799
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.211827610
Short name T764
Test name
Test status
Simulation time 17771767 ps
CPU time 0.74 seconds
Started Apr 02 12:27:55 PM PDT 24
Finished Apr 02 12:27:56 PM PDT 24
Peak memory 203528 kb
Host smart-e0180f8b-2957-4af5-be42-6eb33a66c871
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211827610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.211827610
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3538274137
Short name T814
Test name
Test status
Simulation time 81332212 ps
CPU time 1.51 seconds
Started Apr 02 12:27:54 PM PDT 24
Finished Apr 02 12:27:55 PM PDT 24
Peak memory 215128 kb
Host smart-dcab85aa-036e-4678-98f3-af95350b522d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538274137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.3538274137
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1364517659
Short name T812
Test name
Test status
Simulation time 19727886 ps
CPU time 0.69 seconds
Started Apr 02 12:27:57 PM PDT 24
Finished Apr 02 12:27:58 PM PDT 24
Peak memory 203396 kb
Host smart-a44be907-40a2-4338-9694-5640f162def8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364517659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.1364517659
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3981155389
Short name T765
Test name
Test status
Simulation time 27774041 ps
CPU time 1.63 seconds
Started Apr 02 12:27:56 PM PDT 24
Finished Apr 02 12:27:58 PM PDT 24
Peak memory 215116 kb
Host smart-db78ef55-6d1a-4b6e-b508-27f77cf7c827
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981155389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.3981155389
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2139196124
Short name T791
Test name
Test status
Simulation time 59722508 ps
CPU time 1.82 seconds
Started Apr 02 12:27:57 PM PDT 24
Finished Apr 02 12:27:59 PM PDT 24
Peak memory 215176 kb
Host smart-9c075427-d9db-46f3-a47d-3dc3c590d425
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139196124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.2
139196124
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3319479643
Short name T366
Test name
Test status
Simulation time 107655396 ps
CPU time 6.16 seconds
Started Apr 02 12:27:58 PM PDT 24
Finished Apr 02 12:28:04 PM PDT 24
Peak memory 221944 kb
Host smart-152bb703-7150-41aa-99fe-76d045063558
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319479643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.3319479643
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.385021780
Short name T743
Test name
Test status
Simulation time 17545240 ps
CPU time 0.74 seconds
Started Apr 02 12:27:57 PM PDT 24
Finished Apr 02 12:27:58 PM PDT 24
Peak memory 203584 kb
Host smart-5ba7a569-2475-41eb-b8c6-21f4eb99c06b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385021780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.385021780
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3071430266
Short name T782
Test name
Test status
Simulation time 42750668 ps
CPU time 0.72 seconds
Started Apr 02 12:27:53 PM PDT 24
Finished Apr 02 12:27:54 PM PDT 24
Peak memory 203568 kb
Host smart-569dfb12-4ac0-49cb-be83-42872a284b71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071430266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
3071430266
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2567895121
Short name T839
Test name
Test status
Simulation time 41252474 ps
CPU time 0.65 seconds
Started Apr 02 12:28:01 PM PDT 24
Finished Apr 02 12:28:02 PM PDT 24
Peak memory 203516 kb
Host smart-59dc81d2-6816-4d3d-8587-843ca253d8ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567895121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
2567895121
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.3287066085
Short name T784
Test name
Test status
Simulation time 54085717 ps
CPU time 0.66 seconds
Started Apr 02 12:27:57 PM PDT 24
Finished Apr 02 12:27:58 PM PDT 24
Peak memory 203972 kb
Host smart-46888bbf-d271-4d51-88d1-93f119501a7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287066085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
3287066085
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1162794486
Short name T810
Test name
Test status
Simulation time 70619269 ps
CPU time 0.73 seconds
Started Apr 02 12:27:55 PM PDT 24
Finished Apr 02 12:27:56 PM PDT 24
Peak memory 203584 kb
Host smart-17cd1679-7924-411a-91ac-b24e2adef517
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162794486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
1162794486
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3689065039
Short name T831
Test name
Test status
Simulation time 47143723 ps
CPU time 0.78 seconds
Started Apr 02 12:27:55 PM PDT 24
Finished Apr 02 12:27:56 PM PDT 24
Peak memory 203500 kb
Host smart-532b49da-c318-49d3-80d7-6a49c78974d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689065039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
3689065039
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.264694600
Short name T816
Test name
Test status
Simulation time 33195401 ps
CPU time 0.73 seconds
Started Apr 02 12:27:52 PM PDT 24
Finished Apr 02 12:27:52 PM PDT 24
Peak memory 203484 kb
Host smart-d4608646-3c26-40dc-b261-291d075b5913
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264694600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.264694600
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3191090533
Short name T758
Test name
Test status
Simulation time 31768033 ps
CPU time 0.79 seconds
Started Apr 02 12:27:53 PM PDT 24
Finished Apr 02 12:27:54 PM PDT 24
Peak memory 203560 kb
Host smart-cdfc9533-7872-4ab6-84cc-00da92da2268
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191090533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
3191090533
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.463905979
Short name T781
Test name
Test status
Simulation time 33103055 ps
CPU time 0.7 seconds
Started Apr 02 12:27:57 PM PDT 24
Finished Apr 02 12:27:58 PM PDT 24
Peak memory 203544 kb
Host smart-df6444c6-7426-40bc-9f5f-c7e0bdf3d6b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463905979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.463905979
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2075085050
Short name T768
Test name
Test status
Simulation time 50921482 ps
CPU time 0.71 seconds
Started Apr 02 12:27:56 PM PDT 24
Finished Apr 02 12:27:57 PM PDT 24
Peak memory 203580 kb
Host smart-176589cb-85a7-4ae8-8e52-1bb9030a26f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075085050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
2075085050
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1015422057
Short name T802
Test name
Test status
Simulation time 9940913795 ps
CPU time 22.07 seconds
Started Apr 02 12:27:56 PM PDT 24
Finished Apr 02 12:28:28 PM PDT 24
Peak memory 216244 kb
Host smart-499d85ad-62e3-46b4-9979-ce2f32d40d04
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015422057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.1015422057
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1545797514
Short name T744
Test name
Test status
Simulation time 1499173864 ps
CPU time 11.61 seconds
Started Apr 02 12:28:01 PM PDT 24
Finished Apr 02 12:28:13 PM PDT 24
Peak memory 206848 kb
Host smart-141c1d0d-b5b5-442e-9340-b441deaf9f62
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545797514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.1545797514
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1515532325
Short name T827
Test name
Test status
Simulation time 100553310 ps
CPU time 1.1 seconds
Started Apr 02 12:27:54 PM PDT 24
Finished Apr 02 12:28:00 PM PDT 24
Peak memory 206828 kb
Host smart-9846d20d-c072-42d7-a5fe-8363f5f26030
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515532325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.1515532325
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2481577889
Short name T163
Test name
Test status
Simulation time 344744011 ps
CPU time 2.82 seconds
Started Apr 02 12:27:55 PM PDT 24
Finished Apr 02 12:27:58 PM PDT 24
Peak memory 216128 kb
Host smart-7f2ff6b1-5525-4415-896f-4d8e3cab4443
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481577889 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.2481577889
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1182234728
Short name T842
Test name
Test status
Simulation time 88332134 ps
CPU time 1.7 seconds
Started Apr 02 12:27:59 PM PDT 24
Finished Apr 02 12:28:01 PM PDT 24
Peak memory 206848 kb
Host smart-b7972907-cd90-42fe-8fcc-dd269bdf0b61
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182234728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.1
182234728
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3476818945
Short name T821
Test name
Test status
Simulation time 47065874 ps
CPU time 0.75 seconds
Started Apr 02 12:28:00 PM PDT 24
Finished Apr 02 12:28:06 PM PDT 24
Peak memory 203880 kb
Host smart-9b6c2b7e-7277-4a4a-8270-44471f22a4bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476818945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.3
476818945
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2519494752
Short name T146
Test name
Test status
Simulation time 18794579 ps
CPU time 1.38 seconds
Started Apr 02 12:28:19 PM PDT 24
Finished Apr 02 12:28:21 PM PDT 24
Peak memory 215060 kb
Host smart-11be1e8f-f8b7-49b2-9a32-6fde762e5183
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519494752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.2519494752
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1091450529
Short name T754
Test name
Test status
Simulation time 177214362 ps
CPU time 0.63 seconds
Started Apr 02 12:28:00 PM PDT 24
Finished Apr 02 12:28:00 PM PDT 24
Peak memory 203400 kb
Host smart-66c5b3c7-7e6f-4fd4-b53f-e378b7984640
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091450529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.1091450529
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2346647512
Short name T788
Test name
Test status
Simulation time 353728627 ps
CPU time 3.96 seconds
Started Apr 02 12:28:18 PM PDT 24
Finished Apr 02 12:28:22 PM PDT 24
Peak memory 215068 kb
Host smart-2fa69fcb-3363-4582-993e-d778b100084b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346647512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.2346647512
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.628850937
Short name T829
Test name
Test status
Simulation time 21504096 ps
CPU time 1.52 seconds
Started Apr 02 12:27:54 PM PDT 24
Finished Apr 02 12:27:55 PM PDT 24
Peak memory 215168 kb
Host smart-36fb903d-9f14-4bff-850b-19fc2964bcb4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628850937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.628850937
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3494027830
Short name T364
Test name
Test status
Simulation time 277965914 ps
CPU time 7.71 seconds
Started Apr 02 12:27:53 PM PDT 24
Finished Apr 02 12:28:01 PM PDT 24
Peak memory 214988 kb
Host smart-645cfa35-b61e-4604-b86b-4f8a2a9c8d1c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494027830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.3494027830
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.152263666
Short name T830
Test name
Test status
Simulation time 35408325 ps
CPU time 0.73 seconds
Started Apr 02 12:27:56 PM PDT 24
Finished Apr 02 12:27:56 PM PDT 24
Peak memory 203676 kb
Host smart-02675962-3d9b-498c-96f7-dc8cd465c5c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152263666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.152263666
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.2644450934
Short name T749
Test name
Test status
Simulation time 38807470 ps
CPU time 0.69 seconds
Started Apr 02 12:27:56 PM PDT 24
Finished Apr 02 12:27:57 PM PDT 24
Peak memory 203864 kb
Host smart-65838a5b-d620-446c-996d-5e5731b52619
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644450934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
2644450934
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.1533328692
Short name T751
Test name
Test status
Simulation time 15150129 ps
CPU time 0.76 seconds
Started Apr 02 12:28:30 PM PDT 24
Finished Apr 02 12:28:31 PM PDT 24
Peak memory 203536 kb
Host smart-dd0ccdb0-7407-40be-86bc-380745c15caf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533328692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
1533328692
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.343358520
Short name T777
Test name
Test status
Simulation time 39266576 ps
CPU time 0.72 seconds
Started Apr 02 12:27:54 PM PDT 24
Finished Apr 02 12:27:55 PM PDT 24
Peak memory 203512 kb
Host smart-69baa057-db07-4a8a-b431-f810d3472b27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343358520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.343358520
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.693880394
Short name T748
Test name
Test status
Simulation time 22483086 ps
CPU time 0.73 seconds
Started Apr 02 12:28:28 PM PDT 24
Finished Apr 02 12:28:29 PM PDT 24
Peak memory 203880 kb
Host smart-7003fe3c-24bc-442e-80b4-e2a650a12d23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693880394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.693880394
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.4133859130
Short name T789
Test name
Test status
Simulation time 14005061 ps
CPU time 0.72 seconds
Started Apr 02 12:27:56 PM PDT 24
Finished Apr 02 12:27:57 PM PDT 24
Peak memory 203600 kb
Host smart-a3723401-028e-45f0-9003-ab315e4e4e6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133859130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
4133859130
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2217134507
Short name T757
Test name
Test status
Simulation time 44397778 ps
CPU time 0.76 seconds
Started Apr 02 12:28:01 PM PDT 24
Finished Apr 02 12:28:02 PM PDT 24
Peak memory 203560 kb
Host smart-4ffa70ab-d449-4dfe-988e-f68028dc6d81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217134507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
2217134507
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2735399269
Short name T738
Test name
Test status
Simulation time 39574125 ps
CPU time 0.7 seconds
Started Apr 02 12:28:32 PM PDT 24
Finished Apr 02 12:28:34 PM PDT 24
Peak memory 203512 kb
Host smart-931b0c9a-ba35-4041-9d4d-b2d740175913
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735399269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
2735399269
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2165763246
Short name T740
Test name
Test status
Simulation time 21629865 ps
CPU time 0.69 seconds
Started Apr 02 12:28:19 PM PDT 24
Finished Apr 02 12:28:19 PM PDT 24
Peak memory 203540 kb
Host smart-eea49b15-93a3-4fba-8328-8c4d20d673d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165763246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
2165763246
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1156594823
Short name T826
Test name
Test status
Simulation time 20941105 ps
CPU time 0.7 seconds
Started Apr 02 12:28:06 PM PDT 24
Finished Apr 02 12:28:07 PM PDT 24
Peak memory 203548 kb
Host smart-49507704-d7e5-4654-abc7-f4ed149f6ac7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156594823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
1156594823
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3718880803
Short name T815
Test name
Test status
Simulation time 835214576 ps
CPU time 14.3 seconds
Started Apr 02 12:27:50 PM PDT 24
Finished Apr 02 12:28:04 PM PDT 24
Peak memory 215068 kb
Host smart-56ab08b2-7766-4927-abc7-2bda8a57dd05
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718880803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.3718880803
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2360592288
Short name T756
Test name
Test status
Simulation time 6222465370 ps
CPU time 36.37 seconds
Started Apr 02 12:27:56 PM PDT 24
Finished Apr 02 12:28:33 PM PDT 24
Peak memory 206968 kb
Host smart-195ddbd0-248c-475a-861b-f19c7401c58d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360592288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.2360592288
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3632112997
Short name T105
Test name
Test status
Simulation time 176701922 ps
CPU time 1.12 seconds
Started Apr 02 12:27:55 PM PDT 24
Finished Apr 02 12:27:56 PM PDT 24
Peak memory 216012 kb
Host smart-88de2681-a4d9-4e58-a036-365232f1eb53
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632112997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.3632112997
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.4043542728
Short name T34
Test name
Test status
Simulation time 315215545 ps
CPU time 2.58 seconds
Started Apr 02 12:28:01 PM PDT 24
Finished Apr 02 12:28:04 PM PDT 24
Peak memory 216144 kb
Host smart-cfde6be9-bac4-4b86-be17-1094cac1c676
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043542728 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.4043542728
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1573678674
Short name T834
Test name
Test status
Simulation time 43480500 ps
CPU time 1.31 seconds
Started Apr 02 12:27:53 PM PDT 24
Finished Apr 02 12:27:54 PM PDT 24
Peak memory 215048 kb
Host smart-2edaabae-4702-4160-8bc8-ffa786d62708
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573678674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.1
573678674
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3351972453
Short name T817
Test name
Test status
Simulation time 21991426 ps
CPU time 0.69 seconds
Started Apr 02 12:27:57 PM PDT 24
Finished Apr 02 12:27:58 PM PDT 24
Peak memory 203532 kb
Host smart-dab11749-b247-4e47-bc33-a500be626c30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351972453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.3
351972453
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.749833333
Short name T819
Test name
Test status
Simulation time 28486394 ps
CPU time 2.04 seconds
Started Apr 02 12:28:17 PM PDT 24
Finished Apr 02 12:28:19 PM PDT 24
Peak memory 215200 kb
Host smart-7b879d2d-2c45-42e1-b6e3-cf64705cf63e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749833333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_
device_mem_partial_access.749833333
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.831963966
Short name T799
Test name
Test status
Simulation time 11198765 ps
CPU time 0.65 seconds
Started Apr 02 12:27:52 PM PDT 24
Finished Apr 02 12:27:53 PM PDT 24
Peak memory 203388 kb
Host smart-468b9c51-973f-4d3a-8354-86c6b047ef5f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831963966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem
_walk.831963966
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3394367924
Short name T774
Test name
Test status
Simulation time 540678159 ps
CPU time 1.79 seconds
Started Apr 02 12:28:01 PM PDT 24
Finished Apr 02 12:28:03 PM PDT 24
Peak memory 214976 kb
Host smart-ad0a87e0-b79d-4c85-9d24-f2be45ebe929
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394367924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.3394367924
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2867371458
Short name T843
Test name
Test status
Simulation time 66798653 ps
CPU time 2.13 seconds
Started Apr 02 12:28:20 PM PDT 24
Finished Apr 02 12:28:22 PM PDT 24
Peak memory 215276 kb
Host smart-0f5ee260-e9de-478f-80f5-cc9333008fce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867371458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2
867371458
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2246776860
Short name T848
Test name
Test status
Simulation time 613611984 ps
CPU time 15.11 seconds
Started Apr 02 12:28:01 PM PDT 24
Finished Apr 02 12:28:17 PM PDT 24
Peak memory 215084 kb
Host smart-68489c6c-7cc4-4963-8d45-d258d9a3a378
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246776860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.2246776860
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1525692984
Short name T166
Test name
Test status
Simulation time 20262789 ps
CPU time 0.77 seconds
Started Apr 02 12:27:55 PM PDT 24
Finished Apr 02 12:27:56 PM PDT 24
Peak memory 203888 kb
Host smart-56d9b2f0-60f4-4154-8500-6d86615e852c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525692984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
1525692984
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1848959661
Short name T770
Test name
Test status
Simulation time 16523102 ps
CPU time 0.75 seconds
Started Apr 02 12:28:00 PM PDT 24
Finished Apr 02 12:28:01 PM PDT 24
Peak memory 203536 kb
Host smart-29611fd8-01d3-4e53-9885-74b9ab50b0b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848959661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
1848959661
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3384693813
Short name T773
Test name
Test status
Simulation time 13887634 ps
CPU time 0.69 seconds
Started Apr 02 12:27:55 PM PDT 24
Finished Apr 02 12:27:55 PM PDT 24
Peak memory 203552 kb
Host smart-ab13ffe6-f860-4bc0-8685-142463abe282
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384693813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
3384693813
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2087042181
Short name T772
Test name
Test status
Simulation time 36209163 ps
CPU time 0.69 seconds
Started Apr 02 12:27:56 PM PDT 24
Finished Apr 02 12:27:56 PM PDT 24
Peak memory 203528 kb
Host smart-1d1a598e-1b66-4d33-b98a-2668aab349fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087042181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
2087042181
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3082769374
Short name T851
Test name
Test status
Simulation time 31521934 ps
CPU time 0.72 seconds
Started Apr 02 12:28:15 PM PDT 24
Finished Apr 02 12:28:16 PM PDT 24
Peak memory 203876 kb
Host smart-ae3b02ea-ac7a-4a27-9f96-82c6996767f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082769374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
3082769374
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1336325402
Short name T769
Test name
Test status
Simulation time 18273999 ps
CPU time 0.76 seconds
Started Apr 02 12:28:00 PM PDT 24
Finished Apr 02 12:28:01 PM PDT 24
Peak memory 203880 kb
Host smart-4fe8c8e6-db86-468a-9912-9decca00cd04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336325402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
1336325402
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2683197005
Short name T820
Test name
Test status
Simulation time 49361447 ps
CPU time 0.73 seconds
Started Apr 02 12:28:01 PM PDT 24
Finished Apr 02 12:28:02 PM PDT 24
Peak memory 203592 kb
Host smart-68b17da7-30f6-4df1-8677-1681fe321746
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683197005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
2683197005
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2713095379
Short name T798
Test name
Test status
Simulation time 23526124 ps
CPU time 0.72 seconds
Started Apr 02 12:27:58 PM PDT 24
Finished Apr 02 12:27:59 PM PDT 24
Peak memory 203560 kb
Host smart-88d3ca13-f58b-45e7-9046-1f26d1be7a31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713095379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
2713095379
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.999034515
Short name T742
Test name
Test status
Simulation time 16170286 ps
CPU time 0.76 seconds
Started Apr 02 12:27:54 PM PDT 24
Finished Apr 02 12:27:55 PM PDT 24
Peak memory 203524 kb
Host smart-c80a6d9b-7cc7-4c5a-844c-752bde5c4f05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999034515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.999034515
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1275825976
Short name T766
Test name
Test status
Simulation time 53227876 ps
CPU time 0.77 seconds
Started Apr 02 12:28:00 PM PDT 24
Finished Apr 02 12:28:01 PM PDT 24
Peak memory 203576 kb
Host smart-05b82be4-6872-4b2c-9a03-5a5048dba957
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275825976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
1275825976
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1574141267
Short name T795
Test name
Test status
Simulation time 45205394 ps
CPU time 2.81 seconds
Started Apr 02 12:28:00 PM PDT 24
Finished Apr 02 12:28:03 PM PDT 24
Peak memory 216788 kb
Host smart-7ffb318c-8ca7-407a-874d-8bbcc303196f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574141267 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.1574141267
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2682558658
Short name T808
Test name
Test status
Simulation time 146513174 ps
CPU time 1.43 seconds
Started Apr 02 12:27:55 PM PDT 24
Finished Apr 02 12:27:57 PM PDT 24
Peak memory 206944 kb
Host smart-1729020d-9deb-4206-9378-e054669574d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682558658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.2
682558658
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3895155656
Short name T783
Test name
Test status
Simulation time 15663618 ps
CPU time 0.76 seconds
Started Apr 02 12:27:57 PM PDT 24
Finished Apr 02 12:27:58 PM PDT 24
Peak memory 203876 kb
Host smart-7f75a28b-1c4e-48f9-9da2-73952cd0ec61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895155656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.3
895155656
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3158312573
Short name T150
Test name
Test status
Simulation time 68420468 ps
CPU time 1.76 seconds
Started Apr 02 12:27:54 PM PDT 24
Finished Apr 02 12:27:56 PM PDT 24
Peak memory 215124 kb
Host smart-f8c34232-7464-4b08-b096-b543d4c6fcbd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158312573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.3158312573
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.160970093
Short name T113
Test name
Test status
Simulation time 628619639 ps
CPU time 3.72 seconds
Started Apr 02 12:27:57 PM PDT 24
Finished Apr 02 12:28:01 PM PDT 24
Peak memory 215164 kb
Host smart-97ce3a43-d14f-43b8-b434-0f6f21127732
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160970093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.160970093
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1523605256
Short name T35
Test name
Test status
Simulation time 578318681 ps
CPU time 13.87 seconds
Started Apr 02 12:27:54 PM PDT 24
Finished Apr 02 12:28:08 PM PDT 24
Peak memory 214992 kb
Host smart-793f3ffe-d549-4509-9d2d-bae86aa7e886
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523605256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.1523605256
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3413647446
Short name T794
Test name
Test status
Simulation time 23392791 ps
CPU time 1.62 seconds
Started Apr 02 12:27:54 PM PDT 24
Finished Apr 02 12:27:56 PM PDT 24
Peak memory 215160 kb
Host smart-726389e1-5caa-4467-9f8a-a28f26f7bb6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413647446 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.3413647446
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1798806238
Short name T803
Test name
Test status
Simulation time 132960887 ps
CPU time 1.95 seconds
Started Apr 02 12:27:55 PM PDT 24
Finished Apr 02 12:27:57 PM PDT 24
Peak memory 206872 kb
Host smart-09e171c2-15c4-4d8a-af54-f7596a6bc55e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798806238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.1
798806238
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3112653809
Short name T779
Test name
Test status
Simulation time 31555411 ps
CPU time 0.72 seconds
Started Apr 02 12:27:57 PM PDT 24
Finished Apr 02 12:27:58 PM PDT 24
Peak memory 203828 kb
Host smart-971be850-5c6f-47ad-9e68-ac6353db667e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112653809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.3
112653809
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1494713871
Short name T153
Test name
Test status
Simulation time 220951368 ps
CPU time 4.09 seconds
Started Apr 02 12:27:54 PM PDT 24
Finished Apr 02 12:27:58 PM PDT 24
Peak memory 215520 kb
Host smart-05321932-46a6-420c-949e-ab5636a43b08
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494713871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.1494713871
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.859273977
Short name T130
Test name
Test status
Simulation time 93535471 ps
CPU time 1.76 seconds
Started Apr 02 12:27:57 PM PDT 24
Finished Apr 02 12:27:59 PM PDT 24
Peak memory 215240 kb
Host smart-f6ca68bf-fbde-41ee-8469-03c338d4edee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859273977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.859273977
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.694141253
Short name T811
Test name
Test status
Simulation time 934174074 ps
CPU time 15.42 seconds
Started Apr 02 12:27:55 PM PDT 24
Finished Apr 02 12:28:10 PM PDT 24
Peak memory 215140 kb
Host smart-f1779dca-239f-48e2-8299-a2d208071839
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694141253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_
tl_intg_err.694141253
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3418110112
Short name T134
Test name
Test status
Simulation time 104359997 ps
CPU time 1.61 seconds
Started Apr 02 12:27:57 PM PDT 24
Finished Apr 02 12:27:59 PM PDT 24
Peak memory 215096 kb
Host smart-21f7b45a-d737-428f-8256-fea74a82c52f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418110112 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.3418110112
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2443662374
Short name T142
Test name
Test status
Simulation time 217268774 ps
CPU time 1.76 seconds
Started Apr 02 12:28:21 PM PDT 24
Finished Apr 02 12:28:23 PM PDT 24
Peak memory 206872 kb
Host smart-96174398-2ea9-4087-8125-6e2f4bdedaab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443662374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.2
443662374
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.868210377
Short name T775
Test name
Test status
Simulation time 20456045 ps
CPU time 0.7 seconds
Started Apr 02 12:28:22 PM PDT 24
Finished Apr 02 12:28:23 PM PDT 24
Peak memory 203512 kb
Host smart-e1e2d537-1868-47c4-9486-be5678ea0575
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868210377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.868210377
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1879213622
Short name T805
Test name
Test status
Simulation time 420159129 ps
CPU time 2.97 seconds
Started Apr 02 12:27:53 PM PDT 24
Finished Apr 02 12:27:56 PM PDT 24
Peak memory 215052 kb
Host smart-b6d25006-f881-4290-a5cb-a98df07fe407
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879213622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.1879213622
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1304680853
Short name T123
Test name
Test status
Simulation time 110204243 ps
CPU time 3.27 seconds
Started Apr 02 12:28:01 PM PDT 24
Finished Apr 02 12:28:04 PM PDT 24
Peak memory 215220 kb
Host smart-9d202a08-3228-41f2-8447-0d8e83aa7322
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304680853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.1
304680853
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.638644501
Short name T801
Test name
Test status
Simulation time 577515158 ps
CPU time 16.06 seconds
Started Apr 02 12:28:17 PM PDT 24
Finished Apr 02 12:28:33 PM PDT 24
Peak memory 216544 kb
Host smart-b3eb183c-864f-4160-91f1-5c86542e9512
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638644501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_
tl_intg_err.638644501
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.825641559
Short name T837
Test name
Test status
Simulation time 302178281 ps
CPU time 1.66 seconds
Started Apr 02 12:27:56 PM PDT 24
Finished Apr 02 12:27:57 PM PDT 24
Peak memory 215232 kb
Host smart-791925d1-a2d2-48bc-8131-7ec005076e1a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825641559 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.825641559
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.4192346570
Short name T800
Test name
Test status
Simulation time 29169175 ps
CPU time 1.84 seconds
Started Apr 02 12:28:17 PM PDT 24
Finished Apr 02 12:28:19 PM PDT 24
Peak memory 206856 kb
Host smart-543bda56-fbe3-42e8-86db-a815222d8c59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192346570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.4
192346570
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.362643406
Short name T745
Test name
Test status
Simulation time 17534088 ps
CPU time 0.77 seconds
Started Apr 02 12:28:26 PM PDT 24
Finished Apr 02 12:28:27 PM PDT 24
Peak memory 203556 kb
Host smart-082e04d1-1891-4cdc-bdc0-9e32cd37d40b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362643406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.362643406
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.294231801
Short name T151
Test name
Test status
Simulation time 270214931 ps
CPU time 1.83 seconds
Started Apr 02 12:28:40 PM PDT 24
Finished Apr 02 12:28:43 PM PDT 24
Peak memory 215000 kb
Host smart-378aacdb-2bb1-44a2-8870-c62ccf53978e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294231801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sp
i_device_same_csr_outstanding.294231801
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1050653761
Short name T114
Test name
Test status
Simulation time 612267880 ps
CPU time 4.16 seconds
Started Apr 02 12:28:27 PM PDT 24
Finished Apr 02 12:28:31 PM PDT 24
Peak memory 215372 kb
Host smart-b53a74b6-9135-4f6c-93d2-40e5b487b014
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050653761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.1
050653761
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2254552235
Short name T365
Test name
Test status
Simulation time 829027206 ps
CPU time 22.24 seconds
Started Apr 02 12:27:53 PM PDT 24
Finished Apr 02 12:28:15 PM PDT 24
Peak memory 215052 kb
Host smart-8a364ed1-9e54-4c95-b095-4fe011f87b94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254552235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.2254552235
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1802077427
Short name T792
Test name
Test status
Simulation time 165437906 ps
CPU time 4.19 seconds
Started Apr 02 12:27:55 PM PDT 24
Finished Apr 02 12:28:00 PM PDT 24
Peak memory 217552 kb
Host smart-67411b8f-0a02-40f3-a3de-bd28d77bfdb4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802077427 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.1802077427
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.84299614
Short name T840
Test name
Test status
Simulation time 101044909 ps
CPU time 2.53 seconds
Started Apr 02 12:28:33 PM PDT 24
Finished Apr 02 12:28:36 PM PDT 24
Peak memory 215064 kb
Host smart-7f9a385c-e356-49f4-a9bc-58ba3322bf2c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84299614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.84299614
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1172740501
Short name T832
Test name
Test status
Simulation time 26062743 ps
CPU time 0.8 seconds
Started Apr 02 12:28:28 PM PDT 24
Finished Apr 02 12:28:28 PM PDT 24
Peak memory 203876 kb
Host smart-d71d14fe-c504-418e-9e87-35d346417a97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172740501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.1
172740501
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2496094248
Short name T806
Test name
Test status
Simulation time 242056667 ps
CPU time 2.83 seconds
Started Apr 02 12:28:26 PM PDT 24
Finished Apr 02 12:28:29 PM PDT 24
Peak memory 214992 kb
Host smart-08cf17c1-6593-449a-9b0b-63f7df238968
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496094248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.2496094248
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3413599153
Short name T833
Test name
Test status
Simulation time 271643663 ps
CPU time 4.1 seconds
Started Apr 02 12:27:55 PM PDT 24
Finished Apr 02 12:27:59 PM PDT 24
Peak memory 215204 kb
Host smart-abd37a19-031a-45a4-b47f-291080d5cd7e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413599153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.3
413599153
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1299712289
Short name T367
Test name
Test status
Simulation time 584961576 ps
CPU time 7.66 seconds
Started Apr 02 12:27:56 PM PDT 24
Finished Apr 02 12:28:04 PM PDT 24
Peak memory 215112 kb
Host smart-1cc9f2b9-d7db-420b-b9cf-0c079482120f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299712289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.1299712289
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.3602435448
Short name T734
Test name
Test status
Simulation time 24294395 ps
CPU time 0.76 seconds
Started Apr 02 01:38:52 PM PDT 24
Finished Apr 02 01:38:53 PM PDT 24
Peak memory 206044 kb
Host smart-bf098451-a152-4ac6-bc91-e571483b10b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602435448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.3602435448
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.164388462
Short name T646
Test name
Test status
Simulation time 32236564 ps
CPU time 0.75 seconds
Started Apr 02 01:38:51 PM PDT 24
Finished Apr 02 01:38:52 PM PDT 24
Peak memory 216756 kb
Host smart-fed13ee6-eafa-4415-95dd-5a27a805c072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164388462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.164388462
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.967952340
Short name T677
Test name
Test status
Simulation time 7434414763 ps
CPU time 18.1 seconds
Started Apr 02 01:38:50 PM PDT 24
Finished Apr 02 01:39:08 PM PDT 24
Peak memory 223476 kb
Host smart-27f02c31-cf84-4ac7-9743-3e79c914d07b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=967952340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_direc
t.967952340
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.3525335420
Short name T49
Test name
Test status
Simulation time 44993482 ps
CPU time 0.99 seconds
Started Apr 02 01:38:54 PM PDT 24
Finished Apr 02 01:38:56 PM PDT 24
Peak memory 235716 kb
Host smart-ba3f56e4-d1e6-486a-a299-eadbeb4c62cf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525335420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.3525335420
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.637770742
Short name T609
Test name
Test status
Simulation time 3655898857 ps
CPU time 6.8 seconds
Started Apr 02 01:38:54 PM PDT 24
Finished Apr 02 01:39:01 PM PDT 24
Peak memory 216760 kb
Host smart-d147c74a-3d12-4b79-80ad-4a349e916341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637770742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.637770742
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.136042092
Short name T478
Test name
Test status
Simulation time 233618564 ps
CPU time 1 seconds
Started Apr 02 01:38:51 PM PDT 24
Finished Apr 02 01:38:52 PM PDT 24
Peak memory 207304 kb
Host smart-3ebfeda7-035b-4fa7-9c61-b26bb9e42f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136042092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.136042092
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.1644389790
Short name T441
Test name
Test status
Simulation time 62981857 ps
CPU time 0.92 seconds
Started Apr 02 01:38:52 PM PDT 24
Finished Apr 02 01:38:53 PM PDT 24
Peak memory 206768 kb
Host smart-37b2a4b1-013f-4359-b769-e2f9754ebb64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644389790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1644389790
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.939671612
Short name T598
Test name
Test status
Simulation time 13693362 ps
CPU time 0.74 seconds
Started Apr 02 01:38:56 PM PDT 24
Finished Apr 02 01:38:57 PM PDT 24
Peak memory 205992 kb
Host smart-33426106-cf43-4be3-9fef-8897ea3c1d56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939671612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.939671612
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.737221563
Short name T564
Test name
Test status
Simulation time 40642630 ps
CPU time 0.83 seconds
Started Apr 02 01:38:53 PM PDT 24
Finished Apr 02 01:38:53 PM PDT 24
Peak memory 207132 kb
Host smart-1d0a0cca-9956-40ea-b31f-d816b690dec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737221563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.737221563
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_intercept.3057606424
Short name T119
Test name
Test status
Simulation time 191169991 ps
CPU time 3.41 seconds
Started Apr 02 01:39:01 PM PDT 24
Finished Apr 02 01:39:07 PM PDT 24
Peak memory 224608 kb
Host smart-b9c3c27c-7440-471f-88d6-7c1073038bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057606424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.3057606424
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.2928000606
Short name T171
Test name
Test status
Simulation time 3963837929 ps
CPU time 52.28 seconds
Started Apr 02 01:38:57 PM PDT 24
Finished Apr 02 01:39:49 PM PDT 24
Peak memory 236032 kb
Host smart-81011420-241d-4531-90c4-3bbc738b0f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928000606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.2928000606
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_ram_cfg.4029432092
Short name T737
Test name
Test status
Simulation time 26474292 ps
CPU time 0.76 seconds
Started Apr 02 01:38:55 PM PDT 24
Finished Apr 02 01:38:56 PM PDT 24
Peak memory 216748 kb
Host smart-6e20c0bc-cca6-4cd7-a5c9-7ac7060a6f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029432092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_ram_cfg.4029432092
Directory /workspace/1.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.2809960064
Short name T507
Test name
Test status
Simulation time 356956855 ps
CPU time 6.8 seconds
Started Apr 02 01:38:56 PM PDT 24
Finished Apr 02 01:39:03 PM PDT 24
Peak memory 220808 kb
Host smart-b327ba17-f978-42bc-921b-f35099513bb4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2809960064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.2809960064
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.2925480433
Short name T164
Test name
Test status
Simulation time 272274970 ps
CPU time 1.19 seconds
Started Apr 02 01:38:56 PM PDT 24
Finished Apr 02 01:38:57 PM PDT 24
Peak memory 216004 kb
Host smart-d65b0f4a-5294-491d-9276-9e5ae31073eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925480433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.2925480433
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.2255055764
Short name T102
Test name
Test status
Simulation time 21756771236 ps
CPU time 19.75 seconds
Started Apr 02 01:38:52 PM PDT 24
Finished Apr 02 01:39:12 PM PDT 24
Peak memory 216784 kb
Host smart-d651961a-a462-454b-b8f1-1e4981298c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255055764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.2255055764
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1422714454
Short name T613
Test name
Test status
Simulation time 46446642625 ps
CPU time 14.53 seconds
Started Apr 02 01:38:52 PM PDT 24
Finished Apr 02 01:39:07 PM PDT 24
Peak memory 216844 kb
Host smart-550acd4b-4161-4b46-a9ce-3bc1f15472f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422714454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1422714454
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.3146580595
Short name T630
Test name
Test status
Simulation time 507350523 ps
CPU time 1.01 seconds
Started Apr 02 01:38:55 PM PDT 24
Finished Apr 02 01:38:56 PM PDT 24
Peak memory 208120 kb
Host smart-f855e589-a0ad-4f6a-848e-fc03357f38f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146580595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.3146580595
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.700910127
Short name T728
Test name
Test status
Simulation time 88941289 ps
CPU time 1.02 seconds
Started Apr 02 01:38:52 PM PDT 24
Finished Apr 02 01:38:53 PM PDT 24
Peak memory 207304 kb
Host smart-ed207a30-c1ea-4690-a9b4-0874c398ed2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700910127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.700910127
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.232419706
Short name T540
Test name
Test status
Simulation time 11904442 ps
CPU time 0.7 seconds
Started Apr 02 01:39:42 PM PDT 24
Finished Apr 02 01:39:43 PM PDT 24
Peak memory 205960 kb
Host smart-d87b3be5-b3b7-4e98-9944-8f25488a96f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232419706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.232419706
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.716588996
Short name T493
Test name
Test status
Simulation time 15957441 ps
CPU time 0.74 seconds
Started Apr 02 01:39:49 PM PDT 24
Finished Apr 02 01:39:49 PM PDT 24
Peak memory 206128 kb
Host smart-f723b097-ae75-478f-a5dc-c9fed90f5b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716588996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.716588996
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.1691193080
Short name T468
Test name
Test status
Simulation time 1936593015 ps
CPU time 19.16 seconds
Started Apr 02 01:39:43 PM PDT 24
Finished Apr 02 01:40:02 PM PDT 24
Peak memory 255896 kb
Host smart-f60a45b6-80f3-4cf7-83d5-afe431a0e2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691193080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.1691193080
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_ram_cfg.1762858356
Short name T647
Test name
Test status
Simulation time 34361887 ps
CPU time 0.74 seconds
Started Apr 02 01:39:44 PM PDT 24
Finished Apr 02 01:39:44 PM PDT 24
Peak memory 216632 kb
Host smart-bfce9a26-215b-43c2-8278-5386e38e5e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762858356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_ram_cfg.1762858356
Directory /workspace/10.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.2869751701
Short name T725
Test name
Test status
Simulation time 1075427369 ps
CPU time 7.86 seconds
Started Apr 02 01:39:43 PM PDT 24
Finished Apr 02 01:39:51 PM PDT 24
Peak memory 220900 kb
Host smart-1305b406-600b-46ba-b003-3603c1ebe56b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2869751701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.2869751701
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.1324304825
Short name T464
Test name
Test status
Simulation time 8343861084 ps
CPU time 20.97 seconds
Started Apr 02 01:39:46 PM PDT 24
Finished Apr 02 01:40:08 PM PDT 24
Peak memory 216884 kb
Host smart-dcc35dab-1857-44c5-9ce5-7db5dd8d2aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324304825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.1324304825
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.1771569541
Short name T621
Test name
Test status
Simulation time 12844606 ps
CPU time 0.73 seconds
Started Apr 02 01:39:43 PM PDT 24
Finished Apr 02 01:39:43 PM PDT 24
Peak memory 206240 kb
Host smart-53eaffec-6cc1-425f-8c57-6d9ab47abef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771569541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.1771569541
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.511873742
Short name T581
Test name
Test status
Simulation time 75546508 ps
CPU time 0.95 seconds
Started Apr 02 01:39:44 PM PDT 24
Finished Apr 02 01:39:45 PM PDT 24
Peak memory 206248 kb
Host smart-d94f6032-aece-483b-bad6-7c54886bf1f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511873742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.511873742
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.2138374869
Short name T205
Test name
Test status
Simulation time 161914518 ps
CPU time 3.81 seconds
Started Apr 02 01:39:43 PM PDT 24
Finished Apr 02 01:39:47 PM PDT 24
Peak memory 217172 kb
Host smart-d7dc5f3f-d8ef-494b-9e7a-f08c83e0343d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138374869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.2138374869
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.2805751554
Short name T410
Test name
Test status
Simulation time 15694955 ps
CPU time 0.75 seconds
Started Apr 02 01:39:52 PM PDT 24
Finished Apr 02 01:39:52 PM PDT 24
Peak memory 205996 kb
Host smart-036f6092-6a06-4de5-b21b-a5a1c22edefb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805751554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
2805751554
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.2128574892
Short name T585
Test name
Test status
Simulation time 13999981 ps
CPU time 0.78 seconds
Started Apr 02 01:39:44 PM PDT 24
Finished Apr 02 01:39:45 PM PDT 24
Peak memory 207108 kb
Host smart-f372cab8-bfd7-4133-a232-78e0fedd0b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128574892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.2128574892
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.2780226543
Short name T288
Test name
Test status
Simulation time 4762227883 ps
CPU time 86.98 seconds
Started Apr 02 01:39:48 PM PDT 24
Finished Apr 02 01:41:15 PM PDT 24
Peak memory 252564 kb
Host smart-56301350-afe6-44dc-a2d8-02658bd94469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780226543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.2780226543
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.1584396968
Short name T248
Test name
Test status
Simulation time 21671526127 ps
CPU time 33.43 seconds
Started Apr 02 01:39:46 PM PDT 24
Finished Apr 02 01:40:20 PM PDT 24
Peak memory 233064 kb
Host smart-c6c1f0d5-d2d8-458a-9a32-0ea0fab3bf65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584396968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.1584396968
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.674219147
Short name T185
Test name
Test status
Simulation time 11627677722 ps
CPU time 89.23 seconds
Started Apr 02 01:39:45 PM PDT 24
Finished Apr 02 01:41:15 PM PDT 24
Peak memory 249340 kb
Host smart-19f2e954-fbfe-4d99-af74-031a5091cca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674219147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.674219147
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.2545110520
Short name T470
Test name
Test status
Simulation time 244352034 ps
CPU time 6.03 seconds
Started Apr 02 01:39:48 PM PDT 24
Finished Apr 02 01:39:55 PM PDT 24
Peak memory 223524 kb
Host smart-01510ff1-9b50-43da-935d-5a05cbd7001d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2545110520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.2545110520
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.3649839572
Short name T384
Test name
Test status
Simulation time 127447332864 ps
CPU time 40.73 seconds
Started Apr 02 01:39:46 PM PDT 24
Finished Apr 02 01:40:27 PM PDT 24
Peak memory 216728 kb
Host smart-53acffe3-c1a2-4ed7-b299-79ed8776e7f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649839572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.3649839572
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.1760828714
Short name T662
Test name
Test status
Simulation time 53179140141 ps
CPU time 30.54 seconds
Started Apr 02 01:39:45 PM PDT 24
Finished Apr 02 01:40:16 PM PDT 24
Peak memory 217832 kb
Host smart-a3ea1895-0044-4c2d-b8ce-d5be411e7b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760828714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.1760828714
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.4103943057
Short name T640
Test name
Test status
Simulation time 241189154 ps
CPU time 7.59 seconds
Started Apr 02 01:39:46 PM PDT 24
Finished Apr 02 01:39:53 PM PDT 24
Peak memory 216852 kb
Host smart-b9615667-8858-4731-92e7-23fef6fa3954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103943057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.4103943057
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.3210374087
Short name T666
Test name
Test status
Simulation time 119386263 ps
CPU time 0.74 seconds
Started Apr 02 01:39:47 PM PDT 24
Finished Apr 02 01:39:47 PM PDT 24
Peak memory 206152 kb
Host smart-9a141774-eaad-44a7-a635-df9d9d06e9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210374087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.3210374087
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.3893477543
Short name T177
Test name
Test status
Simulation time 508786858 ps
CPU time 4.44 seconds
Started Apr 02 01:39:45 PM PDT 24
Finished Apr 02 01:39:50 PM PDT 24
Peak memory 223612 kb
Host smart-f1b54a29-a00a-4787-8cad-9c4cafeb2ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893477543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.3893477543
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.287874246
Short name T608
Test name
Test status
Simulation time 127352875 ps
CPU time 0.73 seconds
Started Apr 02 01:39:56 PM PDT 24
Finished Apr 02 01:39:57 PM PDT 24
Peak memory 206000 kb
Host smart-6cb6a11e-5ad2-448b-b534-eea6be82d721
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287874246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.287874246
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.3100808543
Short name T600
Test name
Test status
Simulation time 955083624 ps
CPU time 12.19 seconds
Started Apr 02 01:39:58 PM PDT 24
Finished Apr 02 01:40:10 PM PDT 24
Peak memory 218896 kb
Host smart-c2c7f80a-8783-4e06-a344-80da9d0247f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100808543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.3100808543
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.1575239125
Short name T503
Test name
Test status
Simulation time 55544512 ps
CPU time 0.75 seconds
Started Apr 02 01:39:51 PM PDT 24
Finished Apr 02 01:39:52 PM PDT 24
Peak memory 207492 kb
Host smart-1fad3357-8991-4da9-a41a-35b831aaf8cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575239125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.1575239125
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.3390993257
Short name T697
Test name
Test status
Simulation time 3359657352 ps
CPU time 39.38 seconds
Started Apr 02 01:39:55 PM PDT 24
Finished Apr 02 01:40:35 PM PDT 24
Peak memory 249764 kb
Host smart-9104ce2e-e52b-4d2b-8649-d7beca39103e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390993257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.3390993257
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.2944633789
Short name T116
Test name
Test status
Simulation time 15603834128 ps
CPU time 31.67 seconds
Started Apr 02 01:39:53 PM PDT 24
Finished Apr 02 01:40:25 PM PDT 24
Peak memory 221264 kb
Host smart-46698f36-0c31-40db-9e17-52f5d345c5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944633789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.2944633789
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.1128709088
Short name T206
Test name
Test status
Simulation time 160765388 ps
CPU time 3.54 seconds
Started Apr 02 01:39:54 PM PDT 24
Finished Apr 02 01:39:57 PM PDT 24
Peak memory 224404 kb
Host smart-22ebcd5a-6d0f-48c6-b9c3-4bb3f07b6cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128709088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.1128709088
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_ram_cfg.3004899856
Short name T553
Test name
Test status
Simulation time 30875813 ps
CPU time 0.73 seconds
Started Apr 02 01:39:55 PM PDT 24
Finished Apr 02 01:39:56 PM PDT 24
Peak memory 216732 kb
Host smart-d60e31c2-2b5b-4615-9c33-c78310bb266a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004899856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_ram_cfg.3004899856
Directory /workspace/12.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.2939448957
Short name T423
Test name
Test status
Simulation time 2133486713 ps
CPU time 7.72 seconds
Started Apr 02 01:39:55 PM PDT 24
Finished Apr 02 01:40:03 PM PDT 24
Peak memory 222380 kb
Host smart-586e2392-c6ec-4e6b-b298-8a232a5959d3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2939448957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.2939448957
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.1886958454
Short name T620
Test name
Test status
Simulation time 9171768491 ps
CPU time 25.64 seconds
Started Apr 02 01:39:53 PM PDT 24
Finished Apr 02 01:40:19 PM PDT 24
Peak memory 217004 kb
Host smart-e2249f57-3e3b-4958-9ddf-c3d21925dfc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886958454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.1886958454
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.1644792052
Short name T111
Test name
Test status
Simulation time 3129331729 ps
CPU time 13.33 seconds
Started Apr 02 01:39:57 PM PDT 24
Finished Apr 02 01:40:10 PM PDT 24
Peak memory 216860 kb
Host smart-f3ceb5c1-f5e7-4d2c-b293-650d9997eb0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644792052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.1644792052
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.3732917541
Short name T529
Test name
Test status
Simulation time 89238779 ps
CPU time 1.35 seconds
Started Apr 02 01:39:53 PM PDT 24
Finished Apr 02 01:39:55 PM PDT 24
Peak memory 216740 kb
Host smart-044ac2ed-acb2-447d-bf74-d09d111c515c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732917541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.3732917541
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.1627368344
Short name T710
Test name
Test status
Simulation time 327017452 ps
CPU time 0.83 seconds
Started Apr 02 01:39:53 PM PDT 24
Finished Apr 02 01:39:54 PM PDT 24
Peak memory 206640 kb
Host smart-8027b2b5-5ed6-4e01-bc5d-a216897c578b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627368344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.1627368344
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.2287266582
Short name T523
Test name
Test status
Simulation time 11687715 ps
CPU time 0.73 seconds
Started Apr 02 01:39:59 PM PDT 24
Finished Apr 02 01:40:00 PM PDT 24
Peak memory 205988 kb
Host smart-78166a88-f4c6-415b-af8a-8427ad305ed5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287266582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
2287266582
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.108705178
Short name T654
Test name
Test status
Simulation time 3998790366 ps
CPU time 30.27 seconds
Started Apr 02 01:39:59 PM PDT 24
Finished Apr 02 01:40:30 PM PDT 24
Peak memory 233184 kb
Host smart-cf1d9518-3b71-4a64-94d1-4cbb9aa1b72a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108705178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.108705178
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.3864421605
Short name T722
Test name
Test status
Simulation time 13614493 ps
CPU time 0.74 seconds
Started Apr 02 01:39:57 PM PDT 24
Finished Apr 02 01:39:58 PM PDT 24
Peak memory 207156 kb
Host smart-94cd0d14-8118-4fd9-9ccf-0beb5d583e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864421605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.3864421605
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_ram_cfg.4219319877
Short name T2
Test name
Test status
Simulation time 23125759 ps
CPU time 0.75 seconds
Started Apr 02 01:39:56 PM PDT 24
Finished Apr 02 01:39:58 PM PDT 24
Peak memory 216724 kb
Host smart-322528ac-7d61-4cf6-9059-7710464465e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219319877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_ram_cfg.4219319877
Directory /workspace/13.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.2333728720
Short name T93
Test name
Test status
Simulation time 5243070700 ps
CPU time 17.87 seconds
Started Apr 02 01:40:01 PM PDT 24
Finished Apr 02 01:40:19 PM PDT 24
Peak memory 220744 kb
Host smart-87f77767-15fc-47f9-ae81-5db922cbee33
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2333728720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.2333728720
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.942105
Short name T708
Test name
Test status
Simulation time 9823458117 ps
CPU time 25.12 seconds
Started Apr 02 01:39:58 PM PDT 24
Finished Apr 02 01:40:23 PM PDT 24
Peak memory 216920 kb
Host smart-3347405d-bd38-4968-9f77-5de127e210bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.942105
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.2520022395
Short name T54
Test name
Test status
Simulation time 3493929851 ps
CPU time 5.6 seconds
Started Apr 02 01:39:55 PM PDT 24
Finished Apr 02 01:40:00 PM PDT 24
Peak memory 216708 kb
Host smart-17fc9696-3f5d-4278-a369-68a122606462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520022395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.2520022395
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.1543546177
Short name T62
Test name
Test status
Simulation time 1421404824 ps
CPU time 14.15 seconds
Started Apr 02 01:39:56 PM PDT 24
Finished Apr 02 01:40:10 PM PDT 24
Peak memory 216816 kb
Host smart-737d572b-172f-4658-b9dc-bdb30df8de0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543546177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.1543546177
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.3252134100
Short name T517
Test name
Test status
Simulation time 90192516 ps
CPU time 0.94 seconds
Started Apr 02 01:39:56 PM PDT 24
Finished Apr 02 01:39:58 PM PDT 24
Peak memory 206596 kb
Host smart-f0b01b81-59b8-46b6-a2ed-3851b23a3f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252134100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.3252134100
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.688565365
Short name T439
Test name
Test status
Simulation time 16436585 ps
CPU time 0.71 seconds
Started Apr 02 01:40:06 PM PDT 24
Finished Apr 02 01:40:07 PM PDT 24
Peak memory 205320 kb
Host smart-4a700534-040c-4993-bfef-03e9876350a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688565365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.688565365
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.1587604690
Short name T250
Test name
Test status
Simulation time 192780264 ps
CPU time 2.45 seconds
Started Apr 02 01:40:03 PM PDT 24
Finished Apr 02 01:40:06 PM PDT 24
Peak memory 218964 kb
Host smart-6ab94a87-db0a-402c-9b56-95d30b1c9d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587604690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.1587604690
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.2434683507
Short name T673
Test name
Test status
Simulation time 58786195 ps
CPU time 0.78 seconds
Started Apr 02 01:40:00 PM PDT 24
Finished Apr 02 01:40:01 PM PDT 24
Peak memory 207148 kb
Host smart-676df088-e284-426c-b339-f99441fe36a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434683507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.2434683507
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.4017834110
Short name T354
Test name
Test status
Simulation time 2925306909 ps
CPU time 26.17 seconds
Started Apr 02 01:40:08 PM PDT 24
Finished Apr 02 01:40:35 PM PDT 24
Peak memory 249596 kb
Host smart-18947cb8-f73f-4656-b22a-a03ffb29f445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017834110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.4017834110
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.3314604318
Short name T226
Test name
Test status
Simulation time 10976141195 ps
CPU time 6.15 seconds
Started Apr 02 01:40:04 PM PDT 24
Finished Apr 02 01:40:10 PM PDT 24
Peak memory 219480 kb
Host smart-b60048af-c832-4743-a15c-1951b21bd50e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314604318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.3314604318
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.240003952
Short name T323
Test name
Test status
Simulation time 221404334 ps
CPU time 2.84 seconds
Started Apr 02 01:40:07 PM PDT 24
Finished Apr 02 01:40:10 PM PDT 24
Peak memory 222692 kb
Host smart-37eaf9a9-f06c-4f2e-8bcc-27e2cc8e39a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240003952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.240003952
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_ram_cfg.2159195894
Short name T486
Test name
Test status
Simulation time 18300165 ps
CPU time 0.76 seconds
Started Apr 02 01:40:06 PM PDT 24
Finished Apr 02 01:40:07 PM PDT 24
Peak memory 216764 kb
Host smart-8558e198-5ad3-4391-9e5c-bcbd58b2f308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159195894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_ram_cfg.2159195894
Directory /workspace/14.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.3915826100
Short name T52
Test name
Test status
Simulation time 2095111233 ps
CPU time 6.9 seconds
Started Apr 02 01:40:04 PM PDT 24
Finished Apr 02 01:40:12 PM PDT 24
Peak memory 223332 kb
Host smart-09af6dcb-a3c9-45b3-b11a-f905d5d722f0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3915826100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.3915826100
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.4290828773
Short name T91
Test name
Test status
Simulation time 78463263972 ps
CPU time 37.33 seconds
Started Apr 02 01:40:06 PM PDT 24
Finished Apr 02 01:40:44 PM PDT 24
Peak memory 216860 kb
Host smart-af51776c-4b7e-4f44-a415-a2e3ccd22674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290828773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.4290828773
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.2970019263
Short name T593
Test name
Test status
Simulation time 3906257749 ps
CPU time 15.93 seconds
Started Apr 02 01:40:07 PM PDT 24
Finished Apr 02 01:40:23 PM PDT 24
Peak memory 216736 kb
Host smart-48e88ce5-02ad-4b33-8c0d-599ed6aa988c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970019263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.2970019263
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.2699255646
Short name T403
Test name
Test status
Simulation time 2028578217 ps
CPU time 11.49 seconds
Started Apr 02 01:40:03 PM PDT 24
Finished Apr 02 01:40:15 PM PDT 24
Peak memory 216696 kb
Host smart-2c97b4ea-ab68-4188-82a4-eb6b6b43bfd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699255646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.2699255646
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.592092264
Short name T112
Test name
Test status
Simulation time 246319179 ps
CPU time 0.95 seconds
Started Apr 02 01:40:08 PM PDT 24
Finished Apr 02 01:40:09 PM PDT 24
Peak memory 206216 kb
Host smart-72936e37-0990-41bd-9c10-c0bbd35e3645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592092264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.592092264
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.1416908669
Short name T642
Test name
Test status
Simulation time 33311021 ps
CPU time 0.75 seconds
Started Apr 02 01:40:19 PM PDT 24
Finished Apr 02 01:40:20 PM PDT 24
Peak memory 205420 kb
Host smart-1a48f5a5-c78f-4c31-99ed-fcb5d013a576
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416908669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
1416908669
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.4075202266
Short name T531
Test name
Test status
Simulation time 213184007 ps
CPU time 3.33 seconds
Started Apr 02 01:40:14 PM PDT 24
Finished Apr 02 01:40:17 PM PDT 24
Peak memory 223672 kb
Host smart-09d9e3f7-cb80-4c51-82fc-cb202c14923f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075202266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.4075202266
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.4188400233
Short name T718
Test name
Test status
Simulation time 21216859 ps
CPU time 0.78 seconds
Started Apr 02 01:40:06 PM PDT 24
Finished Apr 02 01:40:07 PM PDT 24
Peak memory 207416 kb
Host smart-34a919cc-599d-4333-b4aa-d9af76fb6c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188400233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.4188400233
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.1920351689
Short name T356
Test name
Test status
Simulation time 4002102182 ps
CPU time 10.13 seconds
Started Apr 02 01:40:11 PM PDT 24
Finished Apr 02 01:40:22 PM PDT 24
Peak memory 233220 kb
Host smart-3cd1f3f1-13cb-4e9c-9b3f-0811e21aefb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920351689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.1920351689
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.2274006021
Short name T184
Test name
Test status
Simulation time 363615706 ps
CPU time 4.59 seconds
Started Apr 02 01:40:12 PM PDT 24
Finished Apr 02 01:40:17 PM PDT 24
Peak memory 216656 kb
Host smart-d8bf1018-13dc-4fe2-97c6-5e4b844ebe71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274006021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.2274006021
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.2427722360
Short name T317
Test name
Test status
Simulation time 12586952497 ps
CPU time 30.43 seconds
Started Apr 02 01:40:06 PM PDT 24
Finished Apr 02 01:40:37 PM PDT 24
Peak memory 219232 kb
Host smart-a6de30e0-0f69-457d-abc5-20dcc5065774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427722360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.2427722360
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_ram_cfg.2173435769
Short name T576
Test name
Test status
Simulation time 22625099 ps
CPU time 0.74 seconds
Started Apr 02 01:40:07 PM PDT 24
Finished Apr 02 01:40:08 PM PDT 24
Peak memory 216652 kb
Host smart-b1b191b2-2b09-4e1d-bc98-efe2d78a85e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173435769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_ram_cfg.2173435769
Directory /workspace/15.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.3769221314
Short name T631
Test name
Test status
Simulation time 222158752 ps
CPU time 3.93 seconds
Started Apr 02 01:40:11 PM PDT 24
Finished Apr 02 01:40:15 PM PDT 24
Peak memory 220524 kb
Host smart-185aee54-0601-47fc-83ed-9858fa619845
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3769221314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.3769221314
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.2924777837
Short name T376
Test name
Test status
Simulation time 3368700289 ps
CPU time 34.49 seconds
Started Apr 02 01:40:08 PM PDT 24
Finished Apr 02 01:40:43 PM PDT 24
Peak memory 216836 kb
Host smart-ca9e896a-7704-40e1-b279-ef37b2e44016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924777837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.2924777837
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.764698132
Short name T457
Test name
Test status
Simulation time 216980558 ps
CPU time 2.11 seconds
Started Apr 02 01:40:06 PM PDT 24
Finished Apr 02 01:40:09 PM PDT 24
Peak memory 216704 kb
Host smart-a412f5b2-ada8-40b1-8b14-9fc7fce5ac2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764698132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.764698132
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.1847092
Short name T648
Test name
Test status
Simulation time 214106452 ps
CPU time 3.91 seconds
Started Apr 02 01:40:08 PM PDT 24
Finished Apr 02 01:40:12 PM PDT 24
Peak memory 216720 kb
Host smart-4f0de771-2642-4203-a875-31c52c8fafbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.1847092
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.2541946224
Short name T714
Test name
Test status
Simulation time 374486748 ps
CPU time 0.87 seconds
Started Apr 02 01:40:07 PM PDT 24
Finished Apr 02 01:40:08 PM PDT 24
Peak memory 206240 kb
Host smart-3f13963f-3478-4760-ab3e-84ef86524b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541946224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.2541946224
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.2055418048
Short name T670
Test name
Test status
Simulation time 27367640 ps
CPU time 0.7 seconds
Started Apr 02 01:40:21 PM PDT 24
Finished Apr 02 01:40:22 PM PDT 24
Peak memory 206288 kb
Host smart-e864c2be-24c1-4391-912c-6406669c190f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055418048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
2055418048
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.267626067
Short name T534
Test name
Test status
Simulation time 21911519 ps
CPU time 0.73 seconds
Started Apr 02 01:40:13 PM PDT 24
Finished Apr 02 01:40:14 PM PDT 24
Peak memory 206104 kb
Host smart-344475e5-46a9-4470-9512-d9d70bc2d0fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267626067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.267626067
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.2972158743
Short name T294
Test name
Test status
Simulation time 5441120913 ps
CPU time 86.91 seconds
Started Apr 02 01:40:22 PM PDT 24
Finished Apr 02 01:41:49 PM PDT 24
Peak memory 253788 kb
Host smart-14cf0399-d0e7-4e67-8716-3c03dbef784f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972158743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.2972158743
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.1007693760
Short name T641
Test name
Test status
Simulation time 1082281922 ps
CPU time 15.23 seconds
Started Apr 02 01:40:18 PM PDT 24
Finished Apr 02 01:40:33 PM PDT 24
Peak memory 220252 kb
Host smart-5d99b1de-278b-41be-ab65-f1b1a01afb4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007693760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.1007693760
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.1946652198
Short name T182
Test name
Test status
Simulation time 3212054807 ps
CPU time 13.92 seconds
Started Apr 02 01:40:19 PM PDT 24
Finished Apr 02 01:40:33 PM PDT 24
Peak memory 219004 kb
Host smart-e9fa3d96-0d75-47b8-b4ac-77e92e5242b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946652198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.1946652198
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_ram_cfg.474864620
Short name T533
Test name
Test status
Simulation time 94032948 ps
CPU time 0.77 seconds
Started Apr 02 01:40:16 PM PDT 24
Finished Apr 02 01:40:18 PM PDT 24
Peak memory 216688 kb
Host smart-f5164ede-53a8-447e-8e91-1d66c984b02a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474864620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_ram_cfg.474864620
Directory /workspace/16.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.2361339840
Short name T574
Test name
Test status
Simulation time 95741234 ps
CPU time 4.21 seconds
Started Apr 02 01:40:19 PM PDT 24
Finished Apr 02 01:40:23 PM PDT 24
Peak memory 223260 kb
Host smart-4690866b-aec1-40b1-9426-a23ed8096222
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2361339840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.2361339840
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.573426470
Short name T541
Test name
Test status
Simulation time 11509708809 ps
CPU time 10.1 seconds
Started Apr 02 01:40:17 PM PDT 24
Finished Apr 02 01:40:28 PM PDT 24
Peak memory 220636 kb
Host smart-ac8508c7-c945-44e9-b085-69ecda251dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573426470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.573426470
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.3775175538
Short name T505
Test name
Test status
Simulation time 5309139501 ps
CPU time 6.19 seconds
Started Apr 02 01:40:13 PM PDT 24
Finished Apr 02 01:40:19 PM PDT 24
Peak memory 216796 kb
Host smart-ba237e7c-a4c4-4843-b0b5-442e7d018191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775175538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.3775175538
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.1856642900
Short name T15
Test name
Test status
Simulation time 576675056 ps
CPU time 2.26 seconds
Started Apr 02 01:40:24 PM PDT 24
Finished Apr 02 01:40:26 PM PDT 24
Peak memory 216736 kb
Host smart-e430b060-4c60-4a48-9960-273b43d38ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856642900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.1856642900
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.2530585046
Short name T556
Test name
Test status
Simulation time 120042715 ps
CPU time 0.9 seconds
Started Apr 02 01:40:17 PM PDT 24
Finished Apr 02 01:40:18 PM PDT 24
Peak memory 206292 kb
Host smart-525604bb-6207-4726-998b-4538f3dcc2bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530585046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.2530585046
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.3389327002
Short name T645
Test name
Test status
Simulation time 11127017 ps
CPU time 0.72 seconds
Started Apr 02 01:40:27 PM PDT 24
Finished Apr 02 01:40:28 PM PDT 24
Peak memory 205976 kb
Host smart-4ce01256-d763-4a5b-8df2-72fee3ee4e3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389327002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
3389327002
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.150544621
Short name T460
Test name
Test status
Simulation time 55006048 ps
CPU time 0.79 seconds
Started Apr 02 01:40:21 PM PDT 24
Finished Apr 02 01:40:22 PM PDT 24
Peak memory 207084 kb
Host smart-ee5e05af-632c-493b-b40d-5d9581cd44ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150544621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.150544621
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.1017804388
Short name T555
Test name
Test status
Simulation time 12518505656 ps
CPU time 62.96 seconds
Started Apr 02 01:40:31 PM PDT 24
Finished Apr 02 01:41:35 PM PDT 24
Peak memory 249656 kb
Host smart-cd60e7c4-10e7-4cb9-8be5-7b9d9a99ef5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017804388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.1017804388
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.1895107496
Short name T597
Test name
Test status
Simulation time 872956241 ps
CPU time 3.76 seconds
Started Apr 02 01:40:28 PM PDT 24
Finished Apr 02 01:40:32 PM PDT 24
Peak memory 219088 kb
Host smart-5d746f31-9273-4b3e-bcb7-f590625c32ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895107496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.1895107496
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.2258259015
Short name T89
Test name
Test status
Simulation time 998837799 ps
CPU time 5.48 seconds
Started Apr 02 01:40:26 PM PDT 24
Finished Apr 02 01:40:32 PM PDT 24
Peak memory 223072 kb
Host smart-2777aa7f-4059-4c90-a3fd-19f1a3236f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258259015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.2258259015
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_ram_cfg.231911250
Short name T432
Test name
Test status
Simulation time 17811342 ps
CPU time 0.75 seconds
Started Apr 02 01:40:26 PM PDT 24
Finished Apr 02 01:40:26 PM PDT 24
Peak memory 216756 kb
Host smart-4aa36942-54ea-4136-9339-5f0035551de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231911250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_ram_cfg.231911250
Directory /workspace/17.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.3798505498
Short name T727
Test name
Test status
Simulation time 2855047098 ps
CPU time 7.38 seconds
Started Apr 02 01:40:31 PM PDT 24
Finished Apr 02 01:40:39 PM PDT 24
Peak memory 222144 kb
Host smart-61ba59d3-6674-4948-90f8-181ca4634884
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3798505498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.3798505498
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.4132124462
Short name T402
Test name
Test status
Simulation time 680032666 ps
CPU time 4.11 seconds
Started Apr 02 01:40:25 PM PDT 24
Finished Apr 02 01:40:29 PM PDT 24
Peak memory 216636 kb
Host smart-855fe4ab-bf34-4405-9110-636641056924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132124462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.4132124462
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.6545840
Short name T526
Test name
Test status
Simulation time 194596540 ps
CPU time 1.99 seconds
Started Apr 02 01:40:24 PM PDT 24
Finished Apr 02 01:40:26 PM PDT 24
Peak memory 216424 kb
Host smart-c56cd501-efeb-4100-aaa7-928fae55c5ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6545840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.6545840
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.4200513021
Short name T392
Test name
Test status
Simulation time 62908876 ps
CPU time 1.03 seconds
Started Apr 02 01:40:28 PM PDT 24
Finished Apr 02 01:40:29 PM PDT 24
Peak memory 208312 kb
Host smart-b63d0e12-2670-4885-b38f-28d296f3cc7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200513021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.4200513021
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.1246162808
Short name T499
Test name
Test status
Simulation time 22673587 ps
CPU time 0.7 seconds
Started Apr 02 01:40:26 PM PDT 24
Finished Apr 02 01:40:26 PM PDT 24
Peak memory 206256 kb
Host smart-59478ef6-7d59-4878-81d5-9fb301521893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246162808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.1246162808
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.749620459
Short name T694
Test name
Test status
Simulation time 2164390882 ps
CPU time 3.87 seconds
Started Apr 02 01:40:26 PM PDT 24
Finished Apr 02 01:40:30 PM PDT 24
Peak memory 219832 kb
Host smart-b0a77e7a-0ebd-4ff2-8505-6ad60e60c74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749620459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.749620459
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.1285059164
Short name T476
Test name
Test status
Simulation time 51559072 ps
CPU time 0.71 seconds
Started Apr 02 01:40:35 PM PDT 24
Finished Apr 02 01:40:36 PM PDT 24
Peak memory 206300 kb
Host smart-7853b511-b479-421a-b581-8f5b3f45a400
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285059164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
1285059164
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.285556691
Short name T198
Test name
Test status
Simulation time 8810445039 ps
CPU time 19.67 seconds
Started Apr 02 01:40:34 PM PDT 24
Finished Apr 02 01:40:54 PM PDT 24
Peak memory 224784 kb
Host smart-68ee8a28-b70d-40db-822b-eacb66bbec47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285556691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.285556691
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.1845556690
Short name T668
Test name
Test status
Simulation time 24190747 ps
CPU time 0.74 seconds
Started Apr 02 01:40:27 PM PDT 24
Finished Apr 02 01:40:28 PM PDT 24
Peak memory 206348 kb
Host smart-6d4f0e9a-0175-4664-a744-2527335e1af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845556690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.1845556690
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_ram_cfg.2983108519
Short name T494
Test name
Test status
Simulation time 38213617 ps
CPU time 0.74 seconds
Started Apr 02 01:40:32 PM PDT 24
Finished Apr 02 01:40:33 PM PDT 24
Peak memory 216764 kb
Host smart-28a175d9-14d2-4927-b626-1710f735230a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983108519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_ram_cfg.2983108519
Directory /workspace/18.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.4156153643
Short name T606
Test name
Test status
Simulation time 1605856444 ps
CPU time 14.71 seconds
Started Apr 02 01:40:30 PM PDT 24
Finished Apr 02 01:40:45 PM PDT 24
Peak memory 220788 kb
Host smart-4744abc4-1aa2-46d5-9ef6-929e50bd66f7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4156153643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.4156153643
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.2620557457
Short name T650
Test name
Test status
Simulation time 3387231078 ps
CPU time 32.72 seconds
Started Apr 02 01:40:30 PM PDT 24
Finished Apr 02 01:41:03 PM PDT 24
Peak memory 216888 kb
Host smart-a011c5b3-8c34-4ebf-b414-b481627327be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620557457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.2620557457
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.2056640124
Short name T520
Test name
Test status
Simulation time 22057239266 ps
CPU time 31.48 seconds
Started Apr 02 01:40:30 PM PDT 24
Finished Apr 02 01:41:01 PM PDT 24
Peak memory 216784 kb
Host smart-4aa3b1ca-c828-48b2-9a7c-232c0efeb127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056640124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.2056640124
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.2204552753
Short name T442
Test name
Test status
Simulation time 245206862 ps
CPU time 2.61 seconds
Started Apr 02 01:40:31 PM PDT 24
Finished Apr 02 01:40:34 PM PDT 24
Peak memory 216700 kb
Host smart-018ecd0f-c039-4f18-a4ba-86c7a48f0381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204552753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.2204552753
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.2069242392
Short name T512
Test name
Test status
Simulation time 141125355 ps
CPU time 0.84 seconds
Started Apr 02 01:40:31 PM PDT 24
Finished Apr 02 01:40:32 PM PDT 24
Peak memory 206228 kb
Host smart-06043655-f0db-4784-942b-12e1f014bbfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069242392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.2069242392
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.957211988
Short name T58
Test name
Test status
Simulation time 443146531 ps
CPU time 7.34 seconds
Started Apr 02 01:40:32 PM PDT 24
Finished Apr 02 01:40:40 PM PDT 24
Peak memory 240704 kb
Host smart-b85061f9-7823-497a-b3ec-0aaa649a8f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957211988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.957211988
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.2165516905
Short name T466
Test name
Test status
Simulation time 40124478 ps
CPU time 0.74 seconds
Started Apr 02 01:40:42 PM PDT 24
Finished Apr 02 01:40:43 PM PDT 24
Peak memory 205976 kb
Host smart-7e0afde8-74b5-4f60-873a-6245098a6632
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165516905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
2165516905
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.1291454218
Short name T615
Test name
Test status
Simulation time 140406440 ps
CPU time 2.94 seconds
Started Apr 02 01:40:44 PM PDT 24
Finished Apr 02 01:40:47 PM PDT 24
Peak memory 219172 kb
Host smart-a87c13a8-7560-4a94-b139-4dc4fcba5b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291454218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.1291454218
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.2797224763
Short name T611
Test name
Test status
Simulation time 63123688 ps
CPU time 0.8 seconds
Started Apr 02 01:40:36 PM PDT 24
Finished Apr 02 01:40:37 PM PDT 24
Peak memory 207068 kb
Host smart-c2211211-3f75-4962-9b25-c5c45d81eb44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797224763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.2797224763
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.296205652
Short name T368
Test name
Test status
Simulation time 5318048886 ps
CPU time 27.8 seconds
Started Apr 02 01:40:42 PM PDT 24
Finished Apr 02 01:41:10 PM PDT 24
Peak memory 241264 kb
Host smart-8e5df899-1e6d-4e6d-8ed9-b13f272e388a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296205652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.296205652
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.3641031090
Short name T225
Test name
Test status
Simulation time 2219673943 ps
CPU time 8.18 seconds
Started Apr 02 01:40:38 PM PDT 24
Finished Apr 02 01:40:46 PM PDT 24
Peak memory 233568 kb
Host smart-335fa2f5-1373-4b84-a3a9-8aa5cdd90d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641031090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.3641031090
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_ram_cfg.2935186786
Short name T404
Test name
Test status
Simulation time 34287616 ps
CPU time 0.74 seconds
Started Apr 02 01:40:35 PM PDT 24
Finished Apr 02 01:40:36 PM PDT 24
Peak memory 216712 kb
Host smart-382eda51-ccaa-408e-ba99-e8750aba5452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935186786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_ram_cfg.2935186786
Directory /workspace/19.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.1848205954
Short name T681
Test name
Test status
Simulation time 435680960 ps
CPU time 3.93 seconds
Started Apr 02 01:40:41 PM PDT 24
Finished Apr 02 01:40:45 PM PDT 24
Peak memory 220452 kb
Host smart-db1ec216-6aad-400b-bf54-7a403709b089
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1848205954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.1848205954
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.1751445205
Short name T433
Test name
Test status
Simulation time 3749784689 ps
CPU time 8.95 seconds
Started Apr 02 01:40:36 PM PDT 24
Finished Apr 02 01:40:45 PM PDT 24
Peak memory 216784 kb
Host smart-7d053cf7-d65d-4390-b384-a4b5203acc60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751445205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.1751445205
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.3039021189
Short name T583
Test name
Test status
Simulation time 195720415 ps
CPU time 2.89 seconds
Started Apr 02 01:40:38 PM PDT 24
Finished Apr 02 01:40:41 PM PDT 24
Peak memory 216912 kb
Host smart-4ccc549e-0c17-4b72-94fc-f3efa777ff9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039021189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.3039021189
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.3661320673
Short name T469
Test name
Test status
Simulation time 41000618 ps
CPU time 0.85 seconds
Started Apr 02 01:40:34 PM PDT 24
Finished Apr 02 01:40:36 PM PDT 24
Peak memory 206248 kb
Host smart-4715778f-8573-4af1-91a2-cdf9ee79ea7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661320673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.3661320673
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.435642974
Short name T565
Test name
Test status
Simulation time 17082344 ps
CPU time 0.72 seconds
Started Apr 02 01:39:03 PM PDT 24
Finished Apr 02 01:39:05 PM PDT 24
Peak memory 205348 kb
Host smart-791f4eaf-aec0-4ac2-a0cc-b38f64815339
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435642974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.435642974
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.3517660235
Short name T522
Test name
Test status
Simulation time 12362456740 ps
CPU time 20.63 seconds
Started Apr 02 01:39:05 PM PDT 24
Finished Apr 02 01:39:26 PM PDT 24
Peak memory 224436 kb
Host smart-d6f11202-8be7-43ec-aab5-1310b9476672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517660235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.3517660235
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.2902443619
Short name T649
Test name
Test status
Simulation time 21554593 ps
CPU time 0.83 seconds
Started Apr 02 01:38:57 PM PDT 24
Finished Apr 02 01:38:58 PM PDT 24
Peak memory 207092 kb
Host smart-a842fb0e-837b-47c0-8a34-e43dd314ef09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902443619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.2902443619
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_intercept.773154357
Short name T183
Test name
Test status
Simulation time 366596226 ps
CPU time 4.94 seconds
Started Apr 02 01:38:57 PM PDT 24
Finished Apr 02 01:39:02 PM PDT 24
Peak memory 219204 kb
Host smart-229094e2-99c5-4b7e-a3a2-1aa8b96bea71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773154357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.773154357
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.2014013264
Short name T243
Test name
Test status
Simulation time 1781570190 ps
CPU time 20.29 seconds
Started Apr 02 01:38:58 PM PDT 24
Finished Apr 02 01:39:18 PM PDT 24
Peak memory 219048 kb
Host smart-5456ebdf-e948-43e1-bb29-720b3dabf18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014013264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.2014013264
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_ram_cfg.2377972817
Short name T40
Test name
Test status
Simulation time 19376136 ps
CPU time 0.76 seconds
Started Apr 02 01:39:02 PM PDT 24
Finished Apr 02 01:39:05 PM PDT 24
Peak memory 216696 kb
Host smart-9542a657-6ac3-46bb-b5d2-380ed78b7fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377972817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_ram_cfg.2377972817
Directory /workspace/2.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.1847241700
Short name T625
Test name
Test status
Simulation time 158780000 ps
CPU time 4.11 seconds
Started Apr 02 01:39:03 PM PDT 24
Finished Apr 02 01:39:08 PM PDT 24
Peak memory 222920 kb
Host smart-201fb218-0ea0-4e27-a19f-aba5f4891d8f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1847241700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.1847241700
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.181213614
Short name T50
Test name
Test status
Simulation time 54677252 ps
CPU time 1.06 seconds
Started Apr 02 01:39:04 PM PDT 24
Finished Apr 02 01:39:06 PM PDT 24
Peak memory 235768 kb
Host smart-9ecc4a16-f224-4528-aeec-0d2b900425bb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181213614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.181213614
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3536000113
Short name T379
Test name
Test status
Simulation time 1841143460 ps
CPU time 8.74 seconds
Started Apr 02 01:39:04 PM PDT 24
Finished Apr 02 01:39:13 PM PDT 24
Peak memory 216976 kb
Host smart-325a8d7d-7947-44a9-a25d-65fac6a0150d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536000113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3536000113
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.1419705774
Short name T632
Test name
Test status
Simulation time 33226941965 ps
CPU time 24.58 seconds
Started Apr 02 01:38:59 PM PDT 24
Finished Apr 02 01:39:25 PM PDT 24
Peak memory 217800 kb
Host smart-7651100b-b026-4d95-9eaf-bbfe7c6ac8de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419705774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.1419705774
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.1407824295
Short name T586
Test name
Test status
Simulation time 51716802 ps
CPU time 0.97 seconds
Started Apr 02 01:38:58 PM PDT 24
Finished Apr 02 01:39:00 PM PDT 24
Peak memory 206820 kb
Host smart-d01960b2-de01-4a28-aafd-62e239a6698c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407824295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.1407824295
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.42575461
Short name T695
Test name
Test status
Simulation time 63619924 ps
CPU time 0.77 seconds
Started Apr 02 01:38:59 PM PDT 24
Finished Apr 02 01:39:01 PM PDT 24
Peak memory 206244 kb
Host smart-ba58e32e-ae6b-4502-b35b-9b86a396141a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42575461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.42575461
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.181030983
Short name T31
Test name
Test status
Simulation time 42966742 ps
CPU time 0.68 seconds
Started Apr 02 01:40:43 PM PDT 24
Finished Apr 02 01:40:44 PM PDT 24
Peak memory 205280 kb
Host smart-db40b409-d0e4-465e-aa8f-e754c2fb0908
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181030983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.181030983
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.4054176255
Short name T57
Test name
Test status
Simulation time 33041969 ps
CPU time 0.79 seconds
Started Apr 02 01:40:40 PM PDT 24
Finished Apr 02 01:40:41 PM PDT 24
Peak memory 207152 kb
Host smart-b0794d60-dd21-4adc-a011-f70d5cdd7514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054176255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.4054176255
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.1260874193
Short name T223
Test name
Test status
Simulation time 304848139 ps
CPU time 2.19 seconds
Started Apr 02 01:40:43 PM PDT 24
Finished Apr 02 01:40:45 PM PDT 24
Peak memory 220612 kb
Host smart-5f67fab9-0840-423d-aaf2-5ec5ca61de6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260874193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.1260874193
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.4215780184
Short name T717
Test name
Test status
Simulation time 567741674 ps
CPU time 7.72 seconds
Started Apr 02 01:40:46 PM PDT 24
Finished Apr 02 01:40:53 PM PDT 24
Peak memory 220984 kb
Host smart-36f58286-d83c-4727-a52c-9b979ba6e8df
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4215780184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.4215780184
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.4173014079
Short name T699
Test name
Test status
Simulation time 11846418396 ps
CPU time 40.43 seconds
Started Apr 02 01:40:44 PM PDT 24
Finished Apr 02 01:41:25 PM PDT 24
Peak memory 217072 kb
Host smart-3f50f13c-52e5-4543-869b-75b12a72b8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173014079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.4173014079
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.2720583761
Short name T473
Test name
Test status
Simulation time 396698003 ps
CPU time 1.33 seconds
Started Apr 02 01:40:41 PM PDT 24
Finished Apr 02 01:40:42 PM PDT 24
Peak memory 208216 kb
Host smart-57c50066-12e9-435e-bd4c-a456f2560c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720583761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.2720583761
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.764138037
Short name T713
Test name
Test status
Simulation time 429862008 ps
CPU time 1.56 seconds
Started Apr 02 01:40:42 PM PDT 24
Finished Apr 02 01:40:44 PM PDT 24
Peak memory 216608 kb
Host smart-c42fa082-38b5-44a7-81c8-d65468e53e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764138037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.764138037
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.513253647
Short name T661
Test name
Test status
Simulation time 26616114 ps
CPU time 0.85 seconds
Started Apr 02 01:40:43 PM PDT 24
Finished Apr 02 01:40:43 PM PDT 24
Peak memory 206160 kb
Host smart-944d9e30-b8c6-4cb6-b46a-9c2325512c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513253647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.513253647
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.890990193
Short name T28
Test name
Test status
Simulation time 16200458278 ps
CPU time 29.76 seconds
Started Apr 02 01:40:44 PM PDT 24
Finished Apr 02 01:41:14 PM PDT 24
Peak memory 232876 kb
Host smart-04009242-45bb-44eb-a7c4-5e30284b07d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890990193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.890990193
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.4198890629
Short name T545
Test name
Test status
Simulation time 14377239 ps
CPU time 0.76 seconds
Started Apr 02 01:40:52 PM PDT 24
Finished Apr 02 01:40:52 PM PDT 24
Peak memory 205984 kb
Host smart-450d4400-259e-4d84-a59d-88eb66f169fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198890629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
4198890629
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.1216791264
Short name T575
Test name
Test status
Simulation time 41945439 ps
CPU time 0.8 seconds
Started Apr 02 01:40:46 PM PDT 24
Finished Apr 02 01:40:46 PM PDT 24
Peak memory 207096 kb
Host smart-72a9838c-3c69-4441-83f9-24c6ceccf19f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216791264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.1216791264
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.1278846872
Short name T230
Test name
Test status
Simulation time 848798168 ps
CPU time 8.32 seconds
Started Apr 02 01:40:48 PM PDT 24
Finished Apr 02 01:40:57 PM PDT 24
Peak memory 218904 kb
Host smart-30f82d4d-a994-4e2f-b77b-105e630ebcba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278846872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.1278846872
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.1270496369
Short name T201
Test name
Test status
Simulation time 43619830560 ps
CPU time 14.32 seconds
Started Apr 02 01:40:46 PM PDT 24
Finished Apr 02 01:41:01 PM PDT 24
Peak memory 234680 kb
Host smart-567580ab-ab30-4b9e-9622-224239652430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270496369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.1270496369
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.948061232
Short name T492
Test name
Test status
Simulation time 99073179 ps
CPU time 3.96 seconds
Started Apr 02 01:40:48 PM PDT 24
Finished Apr 02 01:40:52 PM PDT 24
Peak memory 222848 kb
Host smart-17425088-8b41-42c0-9493-315be602e224
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=948061232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dire
ct.948061232
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.3439687969
Short name T63
Test name
Test status
Simulation time 2235341887 ps
CPU time 22.89 seconds
Started Apr 02 01:40:46 PM PDT 24
Finished Apr 02 01:41:09 PM PDT 24
Peak memory 216848 kb
Host smart-6d12a641-1e36-46ca-bfcc-bc05f4b3be41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439687969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3439687969
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.1112890114
Short name T110
Test name
Test status
Simulation time 35404264182 ps
CPU time 21.95 seconds
Started Apr 02 01:40:43 PM PDT 24
Finished Apr 02 01:41:05 PM PDT 24
Peak memory 217824 kb
Host smart-4f808a8a-0ec9-4ab5-bda6-baf67ddf9571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112890114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.1112890114
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.1741128528
Short name T497
Test name
Test status
Simulation time 20173484 ps
CPU time 1 seconds
Started Apr 02 01:40:46 PM PDT 24
Finished Apr 02 01:40:47 PM PDT 24
Peak memory 207652 kb
Host smart-8d59529c-7b3a-4171-ad87-ab9ace601fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741128528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.1741128528
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.1051250405
Short name T471
Test name
Test status
Simulation time 74926341 ps
CPU time 0.73 seconds
Started Apr 02 01:40:45 PM PDT 24
Finished Apr 02 01:40:46 PM PDT 24
Peak memory 206172 kb
Host smart-d67cf1cf-edd8-40e2-9600-d183a82f1adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051250405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.1051250405
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.2084958012
Short name T733
Test name
Test status
Simulation time 10545984 ps
CPU time 0.72 seconds
Started Apr 02 01:40:58 PM PDT 24
Finished Apr 02 01:40:59 PM PDT 24
Peak memory 205972 kb
Host smart-7406b5a2-0bf7-45c6-942a-4eb28885b6b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084958012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
2084958012
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.2784871439
Short name T619
Test name
Test status
Simulation time 18817241 ps
CPU time 0.76 seconds
Started Apr 02 01:40:50 PM PDT 24
Finished Apr 02 01:40:51 PM PDT 24
Peak memory 207172 kb
Host smart-49510190-b398-4e03-90fb-bd0f73079dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784871439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.2784871439
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.3775874629
Short name T474
Test name
Test status
Simulation time 1976677093 ps
CPU time 29.02 seconds
Started Apr 02 01:40:55 PM PDT 24
Finished Apr 02 01:41:24 PM PDT 24
Peak memory 219040 kb
Host smart-ff0536c1-3e2c-4ae4-ade5-d8e359196251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775874629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.3775874629
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.1010160839
Short name T308
Test name
Test status
Simulation time 5875568072 ps
CPU time 5.74 seconds
Started Apr 02 01:40:52 PM PDT 24
Finished Apr 02 01:40:58 PM PDT 24
Peak memory 221004 kb
Host smart-5460722b-dfe9-4d5d-9172-68d451e14ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010160839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.1010160839
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.3148265252
Short name T4
Test name
Test status
Simulation time 1198924418 ps
CPU time 13.6 seconds
Started Apr 02 01:40:54 PM PDT 24
Finished Apr 02 01:41:08 PM PDT 24
Peak memory 219704 kb
Host smart-2d61ef1b-132e-448e-8e8b-92f0ee791016
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3148265252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.3148265252
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.2759823589
Short name T378
Test name
Test status
Simulation time 16000210036 ps
CPU time 19.71 seconds
Started Apr 02 01:40:50 PM PDT 24
Finished Apr 02 01:41:10 PM PDT 24
Peak memory 216780 kb
Host smart-a7aa8a5b-84fa-424e-8a1e-a5ab7f20cdff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759823589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.2759823589
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.871849686
Short name T550
Test name
Test status
Simulation time 661008233 ps
CPU time 3.12 seconds
Started Apr 02 01:40:50 PM PDT 24
Finished Apr 02 01:40:54 PM PDT 24
Peak memory 216764 kb
Host smart-b901dd79-ccc6-4590-86ca-02f5142f9d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871849686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.871849686
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.3634587551
Short name T627
Test name
Test status
Simulation time 250467021 ps
CPU time 7.59 seconds
Started Apr 02 01:40:53 PM PDT 24
Finished Apr 02 01:41:00 PM PDT 24
Peak memory 216880 kb
Host smart-482e27b3-3b9e-4def-ab42-8ca16bebaaec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634587551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.3634587551
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.550845408
Short name T548
Test name
Test status
Simulation time 117154917 ps
CPU time 1.09 seconds
Started Apr 02 01:40:53 PM PDT 24
Finished Apr 02 01:40:54 PM PDT 24
Peak memory 207276 kb
Host smart-03955efd-e561-43c1-aeb5-acc9a39bd20e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550845408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.550845408
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.3947159908
Short name T370
Test name
Test status
Simulation time 920059835 ps
CPU time 7.11 seconds
Started Apr 02 01:41:01 PM PDT 24
Finished Apr 02 01:41:08 PM PDT 24
Peak memory 216716 kb
Host smart-b372bfa2-18b6-46b5-9ead-b644c19b1c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947159908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.3947159908
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.992796485
Short name T459
Test name
Test status
Simulation time 24885856 ps
CPU time 0.73 seconds
Started Apr 02 01:41:04 PM PDT 24
Finished Apr 02 01:41:05 PM PDT 24
Peak memory 205424 kb
Host smart-be34e8dc-aec4-49dd-b5e4-ba90d4b8e14a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992796485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.992796485
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.2687395637
Short name T25
Test name
Test status
Simulation time 1668282649 ps
CPU time 6.32 seconds
Started Apr 02 01:41:05 PM PDT 24
Finished Apr 02 01:41:11 PM PDT 24
Peak memory 223780 kb
Host smart-7d9dc262-02a3-46b4-845c-62c7b42b8312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687395637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.2687395637
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.3238371284
Short name T592
Test name
Test status
Simulation time 16673018 ps
CPU time 0.77 seconds
Started Apr 02 01:41:00 PM PDT 24
Finished Apr 02 01:41:01 PM PDT 24
Peak memory 207424 kb
Host smart-364336ac-4de0-4c17-affb-7719cee96783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238371284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.3238371284
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_intercept.3373800906
Short name T519
Test name
Test status
Simulation time 359148271 ps
CPU time 2.36 seconds
Started Apr 02 01:41:00 PM PDT 24
Finished Apr 02 01:41:03 PM PDT 24
Peak memory 218912 kb
Host smart-ee1f9faf-91f1-4022-978c-c84ca2afe6ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373800906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.3373800906
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.2960016983
Short name T638
Test name
Test status
Simulation time 2554994028 ps
CPU time 6.16 seconds
Started Apr 02 01:41:00 PM PDT 24
Finished Apr 02 01:41:06 PM PDT 24
Peak memory 223312 kb
Host smart-ce91ad3f-bb48-4cc6-955c-c98f7a5380b5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2960016983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.2960016983
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.1503053578
Short name T382
Test name
Test status
Simulation time 36931555181 ps
CPU time 55.86 seconds
Started Apr 02 01:40:56 PM PDT 24
Finished Apr 02 01:41:52 PM PDT 24
Peak memory 216804 kb
Host smart-f56c27ab-d95f-45c8-82d8-ad8027013206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503053578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.1503053578
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.2095449361
Short name T624
Test name
Test status
Simulation time 7928881771 ps
CPU time 13.56 seconds
Started Apr 02 01:40:56 PM PDT 24
Finished Apr 02 01:41:10 PM PDT 24
Peak memory 216732 kb
Host smart-64c3d75c-235a-48e7-86f1-3f9be321b2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095449361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.2095449361
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.3802538461
Short name T8
Test name
Test status
Simulation time 119800505 ps
CPU time 2.05 seconds
Started Apr 02 01:40:57 PM PDT 24
Finished Apr 02 01:40:59 PM PDT 24
Peak memory 216756 kb
Host smart-d9503c0f-49a8-4169-9a80-cc1314b2a71e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802538461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.3802538461
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.3879158551
Short name T94
Test name
Test status
Simulation time 55636905 ps
CPU time 1.01 seconds
Started Apr 02 01:40:58 PM PDT 24
Finished Apr 02 01:40:59 PM PDT 24
Peak memory 207288 kb
Host smart-9f4bbb7e-47fb-40d8-a9a7-b2f50c38c68d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879158551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.3879158551
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.332463932
Short name T417
Test name
Test status
Simulation time 14485174 ps
CPU time 0.77 seconds
Started Apr 02 01:41:10 PM PDT 24
Finished Apr 02 01:41:11 PM PDT 24
Peak memory 206020 kb
Host smart-1ec05967-a174-4cda-ade6-cf78e773b93a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332463932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.332463932
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.855705179
Short name T406
Test name
Test status
Simulation time 43738878 ps
CPU time 0.8 seconds
Started Apr 02 01:41:04 PM PDT 24
Finished Apr 02 01:41:05 PM PDT 24
Peak memory 207076 kb
Host smart-4aed2c91-8102-4036-b2ad-ef26fe036bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855705179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.855705179
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.1654167975
Short name T663
Test name
Test status
Simulation time 2890905170 ps
CPU time 27.16 seconds
Started Apr 02 01:41:10 PM PDT 24
Finished Apr 02 01:41:37 PM PDT 24
Peak memory 252152 kb
Host smart-f97f3679-e51d-4ddf-a8f4-b952abe1dbd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654167975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.1654167975
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.4148187291
Short name T255
Test name
Test status
Simulation time 1548288624 ps
CPU time 13.15 seconds
Started Apr 02 01:41:07 PM PDT 24
Finished Apr 02 01:41:20 PM PDT 24
Peak memory 219260 kb
Host smart-af16e175-9450-40c4-ab89-114b57cf7cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148187291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.4148187291
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.2402901254
Short name T346
Test name
Test status
Simulation time 85863454 ps
CPU time 3.11 seconds
Started Apr 02 01:41:07 PM PDT 24
Finished Apr 02 01:41:10 PM PDT 24
Peak memory 223544 kb
Host smart-2c2e8cc0-cf63-4fb0-8aaf-69df8f53234d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402901254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.2402901254
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.1684681307
Short name T322
Test name
Test status
Simulation time 5697761812 ps
CPU time 11.07 seconds
Started Apr 02 01:41:07 PM PDT 24
Finished Apr 02 01:41:18 PM PDT 24
Peak memory 224640 kb
Host smart-4f081aa3-adda-47c7-9961-a677c5ccb938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684681307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.1684681307
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.2927272593
Short name T425
Test name
Test status
Simulation time 284527789 ps
CPU time 4.97 seconds
Started Apr 02 01:41:06 PM PDT 24
Finished Apr 02 01:41:11 PM PDT 24
Peak memory 219264 kb
Host smart-e279117a-50a8-40f8-a89c-df80105f3670
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2927272593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.2927272593
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.4140294951
Short name T543
Test name
Test status
Simulation time 52272915426 ps
CPU time 33.3 seconds
Started Apr 02 01:41:04 PM PDT 24
Finished Apr 02 01:41:38 PM PDT 24
Peak memory 216840 kb
Host smart-3b04d6e6-ab19-4bac-96c0-baf369f4e92b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140294951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.4140294951
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.222820140
Short name T391
Test name
Test status
Simulation time 161025739 ps
CPU time 1.29 seconds
Started Apr 02 01:41:05 PM PDT 24
Finished Apr 02 01:41:06 PM PDT 24
Peak memory 216816 kb
Host smart-2c1c65af-828e-4af7-9248-8caf793e31cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222820140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.222820140
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.2957197656
Short name T644
Test name
Test status
Simulation time 305940848 ps
CPU time 0.99 seconds
Started Apr 02 01:41:07 PM PDT 24
Finished Apr 02 01:41:08 PM PDT 24
Peak memory 207280 kb
Host smart-7a7b320b-ce7f-4ced-bf84-c34110dcbbbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957197656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.2957197656
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.3308308348
Short name T700
Test name
Test status
Simulation time 11651429 ps
CPU time 0.71 seconds
Started Apr 02 01:41:15 PM PDT 24
Finished Apr 02 01:41:16 PM PDT 24
Peak memory 205996 kb
Host smart-e197df72-2669-47f1-8315-fe54c873ac3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308308348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
3308308348
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.3440198187
Short name T249
Test name
Test status
Simulation time 1510268889 ps
CPU time 18.83 seconds
Started Apr 02 01:41:13 PM PDT 24
Finished Apr 02 01:41:32 PM PDT 24
Peak memory 224892 kb
Host smart-49e901e2-339d-4a61-b80b-c8993eda3cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440198187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.3440198187
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.2962731701
Short name T514
Test name
Test status
Simulation time 112835197 ps
CPU time 0.73 seconds
Started Apr 02 01:41:10 PM PDT 24
Finished Apr 02 01:41:11 PM PDT 24
Peak memory 206416 kb
Host smart-0e18542b-7933-44e5-a9d7-6e72873f53f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962731701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.2962731701
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.4193925356
Short name T69
Test name
Test status
Simulation time 84124019725 ps
CPU time 237.61 seconds
Started Apr 02 01:41:17 PM PDT 24
Finished Apr 02 01:45:14 PM PDT 24
Peak memory 249592 kb
Host smart-4b680da3-675c-453c-ad80-dceafcf096ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193925356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.4193925356
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.238028619
Short name T55
Test name
Test status
Simulation time 421541236 ps
CPU time 8.54 seconds
Started Apr 02 01:41:13 PM PDT 24
Finished Apr 02 01:41:22 PM PDT 24
Peak memory 219644 kb
Host smart-a3b3d91e-17ae-41a1-b7ee-d33fbe28f00c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238028619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.238028619
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.1391503790
Short name T704
Test name
Test status
Simulation time 1992388985 ps
CPU time 8.62 seconds
Started Apr 02 01:41:14 PM PDT 24
Finished Apr 02 01:41:23 PM PDT 24
Peak memory 224968 kb
Host smart-840a2977-0804-4344-935d-97a61a5abd76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391503790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.1391503790
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.1853677489
Short name T472
Test name
Test status
Simulation time 291839367 ps
CPU time 4.3 seconds
Started Apr 02 01:41:27 PM PDT 24
Finished Apr 02 01:41:31 PM PDT 24
Peak memory 223500 kb
Host smart-1c336e43-4989-43b6-824a-0402408886be
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1853677489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.1853677489
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.3186517530
Short name T634
Test name
Test status
Simulation time 1982590908 ps
CPU time 12.47 seconds
Started Apr 02 01:41:10 PM PDT 24
Finished Apr 02 01:41:23 PM PDT 24
Peak memory 216736 kb
Host smart-686fa395-e5a3-4d76-a972-d75786406745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186517530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.3186517530
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.3813280337
Short name T732
Test name
Test status
Simulation time 1992523715 ps
CPU time 6.24 seconds
Started Apr 02 01:41:10 PM PDT 24
Finished Apr 02 01:41:16 PM PDT 24
Peak memory 216792 kb
Host smart-58f3eb3a-4723-4eb0-a2b1-337573ad57b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813280337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.3813280337
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.2915814127
Short name T579
Test name
Test status
Simulation time 23120677 ps
CPU time 0.94 seconds
Started Apr 02 01:41:15 PM PDT 24
Finished Apr 02 01:41:16 PM PDT 24
Peak memory 207276 kb
Host smart-c98d2555-300f-409a-9026-871c0f3e8ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915814127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.2915814127
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.2295150871
Short name T516
Test name
Test status
Simulation time 172729436 ps
CPU time 0.92 seconds
Started Apr 02 01:41:14 PM PDT 24
Finished Apr 02 01:41:15 PM PDT 24
Peak memory 207272 kb
Host smart-73e9b631-4b90-4c2b-87d3-4e9bcd35c43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295150871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.2295150871
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.3014796783
Short name T639
Test name
Test status
Simulation time 16079195 ps
CPU time 0.74 seconds
Started Apr 02 01:41:23 PM PDT 24
Finished Apr 02 01:41:24 PM PDT 24
Peak memory 205856 kb
Host smart-e21506a7-a4e6-4192-91c1-6ff8a2cf598a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014796783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
3014796783
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.2410297138
Short name T238
Test name
Test status
Simulation time 240056248 ps
CPU time 2.83 seconds
Started Apr 02 01:41:19 PM PDT 24
Finished Apr 02 01:41:22 PM PDT 24
Peak memory 224272 kb
Host smart-7fe6284e-e12e-4cbb-a9a0-c433f66930ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410297138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.2410297138
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.841042952
Short name T651
Test name
Test status
Simulation time 40617500 ps
CPU time 0.79 seconds
Started Apr 02 01:41:17 PM PDT 24
Finished Apr 02 01:41:18 PM PDT 24
Peak memory 207408 kb
Host smart-cd501670-98dd-4fee-9c3e-645b9969feae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841042952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.841042952
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.2067949848
Short name T96
Test name
Test status
Simulation time 87821888831 ps
CPU time 214.52 seconds
Started Apr 02 01:41:19 PM PDT 24
Finished Apr 02 01:44:54 PM PDT 24
Peak memory 257192 kb
Host smart-5ae2b443-a9ef-43d7-850a-20fad83b9197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067949848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.2067949848
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.2112645057
Short name T283
Test name
Test status
Simulation time 4432775394 ps
CPU time 4.56 seconds
Started Apr 02 01:41:17 PM PDT 24
Finished Apr 02 01:41:22 PM PDT 24
Peak memory 217868 kb
Host smart-f82d6380-a896-4223-a3a7-8a014d9942b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112645057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.2112645057
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.2557602788
Short name T327
Test name
Test status
Simulation time 17957125781 ps
CPU time 13.69 seconds
Started Apr 02 01:41:21 PM PDT 24
Finished Apr 02 01:41:35 PM PDT 24
Peak memory 224228 kb
Host smart-ae6eb188-00ea-4e12-860f-5036e702aca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557602788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.2557602788
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.2550983834
Short name T491
Test name
Test status
Simulation time 1748571197 ps
CPU time 21.58 seconds
Started Apr 02 01:41:18 PM PDT 24
Finished Apr 02 01:41:40 PM PDT 24
Peak memory 223324 kb
Host smart-a2be4f61-a142-42a5-a518-9c2b3b0aa7cb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2550983834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.2550983834
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.1365393733
Short name T672
Test name
Test status
Simulation time 44079837935 ps
CPU time 51.96 seconds
Started Apr 02 01:41:15 PM PDT 24
Finished Apr 02 01:42:07 PM PDT 24
Peak memory 216844 kb
Host smart-51a7e3d2-bf2a-483f-ab93-3c86d10890e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365393733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.1365393733
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.3303097678
Short name T682
Test name
Test status
Simulation time 23038062539 ps
CPU time 15.97 seconds
Started Apr 02 01:41:15 PM PDT 24
Finished Apr 02 01:41:32 PM PDT 24
Peak memory 216840 kb
Host smart-f304f7c2-ac64-44dc-8fef-c5242609e2a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303097678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.3303097678
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.3074255843
Short name T683
Test name
Test status
Simulation time 42009622 ps
CPU time 1.29 seconds
Started Apr 02 01:41:21 PM PDT 24
Finished Apr 02 01:41:22 PM PDT 24
Peak memory 208604 kb
Host smart-aaeffc7b-81d8-4ffc-bda9-c45b261db677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074255843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.3074255843
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.2867057721
Short name T446
Test name
Test status
Simulation time 170341153 ps
CPU time 1.01 seconds
Started Apr 02 01:41:17 PM PDT 24
Finished Apr 02 01:41:19 PM PDT 24
Peak memory 207176 kb
Host smart-c6aa4eba-f5d2-43e4-9c22-e27475b8c43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867057721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.2867057721
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.3522847038
Short name T254
Test name
Test status
Simulation time 5430586713 ps
CPU time 16.07 seconds
Started Apr 02 01:41:19 PM PDT 24
Finished Apr 02 01:41:35 PM PDT 24
Peak memory 234700 kb
Host smart-ccedac98-3b87-4b42-9e56-2b5a2d074ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522847038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.3522847038
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.1453813830
Short name T454
Test name
Test status
Simulation time 21453338 ps
CPU time 0.71 seconds
Started Apr 02 01:41:37 PM PDT 24
Finished Apr 02 01:41:38 PM PDT 24
Peak memory 205996 kb
Host smart-e5b29fea-81f4-4e62-823d-65ad58a1b951
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453813830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
1453813830
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.1659110550
Short name T616
Test name
Test status
Simulation time 15310807 ps
CPU time 0.78 seconds
Started Apr 02 01:41:24 PM PDT 24
Finished Apr 02 01:41:26 PM PDT 24
Peak memory 207116 kb
Host smart-fc8d10d7-344e-4814-9111-8768028b66ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659110550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.1659110550
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.1436182167
Short name T284
Test name
Test status
Simulation time 19343715458 ps
CPU time 135.13 seconds
Started Apr 02 01:41:32 PM PDT 24
Finished Apr 02 01:43:47 PM PDT 24
Peak memory 241012 kb
Host smart-c4220396-018b-4814-bdd7-a1b2bab8007e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436182167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.1436182167
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2583743382
Short name T311
Test name
Test status
Simulation time 1390288739 ps
CPU time 6.89 seconds
Started Apr 02 01:41:30 PM PDT 24
Finished Apr 02 01:41:37 PM PDT 24
Peak memory 219036 kb
Host smart-25a479a8-4491-421e-b29d-cde83046d6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583743382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2583743382
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.1769434738
Short name T487
Test name
Test status
Simulation time 238794897 ps
CPU time 5.84 seconds
Started Apr 02 01:41:32 PM PDT 24
Finished Apr 02 01:41:38 PM PDT 24
Peak memory 223432 kb
Host smart-a4c34264-f469-4092-bd21-8db88a3bfbec
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1769434738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.1769434738
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.2532258907
Short name T377
Test name
Test status
Simulation time 19506307207 ps
CPU time 20.36 seconds
Started Apr 02 01:41:25 PM PDT 24
Finished Apr 02 01:41:46 PM PDT 24
Peak memory 216912 kb
Host smart-f555f9b6-0490-4489-b490-762a16abd68a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532258907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.2532258907
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.2488135698
Short name T456
Test name
Test status
Simulation time 16021945154 ps
CPU time 7.55 seconds
Started Apr 02 01:41:27 PM PDT 24
Finished Apr 02 01:41:34 PM PDT 24
Peak memory 216856 kb
Host smart-cb1bf87b-edb7-4edf-87d1-3483bcbfccb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488135698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.2488135698
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.3931468565
Short name T19
Test name
Test status
Simulation time 24861799 ps
CPU time 1.5 seconds
Started Apr 02 01:41:27 PM PDT 24
Finished Apr 02 01:41:28 PM PDT 24
Peak memory 216760 kb
Host smart-01799bb7-1732-42b5-8c03-6ebfe735114c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931468565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.3931468565
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.1682083552
Short name T448
Test name
Test status
Simulation time 16457792 ps
CPU time 0.74 seconds
Started Apr 02 01:41:27 PM PDT 24
Finished Apr 02 01:41:28 PM PDT 24
Peak memory 206248 kb
Host smart-e92dcba3-ae23-49c1-b026-0bd2d601e6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682083552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.1682083552
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.1661272466
Short name T215
Test name
Test status
Simulation time 51945466 ps
CPU time 2.32 seconds
Started Apr 02 01:41:29 PM PDT 24
Finished Apr 02 01:41:32 PM PDT 24
Peak memory 219308 kb
Host smart-86b3ad99-afa5-4da3-9c1d-8b874fcb1054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661272466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.1661272466
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.547524514
Short name T421
Test name
Test status
Simulation time 14682731 ps
CPU time 0.78 seconds
Started Apr 02 01:41:54 PM PDT 24
Finished Apr 02 01:41:55 PM PDT 24
Peak memory 205988 kb
Host smart-cb5b5cb4-d453-4a9b-85da-653e53e1b6b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547524514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.547524514
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.3631722242
Short name T535
Test name
Test status
Simulation time 55746159 ps
CPU time 0.77 seconds
Started Apr 02 01:41:37 PM PDT 24
Finished Apr 02 01:41:38 PM PDT 24
Peak memory 206432 kb
Host smart-fd4155b1-c0ca-4f14-80e5-4b39d373e2fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631722242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.3631722242
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.3816526087
Short name T120
Test name
Test status
Simulation time 8045233711 ps
CPU time 96.54 seconds
Started Apr 02 01:41:47 PM PDT 24
Finished Apr 02 01:43:24 PM PDT 24
Peak memory 232488 kb
Host smart-aade44b0-1422-4138-9f22-5e35aee6d5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816526087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.3816526087
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.694008897
Short name T207
Test name
Test status
Simulation time 35265094526 ps
CPU time 24.97 seconds
Started Apr 02 01:41:45 PM PDT 24
Finished Apr 02 01:42:10 PM PDT 24
Peak memory 223692 kb
Host smart-f0116768-c54d-4e20-a1bb-fe58e946ae9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694008897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap
.694008897
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.2494087284
Short name T264
Test name
Test status
Simulation time 7196678170 ps
CPU time 19.09 seconds
Started Apr 02 01:41:42 PM PDT 24
Finished Apr 02 01:42:02 PM PDT 24
Peak memory 217316 kb
Host smart-f4933413-63a0-4b62-970b-df206f3828a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494087284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.2494087284
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.2570724295
Short name T412
Test name
Test status
Simulation time 119990760 ps
CPU time 3.74 seconds
Started Apr 02 01:41:49 PM PDT 24
Finished Apr 02 01:41:53 PM PDT 24
Peak memory 222920 kb
Host smart-d73547e6-c0bd-4a16-b670-8ed8087e4539
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2570724295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.2570724295
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.4128075915
Short name T61
Test name
Test status
Simulation time 25567635627 ps
CPU time 20.84 seconds
Started Apr 02 01:41:44 PM PDT 24
Finished Apr 02 01:42:05 PM PDT 24
Peak memory 216860 kb
Host smart-42c1c564-6d39-4bef-ae50-08299c3c1409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128075915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.4128075915
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.1638154401
Short name T560
Test name
Test status
Simulation time 3098212519 ps
CPU time 8.69 seconds
Started Apr 02 01:41:45 PM PDT 24
Finished Apr 02 01:41:54 PM PDT 24
Peak memory 216840 kb
Host smart-93e41087-1faa-4e06-9f4a-35bda27c9137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638154401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.1638154401
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.433252762
Short name T60
Test name
Test status
Simulation time 23700300 ps
CPU time 0.81 seconds
Started Apr 02 01:41:45 PM PDT 24
Finished Apr 02 01:41:46 PM PDT 24
Peak memory 207008 kb
Host smart-4a41f6c2-1b42-410f-8d41-491a7d58a9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433252762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.433252762
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.221995572
Short name T587
Test name
Test status
Simulation time 143291607 ps
CPU time 0.82 seconds
Started Apr 02 01:41:41 PM PDT 24
Finished Apr 02 01:41:42 PM PDT 24
Peak memory 206228 kb
Host smart-98ad0e11-c4af-4b40-863e-5ee5a233ae9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221995572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.221995572
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.1178842706
Short name T617
Test name
Test status
Simulation time 207853607 ps
CPU time 3.25 seconds
Started Apr 02 01:41:57 PM PDT 24
Finished Apr 02 01:42:00 PM PDT 24
Peak memory 222700 kb
Host smart-54d90e58-afc1-4376-86ce-8cd505900c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178842706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.1178842706
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.1069242346
Short name T30
Test name
Test status
Simulation time 41841792 ps
CPU time 0.69 seconds
Started Apr 02 01:42:11 PM PDT 24
Finished Apr 02 01:42:11 PM PDT 24
Peak memory 205312 kb
Host smart-bab042d1-9e38-45ba-b8f8-5cb1cc7db96f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069242346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
1069242346
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.280807900
Short name T307
Test name
Test status
Simulation time 82884621 ps
CPU time 2.77 seconds
Started Apr 02 01:42:07 PM PDT 24
Finished Apr 02 01:42:10 PM PDT 24
Peak memory 223592 kb
Host smart-b0abbcf1-9f47-4a84-8ee3-7aebdba89be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280807900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.280807900
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.765643668
Short name T440
Test name
Test status
Simulation time 60440037 ps
CPU time 0.77 seconds
Started Apr 02 01:41:53 PM PDT 24
Finished Apr 02 01:41:55 PM PDT 24
Peak memory 207108 kb
Host smart-50fd01bd-ca47-4cab-a09f-58a1bfd818ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765643668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.765643668
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.1609162982
Short name T721
Test name
Test status
Simulation time 1452089056 ps
CPU time 31.65 seconds
Started Apr 02 01:42:06 PM PDT 24
Finished Apr 02 01:42:38 PM PDT 24
Peak memory 233136 kb
Host smart-ed843b43-d66c-4ce7-be74-15df9ff30cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609162982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.1609162982
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.2374922749
Short name T680
Test name
Test status
Simulation time 1934899670 ps
CPU time 12.4 seconds
Started Apr 02 01:42:06 PM PDT 24
Finished Apr 02 01:42:18 PM PDT 24
Peak memory 220932 kb
Host smart-578b5d4d-9362-4fe9-809d-82b7c7a7dfae
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2374922749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.2374922749
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.2124171364
Short name T348
Test name
Test status
Simulation time 178558469 ps
CPU time 1.04 seconds
Started Apr 02 01:42:11 PM PDT 24
Finished Apr 02 01:42:13 PM PDT 24
Peak memory 207748 kb
Host smart-8fd1a8b3-3a53-4a3b-9f3d-21ed662d54b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124171364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.2124171364
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.1922322445
Short name T637
Test name
Test status
Simulation time 3848370843 ps
CPU time 37.4 seconds
Started Apr 02 01:42:03 PM PDT 24
Finished Apr 02 01:42:40 PM PDT 24
Peak memory 216764 kb
Host smart-a797741f-c4cb-4e11-bc36-2de902ebeb60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922322445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.1922322445
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.1982015796
Short name T416
Test name
Test status
Simulation time 4796562115 ps
CPU time 13.87 seconds
Started Apr 02 01:41:53 PM PDT 24
Finished Apr 02 01:42:08 PM PDT 24
Peak memory 216840 kb
Host smart-94bdf9a9-c024-469c-9f04-0d197c811478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982015796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.1982015796
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.1218543809
Short name T610
Test name
Test status
Simulation time 242116608 ps
CPU time 3.82 seconds
Started Apr 02 01:42:00 PM PDT 24
Finished Apr 02 01:42:04 PM PDT 24
Peak memory 216800 kb
Host smart-e5fb3fac-78ce-4a41-a63f-0c5c5c0a554d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218543809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.1218543809
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.133908961
Short name T418
Test name
Test status
Simulation time 90232880 ps
CPU time 1.01 seconds
Started Apr 02 01:41:55 PM PDT 24
Finished Apr 02 01:41:57 PM PDT 24
Peak memory 207236 kb
Host smart-3e4cbe17-27cd-4b8d-ac8a-9e7a5497d244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133908961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.133908961
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.1166877329
Short name T309
Test name
Test status
Simulation time 206755801 ps
CPU time 2.15 seconds
Started Apr 02 01:42:02 PM PDT 24
Finished Apr 02 01:42:04 PM PDT 24
Peak memory 218908 kb
Host smart-5a9b76c4-61d3-4562-a6e4-ed31b26b7e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166877329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.1166877329
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.577350733
Short name T485
Test name
Test status
Simulation time 19445859 ps
CPU time 0.69 seconds
Started Apr 02 01:39:06 PM PDT 24
Finished Apr 02 01:39:07 PM PDT 24
Peak memory 205980 kb
Host smart-511b2f43-d7be-4d65-9716-e58cda7d9d28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577350733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.577350733
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.2012580825
Short name T731
Test name
Test status
Simulation time 613923406 ps
CPU time 10.77 seconds
Started Apr 02 01:39:04 PM PDT 24
Finished Apr 02 01:39:15 PM PDT 24
Peak memory 219020 kb
Host smart-05de24e0-1c04-48cf-9441-e4a5773518e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012580825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.2012580825
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.3419760425
Short name T419
Test name
Test status
Simulation time 47624581 ps
CPU time 0.8 seconds
Started Apr 02 01:39:02 PM PDT 24
Finished Apr 02 01:39:05 PM PDT 24
Peak memory 207076 kb
Host smart-4e94da28-d8a2-4871-a096-1717c6d7b04b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419760425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.3419760425
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.1387715310
Short name T353
Test name
Test status
Simulation time 763152957 ps
CPU time 16.88 seconds
Started Apr 02 01:39:05 PM PDT 24
Finished Apr 02 01:39:23 PM PDT 24
Peak memory 233188 kb
Host smart-ce78cce3-0e38-427f-b78a-48dc657c48f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387715310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.1387715310
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.3855192153
Short name T253
Test name
Test status
Simulation time 3251360438 ps
CPU time 5.43 seconds
Started Apr 02 01:39:05 PM PDT 24
Finished Apr 02 01:39:11 PM PDT 24
Peak memory 219192 kb
Host smart-60a7766b-1885-467e-abe3-1bf95915c09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855192153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.3855192153
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.647526585
Short name T7
Test name
Test status
Simulation time 45562769720 ps
CPU time 56.95 seconds
Started Apr 02 01:39:04 PM PDT 24
Finished Apr 02 01:40:02 PM PDT 24
Peak memory 222208 kb
Host smart-587aa1bf-ff92-43ef-8326-9938c3885c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647526585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.647526585
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.1229068630
Short name T265
Test name
Test status
Simulation time 3199494788 ps
CPU time 8.97 seconds
Started Apr 02 01:39:05 PM PDT 24
Finished Apr 02 01:39:14 PM PDT 24
Peak memory 233644 kb
Host smart-cd176f7d-8e2d-45e1-8f1e-348f7c509e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229068630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.1229068630
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.1204513518
Short name T53
Test name
Test status
Simulation time 465129813 ps
CPU time 2.29 seconds
Started Apr 02 01:39:07 PM PDT 24
Finished Apr 02 01:39:10 PM PDT 24
Peak memory 217372 kb
Host smart-4e46b737-36a9-4751-9421-19044492025e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204513518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1204513518
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_ram_cfg.2584468904
Short name T568
Test name
Test status
Simulation time 120176485 ps
CPU time 0.76 seconds
Started Apr 02 01:39:07 PM PDT 24
Finished Apr 02 01:39:08 PM PDT 24
Peak memory 216716 kb
Host smart-96f78d10-1487-45c6-9e5e-e07bb1e7f5f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584468904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_ram_cfg.2584468904
Directory /workspace/3.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.2916059898
Short name T405
Test name
Test status
Simulation time 1830667737 ps
CPU time 20.03 seconds
Started Apr 02 01:39:06 PM PDT 24
Finished Apr 02 01:39:26 PM PDT 24
Peak memory 223244 kb
Host smart-7d053d0d-611c-4934-aea1-2420e7afdc85
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2916059898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.2916059898
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.811828680
Short name T48
Test name
Test status
Simulation time 36295954 ps
CPU time 0.94 seconds
Started Apr 02 01:39:06 PM PDT 24
Finished Apr 02 01:39:07 PM PDT 24
Peak memory 235388 kb
Host smart-65c20af2-1017-459f-93ec-466376755be8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811828680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.811828680
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.2054937416
Short name T596
Test name
Test status
Simulation time 13056574056 ps
CPU time 8.48 seconds
Started Apr 02 01:39:08 PM PDT 24
Finished Apr 02 01:39:16 PM PDT 24
Peak memory 216748 kb
Host smart-6c4e0129-612b-44a2-a5d3-47bab65fe71f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054937416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.2054937416
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.664197534
Short name T601
Test name
Test status
Simulation time 53098642 ps
CPU time 1.2 seconds
Started Apr 02 01:39:06 PM PDT 24
Finished Apr 02 01:39:07 PM PDT 24
Peak memory 208388 kb
Host smart-ee881656-200f-4af6-a66d-1a42cba6b1ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664197534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.664197534
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.1201631473
Short name T658
Test name
Test status
Simulation time 61255882 ps
CPU time 0.78 seconds
Started Apr 02 01:39:06 PM PDT 24
Finished Apr 02 01:39:06 PM PDT 24
Peak memory 206244 kb
Host smart-e09de4c1-d4df-4d3b-a3ac-390a2cb308f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201631473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.1201631473
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.544107760
Short name T32
Test name
Test status
Simulation time 23737233 ps
CPU time 0.74 seconds
Started Apr 02 01:42:27 PM PDT 24
Finished Apr 02 01:42:28 PM PDT 24
Peak memory 205980 kb
Host smart-ece6f33b-4ed3-4abd-801f-bc17a27e9622
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544107760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.544107760
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.1834772659
Short name T481
Test name
Test status
Simulation time 77111496 ps
CPU time 0.8 seconds
Started Apr 02 01:42:10 PM PDT 24
Finished Apr 02 01:42:11 PM PDT 24
Peak memory 207176 kb
Host smart-97b1a11f-fd48-445c-acc5-e74af468cdc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834772659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.1834772659
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.1835536412
Short name T357
Test name
Test status
Simulation time 474977116 ps
CPU time 15.16 seconds
Started Apr 02 01:42:20 PM PDT 24
Finished Apr 02 01:42:36 PM PDT 24
Peak memory 257680 kb
Host smart-59037ec3-971e-4129-bdd3-8dd29b250059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835536412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1835536412
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.516001897
Short name T244
Test name
Test status
Simulation time 1121047979 ps
CPU time 13.6 seconds
Started Apr 02 01:42:18 PM PDT 24
Finished Apr 02 01:42:32 PM PDT 24
Peak memory 219100 kb
Host smart-9fe00272-83e2-437c-93b4-ff3fbe7a041b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516001897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.516001897
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.3483384094
Short name T174
Test name
Test status
Simulation time 848010586 ps
CPU time 7.59 seconds
Started Apr 02 01:42:13 PM PDT 24
Finished Apr 02 01:42:21 PM PDT 24
Peak memory 236472 kb
Host smart-24fbbab9-8772-43c3-8320-5e27bd9a558d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483384094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.3483384094
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.2606216150
Short name T652
Test name
Test status
Simulation time 955832541 ps
CPU time 4.06 seconds
Started Apr 02 01:42:23 PM PDT 24
Finished Apr 02 01:42:27 PM PDT 24
Peak memory 219604 kb
Host smart-01707814-ceec-4142-ac65-8feba7b09569
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2606216150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.2606216150
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.1565643614
Short name T578
Test name
Test status
Simulation time 79105286 ps
CPU time 1.06 seconds
Started Apr 02 01:42:25 PM PDT 24
Finished Apr 02 01:42:26 PM PDT 24
Peak memory 207732 kb
Host smart-839e2bbf-61b8-4dbc-858d-ac5d8bc91734
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565643614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.1565643614
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.2223465361
Short name T557
Test name
Test status
Simulation time 8418202332 ps
CPU time 24.58 seconds
Started Apr 02 01:42:12 PM PDT 24
Finished Apr 02 01:42:37 PM PDT 24
Peak memory 216920 kb
Host smart-82c9ac4b-dbcf-49ee-96ea-0d38762e004c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223465361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.2223465361
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.585255186
Short name T510
Test name
Test status
Simulation time 3646872003 ps
CPU time 5.45 seconds
Started Apr 02 01:42:10 PM PDT 24
Finished Apr 02 01:42:16 PM PDT 24
Peak memory 216800 kb
Host smart-aad83804-8884-4e9f-80ad-1f2209e03df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585255186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.585255186
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.678652018
Short name T696
Test name
Test status
Simulation time 140715210 ps
CPU time 1.69 seconds
Started Apr 02 01:42:15 PM PDT 24
Finished Apr 02 01:42:17 PM PDT 24
Peak memory 216740 kb
Host smart-9907993f-febf-4d99-9ca1-b2eb625ac786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678652018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.678652018
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.1258976093
Short name T588
Test name
Test status
Simulation time 40192186 ps
CPU time 0.78 seconds
Started Apr 02 01:42:14 PM PDT 24
Finished Apr 02 01:42:14 PM PDT 24
Peak memory 206200 kb
Host smart-15dfd208-3230-4924-8d2c-f7aa255bcb63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258976093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.1258976093
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.39826642
Short name T716
Test name
Test status
Simulation time 11494880 ps
CPU time 0.72 seconds
Started Apr 02 01:42:37 PM PDT 24
Finished Apr 02 01:42:38 PM PDT 24
Peak memory 205904 kb
Host smart-e54d0bdb-5cc0-47f9-8ce5-48b6945feb9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39826642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.39826642
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.3155238752
Short name T479
Test name
Test status
Simulation time 32401102 ps
CPU time 0.79 seconds
Started Apr 02 01:42:28 PM PDT 24
Finished Apr 02 01:42:29 PM PDT 24
Peak memory 207128 kb
Host smart-2e87cf71-d57b-48e0-8e53-3360d513a17c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155238752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.3155238752
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.2574072628
Short name T351
Test name
Test status
Simulation time 22891525064 ps
CPU time 96.78 seconds
Started Apr 02 01:42:36 PM PDT 24
Finished Apr 02 01:44:13 PM PDT 24
Peak memory 253452 kb
Host smart-bb26eeaa-3815-40b7-8455-f72a25dedcda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574072628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.2574072628
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.1968736104
Short name T47
Test name
Test status
Simulation time 5804983746 ps
CPU time 16.63 seconds
Started Apr 02 01:42:34 PM PDT 24
Finished Apr 02 01:42:50 PM PDT 24
Peak memory 219600 kb
Host smart-7d84fb7c-d318-4d93-a22f-d7f69d99fa78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968736104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.1968736104
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.1383729309
Short name T176
Test name
Test status
Simulation time 17000234227 ps
CPU time 68.99 seconds
Started Apr 02 01:42:39 PM PDT 24
Finished Apr 02 01:43:49 PM PDT 24
Peak memory 233424 kb
Host smart-e5328a8c-bedb-4163-aba6-8e1167b89613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383729309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.1383729309
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.1058464019
Short name T257
Test name
Test status
Simulation time 31241350823 ps
CPU time 22.28 seconds
Started Apr 02 01:42:30 PM PDT 24
Finished Apr 02 01:42:53 PM PDT 24
Peak memory 232932 kb
Host smart-047aeca6-e74c-4be5-8cb8-909e2ae948ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058464019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.1058464019
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.339550737
Short name T719
Test name
Test status
Simulation time 200996916 ps
CPU time 3.65 seconds
Started Apr 02 01:42:37 PM PDT 24
Finished Apr 02 01:42:40 PM PDT 24
Peak memory 219344 kb
Host smart-a33a7672-cdcf-4b08-916b-aac03dbcf247
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=339550737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dire
ct.339550737
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.2296977935
Short name T394
Test name
Test status
Simulation time 4076791631 ps
CPU time 29.02 seconds
Started Apr 02 01:42:29 PM PDT 24
Finished Apr 02 01:42:58 PM PDT 24
Peak memory 216784 kb
Host smart-a3b05629-5c17-4ad0-bb73-937e3f8be1fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296977935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.2296977935
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.346039442
Short name T528
Test name
Test status
Simulation time 959612122 ps
CPU time 5.69 seconds
Started Apr 02 01:42:30 PM PDT 24
Finished Apr 02 01:42:36 PM PDT 24
Peak memory 216688 kb
Host smart-2abc898f-3cee-480d-bc74-39202476eebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346039442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.346039442
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.1441744179
Short name T501
Test name
Test status
Simulation time 221455016 ps
CPU time 2.3 seconds
Started Apr 02 01:42:30 PM PDT 24
Finished Apr 02 01:42:32 PM PDT 24
Peak memory 216704 kb
Host smart-b15d06a2-ba92-4908-a737-d7a9ef2543d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441744179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.1441744179
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.1533190374
Short name T706
Test name
Test status
Simulation time 167007032 ps
CPU time 0.84 seconds
Started Apr 02 01:42:40 PM PDT 24
Finished Apr 02 01:42:41 PM PDT 24
Peak memory 206216 kb
Host smart-02f08a1b-1660-4e13-88cd-2b7cfaaa3323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533190374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.1533190374
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.2293096938
Short name T212
Test name
Test status
Simulation time 3696321454 ps
CPU time 15.47 seconds
Started Apr 02 01:42:32 PM PDT 24
Finished Apr 02 01:42:48 PM PDT 24
Peak memory 225012 kb
Host smart-19959e8c-8e29-4762-aaad-76a7fc034554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293096938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.2293096938
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.2045671722
Short name T572
Test name
Test status
Simulation time 12564212 ps
CPU time 0.72 seconds
Started Apr 02 01:42:58 PM PDT 24
Finished Apr 02 01:42:59 PM PDT 24
Peak memory 205912 kb
Host smart-09d29aed-9534-41bf-bc7f-c31c329bf638
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045671722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
2045671722
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.3057778385
Short name T281
Test name
Test status
Simulation time 1277536600 ps
CPU time 12.55 seconds
Started Apr 02 01:42:50 PM PDT 24
Finished Apr 02 01:43:03 PM PDT 24
Peak memory 219052 kb
Host smart-1ad35445-fd9e-4a13-8175-980dd006997c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057778385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.3057778385
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.2477592811
Short name T566
Test name
Test status
Simulation time 46633280 ps
CPU time 0.76 seconds
Started Apr 02 01:42:40 PM PDT 24
Finished Apr 02 01:42:41 PM PDT 24
Peak memory 207068 kb
Host smart-b1855633-1c1b-401b-afc9-c3294bdddfd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477592811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.2477592811
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.3848147971
Short name T549
Test name
Test status
Simulation time 6555930889 ps
CPU time 31.24 seconds
Started Apr 02 01:42:50 PM PDT 24
Finished Apr 02 01:43:21 PM PDT 24
Peak memory 254408 kb
Host smart-400cc7d4-4cfe-4d11-9dd7-103699043841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848147971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.3848147971
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.779662931
Short name T117
Test name
Test status
Simulation time 12708771084 ps
CPU time 29.72 seconds
Started Apr 02 01:42:47 PM PDT 24
Finished Apr 02 01:43:17 PM PDT 24
Peak memory 233584 kb
Host smart-09bb2e43-159b-481b-9bb3-acacef2e3c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779662931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.779662931
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.3276463544
Short name T345
Test name
Test status
Simulation time 6952645717 ps
CPU time 82.76 seconds
Started Apr 02 01:42:52 PM PDT 24
Finished Apr 02 01:44:15 PM PDT 24
Peak memory 225040 kb
Host smart-fe48a325-c27b-4108-beef-4a0e4226c8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276463544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.3276463544
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.472578191
Short name T482
Test name
Test status
Simulation time 3005654944 ps
CPU time 12.7 seconds
Started Apr 02 01:42:52 PM PDT 24
Finished Apr 02 01:43:04 PM PDT 24
Peak memory 222600 kb
Host smart-f742e055-18be-47b8-82b9-78939688310a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=472578191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dire
ct.472578191
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.4083670666
Short name T395
Test name
Test status
Simulation time 665733127 ps
CPU time 2.14 seconds
Started Apr 02 01:42:47 PM PDT 24
Finished Apr 02 01:42:49 PM PDT 24
Peak memory 216944 kb
Host smart-bf997a2c-0ef0-4660-bc25-88275a901e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083670666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.4083670666
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.2175600511
Short name T602
Test name
Test status
Simulation time 297374739 ps
CPU time 1.22 seconds
Started Apr 02 01:42:42 PM PDT 24
Finished Apr 02 01:42:44 PM PDT 24
Peak memory 207272 kb
Host smart-6aaf910b-35d0-4fdb-84af-832512108cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175600511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.2175600511
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.1609520035
Short name T266
Test name
Test status
Simulation time 19580898345 ps
CPU time 22.72 seconds
Started Apr 02 01:42:49 PM PDT 24
Finished Apr 02 01:43:12 PM PDT 24
Peak memory 221092 kb
Host smart-6bfdf7f2-91fd-40d4-ac6f-182106baf5d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609520035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.1609520035
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.381583913
Short name T552
Test name
Test status
Simulation time 15039309 ps
CPU time 0.77 seconds
Started Apr 02 01:43:09 PM PDT 24
Finished Apr 02 01:43:11 PM PDT 24
Peak memory 205872 kb
Host smart-4615ceda-4b22-4634-9942-8aca3e728c8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381583913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.381583913
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.2283300477
Short name T603
Test name
Test status
Simulation time 15974373 ps
CPU time 0.75 seconds
Started Apr 02 01:42:55 PM PDT 24
Finished Apr 02 01:42:56 PM PDT 24
Peak memory 207472 kb
Host smart-0b40b630-1126-4fe3-8806-e186e763a020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283300477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.2283300477
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_intercept.2948564316
Short name T236
Test name
Test status
Simulation time 1350121541 ps
CPU time 6.15 seconds
Started Apr 02 01:43:02 PM PDT 24
Finished Apr 02 01:43:09 PM PDT 24
Peak memory 219232 kb
Host smart-07e33b96-cd17-40f2-a08f-815511415659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948564316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.2948564316
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.2404373264
Short name T591
Test name
Test status
Simulation time 199645529 ps
CPU time 2.44 seconds
Started Apr 02 01:42:57 PM PDT 24
Finished Apr 02 01:43:00 PM PDT 24
Peak memory 216728 kb
Host smart-0cae5487-eeef-4040-a3e8-b18739400454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404373264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.2404373264
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.409101124
Short name T337
Test name
Test status
Simulation time 355632234 ps
CPU time 2.69 seconds
Started Apr 02 01:42:57 PM PDT 24
Finished Apr 02 01:43:00 PM PDT 24
Peak memory 223404 kb
Host smart-1cb0d170-88e4-4cc7-99cd-0b984c382fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409101124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swap
.409101124
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.128038007
Short name T271
Test name
Test status
Simulation time 6060040446 ps
CPU time 10.99 seconds
Started Apr 02 01:43:00 PM PDT 24
Finished Apr 02 01:43:11 PM PDT 24
Peak memory 222320 kb
Host smart-ba11f759-1ae1-4373-8878-15c9dd0f3eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128038007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.128038007
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.1957662739
Short name T688
Test name
Test status
Simulation time 3846233966 ps
CPU time 15.88 seconds
Started Apr 02 01:43:06 PM PDT 24
Finished Apr 02 01:43:22 PM PDT 24
Peak memory 220984 kb
Host smart-20b53c25-da0d-4f5b-84c9-8737208a94f1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1957662739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.1957662739
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.2420277893
Short name T381
Test name
Test status
Simulation time 3987492516 ps
CPU time 26.59 seconds
Started Apr 02 01:42:59 PM PDT 24
Finished Apr 02 01:43:25 PM PDT 24
Peak memory 217076 kb
Host smart-d1e07384-89c7-4afa-bd06-6160debb3433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420277893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.2420277893
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.1634215932
Short name T720
Test name
Test status
Simulation time 2200379538 ps
CPU time 5.2 seconds
Started Apr 02 01:42:55 PM PDT 24
Finished Apr 02 01:43:00 PM PDT 24
Peak memory 216720 kb
Host smart-2e04390c-4147-4da4-8553-2cf5fca38104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634215932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.1634215932
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.2855356103
Short name T387
Test name
Test status
Simulation time 101362286 ps
CPU time 1.38 seconds
Started Apr 02 01:42:59 PM PDT 24
Finished Apr 02 01:43:01 PM PDT 24
Peak memory 216736 kb
Host smart-04fcff47-3081-4bcc-969d-f94225a51a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855356103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.2855356103
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.1032782565
Short name T537
Test name
Test status
Simulation time 60692958 ps
CPU time 0.7 seconds
Started Apr 02 01:42:55 PM PDT 24
Finished Apr 02 01:42:55 PM PDT 24
Peak memory 206208 kb
Host smart-03eb3cff-6fc8-4333-ad92-c08ec36718f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032782565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.1032782565
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.1762079618
Short name T319
Test name
Test status
Simulation time 11919482195 ps
CPU time 10.86 seconds
Started Apr 02 01:43:07 PM PDT 24
Finished Apr 02 01:43:19 PM PDT 24
Peak memory 221004 kb
Host smart-a7d98a9e-d9b5-4d88-b90e-1b26f727a009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762079618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.1762079618
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.1543812909
Short name T660
Test name
Test status
Simulation time 21992222 ps
CPU time 0.71 seconds
Started Apr 02 01:43:22 PM PDT 24
Finished Apr 02 01:43:23 PM PDT 24
Peak memory 206000 kb
Host smart-9732819b-60db-47f6-bf06-d046ca064499
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543812909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
1543812909
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.3459234316
Short name T306
Test name
Test status
Simulation time 1072089441 ps
CPU time 10.7 seconds
Started Apr 02 01:43:19 PM PDT 24
Finished Apr 02 01:43:30 PM PDT 24
Peak memory 219396 kb
Host smart-be21e529-7185-41fd-aa90-47bd5c706640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459234316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.3459234316
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.2512979924
Short name T599
Test name
Test status
Simulation time 116962854 ps
CPU time 0.76 seconds
Started Apr 02 01:43:07 PM PDT 24
Finished Apr 02 01:43:08 PM PDT 24
Peak memory 207040 kb
Host smart-e500b885-4371-4558-9629-3992ea59f3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512979924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.2512979924
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.2803999263
Short name T297
Test name
Test status
Simulation time 2989899910 ps
CPU time 22.08 seconds
Started Apr 02 01:43:14 PM PDT 24
Finished Apr 02 01:43:37 PM PDT 24
Peak memory 236568 kb
Host smart-074e6170-aba4-4c04-8fe4-6e622b0431b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803999263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.2803999263
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.2847998340
Short name T180
Test name
Test status
Simulation time 1946575512 ps
CPU time 7.8 seconds
Started Apr 02 01:43:14 PM PDT 24
Finished Apr 02 01:43:22 PM PDT 24
Peak memory 219124 kb
Host smart-40c251e9-107a-4f06-bc9f-2d0903942b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847998340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.2847998340
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.3306522745
Short name T339
Test name
Test status
Simulation time 7256737057 ps
CPU time 21.77 seconds
Started Apr 02 01:43:13 PM PDT 24
Finished Apr 02 01:43:35 PM PDT 24
Peak memory 236660 kb
Host smart-5b6888e3-3adb-48ec-a5a8-9fcfd461491b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306522745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.3306522745
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.1686820361
Short name T14
Test name
Test status
Simulation time 93389579 ps
CPU time 3.51 seconds
Started Apr 02 01:43:17 PM PDT 24
Finished Apr 02 01:43:21 PM PDT 24
Peak memory 220456 kb
Host smart-605ef735-6de3-44ec-aa1b-9bcb44585182
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1686820361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.1686820361
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.3533483754
Short name T401
Test name
Test status
Simulation time 77147223793 ps
CPU time 75.35 seconds
Started Apr 02 01:43:11 PM PDT 24
Finished Apr 02 01:44:27 PM PDT 24
Peak memory 216792 kb
Host smart-37944b47-a13f-4d92-9cc9-2a4d56ec2f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533483754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.3533483754
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.614813829
Short name T496
Test name
Test status
Simulation time 8849879324 ps
CPU time 22.76 seconds
Started Apr 02 01:43:12 PM PDT 24
Finished Apr 02 01:43:35 PM PDT 24
Peak memory 216736 kb
Host smart-7cd49daa-8fe3-4976-ac15-ea0dab97cc77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614813829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.614813829
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.1689900638
Short name T730
Test name
Test status
Simulation time 231330891 ps
CPU time 0.94 seconds
Started Apr 02 01:43:11 PM PDT 24
Finished Apr 02 01:43:12 PM PDT 24
Peak memory 207648 kb
Host smart-fc17d090-bbc2-4e58-924f-657c6c2005d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689900638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.1689900638
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.1749641544
Short name T612
Test name
Test status
Simulation time 25628501 ps
CPU time 0.82 seconds
Started Apr 02 01:43:14 PM PDT 24
Finished Apr 02 01:43:15 PM PDT 24
Peak memory 206256 kb
Host smart-1280011d-0ef1-4cf4-ac73-e275e646898a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749641544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.1749641544
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.2214434899
Short name T313
Test name
Test status
Simulation time 190755196 ps
CPU time 3.91 seconds
Started Apr 02 01:43:17 PM PDT 24
Finished Apr 02 01:43:21 PM PDT 24
Peak memory 223596 kb
Host smart-32a134f3-27d4-4972-8b5f-4755d34ad3d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214434899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.2214434899
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.3236585498
Short name T711
Test name
Test status
Simulation time 39537910 ps
CPU time 0.71 seconds
Started Apr 02 01:43:36 PM PDT 24
Finished Apr 02 01:43:38 PM PDT 24
Peak memory 205424 kb
Host smart-e5b1f7a0-b66c-4e6a-a581-01ddff012170
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236585498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
3236585498
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.1195434941
Short name T407
Test name
Test status
Simulation time 16351198 ps
CPU time 0.74 seconds
Started Apr 02 01:43:21 PM PDT 24
Finished Apr 02 01:43:22 PM PDT 24
Peak memory 207456 kb
Host smart-dd3795a8-9da6-4a83-abff-2bfd33794e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195434941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.1195434941
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.3399094058
Short name T656
Test name
Test status
Simulation time 403883635 ps
CPU time 10.89 seconds
Started Apr 02 01:43:32 PM PDT 24
Finished Apr 02 01:43:43 PM PDT 24
Peak memory 233344 kb
Host smart-3fd37e8b-a3e9-4896-981a-b2e164a60f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399094058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.3399094058
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.1584309400
Short name T314
Test name
Test status
Simulation time 183837782 ps
CPU time 4.94 seconds
Started Apr 02 01:43:30 PM PDT 24
Finished Apr 02 01:43:35 PM PDT 24
Peak memory 224500 kb
Host smart-bbee30d1-e39a-48a0-8179-f70374c27c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584309400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.1584309400
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.831144623
Short name T665
Test name
Test status
Simulation time 352295432 ps
CPU time 8.48 seconds
Started Apr 02 01:43:31 PM PDT 24
Finished Apr 02 01:43:40 PM PDT 24
Peak memory 238880 kb
Host smart-8fc42144-fd6d-4f6f-b854-2299a4b40fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831144623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.831144623
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.3809630441
Short name T443
Test name
Test status
Simulation time 178094037 ps
CPU time 4.69 seconds
Started Apr 02 01:43:34 PM PDT 24
Finished Apr 02 01:43:39 PM PDT 24
Peak memory 221080 kb
Host smart-8c088d5f-602b-4ef3-8559-3616bc26eefd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3809630441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.3809630441
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.2325840149
Short name T685
Test name
Test status
Simulation time 2576135623 ps
CPU time 39.67 seconds
Started Apr 02 01:43:24 PM PDT 24
Finished Apr 02 01:44:04 PM PDT 24
Peak memory 217092 kb
Host smart-17663c9e-9567-4bde-878c-9bad14e3c2a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325840149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.2325840149
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.3328711590
Short name T109
Test name
Test status
Simulation time 6613631052 ps
CPU time 9.38 seconds
Started Apr 02 01:43:22 PM PDT 24
Finished Apr 02 01:43:32 PM PDT 24
Peak memory 216764 kb
Host smart-efec591e-c63c-4b41-aed1-dd9c068b3db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328711590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.3328711590
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.1462983410
Short name T536
Test name
Test status
Simulation time 108990042 ps
CPU time 1.02 seconds
Started Apr 02 01:43:26 PM PDT 24
Finished Apr 02 01:43:27 PM PDT 24
Peak memory 207772 kb
Host smart-2e46abd6-3c70-4cf0-b66c-d192cbb9a3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462983410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.1462983410
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.3015488861
Short name T628
Test name
Test status
Simulation time 38177947 ps
CPU time 0.9 seconds
Started Apr 02 01:43:26 PM PDT 24
Finished Apr 02 01:43:27 PM PDT 24
Peak memory 207216 kb
Host smart-7e19f8b2-1cf2-445c-a806-ebe4d4689109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015488861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.3015488861
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.1334019421
Short name T525
Test name
Test status
Simulation time 14683963 ps
CPU time 0.69 seconds
Started Apr 02 01:43:46 PM PDT 24
Finished Apr 02 01:43:47 PM PDT 24
Peak memory 205396 kb
Host smart-3d5c942d-b815-4eb5-8bb3-e7d15e440866
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334019421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
1334019421
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.79366639
Short name T453
Test name
Test status
Simulation time 25712739 ps
CPU time 0.81 seconds
Started Apr 02 01:43:36 PM PDT 24
Finished Apr 02 01:43:38 PM PDT 24
Peak memory 207172 kb
Host smart-2de0cff5-9888-437e-be04-84335e22f540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79366639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.79366639
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.1213957536
Short name T296
Test name
Test status
Simulation time 1682103845 ps
CPU time 37.57 seconds
Started Apr 02 01:43:44 PM PDT 24
Finished Apr 02 01:44:21 PM PDT 24
Peak memory 249580 kb
Host smart-81976823-a6c5-4344-928e-fc2ee806008b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213957536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.1213957536
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.2518897275
Short name T674
Test name
Test status
Simulation time 2654588237 ps
CPU time 36.5 seconds
Started Apr 02 01:43:40 PM PDT 24
Finished Apr 02 01:44:16 PM PDT 24
Peak memory 227420 kb
Host smart-7f54a06c-24b5-4fa6-9d4c-e1b3b0e903b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518897275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.2518897275
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.2323385310
Short name T73
Test name
Test status
Simulation time 5573708998 ps
CPU time 15.62 seconds
Started Apr 02 01:43:42 PM PDT 24
Finished Apr 02 01:43:58 PM PDT 24
Peak memory 223024 kb
Host smart-0d83028a-4e85-4890-aced-592d16b09a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323385310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.2323385310
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.4096746448
Short name T429
Test name
Test status
Simulation time 773593303 ps
CPU time 9.54 seconds
Started Apr 02 01:43:43 PM PDT 24
Finished Apr 02 01:43:52 PM PDT 24
Peak memory 223392 kb
Host smart-52cbdcb2-e9f9-48e9-9f63-c62faef0b74c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4096746448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.4096746448
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.1355862267
Short name T687
Test name
Test status
Simulation time 66697201 ps
CPU time 1.14 seconds
Started Apr 02 01:43:45 PM PDT 24
Finished Apr 02 01:43:47 PM PDT 24
Peak memory 207732 kb
Host smart-efc9eab0-3f67-407c-96f7-dbd89ec6ad76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355862267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.1355862267
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.1671102760
Short name T383
Test name
Test status
Simulation time 10360508028 ps
CPU time 29.41 seconds
Started Apr 02 01:43:36 PM PDT 24
Finished Apr 02 01:44:06 PM PDT 24
Peak memory 216776 kb
Host smart-ec763626-b3d3-4d01-8212-f6cddcdc9665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671102760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.1671102760
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.2011582067
Short name T539
Test name
Test status
Simulation time 4763778698 ps
CPU time 5.7 seconds
Started Apr 02 01:43:35 PM PDT 24
Finished Apr 02 01:43:41 PM PDT 24
Peak memory 216768 kb
Host smart-7655bd52-959f-46f4-b8cc-9c5e502c76d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011582067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.2011582067
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.3413590228
Short name T445
Test name
Test status
Simulation time 976594094 ps
CPU time 2.99 seconds
Started Apr 02 01:43:39 PM PDT 24
Finished Apr 02 01:43:42 PM PDT 24
Peak memory 216776 kb
Host smart-db06b251-6607-4e3e-a609-d605a8b9f0b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413590228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.3413590228
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.1625858138
Short name T458
Test name
Test status
Simulation time 492337211 ps
CPU time 0.98 seconds
Started Apr 02 01:43:40 PM PDT 24
Finished Apr 02 01:43:41 PM PDT 24
Peak memory 207280 kb
Host smart-e50cd116-6280-4eb3-a662-8af331fa2cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625858138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.1625858138
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.369880271
Short name T679
Test name
Test status
Simulation time 14323350 ps
CPU time 0.75 seconds
Started Apr 02 01:44:00 PM PDT 24
Finished Apr 02 01:44:01 PM PDT 24
Peak memory 205972 kb
Host smart-1943ea7a-b227-4e14-ba5c-0614be405d99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369880271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.369880271
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.4257198551
Short name T9
Test name
Test status
Simulation time 730885735 ps
CPU time 3.82 seconds
Started Apr 02 01:43:56 PM PDT 24
Finished Apr 02 01:44:00 PM PDT 24
Peak memory 219184 kb
Host smart-83bf5f87-0814-4439-bea2-2ca68d782858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257198551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.4257198551
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.1298073991
Short name T455
Test name
Test status
Simulation time 105685314 ps
CPU time 0.81 seconds
Started Apr 02 01:43:47 PM PDT 24
Finished Apr 02 01:43:48 PM PDT 24
Peak memory 207072 kb
Host smart-80d435ff-9211-4f71-b880-a6e0fa6bf733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298073991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.1298073991
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.3097141203
Short name T360
Test name
Test status
Simulation time 5702793202 ps
CPU time 64.89 seconds
Started Apr 02 01:43:56 PM PDT 24
Finished Apr 02 01:45:01 PM PDT 24
Peak memory 234288 kb
Host smart-7b678149-22d7-47cf-b367-7e29f288cabe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097141203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.3097141203
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.2844709767
Short name T44
Test name
Test status
Simulation time 284694937 ps
CPU time 4.31 seconds
Started Apr 02 01:43:55 PM PDT 24
Finished Apr 02 01:44:00 PM PDT 24
Peak memory 219248 kb
Host smart-19120087-6212-49d1-9029-68c13117be8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844709767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.2844709767
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.3240438084
Short name T506
Test name
Test status
Simulation time 222858972 ps
CPU time 5.66 seconds
Started Apr 02 01:43:58 PM PDT 24
Finished Apr 02 01:44:04 PM PDT 24
Peak memory 222240 kb
Host smart-649e2c7d-ca72-4c8b-9c98-5e7dec8dcd40
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3240438084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.3240438084
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.3977507661
Short name T723
Test name
Test status
Simulation time 7403595981 ps
CPU time 41.27 seconds
Started Apr 02 01:43:48 PM PDT 24
Finished Apr 02 01:44:30 PM PDT 24
Peak memory 216712 kb
Host smart-ee136e0e-6f05-442e-ba58-6a36c2645296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977507661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.3977507661
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.583297874
Short name T17
Test name
Test status
Simulation time 1257485388 ps
CPU time 7.76 seconds
Started Apr 02 01:43:51 PM PDT 24
Finished Apr 02 01:43:59 PM PDT 24
Peak memory 216608 kb
Host smart-d7cf8e49-312e-46e1-9853-60238674c2db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583297874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.583297874
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.3417111625
Short name T59
Test name
Test status
Simulation time 698381414 ps
CPU time 6.78 seconds
Started Apr 02 01:43:50 PM PDT 24
Finished Apr 02 01:43:57 PM PDT 24
Peak memory 216880 kb
Host smart-a4d6c3c5-9f17-4914-b6d0-2ec1d9a40aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417111625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.3417111625
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.3462602089
Short name T477
Test name
Test status
Simulation time 28671585 ps
CPU time 0.7 seconds
Started Apr 02 01:43:50 PM PDT 24
Finished Apr 02 01:43:51 PM PDT 24
Peak memory 206308 kb
Host smart-e0b4c0ab-a280-4750-bf57-13a6ab03b226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462602089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.3462602089
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.1464747180
Short name T635
Test name
Test status
Simulation time 37291207 ps
CPU time 0.72 seconds
Started Apr 02 01:44:11 PM PDT 24
Finished Apr 02 01:44:12 PM PDT 24
Peak memory 205924 kb
Host smart-c769ba28-7ab7-46a8-b0fc-797ea9ffc4b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464747180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
1464747180
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.3614780857
Short name T428
Test name
Test status
Simulation time 54558839 ps
CPU time 0.74 seconds
Started Apr 02 01:44:00 PM PDT 24
Finished Apr 02 01:44:01 PM PDT 24
Peak memory 206460 kb
Host smart-d5700dff-a6a6-4277-92d3-531f55522a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614780857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.3614780857
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.2754751446
Short name T336
Test name
Test status
Simulation time 407780009 ps
CPU time 4.72 seconds
Started Apr 02 01:44:08 PM PDT 24
Finished Apr 02 01:44:13 PM PDT 24
Peak memory 223888 kb
Host smart-57110f46-bc15-4a3e-b959-7012bfcf08f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754751446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.2754751446
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.3917139464
Short name T655
Test name
Test status
Simulation time 853919540 ps
CPU time 9.74 seconds
Started Apr 02 01:44:11 PM PDT 24
Finished Apr 02 01:44:20 PM PDT 24
Peak memory 223356 kb
Host smart-2eaca737-3b0b-41c1-a7b2-18546314bec7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3917139464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.3917139464
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.572237638
Short name T561
Test name
Test status
Simulation time 17112031831 ps
CPU time 16.19 seconds
Started Apr 02 01:44:00 PM PDT 24
Finished Apr 02 01:44:16 PM PDT 24
Peak memory 216784 kb
Host smart-7644021a-139d-4b5f-844c-1ae0d7c7ba07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572237638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.572237638
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.2319699356
Short name T594
Test name
Test status
Simulation time 14365451 ps
CPU time 0.78 seconds
Started Apr 02 01:44:04 PM PDT 24
Finished Apr 02 01:44:05 PM PDT 24
Peak memory 206248 kb
Host smart-45110008-a291-4c8f-859e-642a2b669d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319699356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.2319699356
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.1185654833
Short name T590
Test name
Test status
Simulation time 32908882 ps
CPU time 0.82 seconds
Started Apr 02 01:44:02 PM PDT 24
Finished Apr 02 01:44:03 PM PDT 24
Peak memory 206216 kb
Host smart-4022510b-ba15-4069-a827-c0c7333e4a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185654833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.1185654833
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.3658258632
Short name T462
Test name
Test status
Simulation time 16492233 ps
CPU time 0.69 seconds
Started Apr 02 01:44:29 PM PDT 24
Finished Apr 02 01:44:30 PM PDT 24
Peak memory 205952 kb
Host smart-a1af5871-e874-42cb-b15a-fb4d63a6a122
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658258632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
3658258632
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.4033646469
Short name T589
Test name
Test status
Simulation time 6026909781 ps
CPU time 9.72 seconds
Started Apr 02 01:44:27 PM PDT 24
Finished Apr 02 01:44:37 PM PDT 24
Peak memory 234024 kb
Host smart-6218bdf2-f921-4611-86c2-712f65288cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033646469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.4033646469
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.2630055389
Short name T168
Test name
Test status
Simulation time 36137009 ps
CPU time 0.81 seconds
Started Apr 02 01:44:13 PM PDT 24
Finished Apr 02 01:44:14 PM PDT 24
Peak memory 206048 kb
Host smart-508819d9-f802-4c26-a62b-75b717908d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630055389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.2630055389
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.4093573844
Short name T293
Test name
Test status
Simulation time 3569035126 ps
CPU time 60.61 seconds
Started Apr 02 01:44:18 PM PDT 24
Finished Apr 02 01:45:19 PM PDT 24
Peak memory 240460 kb
Host smart-9459aec1-5b72-47ea-8273-c8cda1c8e7ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093573844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.4093573844
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.4211408711
Short name T316
Test name
Test status
Simulation time 9544179685 ps
CPU time 26.26 seconds
Started Apr 02 01:44:19 PM PDT 24
Finished Apr 02 01:44:45 PM PDT 24
Peak memory 227880 kb
Host smart-023395ce-6f25-4aee-a75f-0b96ab8c202b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211408711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.4211408711
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.3342655596
Short name T277
Test name
Test status
Simulation time 1711029010 ps
CPU time 12.44 seconds
Started Apr 02 01:44:21 PM PDT 24
Finished Apr 02 01:44:33 PM PDT 24
Peak memory 241040 kb
Host smart-e5c08e2a-13eb-4860-b88b-14bea2e585a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342655596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.3342655596
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.3036835225
Short name T161
Test name
Test status
Simulation time 471938865 ps
CPU time 5.95 seconds
Started Apr 02 01:44:22 PM PDT 24
Finished Apr 02 01:44:28 PM PDT 24
Peak memory 221104 kb
Host smart-c76c4be3-44fe-4a36-b383-43d8f09df585
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3036835225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.3036835225
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.3895654258
Short name T450
Test name
Test status
Simulation time 1306276900 ps
CPU time 3.88 seconds
Started Apr 02 01:44:15 PM PDT 24
Finished Apr 02 01:44:19 PM PDT 24
Peak memory 216760 kb
Host smart-9d878d97-afd5-46f1-9067-facf8950d74b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895654258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.3895654258
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.3727312122
Short name T633
Test name
Test status
Simulation time 25535567 ps
CPU time 1 seconds
Started Apr 02 01:44:19 PM PDT 24
Finished Apr 02 01:44:20 PM PDT 24
Peak memory 207800 kb
Host smart-a2b3e75e-48a8-43de-b95a-fa4e2e843306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727312122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.3727312122
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.76156100
Short name T684
Test name
Test status
Simulation time 105238444 ps
CPU time 1.03 seconds
Started Apr 02 01:44:13 PM PDT 24
Finished Apr 02 01:44:14 PM PDT 24
Peak memory 206588 kb
Host smart-a1e1a82d-9e39-4a9e-956f-1c3eb3e1349e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76156100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.76156100
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.4106659955
Short name T332
Test name
Test status
Simulation time 23667590259 ps
CPU time 41.7 seconds
Started Apr 02 01:44:20 PM PDT 24
Finished Apr 02 01:45:02 PM PDT 24
Peak memory 216844 kb
Host smart-591f3a9e-b185-437a-8add-7979b6169e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106659955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.4106659955
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.1149214321
Short name T422
Test name
Test status
Simulation time 21146238 ps
CPU time 0.73 seconds
Started Apr 02 01:39:15 PM PDT 24
Finished Apr 02 01:39:16 PM PDT 24
Peak memory 206324 kb
Host smart-a8518ffe-00d2-4066-91bc-62d85920fa40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149214321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.1
149214321
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.4246331889
Short name T715
Test name
Test status
Simulation time 36543982 ps
CPU time 0.79 seconds
Started Apr 02 01:39:15 PM PDT 24
Finished Apr 02 01:39:16 PM PDT 24
Peak memory 207024 kb
Host smart-f557640b-c6f0-4534-9e42-6b473f33a2e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246331889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.4246331889
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.173918189
Short name T350
Test name
Test status
Simulation time 18449092975 ps
CPU time 113.1 seconds
Started Apr 02 01:39:15 PM PDT 24
Finished Apr 02 01:41:09 PM PDT 24
Peak memory 237440 kb
Host smart-ec9dc7f6-3052-46f7-8d14-bee8b07d6d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173918189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.173918189
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.352117139
Short name T320
Test name
Test status
Simulation time 4431099523 ps
CPU time 26.88 seconds
Started Apr 02 01:39:08 PM PDT 24
Finished Apr 02 01:39:35 PM PDT 24
Peak memory 223828 kb
Host smart-2c22a09a-148a-43cd-95f9-ee31c71230da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352117139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.352117139
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.4189320606
Short name T175
Test name
Test status
Simulation time 593051150 ps
CPU time 5.74 seconds
Started Apr 02 01:39:09 PM PDT 24
Finished Apr 02 01:39:15 PM PDT 24
Peak memory 217276 kb
Host smart-f03ee745-3663-4e26-9135-5eba3cd773a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189320606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.4189320606
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_ram_cfg.1106680188
Short name T686
Test name
Test status
Simulation time 14951959 ps
CPU time 0.76 seconds
Started Apr 02 01:39:09 PM PDT 24
Finished Apr 02 01:39:10 PM PDT 24
Peak memory 216748 kb
Host smart-9516a82c-1275-4421-a774-37256f3b5dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106680188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_ram_cfg.1106680188
Directory /workspace/4.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.2198733096
Short name T436
Test name
Test status
Simulation time 249923560 ps
CPU time 4.39 seconds
Started Apr 02 01:39:18 PM PDT 24
Finished Apr 02 01:39:22 PM PDT 24
Peak memory 219440 kb
Host smart-23785317-8ea0-4df1-b897-10b6b55d64a5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2198733096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.2198733096
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.201059882
Short name T51
Test name
Test status
Simulation time 65667931 ps
CPU time 0.97 seconds
Started Apr 02 01:39:28 PM PDT 24
Finished Apr 02 01:39:29 PM PDT 24
Peak memory 235752 kb
Host smart-3d000b50-cac9-41f3-b139-3662742c829c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201059882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.201059882
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.3997844832
Short name T373
Test name
Test status
Simulation time 1251414456 ps
CPU time 18.71 seconds
Started Apr 02 01:39:10 PM PDT 24
Finished Apr 02 01:39:30 PM PDT 24
Peak memory 219500 kb
Host smart-cf05a39a-f882-432a-b908-1d2ff6838513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997844832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.3997844832
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.3466248508
Short name T20
Test name
Test status
Simulation time 7399406822 ps
CPU time 23.44 seconds
Started Apr 02 01:39:15 PM PDT 24
Finished Apr 02 01:39:39 PM PDT 24
Peak memory 216820 kb
Host smart-1b2b0ee3-b0ca-4699-856f-1c368f10f3e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466248508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.3466248508
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.1227325241
Short name T434
Test name
Test status
Simulation time 195555147 ps
CPU time 3.3 seconds
Started Apr 02 01:39:13 PM PDT 24
Finished Apr 02 01:39:16 PM PDT 24
Peak memory 216784 kb
Host smart-96bfc5f4-8bd7-452f-af21-565d883d2d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227325241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.1227325241
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.2412039536
Short name T691
Test name
Test status
Simulation time 152558860 ps
CPU time 1.05 seconds
Started Apr 02 01:39:09 PM PDT 24
Finished Apr 02 01:39:10 PM PDT 24
Peak memory 207204 kb
Host smart-6b1a26e6-d376-4733-b99d-9642180d05db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412039536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.2412039536
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.3053049934
Short name T349
Test name
Test status
Simulation time 5290764762 ps
CPU time 21.49 seconds
Started Apr 02 01:39:09 PM PDT 24
Finished Apr 02 01:39:31 PM PDT 24
Peak memory 235284 kb
Host smart-f33ceb98-c527-4788-946d-b5d37ef4b8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053049934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.3053049934
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.3381204880
Short name T735
Test name
Test status
Simulation time 21127636 ps
CPU time 0.72 seconds
Started Apr 02 01:44:37 PM PDT 24
Finished Apr 02 01:44:39 PM PDT 24
Peak memory 205948 kb
Host smart-cc2467c6-4c31-40c2-85f0-2c0d9c5d6465
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381204880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
3381204880
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.3689170981
Short name T729
Test name
Test status
Simulation time 30488407 ps
CPU time 0.76 seconds
Started Apr 02 01:44:28 PM PDT 24
Finished Apr 02 01:44:28 PM PDT 24
Peak memory 207408 kb
Host smart-68f453d9-7c4b-44f3-b626-55eb828535e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689170981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.3689170981
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.25667046
Short name T605
Test name
Test status
Simulation time 47151269971 ps
CPU time 111.81 seconds
Started Apr 02 01:44:34 PM PDT 24
Finished Apr 02 01:46:26 PM PDT 24
Peak memory 240640 kb
Host smart-1ddeb12b-9d06-488c-a1bc-8642ba4cf0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25667046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.25667046
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.1180480895
Short name T643
Test name
Test status
Simulation time 617766412 ps
CPU time 9.61 seconds
Started Apr 02 01:44:34 PM PDT 24
Finished Apr 02 01:44:43 PM PDT 24
Peak memory 217220 kb
Host smart-7f5be40c-6b6c-4c13-9401-5fe09bd6547c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180480895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.1180480895
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.1590981545
Short name T359
Test name
Test status
Simulation time 38377959 ps
CPU time 2.52 seconds
Started Apr 02 01:44:32 PM PDT 24
Finished Apr 02 01:44:35 PM PDT 24
Peak memory 222324 kb
Host smart-db421ada-3ced-415b-9908-a327aaf96b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590981545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.1590981545
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.1153984093
Short name T95
Test name
Test status
Simulation time 143965501 ps
CPU time 3.17 seconds
Started Apr 02 01:44:34 PM PDT 24
Finished Apr 02 01:44:38 PM PDT 24
Peak memory 223488 kb
Host smart-a7664eba-0a58-4d09-a9f6-6f0c4bd2e36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153984093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.1153984093
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.2182300778
Short name T736
Test name
Test status
Simulation time 3692826347 ps
CPU time 8.49 seconds
Started Apr 02 01:44:37 PM PDT 24
Finished Apr 02 01:44:46 PM PDT 24
Peak memory 221092 kb
Host smart-3b11629f-b698-4a55-8ff8-3fff03c1fe52
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2182300778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.2182300778
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.433004363
Short name T22
Test name
Test status
Simulation time 350344413 ps
CPU time 1.21 seconds
Started Apr 02 01:44:37 PM PDT 24
Finished Apr 02 01:44:39 PM PDT 24
Peak memory 207708 kb
Host smart-4d01b687-7ca4-46de-b636-32191fbeea11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433004363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stres
s_all.433004363
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.662368967
Short name T702
Test name
Test status
Simulation time 691183075 ps
CPU time 2.58 seconds
Started Apr 02 01:44:31 PM PDT 24
Finished Apr 02 01:44:34 PM PDT 24
Peak memory 216960 kb
Host smart-38add15b-4723-4b35-a765-a1d3a97b13af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662368967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.662368967
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.3288501864
Short name T563
Test name
Test status
Simulation time 2085213365 ps
CPU time 11.37 seconds
Started Apr 02 01:44:28 PM PDT 24
Finished Apr 02 01:44:39 PM PDT 24
Peak memory 216668 kb
Host smart-3c9bd731-4c4f-418a-a97c-1197df45853c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288501864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.3288501864
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.2131744148
Short name T551
Test name
Test status
Simulation time 87641390 ps
CPU time 1.59 seconds
Started Apr 02 01:44:36 PM PDT 24
Finished Apr 02 01:44:39 PM PDT 24
Peak memory 216764 kb
Host smart-8f2f1f1e-e006-43cf-a016-d636681e2119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131744148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.2131744148
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.3841280085
Short name T411
Test name
Test status
Simulation time 87741099 ps
CPU time 0.83 seconds
Started Apr 02 01:44:32 PM PDT 24
Finished Apr 02 01:44:34 PM PDT 24
Peak memory 206236 kb
Host smart-3be70b32-84cd-4cbc-a5a9-a9cf9f810b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841280085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.3841280085
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.3594616179
Short name T467
Test name
Test status
Simulation time 15084660 ps
CPU time 0.76 seconds
Started Apr 02 01:44:51 PM PDT 24
Finished Apr 02 01:44:52 PM PDT 24
Peak memory 205980 kb
Host smart-2bf5f07b-4249-4545-b23a-80a8d27137b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594616179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
3594616179
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.3919004282
Short name T524
Test name
Test status
Simulation time 31406924 ps
CPU time 0.81 seconds
Started Apr 02 01:44:41 PM PDT 24
Finished Apr 02 01:44:42 PM PDT 24
Peak memory 207060 kb
Host smart-3db5cc3b-bfb4-4da5-ae72-91a8fbd60d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919004282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.3919004282
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.3547335351
Short name T544
Test name
Test status
Simulation time 7344594703 ps
CPU time 91.92 seconds
Started Apr 02 01:44:47 PM PDT 24
Finished Apr 02 01:46:20 PM PDT 24
Peak memory 252488 kb
Host smart-e98938df-80a1-45d1-b260-72c03a16b2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547335351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.3547335351
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.3195750692
Short name T209
Test name
Test status
Simulation time 9794561432 ps
CPU time 24.23 seconds
Started Apr 02 01:44:46 PM PDT 24
Finished Apr 02 01:45:11 PM PDT 24
Peak memory 223436 kb
Host smart-b6ca3541-4cfc-405f-9c6e-d0b2eb0a2fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195750692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.3195750692
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.1066391905
Short name T326
Test name
Test status
Simulation time 2824370304 ps
CPU time 13.17 seconds
Started Apr 02 01:44:48 PM PDT 24
Finished Apr 02 01:45:01 PM PDT 24
Peak memory 223348 kb
Host smart-5afe0434-b32e-4e5d-bf30-3e323de80006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066391905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.1066391905
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.4124746851
Short name T195
Test name
Test status
Simulation time 19999407351 ps
CPU time 27.85 seconds
Started Apr 02 01:44:44 PM PDT 24
Finished Apr 02 01:45:12 PM PDT 24
Peak memory 236332 kb
Host smart-f6f5506d-5a4d-43f1-8d4f-cddb859b1e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124746851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.4124746851
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.2430386294
Short name T196
Test name
Test status
Simulation time 73292627222 ps
CPU time 26.33 seconds
Started Apr 02 01:44:49 PM PDT 24
Finished Apr 02 01:45:16 PM PDT 24
Peak memory 222576 kb
Host smart-fa9012bb-63b7-41ec-9cca-7805943c078f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430386294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.2430386294
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.432685774
Short name T511
Test name
Test status
Simulation time 442361116 ps
CPU time 5 seconds
Started Apr 02 01:44:52 PM PDT 24
Finished Apr 02 01:44:58 PM PDT 24
Peak memory 223448 kb
Host smart-02340178-69e0-4fab-a662-f5f1e347324f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=432685774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dire
ct.432685774
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.1560335762
Short name T675
Test name
Test status
Simulation time 12398170366 ps
CPU time 40.95 seconds
Started Apr 02 01:44:38 PM PDT 24
Finished Apr 02 01:45:19 PM PDT 24
Peak memory 216828 kb
Host smart-a0a4fb1a-bd8c-4d1b-b260-e47514905184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560335762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.1560335762
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.3677099615
Short name T690
Test name
Test status
Simulation time 9840728022 ps
CPU time 11.19 seconds
Started Apr 02 01:44:42 PM PDT 24
Finished Apr 02 01:44:53 PM PDT 24
Peak memory 216752 kb
Host smart-60eeacdb-c8e1-4bda-b0d9-57bbc8177e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677099615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.3677099615
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.157087680
Short name T498
Test name
Test status
Simulation time 115656543 ps
CPU time 2.96 seconds
Started Apr 02 01:44:44 PM PDT 24
Finished Apr 02 01:44:47 PM PDT 24
Peak memory 216724 kb
Host smart-afe4227f-724a-4a43-9291-2813ebba6c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157087680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.157087680
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.4095315905
Short name T678
Test name
Test status
Simulation time 170767590 ps
CPU time 1.25 seconds
Started Apr 02 01:44:43 PM PDT 24
Finished Apr 02 01:44:45 PM PDT 24
Peak memory 207256 kb
Host smart-72af30a6-b535-4410-918f-6eeaf0c75a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095315905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.4095315905
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.2575499923
Short name T278
Test name
Test status
Simulation time 16866206413 ps
CPU time 51.94 seconds
Started Apr 02 01:44:47 PM PDT 24
Finished Apr 02 01:45:40 PM PDT 24
Peak memory 233240 kb
Host smart-00e76846-979d-4205-b045-100c6ba101f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575499923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.2575499923
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.1080819001
Short name T475
Test name
Test status
Simulation time 18909976 ps
CPU time 0.73 seconds
Started Apr 02 01:45:05 PM PDT 24
Finished Apr 02 01:45:06 PM PDT 24
Peak memory 205408 kb
Host smart-8a1c66ba-9465-4799-9b9f-607306def0ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080819001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
1080819001
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.3377123408
Short name T108
Test name
Test status
Simulation time 3285462544 ps
CPU time 28.5 seconds
Started Apr 02 01:44:59 PM PDT 24
Finished Apr 02 01:45:28 PM PDT 24
Peak memory 224920 kb
Host smart-e796238f-a9ae-4f01-9caf-783722abcbb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377123408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.3377123408
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.3019607365
Short name T420
Test name
Test status
Simulation time 28475484 ps
CPU time 0.76 seconds
Started Apr 02 01:44:55 PM PDT 24
Finished Apr 02 01:44:56 PM PDT 24
Peak memory 207140 kb
Host smart-0af0028a-9e8f-4e2b-b2a8-a649c0e44ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019607365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.3019607365
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.2316945552
Short name T291
Test name
Test status
Simulation time 5232478120 ps
CPU time 70.7 seconds
Started Apr 02 01:45:02 PM PDT 24
Finished Apr 02 01:46:12 PM PDT 24
Peak memory 240904 kb
Host smart-fd307867-73fd-456f-b808-3b56a8909bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316945552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.2316945552
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.1774675788
Short name T261
Test name
Test status
Simulation time 1768008529 ps
CPU time 6.91 seconds
Started Apr 02 01:44:57 PM PDT 24
Finished Apr 02 01:45:04 PM PDT 24
Peak memory 217060 kb
Host smart-8f0d015f-4d16-41d6-9549-68c56533adf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774675788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.1774675788
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.3943946997
Short name T344
Test name
Test status
Simulation time 4516444271 ps
CPU time 12.36 seconds
Started Apr 02 01:45:02 PM PDT 24
Finished Apr 02 01:45:15 PM PDT 24
Peak memory 233288 kb
Host smart-15029550-cf26-4894-a4c1-8d2d8d28a06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943946997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.3943946997
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.920189574
Short name T187
Test name
Test status
Simulation time 571301798 ps
CPU time 3.74 seconds
Started Apr 02 01:44:59 PM PDT 24
Finished Apr 02 01:45:03 PM PDT 24
Peak memory 218700 kb
Host smart-c209b1ba-3557-4171-913d-2feda5240dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920189574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.920189574
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.2119726941
Short name T569
Test name
Test status
Simulation time 1062964381 ps
CPU time 10 seconds
Started Apr 02 01:45:02 PM PDT 24
Finished Apr 02 01:45:13 PM PDT 24
Peak memory 219500 kb
Host smart-dc2d05e0-327c-4416-9753-e58113fa9ba5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2119726941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.2119726941
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.364702679
Short name T385
Test name
Test status
Simulation time 23185164004 ps
CPU time 27.05 seconds
Started Apr 02 01:44:59 PM PDT 24
Finished Apr 02 01:45:27 PM PDT 24
Peak memory 216864 kb
Host smart-fe9cba4e-6f80-4708-bba2-124844cd03c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364702679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.364702679
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.1005474164
Short name T424
Test name
Test status
Simulation time 559137172 ps
CPU time 4.3 seconds
Started Apr 02 01:44:50 PM PDT 24
Finished Apr 02 01:44:55 PM PDT 24
Peak memory 216772 kb
Host smart-4dcc39a4-6578-4c22-b6f6-6bc7fb2a8217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005474164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.1005474164
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.3289824892
Short name T397
Test name
Test status
Simulation time 319499609 ps
CPU time 1.62 seconds
Started Apr 02 01:44:55 PM PDT 24
Finished Apr 02 01:44:56 PM PDT 24
Peak memory 216372 kb
Host smart-f80f55ea-7a5e-4f75-8230-eef2107220b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289824892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.3289824892
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.2415404013
Short name T584
Test name
Test status
Simulation time 68419287 ps
CPU time 0.72 seconds
Started Apr 02 01:44:53 PM PDT 24
Finished Apr 02 01:44:54 PM PDT 24
Peak memory 206252 kb
Host smart-fdc90337-5788-4dc1-bc76-8b8b8eaac319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415404013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.2415404013
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.3813432867
Short name T214
Test name
Test status
Simulation time 3698418285 ps
CPU time 5.64 seconds
Started Apr 02 01:44:57 PM PDT 24
Finished Apr 02 01:45:03 PM PDT 24
Peak memory 223684 kb
Host smart-87a9df5f-4db0-47fe-a71f-d4fb0df7a5d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813432867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.3813432867
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.2531439296
Short name T542
Test name
Test status
Simulation time 32823090 ps
CPU time 0.71 seconds
Started Apr 02 01:45:19 PM PDT 24
Finished Apr 02 01:45:20 PM PDT 24
Peak memory 206312 kb
Host smart-16750007-32bc-4492-af7a-d886fb2cfb71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531439296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
2531439296
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.2622486372
Short name T508
Test name
Test status
Simulation time 406254247 ps
CPU time 3.96 seconds
Started Apr 02 01:45:13 PM PDT 24
Finished Apr 02 01:45:17 PM PDT 24
Peak memory 232736 kb
Host smart-4c65c44e-0807-46f3-89c2-a2bc2690c392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622486372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.2622486372
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.955236002
Short name T489
Test name
Test status
Simulation time 26295040 ps
CPU time 0.76 seconds
Started Apr 02 01:45:05 PM PDT 24
Finished Apr 02 01:45:06 PM PDT 24
Peak memory 207080 kb
Host smart-0396456a-eb32-40fc-837f-70c7a7dba873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955236002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.955236002
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.32114752
Short name T358
Test name
Test status
Simulation time 327490667 ps
CPU time 16.38 seconds
Started Apr 02 01:45:13 PM PDT 24
Finished Apr 02 01:45:30 PM PDT 24
Peak memory 233060 kb
Host smart-cc05c8e2-a477-4693-999c-8dc7e4d73044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32114752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.32114752
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.859199991
Short name T559
Test name
Test status
Simulation time 1222374230 ps
CPU time 7.53 seconds
Started Apr 02 01:45:15 PM PDT 24
Finished Apr 02 01:45:22 PM PDT 24
Peak memory 235340 kb
Host smart-351f1952-7a22-4570-b015-8138c14c52b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859199991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.859199991
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.1993484676
Short name T341
Test name
Test status
Simulation time 262021360 ps
CPU time 3.41 seconds
Started Apr 02 01:45:10 PM PDT 24
Finished Apr 02 01:45:14 PM PDT 24
Peak memory 222888 kb
Host smart-71df1d97-9a61-469c-b2e3-5536c33a5134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993484676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.1993484676
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.3545535689
Short name T726
Test name
Test status
Simulation time 5434958554 ps
CPU time 5.54 seconds
Started Apr 02 01:45:11 PM PDT 24
Finished Apr 02 01:45:17 PM PDT 24
Peak memory 219076 kb
Host smart-092eef05-cea7-4442-bdc0-ba55fef73119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545535689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.3545535689
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.314088068
Short name T160
Test name
Test status
Simulation time 21966176228 ps
CPU time 16.12 seconds
Started Apr 02 01:45:19 PM PDT 24
Finished Apr 02 01:45:36 PM PDT 24
Peak memory 220692 kb
Host smart-58d01929-3901-4949-b57f-15eb2063950e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=314088068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dire
ct.314088068
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.2207565417
Short name T372
Test name
Test status
Simulation time 38067008115 ps
CPU time 49.74 seconds
Started Apr 02 01:45:05 PM PDT 24
Finished Apr 02 01:45:55 PM PDT 24
Peak memory 217108 kb
Host smart-fa6bfeb9-bcfe-41a4-92b3-f98b498c01c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207565417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.2207565417
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.789789321
Short name T447
Test name
Test status
Simulation time 1180181871 ps
CPU time 6.01 seconds
Started Apr 02 01:45:06 PM PDT 24
Finished Apr 02 01:45:12 PM PDT 24
Peak memory 216648 kb
Host smart-b414c936-4d54-481a-bfd6-27b957824b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789789321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.789789321
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.3851666202
Short name T626
Test name
Test status
Simulation time 91622369 ps
CPU time 1.22 seconds
Started Apr 02 01:45:10 PM PDT 24
Finished Apr 02 01:45:11 PM PDT 24
Peak memory 216652 kb
Host smart-4bb318f0-1f63-4a05-9859-c89ab9a6b8fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851666202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.3851666202
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.2056928947
Short name T21
Test name
Test status
Simulation time 1168194445 ps
CPU time 0.98 seconds
Started Apr 02 01:45:09 PM PDT 24
Finished Apr 02 01:45:10 PM PDT 24
Peak memory 207252 kb
Host smart-a4d46028-bb33-49dd-9a6f-37436196ad96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056928947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.2056928947
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.3338020433
Short name T262
Test name
Test status
Simulation time 2010533271 ps
CPU time 7.56 seconds
Started Apr 02 01:45:12 PM PDT 24
Finished Apr 02 01:45:20 PM PDT 24
Peak memory 219336 kb
Host smart-92d965a7-8b82-4970-a05e-6c8a2a1def87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338020433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3338020433
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.2680638591
Short name T509
Test name
Test status
Simulation time 41906873 ps
CPU time 0.7 seconds
Started Apr 02 01:45:32 PM PDT 24
Finished Apr 02 01:45:33 PM PDT 24
Peak memory 205996 kb
Host smart-d0d08658-8d49-45d2-95f5-92a618e2da04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680638591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
2680638591
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.1232130815
Short name T234
Test name
Test status
Simulation time 787900681 ps
CPU time 4.54 seconds
Started Apr 02 01:45:31 PM PDT 24
Finished Apr 02 01:45:36 PM PDT 24
Peak memory 224804 kb
Host smart-58e185cc-c0ca-4887-b832-60bd8a9c85b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232130815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.1232130815
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.3973484335
Short name T521
Test name
Test status
Simulation time 28539286 ps
CPU time 0.82 seconds
Started Apr 02 01:45:26 PM PDT 24
Finished Apr 02 01:45:27 PM PDT 24
Peak memory 207152 kb
Host smart-f73e5c1b-813a-41ae-9301-94faa7a0db35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973484335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.3973484335
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.3263004433
Short name T629
Test name
Test status
Simulation time 881182585 ps
CPU time 5.64 seconds
Started Apr 02 01:45:28 PM PDT 24
Finished Apr 02 01:45:33 PM PDT 24
Peak memory 233164 kb
Host smart-9a51b4d9-6080-40d0-b0bf-ddc29439b037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263004433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.3263004433
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.318868583
Short name T204
Test name
Test status
Simulation time 1723430754 ps
CPU time 4.8 seconds
Started Apr 02 01:45:26 PM PDT 24
Finished Apr 02 01:45:31 PM PDT 24
Peak memory 223788 kb
Host smart-fb3d01a4-24ef-498b-b2f5-b334c33d738b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318868583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.318868583
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.1258185175
Short name T12
Test name
Test status
Simulation time 1673585176 ps
CPU time 10.37 seconds
Started Apr 02 01:45:27 PM PDT 24
Finished Apr 02 01:45:37 PM PDT 24
Peak memory 221816 kb
Host smart-c25eca9d-77bc-4de5-998f-a7996443cfbe
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1258185175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.1258185175
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.774242517
Short name T664
Test name
Test status
Simulation time 6505803892 ps
CPU time 26.71 seconds
Started Apr 02 01:45:24 PM PDT 24
Finished Apr 02 01:45:51 PM PDT 24
Peak memory 216716 kb
Host smart-3d9662b0-190f-4543-bb7b-9e6f4f0e42ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774242517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.774242517
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.4036426719
Short name T431
Test name
Test status
Simulation time 4641540420 ps
CPU time 15.51 seconds
Started Apr 02 01:45:22 PM PDT 24
Finished Apr 02 01:45:38 PM PDT 24
Peak memory 216844 kb
Host smart-e00188b8-03b9-4ed8-947a-878034797c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036426719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.4036426719
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.3540035356
Short name T667
Test name
Test status
Simulation time 569980204 ps
CPU time 2.14 seconds
Started Apr 02 01:45:24 PM PDT 24
Finished Apr 02 01:45:27 PM PDT 24
Peak memory 216796 kb
Host smart-3acf8b5c-0755-4eee-bbbf-aa097f108c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540035356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.3540035356
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.1371242100
Short name T90
Test name
Test status
Simulation time 187120467 ps
CPU time 0.84 seconds
Started Apr 02 01:45:19 PM PDT 24
Finished Apr 02 01:45:20 PM PDT 24
Peak memory 206256 kb
Host smart-10969d62-e994-4716-8b04-8cc79cf098b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371242100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.1371242100
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.207431629
Short name T192
Test name
Test status
Simulation time 22155363620 ps
CPU time 19.29 seconds
Started Apr 02 01:45:30 PM PDT 24
Finished Apr 02 01:45:50 PM PDT 24
Peak memory 224892 kb
Host smart-b34e7585-87f9-4214-a4e7-7c5b5feff390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207431629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.207431629
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.3664388941
Short name T490
Test name
Test status
Simulation time 24809572 ps
CPU time 0.71 seconds
Started Apr 02 01:45:43 PM PDT 24
Finished Apr 02 01:45:44 PM PDT 24
Peak memory 205988 kb
Host smart-e510bc94-2427-4b9c-9770-c80945ff80df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664388941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
3664388941
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.856151447
Short name T430
Test name
Test status
Simulation time 19620810 ps
CPU time 0.75 seconds
Started Apr 02 01:45:31 PM PDT 24
Finished Apr 02 01:45:32 PM PDT 24
Peak memory 207372 kb
Host smart-2fc258e2-62a5-4e46-a0fa-2415d2d56900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856151447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.856151447
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.992397830
Short name T623
Test name
Test status
Simulation time 15978673749 ps
CPU time 63.35 seconds
Started Apr 02 01:45:41 PM PDT 24
Finished Apr 02 01:46:44 PM PDT 24
Peak memory 250372 kb
Host smart-484a7225-aedd-4016-9e53-877610362f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992397830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.992397830
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.3914529595
Short name T103
Test name
Test status
Simulation time 2418285090 ps
CPU time 9.37 seconds
Started Apr 02 01:45:36 PM PDT 24
Finished Apr 02 01:45:46 PM PDT 24
Peak memory 219604 kb
Host smart-0e90e465-e28f-48fd-bc67-05548e3ea612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914529595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.3914529595
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.3213038458
Short name T221
Test name
Test status
Simulation time 46101182021 ps
CPU time 98.41 seconds
Started Apr 02 01:45:41 PM PDT 24
Finished Apr 02 01:47:20 PM PDT 24
Peak memory 221404 kb
Host smart-7ac3baf5-be65-4752-afd7-5e5e68ca8c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213038458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.3213038458
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.3336990199
Short name T190
Test name
Test status
Simulation time 1151638618 ps
CPU time 8.24 seconds
Started Apr 02 01:45:36 PM PDT 24
Finished Apr 02 01:45:44 PM PDT 24
Peak memory 219144 kb
Host smart-81cfd775-3668-4ebe-b4fc-f6377b517717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336990199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.3336990199
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.3658940957
Short name T159
Test name
Test status
Simulation time 1799729201 ps
CPU time 7.69 seconds
Started Apr 02 01:45:43 PM PDT 24
Finished Apr 02 01:45:50 PM PDT 24
Peak memory 222360 kb
Host smart-f0a9910f-f48a-4477-a100-3c2c39c57a27
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3658940957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.3658940957
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.1761979102
Short name T676
Test name
Test status
Simulation time 2732081575 ps
CPU time 7.32 seconds
Started Apr 02 01:45:31 PM PDT 24
Finished Apr 02 01:45:38 PM PDT 24
Peak memory 216756 kb
Host smart-22c59db3-8053-464c-b2c8-d65ea850a0d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761979102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.1761979102
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.1897347636
Short name T390
Test name
Test status
Simulation time 276266255 ps
CPU time 1.48 seconds
Started Apr 02 01:45:34 PM PDT 24
Finished Apr 02 01:45:36 PM PDT 24
Peak memory 216720 kb
Host smart-f4dfb556-69ec-4747-b8a5-f382d81d28ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897347636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.1897347636
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.746738114
Short name T538
Test name
Test status
Simulation time 147615113 ps
CPU time 0.8 seconds
Started Apr 02 01:45:34 PM PDT 24
Finished Apr 02 01:45:35 PM PDT 24
Peak memory 206200 kb
Host smart-583e7901-987c-4e25-8809-d5450e60f575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746738114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.746738114
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.929572467
Short name T659
Test name
Test status
Simulation time 38981707 ps
CPU time 0.71 seconds
Started Apr 02 01:45:53 PM PDT 24
Finished Apr 02 01:45:54 PM PDT 24
Peak memory 205356 kb
Host smart-ef003eae-fb19-48de-a925-97e15429294a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929572467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.929572467
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.1419288834
Short name T480
Test name
Test status
Simulation time 26762781 ps
CPU time 0.81 seconds
Started Apr 02 01:45:47 PM PDT 24
Finished Apr 02 01:45:47 PM PDT 24
Peak memory 207148 kb
Host smart-8b148b6d-24e9-4a53-b4dc-aef8007e3ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419288834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.1419288834
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.3082160660
Short name T352
Test name
Test status
Simulation time 2370504325 ps
CPU time 33.44 seconds
Started Apr 02 01:45:51 PM PDT 24
Finished Apr 02 01:46:25 PM PDT 24
Peak memory 233196 kb
Host smart-e9e8e519-fc4a-4d3c-8000-8a7ffbf54d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082160660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.3082160660
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.979588313
Short name T547
Test name
Test status
Simulation time 275809670 ps
CPU time 2.98 seconds
Started Apr 02 01:45:49 PM PDT 24
Finished Apr 02 01:45:52 PM PDT 24
Peak memory 219144 kb
Host smart-2e7add23-fb69-48c8-bfdc-782b3f79eb80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979588313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.979588313
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.298135844
Short name T200
Test name
Test status
Simulation time 1797498987 ps
CPU time 5.82 seconds
Started Apr 02 01:45:48 PM PDT 24
Finished Apr 02 01:45:55 PM PDT 24
Peak memory 222780 kb
Host smart-10d88f2b-f967-4d52-a807-59e2c8b5ff5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298135844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap
.298135844
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.3842736667
Short name T68
Test name
Test status
Simulation time 16197524795 ps
CPU time 7.26 seconds
Started Apr 02 01:45:49 PM PDT 24
Finished Apr 02 01:45:56 PM PDT 24
Peak memory 223852 kb
Host smart-39b3d905-d3e0-46df-909b-9d7d127aec58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842736667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.3842736667
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.3321769723
Short name T408
Test name
Test status
Simulation time 465586126 ps
CPU time 4.2 seconds
Started Apr 02 01:45:50 PM PDT 24
Finished Apr 02 01:45:54 PM PDT 24
Peak memory 223576 kb
Host smart-48cc7ad7-89f5-4da6-8b20-d80286922114
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3321769723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.3321769723
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.785567433
Short name T38
Test name
Test status
Simulation time 173885398 ps
CPU time 0.99 seconds
Started Apr 02 01:45:55 PM PDT 24
Finished Apr 02 01:45:56 PM PDT 24
Peak memory 207536 kb
Host smart-d9b5f58f-c67a-4a99-9969-75dd23b412ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785567433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stres
s_all.785567433
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.1127075733
Short name T386
Test name
Test status
Simulation time 9483286092 ps
CPU time 26.54 seconds
Started Apr 02 01:45:44 PM PDT 24
Finished Apr 02 01:46:11 PM PDT 24
Peak memory 217060 kb
Host smart-d2f863e5-0c99-4863-baab-18cd9bba4b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127075733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.1127075733
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2972884916
Short name T463
Test name
Test status
Simulation time 2156922780 ps
CPU time 3.62 seconds
Started Apr 02 01:45:46 PM PDT 24
Finished Apr 02 01:45:50 PM PDT 24
Peak memory 216780 kb
Host smart-ae810719-051b-462b-aa8d-2723017088c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972884916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2972884916
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.795662278
Short name T461
Test name
Test status
Simulation time 33191512 ps
CPU time 0.73 seconds
Started Apr 02 01:45:44 PM PDT 24
Finished Apr 02 01:45:45 PM PDT 24
Peak memory 206188 kb
Host smart-128c8b82-af16-45af-a1fc-99e14282ceca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795662278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.795662278
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.296219764
Short name T414
Test name
Test status
Simulation time 16145937 ps
CPU time 0.72 seconds
Started Apr 02 01:45:47 PM PDT 24
Finished Apr 02 01:45:48 PM PDT 24
Peak memory 206228 kb
Host smart-2fdff890-4c01-4d4a-8f5c-d21e8cf385cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296219764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.296219764
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.1090060365
Short name T199
Test name
Test status
Simulation time 1616147569 ps
CPU time 4.55 seconds
Started Apr 02 01:45:48 PM PDT 24
Finished Apr 02 01:45:52 PM PDT 24
Peak memory 238496 kb
Host smart-79d88fec-98c4-400f-87a3-61e7ccdabe02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090060365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.1090060365
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.2849458325
Short name T554
Test name
Test status
Simulation time 38528010 ps
CPU time 0.73 seconds
Started Apr 02 01:46:11 PM PDT 24
Finished Apr 02 01:46:12 PM PDT 24
Peak memory 205916 kb
Host smart-c9b0425f-cb25-47f8-af60-4ae4e1198512
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849458325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
2849458325
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.2655291755
Short name T703
Test name
Test status
Simulation time 38694944 ps
CPU time 0.81 seconds
Started Apr 02 01:45:59 PM PDT 24
Finished Apr 02 01:46:01 PM PDT 24
Peak memory 207128 kb
Host smart-6c8fa862-e373-4a78-8cac-808ec5fefcb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655291755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.2655291755
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.2821596735
Short name T618
Test name
Test status
Simulation time 16643104413 ps
CPU time 118.33 seconds
Started Apr 02 01:46:03 PM PDT 24
Finished Apr 02 01:48:02 PM PDT 24
Peak memory 249632 kb
Host smart-9abbbe92-5f19-416a-8348-b827e5e0a860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821596735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.2821596735
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.340064988
Short name T229
Test name
Test status
Simulation time 1180591625 ps
CPU time 13.92 seconds
Started Apr 02 01:45:58 PM PDT 24
Finished Apr 02 01:46:12 PM PDT 24
Peak memory 221848 kb
Host smart-20b000ab-ab6c-4a18-a995-b5f445f82371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340064988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.340064988
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.2988923374
Short name T303
Test name
Test status
Simulation time 2717737897 ps
CPU time 30.75 seconds
Started Apr 02 01:46:06 PM PDT 24
Finished Apr 02 01:46:37 PM PDT 24
Peak memory 225380 kb
Host smart-5ef65a79-e640-4a35-be50-648f931295fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988923374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.2988923374
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.2315234666
Short name T92
Test name
Test status
Simulation time 9060278598 ps
CPU time 25.68 seconds
Started Apr 02 01:45:59 PM PDT 24
Finished Apr 02 01:46:25 PM PDT 24
Peak memory 224480 kb
Host smart-7341b72e-9cc7-4aa8-9f92-4642e195d308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315234666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.2315234666
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.1856373221
Short name T495
Test name
Test status
Simulation time 91038187 ps
CPU time 3.78 seconds
Started Apr 02 01:46:06 PM PDT 24
Finished Apr 02 01:46:10 PM PDT 24
Peak memory 219964 kb
Host smart-d3299834-389d-4f4f-9103-af56c0a8e1f0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1856373221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.1856373221
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.3109448744
Short name T388
Test name
Test status
Simulation time 14124512456 ps
CPU time 29.61 seconds
Started Apr 02 01:45:58 PM PDT 24
Finished Apr 02 01:46:29 PM PDT 24
Peak memory 216788 kb
Host smart-3887be95-8ecf-44f1-8aa8-27ba4bdf3878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109448744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.3109448744
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.3827049879
Short name T614
Test name
Test status
Simulation time 328919518 ps
CPU time 2.11 seconds
Started Apr 02 01:45:59 PM PDT 24
Finished Apr 02 01:46:02 PM PDT 24
Peak memory 216412 kb
Host smart-f054e064-5d48-4f8c-93f1-4a8c4ae73951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827049879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.3827049879
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.3070640841
Short name T607
Test name
Test status
Simulation time 203530863 ps
CPU time 5.45 seconds
Started Apr 02 01:46:00 PM PDT 24
Finished Apr 02 01:46:06 PM PDT 24
Peak memory 216792 kb
Host smart-7db6b275-0683-490a-8332-02ae574f506b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070640841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.3070640841
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.1966360662
Short name T504
Test name
Test status
Simulation time 46601023 ps
CPU time 0.81 seconds
Started Apr 02 01:46:00 PM PDT 24
Finished Apr 02 01:46:02 PM PDT 24
Peak memory 206244 kb
Host smart-efe946ae-40e0-4acb-9c10-588b36f091d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966360662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.1966360662
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.568081391
Short name T518
Test name
Test status
Simulation time 22047589 ps
CPU time 0.76 seconds
Started Apr 02 01:46:24 PM PDT 24
Finished Apr 02 01:46:25 PM PDT 24
Peak memory 205428 kb
Host smart-6e2f017b-ddcb-412a-ae31-d4ad759102d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568081391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.568081391
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.3860189568
Short name T709
Test name
Test status
Simulation time 47877402 ps
CPU time 0.78 seconds
Started Apr 02 01:46:09 PM PDT 24
Finished Apr 02 01:46:10 PM PDT 24
Peak memory 207456 kb
Host smart-c7c218e6-f6a4-4509-9257-cea54d505466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860189568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.3860189568
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_intercept.122054115
Short name T173
Test name
Test status
Simulation time 646874475 ps
CPU time 4.5 seconds
Started Apr 02 01:46:15 PM PDT 24
Finished Apr 02 01:46:19 PM PDT 24
Peak memory 217268 kb
Host smart-f294da1e-9cf8-45f3-9f2c-e53f19fb2c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122054115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.122054115
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.4038075447
Short name T231
Test name
Test status
Simulation time 14310482861 ps
CPU time 70.54 seconds
Started Apr 02 01:46:15 PM PDT 24
Finished Apr 02 01:47:26 PM PDT 24
Peak memory 235304 kb
Host smart-fcc9f366-306d-4694-99ea-df2f81691a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038075447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.4038075447
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.2258302233
Short name T302
Test name
Test status
Simulation time 8743385148 ps
CPU time 25.9 seconds
Started Apr 02 01:46:11 PM PDT 24
Finished Apr 02 01:46:37 PM PDT 24
Peak memory 223876 kb
Host smart-6f914075-ae71-4046-b42e-5e390577c037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258302233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.2258302233
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.2132603754
Short name T698
Test name
Test status
Simulation time 544045390 ps
CPU time 5.1 seconds
Started Apr 02 01:46:16 PM PDT 24
Finished Apr 02 01:46:22 PM PDT 24
Peak memory 222100 kb
Host smart-29a31004-efa9-4822-b7dd-84d7141e6d19
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2132603754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.2132603754
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.1153033797
Short name T692
Test name
Test status
Simulation time 22443411438 ps
CPU time 30.88 seconds
Started Apr 02 01:46:18 PM PDT 24
Finished Apr 02 01:46:49 PM PDT 24
Peak memory 216840 kb
Host smart-1a4145df-4057-4e15-b4f7-4d33ba9b47a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153033797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.1153033797
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.1859522358
Short name T570
Test name
Test status
Simulation time 1456330599 ps
CPU time 6.69 seconds
Started Apr 02 01:46:09 PM PDT 24
Finished Apr 02 01:46:16 PM PDT 24
Peak memory 216676 kb
Host smart-f8dbd452-922a-4ba9-a1cb-b37395c6a6f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859522358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.1859522358
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.3372201208
Short name T693
Test name
Test status
Simulation time 118845129 ps
CPU time 2.26 seconds
Started Apr 02 01:46:14 PM PDT 24
Finished Apr 02 01:46:17 PM PDT 24
Peak memory 216784 kb
Host smart-6786ddb8-f00b-40b8-b0db-e78b174fd39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372201208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.3372201208
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.1808471315
Short name T701
Test name
Test status
Simulation time 37514801 ps
CPU time 0.72 seconds
Started Apr 02 01:46:17 PM PDT 24
Finished Apr 02 01:46:18 PM PDT 24
Peak memory 206228 kb
Host smart-44d20e84-8ff8-4a5b-9283-eab58d2056b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808471315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.1808471315
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.1409011512
Short name T582
Test name
Test status
Simulation time 47433218 ps
CPU time 0.68 seconds
Started Apr 02 01:46:36 PM PDT 24
Finished Apr 02 01:46:37 PM PDT 24
Peak memory 205916 kb
Host smart-a5bafa08-e3e2-4394-bfcd-b2ea7b4d5c9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409011512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
1409011512
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.2126949601
Short name T3
Test name
Test status
Simulation time 16455576 ps
CPU time 0.76 seconds
Started Apr 02 01:46:19 PM PDT 24
Finished Apr 02 01:46:20 PM PDT 24
Peak memory 207108 kb
Host smart-372dd13d-07da-4a9a-97a4-47c34ae02fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126949601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.2126949601
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_intercept.2769215033
Short name T121
Test name
Test status
Simulation time 9447933160 ps
CPU time 26.4 seconds
Started Apr 02 01:46:24 PM PDT 24
Finished Apr 02 01:46:50 PM PDT 24
Peak memory 219296 kb
Host smart-8901921f-224d-4623-9457-957de4919399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769215033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.2769215033
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.1907468209
Short name T325
Test name
Test status
Simulation time 3255022789 ps
CPU time 30.14 seconds
Started Apr 02 01:46:26 PM PDT 24
Finished Apr 02 01:46:56 PM PDT 24
Peak memory 227360 kb
Host smart-afea0de8-d498-428a-a5f5-89e244c5e481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907468209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.1907468209
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.2644798500
Short name T724
Test name
Test status
Simulation time 714606442 ps
CPU time 7.52 seconds
Started Apr 02 01:46:26 PM PDT 24
Finished Apr 02 01:46:34 PM PDT 24
Peak memory 219200 kb
Host smart-8db576e1-cdcc-4821-99bb-5d761973c36b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2644798500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.2644798500
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.118469635
Short name T39
Test name
Test status
Simulation time 559391934 ps
CPU time 1.15 seconds
Started Apr 02 01:46:37 PM PDT 24
Finished Apr 02 01:46:38 PM PDT 24
Peak memory 207732 kb
Host smart-240d66a8-5eb8-4e13-8961-192bcabebe9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118469635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stres
s_all.118469635
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.715406656
Short name T374
Test name
Test status
Simulation time 10394188305 ps
CPU time 37.98 seconds
Started Apr 02 01:46:22 PM PDT 24
Finished Apr 02 01:47:00 PM PDT 24
Peak memory 220888 kb
Host smart-5d60d079-c3f6-40c7-bda3-a07ad1764072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715406656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.715406656
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.3696390072
Short name T484
Test name
Test status
Simulation time 173363103 ps
CPU time 1.46 seconds
Started Apr 02 01:46:22 PM PDT 24
Finished Apr 02 01:46:24 PM PDT 24
Peak memory 208160 kb
Host smart-09f70d43-bfd7-44ab-b9b2-3b5a16a8fb2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696390072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.3696390072
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.2022488510
Short name T707
Test name
Test status
Simulation time 899231152 ps
CPU time 2.94 seconds
Started Apr 02 01:46:25 PM PDT 24
Finished Apr 02 01:46:28 PM PDT 24
Peak memory 216776 kb
Host smart-a17d06de-a63e-4a98-92c9-8f7e667f30e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022488510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.2022488510
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.837123474
Short name T437
Test name
Test status
Simulation time 508539464 ps
CPU time 1.09 seconds
Started Apr 02 01:46:22 PM PDT 24
Finished Apr 02 01:46:23 PM PDT 24
Peak memory 207284 kb
Host smart-7849f14d-6404-47f5-a402-7978fdb3e902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837123474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.837123474
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.1841909294
Short name T167
Test name
Test status
Simulation time 44621386 ps
CPU time 0.79 seconds
Started Apr 02 01:39:21 PM PDT 24
Finished Apr 02 01:39:22 PM PDT 24
Peak memory 205904 kb
Host smart-616e9afd-88f8-4540-87a1-68dc57bcc31e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841909294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.1
841909294
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.690332316
Short name T97
Test name
Test status
Simulation time 1789338635 ps
CPU time 4.3 seconds
Started Apr 02 01:39:16 PM PDT 24
Finished Apr 02 01:39:21 PM PDT 24
Peak memory 218992 kb
Host smart-611d3d67-b78a-45da-aed4-105066e0a350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690332316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.690332316
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.2069186766
Short name T532
Test name
Test status
Simulation time 21082959 ps
CPU time 0.73 seconds
Started Apr 02 01:39:17 PM PDT 24
Finished Apr 02 01:39:17 PM PDT 24
Peak memory 206120 kb
Host smart-8fd2f87f-06e1-4754-b039-19848a00c15a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069186766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.2069186766
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_intercept.2947229214
Short name T197
Test name
Test status
Simulation time 691785853 ps
CPU time 4.15 seconds
Started Apr 02 01:39:17 PM PDT 24
Finished Apr 02 01:39:22 PM PDT 24
Peak memory 217104 kb
Host smart-d7c1db45-acd9-4109-946f-4857738af9cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947229214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.2947229214
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.1193435492
Short name T274
Test name
Test status
Simulation time 39308803090 ps
CPU time 125.78 seconds
Started Apr 02 01:39:14 PM PDT 24
Finished Apr 02 01:41:20 PM PDT 24
Peak memory 230568 kb
Host smart-731e41e0-7441-41f5-ba70-8a239818b4fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193435492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.1193435492
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_ram_cfg.1291949922
Short name T438
Test name
Test status
Simulation time 37526921 ps
CPU time 0.76 seconds
Started Apr 02 01:39:16 PM PDT 24
Finished Apr 02 01:39:17 PM PDT 24
Peak memory 216676 kb
Host smart-44e47c26-d857-4552-9c1e-8d2b5a7c36c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291949922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_ram_cfg.1291949922
Directory /workspace/5.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.4076065661
Short name T409
Test name
Test status
Simulation time 588869952 ps
CPU time 5.28 seconds
Started Apr 02 01:39:15 PM PDT 24
Finished Apr 02 01:39:20 PM PDT 24
Peak memory 223476 kb
Host smart-9ba6f3f7-f8b2-485a-ae1c-acb9ad32a871
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4076065661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.4076065661
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.1546047426
Short name T653
Test name
Test status
Simulation time 1018657792 ps
CPU time 3.16 seconds
Started Apr 02 01:39:15 PM PDT 24
Finished Apr 02 01:39:18 PM PDT 24
Peak memory 216820 kb
Host smart-3458ef9d-a909-41ac-abce-7138b256cbab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546047426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.1546047426
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.42381274
Short name T427
Test name
Test status
Simulation time 2578954801 ps
CPU time 14.76 seconds
Started Apr 02 01:39:15 PM PDT 24
Finished Apr 02 01:39:30 PM PDT 24
Peak memory 216748 kb
Host smart-6017c578-7e8d-4ab7-92ae-88c6bc5e5876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42381274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.42381274
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.709133214
Short name T577
Test name
Test status
Simulation time 187881810 ps
CPU time 2.27 seconds
Started Apr 02 01:39:16 PM PDT 24
Finished Apr 02 01:39:18 PM PDT 24
Peak memory 216776 kb
Host smart-038cea9e-8731-4864-834f-b465baf94b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709133214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.709133214
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.2269538912
Short name T580
Test name
Test status
Simulation time 112288492 ps
CPU time 0.85 seconds
Started Apr 02 01:39:29 PM PDT 24
Finished Apr 02 01:39:30 PM PDT 24
Peak memory 206256 kb
Host smart-22808e22-d397-43cc-8211-9c9c1cc2271e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269538912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.2269538912
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.2934543176
Short name T321
Test name
Test status
Simulation time 1430766286 ps
CPU time 5.53 seconds
Started Apr 02 01:39:16 PM PDT 24
Finished Apr 02 01:39:22 PM PDT 24
Peak memory 216772 kb
Host smart-46d8190c-cf95-4855-a73c-20b6e5c10897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934543176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.2934543176
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.1009056253
Short name T435
Test name
Test status
Simulation time 19253368 ps
CPU time 0.69 seconds
Started Apr 02 01:39:22 PM PDT 24
Finished Apr 02 01:39:23 PM PDT 24
Peak memory 205376 kb
Host smart-9fa03d54-6b85-4f64-b2f1-2443c7f628d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009056253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.1
009056253
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.3480209659
Short name T451
Test name
Test status
Simulation time 2510654769 ps
CPU time 2.98 seconds
Started Apr 02 01:39:19 PM PDT 24
Finished Apr 02 01:39:22 PM PDT 24
Peak memory 219352 kb
Host smart-3d0e07ea-860c-4fc4-83be-e4f005462689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480209659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.3480209659
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.752677940
Short name T452
Test name
Test status
Simulation time 22632530 ps
CPU time 0.73 seconds
Started Apr 02 01:39:17 PM PDT 24
Finished Apr 02 01:39:18 PM PDT 24
Peak memory 207008 kb
Host smart-cc9d6a36-8ec1-4d80-847c-e5c0e2f8cbe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752677940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.752677940
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.145185537
Short name T669
Test name
Test status
Simulation time 9284838370 ps
CPU time 69.49 seconds
Started Apr 02 01:39:17 PM PDT 24
Finished Apr 02 01:40:27 PM PDT 24
Peak memory 238436 kb
Host smart-2be2d557-02e1-4d8a-82f0-d73bd60cc995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145185537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.145185537
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.523460544
Short name T324
Test name
Test status
Simulation time 994750308 ps
CPU time 5.48 seconds
Started Apr 02 01:39:19 PM PDT 24
Finished Apr 02 01:39:24 PM PDT 24
Peak memory 219112 kb
Host smart-e1cb9741-6276-4fec-93d6-94eef869dbf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523460544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.523460544
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.2916908203
Short name T335
Test name
Test status
Simulation time 6019501857 ps
CPU time 17.59 seconds
Started Apr 02 01:39:21 PM PDT 24
Finished Apr 02 01:39:39 PM PDT 24
Peak memory 219004 kb
Host smart-7393e0dc-d36e-42e5-9eba-a7dec11809f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916908203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.2916908203
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.601908835
Short name T369
Test name
Test status
Simulation time 739103960 ps
CPU time 8.98 seconds
Started Apr 02 01:39:17 PM PDT 24
Finished Apr 02 01:39:26 PM PDT 24
Peak memory 233140 kb
Host smart-815cce21-141d-4f14-b0a8-4cd728c9f24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601908835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.601908835
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_ram_cfg.530127112
Short name T41
Test name
Test status
Simulation time 21293254 ps
CPU time 0.78 seconds
Started Apr 02 01:39:19 PM PDT 24
Finished Apr 02 01:39:20 PM PDT 24
Peak memory 216764 kb
Host smart-e59cf472-17fb-439d-b43d-2cb060755de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530127112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_ram_cfg.530127112
Directory /workspace/6.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.1003023263
Short name T56
Test name
Test status
Simulation time 3740916642 ps
CPU time 9.57 seconds
Started Apr 02 01:39:20 PM PDT 24
Finished Apr 02 01:39:29 PM PDT 24
Peak memory 220996 kb
Host smart-12c0ecb7-9507-4f01-a8d2-4b23e4bb389a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1003023263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.1003023263
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.630968446
Short name T636
Test name
Test status
Simulation time 60806637 ps
CPU time 1.13 seconds
Started Apr 02 01:39:22 PM PDT 24
Finished Apr 02 01:39:23 PM PDT 24
Peak memory 207900 kb
Host smart-6425d503-d547-4367-92dc-1b14416af23f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630968446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress
_all.630968446
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.851831532
Short name T375
Test name
Test status
Simulation time 17364063972 ps
CPU time 37.88 seconds
Started Apr 02 01:39:27 PM PDT 24
Finished Apr 02 01:40:05 PM PDT 24
Peak memory 216852 kb
Host smart-74ad33e3-25e4-4acc-80b8-661b6589014b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851831532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.851831532
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.2336888809
Short name T562
Test name
Test status
Simulation time 4065494352 ps
CPU time 11.43 seconds
Started Apr 02 01:39:21 PM PDT 24
Finished Apr 02 01:39:32 PM PDT 24
Peak memory 216748 kb
Host smart-b03d849d-305c-41d9-8917-69cdb57a8ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336888809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.2336888809
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.2420999282
Short name T398
Test name
Test status
Simulation time 142405940 ps
CPU time 2.88 seconds
Started Apr 02 01:39:16 PM PDT 24
Finished Apr 02 01:39:19 PM PDT 24
Peak memory 216864 kb
Host smart-f675f7a6-de90-4cd6-ab70-521a7e40bb35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420999282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.2420999282
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.357881266
Short name T449
Test name
Test status
Simulation time 78930286 ps
CPU time 1.03 seconds
Started Apr 02 01:39:28 PM PDT 24
Finished Apr 02 01:39:29 PM PDT 24
Peak memory 207280 kb
Host smart-989ce1c2-2353-40ea-826d-1e0d920449a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357881266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.357881266
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.2743128203
Short name T80
Test name
Test status
Simulation time 4203534929 ps
CPU time 13.74 seconds
Started Apr 02 01:39:21 PM PDT 24
Finished Apr 02 01:39:35 PM PDT 24
Peak memory 239232 kb
Host smart-b0a05769-9b52-43e1-a2a2-e25f1f540e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743128203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.2743128203
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.2470993468
Short name T567
Test name
Test status
Simulation time 118579341 ps
CPU time 0.7 seconds
Started Apr 02 01:39:29 PM PDT 24
Finished Apr 02 01:39:29 PM PDT 24
Peak memory 205916 kb
Host smart-a30dc779-6df7-485b-b31c-1e894cb2d0df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470993468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.2
470993468
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.3046508591
Short name T515
Test name
Test status
Simulation time 42921039 ps
CPU time 0.78 seconds
Started Apr 02 01:39:34 PM PDT 24
Finished Apr 02 01:39:35 PM PDT 24
Peak memory 207100 kb
Host smart-c76a3e30-1b0f-425b-93b2-eedbf48d639d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046508591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.3046508591
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_intercept.91518464
Short name T488
Test name
Test status
Simulation time 118867454 ps
CPU time 2.22 seconds
Started Apr 02 01:39:26 PM PDT 24
Finished Apr 02 01:39:28 PM PDT 24
Peak memory 222248 kb
Host smart-90e4757f-f867-4424-a81e-79dbd036a769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91518464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.91518464
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.324685924
Short name T203
Test name
Test status
Simulation time 425810418 ps
CPU time 6.81 seconds
Started Apr 02 01:39:27 PM PDT 24
Finished Apr 02 01:39:34 PM PDT 24
Peak memory 240568 kb
Host smart-c1e82de6-b4ce-4126-94ae-1944d9989282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324685924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.324685924
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_ram_cfg.4180234037
Short name T415
Test name
Test status
Simulation time 16979760 ps
CPU time 0.77 seconds
Started Apr 02 01:39:23 PM PDT 24
Finished Apr 02 01:39:23 PM PDT 24
Peak memory 216768 kb
Host smart-0ba15b9a-c4e3-43ba-930e-9dc99239a554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180234037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_ram_cfg.4180234037
Directory /workspace/7.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.729916683
Short name T444
Test name
Test status
Simulation time 3243586660 ps
CPU time 9.85 seconds
Started Apr 02 01:39:25 PM PDT 24
Finished Apr 02 01:39:35 PM PDT 24
Peak memory 220704 kb
Host smart-b68f61b8-3095-4e28-81da-bc5d5cb27928
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=729916683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direc
t.729916683
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.2804634944
Short name T396
Test name
Test status
Simulation time 8589111183 ps
CPU time 19.29 seconds
Started Apr 02 01:39:34 PM PDT 24
Finished Apr 02 01:39:53 PM PDT 24
Peak memory 216832 kb
Host smart-ba226465-c6c5-4957-bec9-5ea831772547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804634944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.2804634944
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.121846280
Short name T705
Test name
Test status
Simulation time 4392929691 ps
CPU time 5.79 seconds
Started Apr 02 01:39:34 PM PDT 24
Finished Apr 02 01:39:40 PM PDT 24
Peak memory 216840 kb
Host smart-ef60e3f6-3cfb-41be-a546-be7b91580b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121846280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.121846280
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.1301437955
Short name T671
Test name
Test status
Simulation time 434905783 ps
CPU time 2.14 seconds
Started Apr 02 01:39:24 PM PDT 24
Finished Apr 02 01:39:27 PM PDT 24
Peak memory 216776 kb
Host smart-5c55b074-0346-447d-bb98-9b5700669d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301437955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.1301437955
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.3578852314
Short name T573
Test name
Test status
Simulation time 51827174 ps
CPU time 0.8 seconds
Started Apr 02 01:39:22 PM PDT 24
Finished Apr 02 01:39:23 PM PDT 24
Peak memory 206156 kb
Host smart-b6c72fd4-e647-4f90-9427-0de3a26a3cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578852314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.3578852314
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.2185413612
Short name T233
Test name
Test status
Simulation time 1522658563 ps
CPU time 8.38 seconds
Started Apr 02 01:39:25 PM PDT 24
Finished Apr 02 01:39:33 PM PDT 24
Peak memory 223696 kb
Host smart-ee3767c4-2f9d-4cbe-ab5e-cc87c240f679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185413612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.2185413612
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.1018252550
Short name T558
Test name
Test status
Simulation time 30212179 ps
CPU time 0.77 seconds
Started Apr 02 01:39:30 PM PDT 24
Finished Apr 02 01:39:31 PM PDT 24
Peak memory 206324 kb
Host smart-62d5c76d-e42b-455b-8591-fd25eca8b9c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018252550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.1
018252550
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.2389385982
Short name T595
Test name
Test status
Simulation time 21021564 ps
CPU time 0.78 seconds
Started Apr 02 01:39:35 PM PDT 24
Finished Apr 02 01:39:36 PM PDT 24
Peak memory 207148 kb
Host smart-ed04b856-3800-4bcd-97d5-df891471bb57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389385982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.2389385982
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.698018791
Short name T513
Test name
Test status
Simulation time 1803363578 ps
CPU time 17.82 seconds
Started Apr 02 01:39:25 PM PDT 24
Finished Apr 02 01:39:43 PM PDT 24
Peak memory 254528 kb
Host smart-4602e4e4-458e-4eee-a21e-7127d73e2149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698018791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.698018791
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.777918177
Short name T299
Test name
Test status
Simulation time 15617176827 ps
CPU time 45.13 seconds
Started Apr 02 01:39:27 PM PDT 24
Finished Apr 02 01:40:12 PM PDT 24
Peak memory 228264 kb
Host smart-a64c3928-ec2d-4973-a026-8292a9d5439c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777918177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.777918177
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.534691509
Short name T158
Test name
Test status
Simulation time 3603218619 ps
CPU time 4.9 seconds
Started Apr 02 01:39:34 PM PDT 24
Finished Apr 02 01:39:39 PM PDT 24
Peak memory 234636 kb
Host smart-775b9faa-6c78-48f6-8189-657feb950e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534691509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.534691509
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_ram_cfg.798244244
Short name T622
Test name
Test status
Simulation time 43635118 ps
CPU time 0.74 seconds
Started Apr 02 01:39:35 PM PDT 24
Finished Apr 02 01:39:36 PM PDT 24
Peak memory 216776 kb
Host smart-3361379e-06af-4246-a5b0-255eca83924b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798244244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_ram_cfg.798244244
Directory /workspace/8.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.3616400184
Short name T465
Test name
Test status
Simulation time 284030719 ps
CPU time 4.18 seconds
Started Apr 02 01:39:28 PM PDT 24
Finished Apr 02 01:39:32 PM PDT 24
Peak memory 222832 kb
Host smart-360c20de-bb9f-4f0e-adc8-ed4de7813ec7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3616400184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.3616400184
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.4065660252
Short name T712
Test name
Test status
Simulation time 8310782513 ps
CPU time 45.65 seconds
Started Apr 02 01:39:27 PM PDT 24
Finished Apr 02 01:40:12 PM PDT 24
Peak memory 216876 kb
Host smart-6f0af868-da70-4f88-95b9-2a178873fc05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065660252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.4065660252
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.4163041139
Short name T657
Test name
Test status
Simulation time 17586180196 ps
CPU time 14.45 seconds
Started Apr 02 01:39:26 PM PDT 24
Finished Apr 02 01:39:41 PM PDT 24
Peak memory 216784 kb
Host smart-59611355-be4d-4151-9154-e81a3e6454db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163041139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.4163041139
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.1965726994
Short name T399
Test name
Test status
Simulation time 105909049 ps
CPU time 1.68 seconds
Started Apr 02 01:39:34 PM PDT 24
Finished Apr 02 01:39:36 PM PDT 24
Peak memory 216804 kb
Host smart-d42aedfb-01f7-488d-b51b-f077ba86ec0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965726994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.1965726994
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.1301182976
Short name T502
Test name
Test status
Simulation time 310665959 ps
CPU time 0.95 seconds
Started Apr 02 01:39:23 PM PDT 24
Finished Apr 02 01:39:24 PM PDT 24
Peak memory 207276 kb
Host smart-c3572856-cad4-4ceb-8d07-3c683538b697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301182976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.1301182976
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.117582802
Short name T355
Test name
Test status
Simulation time 44425674150 ps
CPU time 27.56 seconds
Started Apr 02 01:39:25 PM PDT 24
Finished Apr 02 01:39:52 PM PDT 24
Peak memory 221300 kb
Host smart-b39d34f0-b8bb-4a6b-9303-d5658d19ea01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117582802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.117582802
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.3800180762
Short name T546
Test name
Test status
Simulation time 14240020 ps
CPU time 0.76 seconds
Started Apr 02 01:39:45 PM PDT 24
Finished Apr 02 01:39:46 PM PDT 24
Peak memory 205928 kb
Host smart-71724e8b-2124-4c1e-8916-a099f60bc5bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800180762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.3
800180762
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.3796858382
Short name T571
Test name
Test status
Simulation time 15756662 ps
CPU time 0.8 seconds
Started Apr 02 01:39:32 PM PDT 24
Finished Apr 02 01:39:33 PM PDT 24
Peak memory 207052 kb
Host smart-419abfaa-d5ad-4999-b929-0d048cdba70c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796858382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.3796858382
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.2218727166
Short name T66
Test name
Test status
Simulation time 24036572892 ps
CPU time 93.63 seconds
Started Apr 02 01:39:34 PM PDT 24
Finished Apr 02 01:41:08 PM PDT 24
Peak memory 249264 kb
Host smart-a44a4c6f-8aa3-40ee-9c7b-c333dbe8ed1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218727166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.2218727166
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.3087908113
Short name T328
Test name
Test status
Simulation time 238247547 ps
CPU time 5.5 seconds
Started Apr 02 01:39:33 PM PDT 24
Finished Apr 02 01:39:38 PM PDT 24
Peak memory 233192 kb
Host smart-736c1bca-b88d-4f9d-8dc8-6176e9c39f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087908113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.3087908113
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.2958793736
Short name T75
Test name
Test status
Simulation time 54642858422 ps
CPU time 36.61 seconds
Started Apr 02 01:39:32 PM PDT 24
Finished Apr 02 01:40:08 PM PDT 24
Peak memory 232572 kb
Host smart-819a7db9-0f6d-47e1-9f3e-1f418101fee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958793736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.2958793736
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.2685465223
Short name T275
Test name
Test status
Simulation time 2158444457 ps
CPU time 6.85 seconds
Started Apr 02 01:39:29 PM PDT 24
Finished Apr 02 01:39:36 PM PDT 24
Peak memory 236880 kb
Host smart-714a9125-9fb6-48ee-bbab-603405f6c92b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685465223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.2685465223
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_ram_cfg.2829945918
Short name T527
Test name
Test status
Simulation time 14716803 ps
CPU time 0.82 seconds
Started Apr 02 01:39:31 PM PDT 24
Finished Apr 02 01:39:32 PM PDT 24
Peak memory 216612 kb
Host smart-797ede5b-2287-431a-8fee-357731698afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829945918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_ram_cfg.2829945918
Directory /workspace/9.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.1462115070
Short name T530
Test name
Test status
Simulation time 2270130244 ps
CPU time 6.63 seconds
Started Apr 02 01:39:36 PM PDT 24
Finished Apr 02 01:39:42 PM PDT 24
Peak memory 219412 kb
Host smart-1d5dc969-35b9-44d4-b9ac-954962ba0f85
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1462115070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.1462115070
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.2967644148
Short name T70
Test name
Test status
Simulation time 5245924124 ps
CPU time 23.58 seconds
Started Apr 02 01:39:31 PM PDT 24
Finished Apr 02 01:39:54 PM PDT 24
Peak memory 216860 kb
Host smart-f603b800-e4b8-4d2e-a2cb-87d392608168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967644148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.2967644148
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.2448267368
Short name T483
Test name
Test status
Simulation time 1613569891 ps
CPU time 4.04 seconds
Started Apr 02 01:39:30 PM PDT 24
Finished Apr 02 01:39:34 PM PDT 24
Peak memory 216756 kb
Host smart-91b500d2-5669-4552-9d4d-1ca18411375e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448267368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.2448267368
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.3507669692
Short name T500
Test name
Test status
Simulation time 705861827 ps
CPU time 2.5 seconds
Started Apr 02 01:39:31 PM PDT 24
Finished Apr 02 01:39:34 PM PDT 24
Peak memory 216688 kb
Host smart-c44d21d1-f813-4d66-a206-27be114c73c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507669692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.3507669692
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.915298027
Short name T604
Test name
Test status
Simulation time 230481011 ps
CPU time 0.87 seconds
Started Apr 02 01:39:31 PM PDT 24
Finished Apr 02 01:39:32 PM PDT 24
Peak memory 206176 kb
Host smart-91258129-9489-4ce7-bd50-63de9c9ed478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915298027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.915298027
Directory /workspace/9.spi_device_tpm_sts_read/latest
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