Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1342349	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1519307

1

T1

3412

T2

1211

T3

35

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2171894	1			T1	5012		T2	650		T3	231
values[0x0]	344714	1			T1	436		T2	459		T3	13
values[0x1]	345048	1			T1	492		T2	432		T3	19

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1015055	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1846601

1

T1

3915

T2

1280

T3

121

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9266	1			T1	28		T4	1		T5	4
valid_sources[0x01]	9322	1			T1	39		T4	2		T12	1
valid_sources[0x02]	9916	1			T1	11		T4	6		T5	2
valid_sources[0x03]	9598	1			T1	28		T4	3		T12	1
valid_sources[0x04]	9611	1			T1	38		T4	3		T12	1
valid_sources[0x05]	9278	1			T1	22		T4	3		T5	6
valid_sources[0x06]	13815	1			T1	4		T4	7		T5	6
valid_sources[0x07]	14523	1			T1	23		T4	4		T5	5
valid_sources[0x08]	9589	1			T1	28		T4	3		T5	5
valid_sources[0x09]	10726	1			T1	32		T4	4		T5	3
valid_sources[0x0a]	9617	1			T1	23		T4	5		T5	3
valid_sources[0x0b]	10356	1			T1	23		T4	1		T5	2
valid_sources[0x0c]	11202	1			T1	23		T4	1		T5	3
valid_sources[0x0d]	11123	1			T1	17		T3	1		T4	2
valid_sources[0x0e]	9656	1			T1	35		T4	2		T5	1
valid_sources[0x0f]	26833	1			T1	29		T4	3		T5	4
valid_sources[0x10]	9345	1			T1	20		T3	1		T4	7
valid_sources[0x11]	10167	1			T1	31		T3	10		T4	3
valid_sources[0x12]	9594	1			T1	41		T4	6		T5	2
valid_sources[0x13]	10395	1			T1	18		T4	6		T5	6
valid_sources[0x14]	9226	1			T1	26		T3	1		T4	4
valid_sources[0x15]	11395	1			T1	32		T3	2		T4	1
valid_sources[0x16]	12592	1			T1	27		T4	3		T12	1
valid_sources[0x17]	9587	1			T1	9		T4	1		T5	3
valid_sources[0x18]	9948	1			T1	7		T4	4		T5	3
valid_sources[0x19]	15540	1			T1	21		T3	2		T4	2
valid_sources[0x1a]	13602	1			T1	35		T4	6		T5	5
valid_sources[0x1b]	10096	1			T1	12		T3	1		T4	1
valid_sources[0x1c]	13299	1			T1	34		T4	3		T12	1
valid_sources[0x1d]	10242	1			T1	25		T4	3		T12	2
valid_sources[0x1e]	9300	1			T1	11		T4	3		T5	3
valid_sources[0x1f]	21255	1			T1	36		T4	5		T12	1
valid_sources[0x20]	9842	1			T1	13		T4	4		T5	4
valid_sources[0x21]	9411	1			T1	13		T4	2		T12	1
valid_sources[0x22]	9095	1			T1	14		T4	3		T5	6
valid_sources[0x23]	9386	1			T1	22		T4	7		T5	4
valid_sources[0x24]	21587	1			T1	26		T4	3		T5	3
valid_sources[0x25]	9941	1			T1	18		T4	2		T5	2
valid_sources[0x26]	9544	1			T1	20		T4	4		T5	3
valid_sources[0x27]	8942	1			T1	7		T3	2		T4	4
valid_sources[0x28]	11062	1			T1	30		T4	7		T5	3
valid_sources[0x29]	9208	1			T1	47		T3	2		T4	3
valid_sources[0x2a]	8726	1			T1	22		T4	4		T12	1
valid_sources[0x2b]	8634	1			T1	33		T4	2		T16	2
valid_sources[0x2c]	10217	1			T1	17		T12	2		T5	2
valid_sources[0x2d]	10487	1			T1	25		T4	2		T5	2
valid_sources[0x2e]	11469	1			T1	15		T4	2		T5	3
valid_sources[0x2f]	10197	1			T1	14		T4	5		T5	5
valid_sources[0x30]	10873	1			T1	13		T4	2		T12	1
valid_sources[0x31]	10976	1			T1	27		T3	3		T4	4
valid_sources[0x32]	8977	1			T1	18		T4	2		T5	5
valid_sources[0x33]	17510	1			T1	24		T3	7		T4	2
valid_sources[0x34]	14761	1			T1	37		T3	4		T4	4
valid_sources[0x35]	9028	1			T1	21		T4	5		T5	7
valid_sources[0x36]	9464	1			T1	37		T4	3		T5	2
valid_sources[0x37]	9120	1			T1	14		T4	4		T5	6
valid_sources[0x38]	21736	1			T1	10		T3	4		T4	4
valid_sources[0x39]	8781	1			T1	17		T3	5		T4	3
valid_sources[0x3a]	10677	1			T1	12		T3	2		T4	2
valid_sources[0x3b]	10396	1			T1	27		T4	4		T12	1
valid_sources[0x3c]	9771	1			T1	18		T4	2		T5	4
valid_sources[0x3d]	10928	1			T1	21		T3	2		T4	4
valid_sources[0x3e]	10079	1			T1	30		T4	3		T5	5
valid_sources[0x3f]	9024	1			T1	17		T4	9		T5	2
valid_sources[0x40]	11145	1			T1	16		T3	1		T4	7
valid_sources[0x41]	8733	1			T1	43		T4	5		T5	4
valid_sources[0x42]	9253	1			T1	8		T4	3		T5	1
valid_sources[0x43]	8878	1			T1	22		T4	5		T5	3
valid_sources[0x44]	18231	1			T1	20		T4	2		T5	5
valid_sources[0x45]	9935	1			T1	35		T3	2		T4	3
valid_sources[0x46]	12086	1			T1	11		T12	1		T5	9
valid_sources[0x47]	10019	1			T1	13		T4	2		T5	5
valid_sources[0x48]	9510	1			T1	8		T4	2		T5	7
valid_sources[0x49]	9575	1			T1	13		T4	8		T5	4
valid_sources[0x4a]	17451	1			T1	10		T4	1		T5	3
valid_sources[0x4b]	10359	1			T1	16		T3	18		T4	1
valid_sources[0x4c]	9174	1			T1	14		T4	3		T5	5
valid_sources[0x4d]	8964	1			T1	23		T3	1		T4	5
valid_sources[0x4e]	15286	1			T1	25		T4	3		T5	7
valid_sources[0x4f]	9777	1			T1	18		T4	2		T5	1
valid_sources[0x50]	9481	1			T1	14		T3	2		T4	7
valid_sources[0x51]	10803	1			T1	19		T4	7		T5	6
valid_sources[0x52]	11135	1			T1	33		T4	5		T5	2
valid_sources[0x53]	10615	1			T1	13		T4	3		T5	5
valid_sources[0x54]	9258	1			T1	8		T3	1		T4	1
valid_sources[0x55]	9063	1			T1	21		T4	7		T12	1
valid_sources[0x56]	9920	1			T1	18		T3	14		T4	4
valid_sources[0x57]	9841	1			T1	12		T3	3		T4	3
valid_sources[0x58]	10344	1			T1	12		T4	2		T5	8
valid_sources[0x59]	9050	1			T1	22		T3	1		T4	5
valid_sources[0x5a]	9052	1			T1	20		T4	8		T5	4
valid_sources[0x5b]	8909	1			T1	25		T4	3		T5	2
valid_sources[0x5c]	8992	1			T1	34		T4	2		T12	1
valid_sources[0x5d]	9462	1			T1	25		T3	2		T4	5
valid_sources[0x5e]	9369	1			T1	27		T4	3		T15	9
valid_sources[0x5f]	9388	1			T1	19		T4	3		T5	3
valid_sources[0x60]	10795	1			T1	31		T4	4		T5	1
valid_sources[0x61]	20086	1			T1	21		T4	1		T5	4
valid_sources[0x62]	10649	1			T1	26		T3	1		T4	8
valid_sources[0x63]	21279	1			T1	16		T4	1		T5	8
valid_sources[0x64]	13815	1			T1	10		T2	198		T5	2
valid_sources[0x65]	9658	1			T1	18		T3	1		T4	1
valid_sources[0x66]	13468	1			T1	20		T4	3		T5	2
valid_sources[0x67]	46130	1			T1	7		T3	2		T4	4
valid_sources[0x68]	11451	1			T1	32		T4	2		T12	1
valid_sources[0x69]	9736	1			T1	12		T4	4		T12	1
valid_sources[0x6a]	10290	1			T1	47		T3	2		T4	6
valid_sources[0x6b]	9145	1			T1	31		T3	1		T4	3
valid_sources[0x6c]	12094	1			T1	6		T4	5		T13	38
valid_sources[0x6d]	10358	1			T1	24		T4	7		T5	6
valid_sources[0x6e]	9692	1			T1	32		T4	1		T5	6
valid_sources[0x6f]	9817	1			T1	21		T3	1		T4	1
valid_sources[0x70]	9303	1			T1	15		T4	7		T5	2
valid_sources[0x71]	12991	1			T1	38		T4	1		T5	1
valid_sources[0x72]	17997	1			T1	22		T3	7		T4	7
valid_sources[0x73]	9003	1			T1	22		T3	7		T4	3
valid_sources[0x74]	10882	1			T1	24		T4	7		T5	3
valid_sources[0x75]	10152	1			T1	22		T4	3		T5	5
valid_sources[0x76]	9774	1			T1	7		T4	3		T5	4
valid_sources[0x77]	17404	1			T1	34		T4	2		T5	1
valid_sources[0x78]	11049	1			T1	21		T4	2		T5	3
valid_sources[0x79]	14512	1			T1	12		T4	2		T5	3
valid_sources[0x7a]	10288	1			T1	48		T2	892		T4	5
valid_sources[0x7b]	10328	1			T1	28		T3	3		T4	5
valid_sources[0x7c]	16804	1			T1	11		T4	3		T5	3
valid_sources[0x7d]	9392	1			T1	9		T4	6		T5	1
valid_sources[0x7e]	8769	1			T1	24		T3	5		T4	7
valid_sources[0x7f]	9097	1			T1	26		T3	2		T4	1
valid_sources[0x80]	9045	1			T1	22		T4	9		T5	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

895772

1

T1

2491

T2

329

T3

8

values[0x0]

all_enables

biggest_size

315389

1

T1

434

T2

455

T3

12

values[0x1]

all_enables

biggest_size

308146

1

T1

487

T2

427

T3

15