Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1363713

1

T1

2528

T2

330

T3

228

full_word

1520616

1

T1

3412

T2

1211

T3

35

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	2883909	1			T1	5940		T2	1541		T3	263
auto[TlIntgErrCmd]	142	1			T36	8		T38	10		T112	11
auto[TlIntgErrData]	144	1			T36	10		T38	11		T112	9
auto[TlIntgErrBoth]	134	1			T36	2		T38	9		T112	10

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2175887

1

T1

5012

T2

650

T3

231

auto[1]

708442

1

T1

928

T2

891

T3

32

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1279629	1			T1	2521		T2	321		T3	223
auto[TlIntgErrNone]	partial	auto[1]	83705	1			T1	7		T2	9		T3	5
auto[TlIntgErrNone]	full_word	auto[0]	896068	1			T1	2491		T2	329		T3	8
auto[TlIntgErrNone]	full_word	auto[1]	624507	1			T1	921		T2	882		T3	27
auto[TlIntgErrCmd]	partial	auto[0]	55	1			T36	3		T38	2		T112	2
auto[TlIntgErrCmd]	partial	auto[1]	74	1			T36	4		T38	8		T112	7
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T112	1		T369	1		T372	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T36	1		T112	1		T373	2
auto[TlIntgErrData]	partial	auto[0]	56	1			T36	6		T38	4		T112	3
auto[TlIntgErrData]	partial	auto[1]	74	1			T36	3		T38	6		T112	4
auto[TlIntgErrData]	full_word	auto[0]	8	1			T36	1		T112	2		T374	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T38	1		T369	1		T375	1
auto[TlIntgErrBoth]	partial	auto[0]	58	1			T36	2		T38	4		T112	5
auto[TlIntgErrBoth]	partial	auto[1]	62	1			T38	5		T112	2		T369	5
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T112	2		T369	1		T373	2
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T112	1		T369	1		T374	1