Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	123678872	2697073	0	0
DepthKnown_A	123678872	123574715	0	0
RvalidKnown_A	123678872	123574715	0	0
WreadyKnown_A	123678872	123574715	0	0
gen_passthru_fifo.paramCheckPass	834	834	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123678872	2697073	0	0
T1	132218	5111	0	0
T2	18762	709	0	0
T3	8327	260	0	0
T4	585864	70	0	0
T5	30758	99	0	0
T12	2020	47	0	0
T13	9582	38	0	0
T16	693	2	0	0
T17	1062	41	0	0
T18	988	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123678872	123574715	0	0
T1	132218	132141	0	0
T2	18762	18666	0	0
T3	8327	8268	0	0
T4	585864	585775	0	0
T5	30758	30661	0	0
T12	2020	1936	0	0
T13	9582	9517	0	0
T16	693	604	0	0
T17	1062	973	0	0
T18	988	917	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123678872	123574715	0	0
T1	132218	132141	0	0
T2	18762	18666	0	0
T3	8327	8268	0	0
T4	585864	585775	0	0
T5	30758	30661	0	0
T12	2020	1936	0	0
T13	9582	9517	0	0
T16	693	604	0	0
T17	1062	973	0	0
T18	988	917	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123678872	123574715	0	0
T1	132218	132141	0	0
T2	18762	18666	0	0
T3	8327	8268	0	0
T4	585864	585775	0	0
T5	30758	30661	0	0
T12	2020	1936	0	0
T13	9582	9517	0	0
T16	693	604	0	0
T17	1062	973	0	0
T18	988	917	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	834	834	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	123678872	5091176	0	0
DepthKnown_A	123678872	123574715	0	0
RvalidKnown_A	123678872	123574715	0	0
WreadyKnown_A	123678872	123574715	0	0
gen_passthru_fifo.paramCheckPass	834	834	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123678872	5091176	0	0
T1	132218	22352	0	0
T2	18762	709	0	0
T3	8327	1144	0	0
T4	585864	290	0	0
T5	30758	323	0	0
T12	2020	158	0	0
T13	9582	38	0	0
T16	693	2	0	0
T17	1062	41	0	0
T18	988	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123678872	123574715	0	0
T1	132218	132141	0	0
T2	18762	18666	0	0
T3	8327	8268	0	0
T4	585864	585775	0	0
T5	30758	30661	0	0
T12	2020	1936	0	0
T13	9582	9517	0	0
T16	693	604	0	0
T17	1062	973	0	0
T18	988	917	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123678872	123574715	0	0
T1	132218	132141	0	0
T2	18762	18666	0	0
T3	8327	8268	0	0
T4	585864	585775	0	0
T5	30758	30661	0	0
T12	2020	1936	0	0
T13	9582	9517	0	0
T16	693	604	0	0
T17	1062	973	0	0
T18	988	917	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123678872	123574715	0	0
T1	132218	132141	0	0
T2	18762	18666	0	0
T3	8327	8268	0	0
T4	585864	585775	0	0
T5	30758	30661	0	0
T12	2020	1936	0	0
T13	9582	9517	0	0
T16	693	604	0	0
T17	1062	973	0	0
T18	988	917	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	834	834	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0