Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.34	100.00	70.37			100.00	75.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	55.51	86.36	44.44			60.00	31.25
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
55.51	86.36	44.44			60.00	31.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
55.51	86.36	44.44			60.00	31.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
58.33	100.00	16.67					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
55.51	86.36

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
90.97	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T12,T15
1	0	Covered	T3,T12,T15

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T12,T13
1	0	Unreachable
1	1	Covered	T3,T12,T15

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
55.51	44.44

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	4	44.44
Logical	9	4	44.44
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Not Covered

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T12,T15

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T12,T15
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T12,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	200944074	160385622	0	0
CheckNGreaterZero_A	1977	1977	0	0
GntImpliesReady_A	200944074	700104	0	0
GntImpliesValid_A	200944074	700104	0	0
GrantKnown_A	200944074	160385622	0	0
IdxKnown_A	200944074	160385622	0	0
IndexIsCorrect_A	200944074	700104	0	0
LockArbDecision_A	200944074	0	0	0
NoReadyValidNoGrant_A	200944074	0	0	0
ReadyAndValidImplyGrant_A	200944074	700104	0	0
ReqAndReadyImplyGrant_A	200944074	700104	0	0
ReqImpliesValid_A	200944074	700104	0	0
ReqStaysHighUntilGranted0_M	200944074	0	0	0
RoundRobin_A	200944074	0	0	659
ValidKnown_A	200944074	160385622	0	0
gen_data_port_assertion.DataFlow_A	200944074	700104	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200944074	160385622	0	0
T1	191420	191149	0	0
T2	34298	34202	0	0
T3	10407	9308	0	0
T4	876920	731303	0	0
T5	133970	81419	0	0
T6	266834	133284	0	0
T7	127280	126792	0	0
T8	6958	6958	0	0
T9	0	45168	0	0
T12	3844	2848	0	0
T13	12218	10381	0	0
T14	3140	1296	0	0
T15	4928	2464	0	0
T16	693	604	0	0
T17	1062	973	0	0
T18	988	917	0	0
T20	0	1368	0	0
T21	0	85240	0	0
T22	0	203840	0	0
T23	0	72	0	0
T59	0	250480	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1977	1977	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T12	3	3	0	0
T13	3	3	0	0
T16	3	3	0	0
T17	3	3	0	0
T18	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200944074	700104	0	0
T1	132218	832	0	0
T2	18762	832	0	0
T3	9367	58	0	0
T4	731392	832	0	0
T5	82364	832	0	0
T6	133417	832	0	0
T7	127280	4416	0	0
T8	6958	832	0	0
T12	2932	50	0	0
T13	10900	0	0	0
T14	1570	0	0	0
T15	2464	273	0	0
T16	693	0	0	0
T17	1062	0	0	0
T18	988	0	0	0
T20	0	128	0	0
T21	0	3398	0	0
T22	0	9384	0	0
T59	0	6057	0	0
T60	0	234	0	0
T61	0	7712	0	0
T62	0	173	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200944074	700104	0	0
T1	132218	832	0	0
T2	18762	832	0	0
T3	9367	58	0	0
T4	731392	832	0	0
T5	82364	832	0	0
T6	133417	832	0	0
T7	127280	4416	0	0
T8	6958	832	0	0
T12	2932	50	0	0
T13	10900	0	0	0
T14	1570	0	0	0
T15	2464	273	0	0
T16	693	0	0	0
T17	1062	0	0	0
T18	988	0	0	0
T20	0	128	0	0
T21	0	3398	0	0
T22	0	9384	0	0
T59	0	6057	0	0
T60	0	234	0	0
T61	0	7712	0	0
T62	0	173	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200944074	160385622	0	0
T1	191420	191149	0	0
T2	34298	34202	0	0
T3	10407	9308	0	0
T4	876920	731303	0	0
T5	133970	81419	0	0
T6	266834	133284	0	0
T7	127280	126792	0	0
T8	6958	6958	0	0
T9	0	45168	0	0
T12	3844	2848	0	0
T13	12218	10381	0	0
T14	3140	1296	0	0
T15	4928	2464	0	0
T16	693	604	0	0
T17	1062	973	0	0
T18	988	917	0	0
T20	0	1368	0	0
T21	0	85240	0	0
T22	0	203840	0	0
T23	0	72	0	0
T59	0	250480	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200944074	160385622	0	0
T1	191420	191149	0	0
T2	34298	34202	0	0
T3	10407	9308	0	0
T4	876920	731303	0	0
T5	133970	81419	0	0
T6	266834	133284	0	0
T7	127280	126792	0	0
T8	6958	6958	0	0
T9	0	45168	0	0
T12	3844	2848	0	0
T13	12218	10381	0	0
T14	3140	1296	0	0
T15	4928	2464	0	0
T16	693	604	0	0
T17	1062	973	0	0
T18	988	917	0	0
T20	0	1368	0	0
T21	0	85240	0	0
T22	0	203840	0	0
T23	0	72	0	0
T59	0	250480	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200944074	700104	0	0
T1	132218	832	0	0
T2	18762	832	0	0
T3	9367	58	0	0
T4	731392	832	0	0
T5	82364	832	0	0
T6	133417	832	0	0
T7	127280	4416	0	0
T8	6958	832	0	0
T12	2932	50	0	0
T13	10900	0	0	0
T14	1570	0	0	0
T15	2464	273	0	0
T16	693	0	0	0
T17	1062	0	0	0
T18	988	0	0	0
T20	0	128	0	0
T21	0	3398	0	0
T22	0	9384	0	0
T59	0	6057	0	0
T60	0	234	0	0
T61	0	7712	0	0
T62	0	173	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200944074	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200944074	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200944074	700104	0	0
T1	132218	832	0	0
T2	18762	832	0	0
T3	9367	58	0	0
T4	731392	832	0	0
T5	82364	832	0	0
T6	133417	832	0	0
T7	127280	4416	0	0
T8	6958	832	0	0
T12	2932	50	0	0
T13	10900	0	0	0
T14	1570	0	0	0
T15	2464	273	0	0
T16	693	0	0	0
T17	1062	0	0	0
T18	988	0	0	0
T20	0	128	0	0
T21	0	3398	0	0
T22	0	9384	0	0
T59	0	6057	0	0
T60	0	234	0	0
T61	0	7712	0	0
T62	0	173	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200944074	700104	0	0
T1	132218	832	0	0
T2	18762	832	0	0
T3	9367	58	0	0
T4	731392	832	0	0
T5	82364	832	0	0
T6	133417	832	0	0
T7	127280	4416	0	0
T8	6958	832	0	0
T12	2932	50	0	0
T13	10900	0	0	0
T14	1570	0	0	0
T15	2464	273	0	0
T16	693	0	0	0
T17	1062	0	0	0
T18	988	0	0	0
T20	0	128	0	0
T21	0	3398	0	0
T22	0	9384	0	0
T59	0	6057	0	0
T60	0	234	0	0
T61	0	7712	0	0
T62	0	173	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200944074	700104	0	0
T1	132218	832	0	0
T2	18762	832	0	0
T3	9367	58	0	0
T4	731392	832	0	0
T5	82364	832	0	0
T6	133417	832	0	0
T7	127280	4416	0	0
T8	6958	832	0	0
T12	2932	50	0	0
T13	10900	0	0	0
T14	1570	0	0	0
T15	2464	273	0	0
T16	693	0	0	0
T17	1062	0	0	0
T18	988	0	0	0
T20	0	128	0	0
T21	0	3398	0	0
T22	0	9384	0	0
T59	0	6057	0	0
T60	0	234	0	0
T61	0	7712	0	0
T62	0	173	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	200944074	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200944074	0	0	659

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200944074	160385622	0	0
T1	191420	191149	0	0
T2	34298	34202	0	0
T3	10407	9308	0	0
T4	876920	731303	0	0
T5	133970	81419	0	0
T6	266834	133284	0	0
T7	127280	126792	0	0
T8	6958	6958	0	0
T9	0	45168	0	0
T12	3844	2848	0	0
T13	12218	10381	0	0
T14	3140	1296	0	0
T15	4928	2464	0	0
T16	693	604	0	0
T17	1062	973	0	0
T18	988	917	0	0
T20	0	1368	0	0
T21	0	85240	0	0
T22	0	203840	0	0
T23	0	72	0	0
T59	0	250480	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200944074	700104	0	0
T1	132218	832	0	0
T2	18762	832	0	0
T3	9367	58	0	0
T4	731392	832	0	0
T5	82364	832	0	0
T6	133417	832	0	0
T7	127280	4416	0	0
T8	6958	832	0	0
T12	2932	50	0	0
T13	10900	0	0	0
T14	1570	0	0	0
T15	2464	273	0	0
T16	693	0	0	0
T17	1062	0	0	0
T18	988	0	0	0
T20	0	128	0	0
T21	0	3398	0	0
T22	0	9384	0	0
T59	0	6057	0	0
T60	0	234	0	0
T61	0	7712	0	0
T62	0	173	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	19	86.36
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	4	80.00
ALWAYS	109	4	3	75.00
ALWAYS	124	4	3	75.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	0	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	0	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	0	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	4	44.44
Logical	9	4	44.44
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Not Covered

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	6	60.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	2	66.67
IF	126	2	1	50.00
IF	111	2	1	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	5	31.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	5	31.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	39930254	25575137	0	0
CheckNGreaterZero_A	659	659	0	0
GntImpliesReady_A	39930254	0	0	0
GntImpliesValid_A	39930254	0	0	0
GrantKnown_A	39930254	25575137	0	0
IdxKnown_A	39930254	25575137	0	0
IndexIsCorrect_A	39930254	0	0	0
LockArbDecision_A	39930254	0	0	0
NoReadyValidNoGrant_A	39930254	0	0	0
ReadyAndValidImplyGrant_A	39930254	0	0	0
ReqAndReadyImplyGrant_A	39930254	0	0	0
ReqImpliesValid_A	39930254	0	0	0
ReqStaysHighUntilGranted0_M	39930254	0	0	0
RoundRobin_A	39930254	0	0	0
ValidKnown_A	39930254	25575137	0	0
gen_data_port_assertion.DataFlow_A	39930254	0	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39930254	25575137	0	0
T1	59202	59008	0	0
T2	15536	15536	0	0
T3	1040	0	0	0
T4	145528	145528	0	0
T5	51606	50758	0	0
T6	133417	133284	0	0
T7	0	126792	0	0
T8	0	6958	0	0
T9	0	45168	0	0
T10	0	31728	0	0
T11	0	12037	0	0
T12	912	0	0	0
T13	1318	0	0	0
T14	1570	0	0	0
T15	2464	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659	659	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39930254	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39930254	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39930254	25575137	0	0
T1	59202	59008	0	0
T2	15536	15536	0	0
T3	1040	0	0	0
T4	145528	145528	0	0
T5	51606	50758	0	0
T6	133417	133284	0	0
T7	0	126792	0	0
T8	0	6958	0	0
T9	0	45168	0	0
T10	0	31728	0	0
T11	0	12037	0	0
T12	912	0	0	0
T13	1318	0	0	0
T14	1570	0	0	0
T15	2464	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39930254	25575137	0	0
T1	59202	59008	0	0
T2	15536	15536	0	0
T3	1040	0	0	0
T4	145528	145528	0	0
T5	51606	50758	0	0
T6	133417	133284	0	0
T7	0	126792	0	0
T8	0	6958	0	0
T9	0	45168	0	0
T10	0	31728	0	0
T11	0	12037	0	0
T12	912	0	0	0
T13	1318	0	0	0
T14	1570	0	0	0
T15	2464	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39930254	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39930254	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39930254	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39930254	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39930254	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39930254	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	39930254	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39930254	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39930254	25575137	0	0
T1	59202	59008	0	0
T2	15536	15536	0	0
T3	1040	0	0	0
T4	145528	145528	0	0
T5	51606	50758	0	0
T6	133417	133284	0	0
T7	0	126792	0	0
T8	0	6958	0	0
T9	0	45168	0	0
T10	0	31728	0	0
T11	0	12037	0	0
T12	912	0	0	0
T13	1318	0	0	0
T14	1570	0	0	0
T15	2464	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39930254	0	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T12,T15
1	0	Covered	T3,T12,T15

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T12,T13
1	0	Unreachable
1	1	Covered	T3,T12,T15

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T12,T15
0	0	1	Unreachable
0	0	0	Covered	T3,T12,T13

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T12,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T12,T15
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	39930254	13784840	0	0
CheckNGreaterZero_A	659	659	0	0
GntImpliesReady_A	39930254	234260	0	0
GntImpliesValid_A	39930254	234260	0	0
GrantKnown_A	39930254	13784840	0	0
IdxKnown_A	39930254	13784840	0	0
IndexIsCorrect_A	39930254	234260	0	0
LockArbDecision_A	39930254	0	0	0
NoReadyValidNoGrant_A	39930254	0	0	0
ReadyAndValidImplyGrant_A	39930254	234260	0	0
ReqAndReadyImplyGrant_A	39930254	234260	0	0
ReqImpliesValid_A	39930254	234260	0	0
ReqStaysHighUntilGranted0_M	39930254	0	0	0
RoundRobin_A	39930254	0	0	0
ValidKnown_A	39930254	13784840	0	0
gen_data_port_assertion.DataFlow_A	39930254	234260	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39930254	13784840	0	0
T3	1040	1040	0	0
T4	145528	0	0	0
T5	51606	0	0	0
T6	133417	0	0	0
T7	127280	0	0	0
T8	6958	0	0	0
T12	912	912	0	0
T13	1318	864	0	0
T14	1570	1296	0	0
T15	2464	2464	0	0
T20	0	1368	0	0
T21	0	85240	0	0
T22	0	203840	0	0
T23	0	72	0	0
T59	0	250480	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659	659	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39930254	234260	0	0
T3	1040	34	0	0
T4	145528	0	0	0
T5	51606	0	0	0
T6	133417	0	0	0
T7	127280	0	0	0
T8	6958	0	0	0
T12	912	33	0	0
T13	1318	0	0	0
T14	1570	0	0	0
T15	2464	207	0	0
T20	0	128	0	0
T21	0	3398	0	0
T22	0	9384	0	0
T59	0	6057	0	0
T60	0	234	0	0
T61	0	7712	0	0
T62	0	173	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39930254	234260	0	0
T3	1040	34	0	0
T4	145528	0	0	0
T5	51606	0	0	0
T6	133417	0	0	0
T7	127280	0	0	0
T8	6958	0	0	0
T12	912	33	0	0
T13	1318	0	0	0
T14	1570	0	0	0
T15	2464	207	0	0
T20	0	128	0	0
T21	0	3398	0	0
T22	0	9384	0	0
T59	0	6057	0	0
T60	0	234	0	0
T61	0	7712	0	0
T62	0	173	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39930254	13784840	0	0
T3	1040	1040	0	0
T4	145528	0	0	0
T5	51606	0	0	0
T6	133417	0	0	0
T7	127280	0	0	0
T8	6958	0	0	0
T12	912	912	0	0
T13	1318	864	0	0
T14	1570	1296	0	0
T15	2464	2464	0	0
T20	0	1368	0	0
T21	0	85240	0	0
T22	0	203840	0	0
T23	0	72	0	0
T59	0	250480	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39930254	13784840	0	0
T3	1040	1040	0	0
T4	145528	0	0	0
T5	51606	0	0	0
T6	133417	0	0	0
T7	127280	0	0	0
T8	6958	0	0	0
T12	912	912	0	0
T13	1318	864	0	0
T14	1570	1296	0	0
T15	2464	2464	0	0
T20	0	1368	0	0
T21	0	85240	0	0
T22	0	203840	0	0
T23	0	72	0	0
T59	0	250480	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39930254	234260	0	0
T3	1040	34	0	0
T4	145528	0	0	0
T5	51606	0	0	0
T6	133417	0	0	0
T7	127280	0	0	0
T8	6958	0	0	0
T12	912	33	0	0
T13	1318	0	0	0
T14	1570	0	0	0
T15	2464	207	0	0
T20	0	128	0	0
T21	0	3398	0	0
T22	0	9384	0	0
T59	0	6057	0	0
T60	0	234	0	0
T61	0	7712	0	0
T62	0	173	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39930254	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39930254	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39930254	234260	0	0
T3	1040	34	0	0
T4	145528	0	0	0
T5	51606	0	0	0
T6	133417	0	0	0
T7	127280	0	0	0
T8	6958	0	0	0
T12	912	33	0	0
T13	1318	0	0	0
T14	1570	0	0	0
T15	2464	207	0	0
T20	0	128	0	0
T21	0	3398	0	0
T22	0	9384	0	0
T59	0	6057	0	0
T60	0	234	0	0
T61	0	7712	0	0
T62	0	173	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39930254	234260	0	0
T3	1040	34	0	0
T4	145528	0	0	0
T5	51606	0	0	0
T6	133417	0	0	0
T7	127280	0	0	0
T8	6958	0	0	0
T12	912	33	0	0
T13	1318	0	0	0
T14	1570	0	0	0
T15	2464	207	0	0
T20	0	128	0	0
T21	0	3398	0	0
T22	0	9384	0	0
T59	0	6057	0	0
T60	0	234	0	0
T61	0	7712	0	0
T62	0	173	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39930254	234260	0	0
T3	1040	34	0	0
T4	145528	0	0	0
T5	51606	0	0	0
T6	133417	0	0	0
T7	127280	0	0	0
T8	6958	0	0	0
T12	912	33	0	0
T13	1318	0	0	0
T14	1570	0	0	0
T15	2464	207	0	0
T20	0	128	0	0
T21	0	3398	0	0
T22	0	9384	0	0
T59	0	6057	0	0
T60	0	234	0	0
T61	0	7712	0	0
T62	0	173	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	39930254	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39930254	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39930254	13784840	0	0
T3	1040	1040	0	0
T4	145528	0	0	0
T5	51606	0	0	0
T6	133417	0	0	0
T7	127280	0	0	0
T8	6958	0	0	0
T12	912	912	0	0
T13	1318	864	0	0
T14	1570	1296	0	0
T15	2464	2464	0	0
T20	0	1368	0	0
T21	0	85240	0	0
T22	0	203840	0	0
T23	0	72	0	0
T59	0	250480	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39930254	234260	0	0
T3	1040	34	0	0
T4	145528	0	0	0
T5	51606	0	0	0
T6	133417	0	0	0
T7	127280	0	0	0
T8	6958	0	0	0
T12	912	33	0	0
T13	1318	0	0	0
T14	1570	0	0	0
T15	2464	207	0	0
T20	0	128	0	0
T21	0	3398	0	0
T22	0	9384	0	0
T59	0	6057	0	0
T60	0	234	0	0
T61	0	7712	0	0
T62	0	173	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T12,T15

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T12,T15
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T12,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	121083566	121025645	0	0
CheckNGreaterZero_A	659	659	0	0
GntImpliesReady_A	121083566	465844	0	0
GntImpliesValid_A	121083566	465844	0	0
GrantKnown_A	121083566	121025645	0	0
IdxKnown_A	121083566	121025645	0	0
IndexIsCorrect_A	121083566	465844	0	0
LockArbDecision_A	121083566	0	0	0
NoReadyValidNoGrant_A	121083566	0	0	0
ReadyAndValidImplyGrant_A	121083566	465844	0	0
ReqAndReadyImplyGrant_A	121083566	465844	0	0
ReqImpliesValid_A	121083566	465844	0	0
ReqStaysHighUntilGranted0_M	121083566	0	0	0
RoundRobin_A	121083566	0	0	659
ValidKnown_A	121083566	121025645	0	0
gen_data_port_assertion.DataFlow_A	121083566	465844	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121083566	121025645	0	0
T1	132218	132141	0	0
T2	18762	18666	0	0
T3	8327	8268	0	0
T4	585864	585775	0	0
T5	30758	30661	0	0
T12	2020	1936	0	0
T13	9582	9517	0	0
T16	693	604	0	0
T17	1062	973	0	0
T18	988	917	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659	659	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121083566	465844	0	0
T1	132218	832	0	0
T2	18762	832	0	0
T3	8327	24	0	0
T4	585864	832	0	0
T5	30758	832	0	0
T6	0	832	0	0
T7	0	4416	0	0
T8	0	832	0	0
T12	2020	17	0	0
T13	9582	0	0	0
T15	0	66	0	0
T16	693	0	0	0
T17	1062	0	0	0
T18	988	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121083566	465844	0	0
T1	132218	832	0	0
T2	18762	832	0	0
T3	8327	24	0	0
T4	585864	832	0	0
T5	30758	832	0	0
T6	0	832	0	0
T7	0	4416	0	0
T8	0	832	0	0
T12	2020	17	0	0
T13	9582	0	0	0
T15	0	66	0	0
T16	693	0	0	0
T17	1062	0	0	0
T18	988	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121083566	121025645	0	0
T1	132218	132141	0	0
T2	18762	18666	0	0
T3	8327	8268	0	0
T4	585864	585775	0	0
T5	30758	30661	0	0
T12	2020	1936	0	0
T13	9582	9517	0	0
T16	693	604	0	0
T17	1062	973	0	0
T18	988	917	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121083566	121025645	0	0
T1	132218	132141	0	0
T2	18762	18666	0	0
T3	8327	8268	0	0
T4	585864	585775	0	0
T5	30758	30661	0	0
T12	2020	1936	0	0
T13	9582	9517	0	0
T16	693	604	0	0
T17	1062	973	0	0
T18	988	917	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121083566	465844	0	0
T1	132218	832	0	0
T2	18762	832	0	0
T3	8327	24	0	0
T4	585864	832	0	0
T5	30758	832	0	0
T6	0	832	0	0
T7	0	4416	0	0
T8	0	832	0	0
T12	2020	17	0	0
T13	9582	0	0	0
T15	0	66	0	0
T16	693	0	0	0
T17	1062	0	0	0
T18	988	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121083566	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121083566	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121083566	465844	0	0
T1	132218	832	0	0
T2	18762	832	0	0
T3	8327	24	0	0
T4	585864	832	0	0
T5	30758	832	0	0
T6	0	832	0	0
T7	0	4416	0	0
T8	0	832	0	0
T12	2020	17	0	0
T13	9582	0	0	0
T15	0	66	0	0
T16	693	0	0	0
T17	1062	0	0	0
T18	988	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121083566	465844	0	0
T1	132218	832	0	0
T2	18762	832	0	0
T3	8327	24	0	0
T4	585864	832	0	0
T5	30758	832	0	0
T6	0	832	0	0
T7	0	4416	0	0
T8	0	832	0	0
T12	2020	17	0	0
T13	9582	0	0	0
T15	0	66	0	0
T16	693	0	0	0
T17	1062	0	0	0
T18	988	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121083566	465844	0	0
T1	132218	832	0	0
T2	18762	832	0	0
T3	8327	24	0	0
T4	585864	832	0	0
T5	30758	832	0	0
T6	0	832	0	0
T7	0	4416	0	0
T8	0	832	0	0
T12	2020	17	0	0
T13	9582	0	0	0
T15	0	66	0	0
T16	693	0	0	0
T17	1062	0	0	0
T18	988	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	121083566	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121083566	0	0	659

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121083566	121025645	0	0
T1	132218	132141	0	0
T2	18762	18666	0	0
T3	8327	8268	0	0
T4	585864	585775	0	0
T5	30758	30661	0	0
T12	2020	1936	0	0
T13	9582	9517	0	0
T16	693	604	0	0
T17	1062	973	0	0
T18	988	917	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121083566	465844	0	0
T1	132218	832	0	0
T2	18762	832	0	0
T3	8327	24	0	0
T4	585864	832	0	0
T5	30758	832	0	0
T6	0	832	0	0
T7	0	4416	0	0
T8	0	832	0	0
T12	2020	17	0	0
T13	9582	0	0	0
T15	0	66	0	0
T16	693	0	0	0
T17	1062	0	0	0
T18	988	0	0	0