Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123678872 |
3893 |
0 |
0 |
T35 |
2698 |
111 |
0 |
0 |
T37 |
6795 |
72 |
0 |
0 |
T38 |
80858 |
5 |
0 |
0 |
T109 |
6635 |
76 |
0 |
0 |
T112 |
101172 |
2 |
0 |
0 |
T119 |
17238 |
335 |
0 |
0 |
T120 |
4136 |
274 |
0 |
0 |
T122 |
3824 |
9 |
0 |
0 |
T125 |
11838 |
7 |
0 |
0 |
T126 |
14618 |
8 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123678872 |
2037 |
0 |
0 |
T112 |
101172 |
112 |
0 |
0 |
T126 |
14618 |
27 |
0 |
0 |
T132 |
157217 |
266 |
0 |
0 |
T138 |
6882 |
4 |
0 |
0 |
T143 |
19170 |
12 |
0 |
0 |
T147 |
6139 |
6 |
0 |
0 |
T149 |
4951 |
3 |
0 |
0 |
T150 |
13682 |
16 |
0 |
0 |
T151 |
5523 |
7 |
0 |
0 |
T152 |
234669 |
394 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123678872 |
2126 |
0 |
0 |
T112 |
101172 |
105 |
0 |
0 |
T126 |
14618 |
22 |
0 |
0 |
T132 |
157217 |
321 |
0 |
0 |
T138 |
6882 |
6 |
0 |
0 |
T143 |
19170 |
20 |
0 |
0 |
T147 |
6139 |
9 |
0 |
0 |
T149 |
4951 |
12 |
0 |
0 |
T150 |
13682 |
19 |
0 |
0 |
T151 |
5523 |
7 |
0 |
0 |
T152 |
234669 |
449 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123678872 |
2544 |
0 |
0 |
T112 |
101172 |
214 |
0 |
0 |
T126 |
14618 |
49 |
0 |
0 |
T132 |
157217 |
213 |
0 |
0 |
T138 |
6882 |
27 |
0 |
0 |
T143 |
19170 |
54 |
0 |
0 |
T147 |
6139 |
13 |
0 |
0 |
T149 |
4951 |
26 |
0 |
0 |
T150 |
13682 |
37 |
0 |
0 |
T151 |
5523 |
16 |
0 |
0 |
T152 |
234669 |
425 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123678872 |
9197 |
0 |
0 |
T112 |
101172 |
2181 |
0 |
0 |
T126 |
14618 |
236 |
0 |
0 |
T132 |
157217 |
338 |
0 |
0 |
T138 |
6882 |
10 |
0 |
0 |
T143 |
19170 |
37 |
0 |
0 |
T147 |
6139 |
134 |
0 |
0 |
T149 |
4951 |
2 |
0 |
0 |
T150 |
13682 |
169 |
0 |
0 |
T151 |
5523 |
12 |
0 |
0 |
T152 |
234669 |
445 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123678872 |
8513 |
0 |
0 |
T112 |
101172 |
2253 |
0 |
0 |
T126 |
14618 |
35 |
0 |
0 |
T132 |
157217 |
211 |
0 |
0 |
T138 |
6882 |
122 |
0 |
0 |
T143 |
19170 |
36 |
0 |
0 |
T147 |
6139 |
11 |
0 |
0 |
T149 |
4951 |
15 |
0 |
0 |
T150 |
13682 |
175 |
0 |
0 |
T151 |
5523 |
134 |
0 |
0 |
T152 |
234669 |
416 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123678872 |
7996 |
0 |
0 |
T112 |
101172 |
1700 |
0 |
0 |
T126 |
14618 |
264 |
0 |
0 |
T132 |
157217 |
350 |
0 |
0 |
T138 |
6882 |
143 |
0 |
0 |
T143 |
19170 |
47 |
0 |
0 |
T147 |
6139 |
149 |
0 |
0 |
T149 |
4951 |
2 |
0 |
0 |
T150 |
13682 |
13 |
0 |
0 |
T151 |
5523 |
12 |
0 |
0 |
T152 |
234669 |
361 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123678872 |
8770 |
0 |
0 |
T112 |
101172 |
1892 |
0 |
0 |
T126 |
14618 |
17 |
0 |
0 |
T132 |
157217 |
253 |
0 |
0 |
T138 |
6882 |
147 |
0 |
0 |
T143 |
19170 |
32 |
0 |
0 |
T147 |
6139 |
141 |
0 |
0 |
T149 |
4951 |
6 |
0 |
0 |
T150 |
13682 |
269 |
0 |
0 |
T151 |
5523 |
168 |
0 |
0 |
T152 |
234669 |
434 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123678872 |
8161 |
0 |
0 |
T112 |
101172 |
2069 |
0 |
0 |
T126 |
14618 |
141 |
0 |
0 |
T132 |
157217 |
237 |
0 |
0 |
T138 |
6882 |
5 |
0 |
0 |
T143 |
19170 |
34 |
0 |
0 |
T147 |
6139 |
2 |
0 |
0 |
T149 |
4951 |
111 |
0 |
0 |
T150 |
13682 |
99 |
0 |
0 |
T151 |
5523 |
132 |
0 |
0 |
T152 |
234669 |
452 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123678872 |
8645 |
0 |
0 |
T112 |
101172 |
2057 |
0 |
0 |
T126 |
14618 |
146 |
0 |
0 |
T132 |
157217 |
254 |
0 |
0 |
T138 |
6882 |
15 |
0 |
0 |
T143 |
19170 |
40 |
0 |
0 |
T147 |
6139 |
2 |
0 |
0 |
T149 |
4951 |
11 |
0 |
0 |
T150 |
13682 |
248 |
0 |
0 |
T151 |
5523 |
5 |
0 |
0 |
T152 |
234669 |
385 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123678872 |
8782 |
0 |
0 |
T112 |
101172 |
2231 |
0 |
0 |
T126 |
14618 |
208 |
0 |
0 |
T132 |
157217 |
283 |
0 |
0 |
T138 |
6882 |
120 |
0 |
0 |
T143 |
19170 |
32 |
0 |
0 |
T147 |
6139 |
130 |
0 |
0 |
T149 |
4951 |
104 |
0 |
0 |
T150 |
13682 |
21 |
0 |
0 |
T151 |
5523 |
14 |
0 |
0 |
T152 |
234669 |
381 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123678872 |
8495 |
0 |
0 |
T112 |
101172 |
2215 |
0 |
0 |
T126 |
14618 |
174 |
0 |
0 |
T132 |
157217 |
299 |
0 |
0 |
T142 |
6865 |
292 |
0 |
0 |
T143 |
19170 |
25 |
0 |
0 |
T147 |
6139 |
135 |
0 |
0 |
T149 |
4951 |
12 |
0 |
0 |
T150 |
13682 |
275 |
0 |
0 |
T151 |
5523 |
114 |
0 |
0 |
T152 |
234669 |
446 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123678872 |
4436 |
0 |
0 |
T112 |
101172 |
663 |
0 |
0 |
T126 |
14618 |
52 |
0 |
0 |
T132 |
157217 |
273 |
0 |
0 |
T138 |
6882 |
58 |
0 |
0 |
T143 |
19170 |
41 |
0 |
0 |
T147 |
6139 |
51 |
0 |
0 |
T149 |
4951 |
8 |
0 |
0 |
T150 |
13682 |
69 |
0 |
0 |
T151 |
5523 |
45 |
0 |
0 |
T152 |
234669 |
414 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123678872 |
4337 |
0 |
0 |
T112 |
101172 |
701 |
0 |
0 |
T126 |
14618 |
22 |
0 |
0 |
T132 |
157217 |
277 |
0 |
0 |
T138 |
6882 |
93 |
0 |
0 |
T142 |
6865 |
53 |
0 |
0 |
T143 |
19170 |
39 |
0 |
0 |
T147 |
6139 |
2 |
0 |
0 |
T150 |
13682 |
129 |
0 |
0 |
T151 |
5523 |
15 |
0 |
0 |
T152 |
234669 |
395 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123678872 |
4568 |
0 |
0 |
T112 |
101172 |
908 |
0 |
0 |
T126 |
14618 |
21 |
0 |
0 |
T132 |
157217 |
260 |
0 |
0 |
T138 |
6882 |
116 |
0 |
0 |
T143 |
19170 |
10 |
0 |
0 |
T147 |
6139 |
60 |
0 |
0 |
T149 |
4951 |
3 |
0 |
0 |
T150 |
13682 |
50 |
0 |
0 |
T151 |
5523 |
59 |
0 |
0 |
T152 |
234669 |
348 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123678872 |
4085 |
0 |
0 |
T112 |
101172 |
720 |
0 |
0 |
T126 |
14618 |
127 |
0 |
0 |
T132 |
157217 |
202 |
0 |
0 |
T138 |
6882 |
9 |
0 |
0 |
T143 |
19170 |
34 |
0 |
0 |
T147 |
6139 |
43 |
0 |
0 |
T149 |
4951 |
57 |
0 |
0 |
T150 |
13682 |
63 |
0 |
0 |
T151 |
5523 |
9 |
0 |
0 |
T152 |
234669 |
350 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123678872 |
4204 |
0 |
0 |
T112 |
101172 |
650 |
0 |
0 |
T126 |
14618 |
78 |
0 |
0 |
T132 |
157217 |
275 |
0 |
0 |
T138 |
6882 |
98 |
0 |
0 |
T143 |
19170 |
20 |
0 |
0 |
T147 |
6139 |
8 |
0 |
0 |
T149 |
4951 |
39 |
0 |
0 |
T150 |
13682 |
131 |
0 |
0 |
T151 |
5523 |
62 |
0 |
0 |
T152 |
234669 |
462 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123678872 |
4972 |
0 |
0 |
T112 |
101172 |
806 |
0 |
0 |
T126 |
14618 |
16 |
0 |
0 |
T132 |
157217 |
289 |
0 |
0 |
T138 |
6882 |
105 |
0 |
0 |
T143 |
19170 |
30 |
0 |
0 |
T147 |
6139 |
72 |
0 |
0 |
T149 |
4951 |
11 |
0 |
0 |
T150 |
13682 |
65 |
0 |
0 |
T151 |
5523 |
57 |
0 |
0 |
T152 |
234669 |
410 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123678872 |
4734 |
0 |
0 |
T112 |
101172 |
769 |
0 |
0 |
T126 |
14618 |
86 |
0 |
0 |
T132 |
157217 |
360 |
0 |
0 |
T138 |
6882 |
59 |
0 |
0 |
T143 |
19170 |
58 |
0 |
0 |
T147 |
6139 |
62 |
0 |
0 |
T149 |
4951 |
65 |
0 |
0 |
T150 |
13682 |
77 |
0 |
0 |
T151 |
5523 |
9 |
0 |
0 |
T152 |
234669 |
403 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123678872 |
4513 |
0 |
0 |
T112 |
101172 |
660 |
0 |
0 |
T126 |
14618 |
99 |
0 |
0 |
T132 |
157217 |
255 |
0 |
0 |
T138 |
6882 |
28 |
0 |
0 |
T143 |
19170 |
49 |
0 |
0 |
T147 |
6139 |
121 |
0 |
0 |
T149 |
4951 |
53 |
0 |
0 |
T150 |
13682 |
136 |
0 |
0 |
T151 |
5523 |
57 |
0 |
0 |
T152 |
234669 |
379 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123678872 |
4842 |
0 |
0 |
T112 |
101172 |
847 |
0 |
0 |
T126 |
14618 |
55 |
0 |
0 |
T132 |
157217 |
278 |
0 |
0 |
T138 |
6882 |
96 |
0 |
0 |
T143 |
19170 |
37 |
0 |
0 |
T147 |
6139 |
57 |
0 |
0 |
T149 |
4951 |
3 |
0 |
0 |
T150 |
13682 |
90 |
0 |
0 |
T151 |
5523 |
5 |
0 |
0 |
T152 |
234669 |
365 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123678872 |
4776 |
0 |
0 |
T112 |
101172 |
976 |
0 |
0 |
T126 |
14618 |
100 |
0 |
0 |
T132 |
157217 |
250 |
0 |
0 |
T138 |
6882 |
49 |
0 |
0 |
T143 |
19170 |
16 |
0 |
0 |
T147 |
6139 |
43 |
0 |
0 |
T149 |
4951 |
5 |
0 |
0 |
T150 |
13682 |
113 |
0 |
0 |
T151 |
5523 |
9 |
0 |
0 |
T152 |
234669 |
363 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123678872 |
5106 |
0 |
0 |
T112 |
101172 |
806 |
0 |
0 |
T126 |
14618 |
73 |
0 |
0 |
T132 |
157217 |
283 |
0 |
0 |
T138 |
6882 |
112 |
0 |
0 |
T143 |
19170 |
72 |
0 |
0 |
T147 |
6139 |
47 |
0 |
0 |
T149 |
4951 |
49 |
0 |
0 |
T150 |
13682 |
130 |
0 |
0 |
T151 |
5523 |
12 |
0 |
0 |
T152 |
234669 |
390 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123678872 |
4398 |
0 |
0 |
T112 |
101172 |
591 |
0 |
0 |
T126 |
14618 |
65 |
0 |
0 |
T132 |
157217 |
286 |
0 |
0 |
T138 |
6882 |
3 |
0 |
0 |
T143 |
19170 |
82 |
0 |
0 |
T147 |
6139 |
93 |
0 |
0 |
T149 |
4951 |
45 |
0 |
0 |
T150 |
13682 |
121 |
0 |
0 |
T151 |
5523 |
4 |
0 |
0 |
T152 |
234669 |
404 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123678872 |
4417 |
0 |
0 |
T112 |
101172 |
707 |
0 |
0 |
T126 |
14618 |
114 |
0 |
0 |
T132 |
157217 |
282 |
0 |
0 |
T138 |
6882 |
10 |
0 |
0 |
T143 |
19170 |
45 |
0 |
0 |
T147 |
6139 |
11 |
0 |
0 |
T149 |
4951 |
13 |
0 |
0 |
T150 |
13682 |
50 |
0 |
0 |
T151 |
5523 |
53 |
0 |
0 |
T152 |
234669 |
445 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123678872 |
4512 |
0 |
0 |
T112 |
101172 |
967 |
0 |
0 |
T126 |
14618 |
107 |
0 |
0 |
T132 |
157217 |
292 |
0 |
0 |
T138 |
6882 |
2 |
0 |
0 |
T143 |
19170 |
26 |
0 |
0 |
T147 |
6139 |
102 |
0 |
0 |
T149 |
4951 |
43 |
0 |
0 |
T150 |
13682 |
58 |
0 |
0 |
T151 |
5523 |
58 |
0 |
0 |
T152 |
234669 |
392 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123678872 |
4686 |
0 |
0 |
T112 |
101172 |
653 |
0 |
0 |
T126 |
14618 |
66 |
0 |
0 |
T132 |
157217 |
296 |
0 |
0 |
T138 |
6882 |
51 |
0 |
0 |
T143 |
19170 |
65 |
0 |
0 |
T147 |
6139 |
56 |
0 |
0 |
T149 |
4951 |
55 |
0 |
0 |
T150 |
13682 |
130 |
0 |
0 |
T151 |
5523 |
12 |
0 |
0 |
T152 |
234669 |
408 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123678872 |
4580 |
0 |
0 |
T112 |
101172 |
886 |
0 |
0 |
T126 |
14618 |
70 |
0 |
0 |
T132 |
157217 |
234 |
0 |
0 |
T138 |
6882 |
38 |
0 |
0 |
T143 |
19170 |
40 |
0 |
0 |
T147 |
6139 |
69 |
0 |
0 |
T149 |
4951 |
37 |
0 |
0 |
T150 |
13682 |
18 |
0 |
0 |
T151 |
5523 |
9 |
0 |
0 |
T152 |
234669 |
482 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123678872 |
4906 |
0 |
0 |
T112 |
101172 |
727 |
0 |
0 |
T126 |
14618 |
103 |
0 |
0 |
T132 |
157217 |
300 |
0 |
0 |
T138 |
6882 |
125 |
0 |
0 |
T143 |
19170 |
18 |
0 |
0 |
T147 |
6139 |
5 |
0 |
0 |
T149 |
4951 |
12 |
0 |
0 |
T150 |
13682 |
176 |
0 |
0 |
T151 |
5523 |
4 |
0 |
0 |
T152 |
234669 |
504 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123678872 |
4606 |
0 |
0 |
T112 |
101172 |
812 |
0 |
0 |
T126 |
14618 |
151 |
0 |
0 |
T132 |
157217 |
280 |
0 |
0 |
T138 |
6882 |
7 |
0 |
0 |
T143 |
19170 |
60 |
0 |
0 |
T147 |
6139 |
3 |
0 |
0 |
T149 |
4951 |
33 |
0 |
0 |
T150 |
13682 |
73 |
0 |
0 |
T151 |
5523 |
8 |
0 |
0 |
T152 |
234669 |
443 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123678872 |
4531 |
0 |
0 |
T112 |
101172 |
1011 |
0 |
0 |
T126 |
14618 |
19 |
0 |
0 |
T132 |
157217 |
220 |
0 |
0 |
T138 |
6882 |
4 |
0 |
0 |
T143 |
19170 |
44 |
0 |
0 |
T147 |
6139 |
121 |
0 |
0 |
T149 |
4951 |
50 |
0 |
0 |
T150 |
13682 |
150 |
0 |
0 |
T151 |
5523 |
13 |
0 |
0 |
T152 |
234669 |
397 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123678872 |
3966 |
0 |
0 |
T112 |
101172 |
676 |
0 |
0 |
T126 |
14618 |
45 |
0 |
0 |
T132 |
157217 |
261 |
0 |
0 |
T138 |
6882 |
75 |
0 |
0 |
T143 |
19170 |
27 |
0 |
0 |
T147 |
6139 |
11 |
0 |
0 |
T149 |
4951 |
6 |
0 |
0 |
T150 |
13682 |
97 |
0 |
0 |
T151 |
5523 |
10 |
0 |
0 |
T152 |
234669 |
310 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123678872 |
4520 |
0 |
0 |
T112 |
101172 |
724 |
0 |
0 |
T126 |
14618 |
76 |
0 |
0 |
T132 |
157217 |
262 |
0 |
0 |
T138 |
6882 |
134 |
0 |
0 |
T143 |
19170 |
18 |
0 |
0 |
T147 |
6139 |
53 |
0 |
0 |
T149 |
4951 |
7 |
0 |
0 |
T150 |
13682 |
112 |
0 |
0 |
T151 |
5523 |
4 |
0 |
0 |
T152 |
234669 |
424 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123678872 |
5141 |
0 |
0 |
T112 |
101172 |
997 |
0 |
0 |
T126 |
14618 |
61 |
0 |
0 |
T132 |
157217 |
306 |
0 |
0 |
T138 |
6882 |
37 |
0 |
0 |
T143 |
19170 |
47 |
0 |
0 |
T147 |
6139 |
59 |
0 |
0 |
T149 |
4951 |
1 |
0 |
0 |
T150 |
13682 |
84 |
0 |
0 |
T151 |
5523 |
61 |
0 |
0 |
T152 |
234669 |
390 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123678872 |
4805 |
0 |
0 |
T112 |
101172 |
1075 |
0 |
0 |
T126 |
14618 |
128 |
0 |
0 |
T132 |
157217 |
243 |
0 |
0 |
T138 |
6882 |
58 |
0 |
0 |
T142 |
6865 |
7 |
0 |
0 |
T143 |
19170 |
41 |
0 |
0 |
T147 |
6139 |
61 |
0 |
0 |
T149 |
4951 |
30 |
0 |
0 |
T150 |
13682 |
51 |
0 |
0 |
T152 |
234669 |
473 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123678872 |
4992 |
0 |
0 |
T112 |
101172 |
821 |
0 |
0 |
T126 |
14618 |
107 |
0 |
0 |
T132 |
157217 |
264 |
0 |
0 |
T138 |
6882 |
70 |
0 |
0 |
T142 |
6865 |
100 |
0 |
0 |
T143 |
19170 |
17 |
0 |
0 |
T149 |
4951 |
17 |
0 |
0 |
T150 |
13682 |
73 |
0 |
0 |
T151 |
5523 |
10 |
0 |
0 |
T152 |
234669 |
468 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123678872 |
2299 |
0 |
0 |
T112 |
101172 |
172 |
0 |
0 |
T126 |
14618 |
40 |
0 |
0 |
T132 |
157217 |
268 |
0 |
0 |
T138 |
6882 |
19 |
0 |
0 |
T143 |
19170 |
19 |
0 |
0 |
T147 |
6139 |
18 |
0 |
0 |
T149 |
4951 |
9 |
0 |
0 |
T150 |
13682 |
28 |
0 |
0 |
T151 |
5523 |
17 |
0 |
0 |
T152 |
234669 |
436 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123678872 |
2296 |
0 |
0 |
T112 |
101172 |
176 |
0 |
0 |
T126 |
14618 |
31 |
0 |
0 |
T132 |
157217 |
350 |
0 |
0 |
T138 |
6882 |
6 |
0 |
0 |
T143 |
19170 |
20 |
0 |
0 |
T147 |
6139 |
3 |
0 |
0 |
T149 |
4951 |
7 |
0 |
0 |
T150 |
13682 |
20 |
0 |
0 |
T151 |
5523 |
13 |
0 |
0 |
T152 |
234669 |
388 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123678872 |
2298 |
0 |
0 |
T112 |
101172 |
168 |
0 |
0 |
T126 |
14618 |
22 |
0 |
0 |
T132 |
157217 |
294 |
0 |
0 |
T138 |
6882 |
6 |
0 |
0 |
T143 |
19170 |
31 |
0 |
0 |
T147 |
6139 |
10 |
0 |
0 |
T149 |
4951 |
12 |
0 |
0 |
T150 |
13682 |
25 |
0 |
0 |
T151 |
5523 |
4 |
0 |
0 |
T152 |
234669 |
374 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123678872 |
2324 |
0 |
0 |
T112 |
101172 |
157 |
0 |
0 |
T126 |
14618 |
34 |
0 |
0 |
T132 |
157217 |
270 |
0 |
0 |
T138 |
6882 |
11 |
0 |
0 |
T143 |
19170 |
17 |
0 |
0 |
T147 |
6139 |
10 |
0 |
0 |
T149 |
4951 |
9 |
0 |
0 |
T150 |
13682 |
38 |
0 |
0 |
T151 |
5523 |
22 |
0 |
0 |
T152 |
234669 |
408 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123678872 |
2637 |
0 |
0 |
T112 |
101172 |
320 |
0 |
0 |
T126 |
14618 |
24 |
0 |
0 |
T132 |
157217 |
365 |
0 |
0 |
T138 |
6882 |
13 |
0 |
0 |
T143 |
19170 |
31 |
0 |
0 |
T147 |
6139 |
10 |
0 |
0 |
T149 |
4951 |
8 |
0 |
0 |
T150 |
13682 |
29 |
0 |
0 |
T151 |
5523 |
21 |
0 |
0 |
T152 |
234669 |
402 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123678872 |
4025 |
0 |
0 |
T32 |
5054 |
23 |
0 |
0 |
T86 |
13510 |
0 |
0 |
0 |
T93 |
240967 |
0 |
0 |
0 |
T103 |
507249 |
0 |
0 |
0 |
T112 |
0 |
406 |
0 |
0 |
T126 |
0 |
28 |
0 |
0 |
T132 |
0 |
241 |
0 |
0 |
T143 |
0 |
80 |
0 |
0 |
T153 |
0 |
21 |
0 |
0 |
T154 |
0 |
23 |
0 |
0 |
T155 |
0 |
18 |
0 |
0 |
T156 |
0 |
22 |
0 |
0 |
T157 |
0 |
11 |
0 |
0 |
T158 |
1257 |
0 |
0 |
0 |
T159 |
21396 |
0 |
0 |
0 |
T160 |
64006 |
0 |
0 |
0 |
T161 |
229864 |
0 |
0 |
0 |
T162 |
171057 |
0 |
0 |
0 |
T163 |
227077 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123678872 |
2399 |
0 |
0 |
T112 |
101172 |
162 |
0 |
0 |
T126 |
14618 |
41 |
0 |
0 |
T132 |
157217 |
317 |
0 |
0 |
T138 |
6882 |
24 |
0 |
0 |
T143 |
19170 |
11 |
0 |
0 |
T147 |
6139 |
21 |
0 |
0 |
T149 |
4951 |
2 |
0 |
0 |
T150 |
13682 |
30 |
0 |
0 |
T151 |
5523 |
10 |
0 |
0 |
T152 |
234669 |
397 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123678872 |
2291 |
0 |
0 |
T112 |
101172 |
178 |
0 |
0 |
T126 |
14618 |
27 |
0 |
0 |
T132 |
157217 |
283 |
0 |
0 |
T138 |
6882 |
19 |
0 |
0 |
T143 |
19170 |
21 |
0 |
0 |
T147 |
6139 |
7 |
0 |
0 |
T149 |
4951 |
6 |
0 |
0 |
T150 |
13682 |
36 |
0 |
0 |
T151 |
5523 |
4 |
0 |
0 |
T152 |
234669 |
350 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123678872 |
2120 |
0 |
0 |
T112 |
101172 |
123 |
0 |
0 |
T126 |
14618 |
30 |
0 |
0 |
T132 |
157217 |
302 |
0 |
0 |
T142 |
6865 |
9 |
0 |
0 |
T143 |
19170 |
24 |
0 |
0 |
T147 |
6139 |
11 |
0 |
0 |
T149 |
4951 |
2 |
0 |
0 |
T150 |
13682 |
17 |
0 |
0 |
T151 |
5523 |
3 |
0 |
0 |
T152 |
234669 |
391 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123678872 |
2018 |
0 |
0 |
T112 |
101172 |
130 |
0 |
0 |
T126 |
14618 |
22 |
0 |
0 |
T132 |
157217 |
323 |
0 |
0 |
T138 |
6882 |
8 |
0 |
0 |
T143 |
19170 |
38 |
0 |
0 |
T147 |
6139 |
10 |
0 |
0 |
T149 |
4951 |
5 |
0 |
0 |
T150 |
13682 |
25 |
0 |
0 |
T151 |
5523 |
5 |
0 |
0 |
T152 |
234669 |
390 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123678872 |
2176 |
0 |
0 |
T112 |
101172 |
146 |
0 |
0 |
T126 |
14618 |
23 |
0 |
0 |
T132 |
157217 |
267 |
0 |
0 |
T138 |
6882 |
12 |
0 |
0 |
T143 |
19170 |
46 |
0 |
0 |
T147 |
6139 |
7 |
0 |
0 |
T149 |
4951 |
2 |
0 |
0 |
T150 |
13682 |
18 |
0 |
0 |
T151 |
5523 |
9 |
0 |
0 |
T152 |
234669 |
456 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123678872 |
1908 |
0 |
0 |
T112 |
101172 |
107 |
0 |
0 |
T126 |
14618 |
9 |
0 |
0 |
T132 |
157217 |
247 |
0 |
0 |
T138 |
6882 |
11 |
0 |
0 |
T143 |
19170 |
36 |
0 |
0 |
T147 |
6139 |
5 |
0 |
0 |
T149 |
4951 |
2 |
0 |
0 |
T150 |
13682 |
16 |
0 |
0 |
T151 |
5523 |
5 |
0 |
0 |
T152 |
234669 |
355 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123678872 |
2580 |
0 |
0 |
T112 |
101172 |
214 |
0 |
0 |
T126 |
14618 |
37 |
0 |
0 |
T132 |
157217 |
253 |
0 |
0 |
T138 |
6882 |
21 |
0 |
0 |
T143 |
19170 |
20 |
0 |
0 |
T147 |
6139 |
18 |
0 |
0 |
T149 |
4951 |
9 |
0 |
0 |
T150 |
13682 |
34 |
0 |
0 |
T151 |
5523 |
1 |
0 |
0 |
T152 |
234669 |
493 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123678872 |
2070 |
0 |
0 |
T112 |
101172 |
110 |
0 |
0 |
T126 |
14618 |
29 |
0 |
0 |
T132 |
157217 |
251 |
0 |
0 |
T138 |
6882 |
4 |
0 |
0 |
T143 |
19170 |
18 |
0 |
0 |
T147 |
6139 |
5 |
0 |
0 |
T149 |
4951 |
2 |
0 |
0 |
T150 |
13682 |
14 |
0 |
0 |
T151 |
5523 |
14 |
0 |
0 |
T152 |
234669 |
373 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123678872 |
2763 |
0 |
0 |
T112 |
101172 |
245 |
0 |
0 |
T126 |
14618 |
48 |
0 |
0 |
T132 |
157217 |
292 |
0 |
0 |
T138 |
6882 |
49 |
0 |
0 |
T143 |
19170 |
18 |
0 |
0 |
T147 |
6139 |
24 |
0 |
0 |
T149 |
4951 |
8 |
0 |
0 |
T150 |
13682 |
75 |
0 |
0 |
T151 |
5523 |
21 |
0 |
0 |
T152 |
234669 |
390 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123678872 |
2235 |
0 |
0 |
T112 |
101172 |
138 |
0 |
0 |
T126 |
14618 |
18 |
0 |
0 |
T132 |
157217 |
249 |
0 |
0 |
T138 |
6882 |
12 |
0 |
0 |
T143 |
19170 |
48 |
0 |
0 |
T147 |
6139 |
15 |
0 |
0 |
T149 |
4951 |
15 |
0 |
0 |
T150 |
13682 |
31 |
0 |
0 |
T151 |
5523 |
4 |
0 |
0 |
T152 |
234669 |
345 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123678872 |
2088 |
0 |
0 |
T112 |
101172 |
112 |
0 |
0 |
T126 |
14618 |
21 |
0 |
0 |
T132 |
157217 |
286 |
0 |
0 |
T138 |
6882 |
3 |
0 |
0 |
T143 |
19170 |
19 |
0 |
0 |
T147 |
6139 |
8 |
0 |
0 |
T149 |
4951 |
7 |
0 |
0 |
T150 |
13682 |
19 |
0 |
0 |
T151 |
5523 |
2 |
0 |
0 |
T152 |
234669 |
435 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123678872 |
2075 |
0 |
0 |
T112 |
101172 |
118 |
0 |
0 |
T126 |
14618 |
27 |
0 |
0 |
T132 |
157217 |
215 |
0 |
0 |
T138 |
6882 |
12 |
0 |
0 |
T143 |
19170 |
30 |
0 |
0 |
T147 |
6139 |
5 |
0 |
0 |
T149 |
4951 |
14 |
0 |
0 |
T150 |
13682 |
26 |
0 |
0 |
T151 |
5523 |
14 |
0 |
0 |
T152 |
234669 |
399 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123678872 |
1900 |
0 |
0 |
T112 |
101172 |
93 |
0 |
0 |
T126 |
14618 |
22 |
0 |
0 |
T132 |
157217 |
252 |
0 |
0 |
T138 |
6882 |
6 |
0 |
0 |
T143 |
19170 |
30 |
0 |
0 |
T147 |
6139 |
8 |
0 |
0 |
T149 |
4951 |
9 |
0 |
0 |
T150 |
13682 |
20 |
0 |
0 |
T151 |
5523 |
11 |
0 |
0 |
T152 |
234669 |
385 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123678872 |
2134 |
0 |
0 |
T112 |
101172 |
120 |
0 |
0 |
T126 |
14618 |
22 |
0 |
0 |
T132 |
157217 |
362 |
0 |
0 |
T138 |
6882 |
7 |
0 |
0 |
T143 |
19170 |
54 |
0 |
0 |
T147 |
6139 |
18 |
0 |
0 |
T149 |
4951 |
8 |
0 |
0 |
T150 |
13682 |
25 |
0 |
0 |
T151 |
5523 |
9 |
0 |
0 |
T152 |
234669 |
370 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123678872 |
2188 |
0 |
0 |
T112 |
101172 |
123 |
0 |
0 |
T126 |
14618 |
30 |
0 |
0 |
T132 |
157217 |
251 |
0 |
0 |
T138 |
6882 |
9 |
0 |
0 |
T143 |
19170 |
34 |
0 |
0 |
T147 |
6139 |
16 |
0 |
0 |
T149 |
4951 |
4 |
0 |
0 |
T150 |
13682 |
28 |
0 |
0 |
T151 |
5523 |
3 |
0 |
0 |
T152 |
234669 |
458 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123678872 |
2091 |
0 |
0 |
T112 |
101172 |
117 |
0 |
0 |
T126 |
14618 |
28 |
0 |
0 |
T132 |
157217 |
312 |
0 |
0 |
T138 |
6882 |
3 |
0 |
0 |
T143 |
19170 |
42 |
0 |
0 |
T147 |
6139 |
3 |
0 |
0 |
T149 |
4951 |
6 |
0 |
0 |
T150 |
13682 |
24 |
0 |
0 |
T151 |
5523 |
10 |
0 |
0 |
T152 |
234669 |
333 |
0 |
0 |