Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.04 97.49 92.82 98.61 80.85 95.85 90.96 87.69


Total test records in report: 834
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T758 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.342753589 Apr 15 12:40:13 PM PDT 24 Apr 15 12:40:22 PM PDT 24 404107424 ps
T123 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3727924780 Apr 15 12:40:15 PM PDT 24 Apr 15 12:40:20 PM PDT 24 51825119 ps
T759 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3430785505 Apr 15 12:40:14 PM PDT 24 Apr 15 12:40:16 PM PDT 24 32218020 ps
T760 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2118624651 Apr 15 12:40:14 PM PDT 24 Apr 15 12:40:17 PM PDT 24 486378258 ps
T761 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1175158226 Apr 15 12:40:26 PM PDT 24 Apr 15 12:40:27 PM PDT 24 37568350 ps
T762 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.498182951 Apr 15 12:40:34 PM PDT 24 Apr 15 12:40:35 PM PDT 24 40108104 ps
T763 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3367204461 Apr 15 12:40:15 PM PDT 24 Apr 15 12:40:25 PM PDT 24 327956698 ps
T764 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3747897646 Apr 15 12:40:24 PM PDT 24 Apr 15 12:40:26 PM PDT 24 256248394 ps
T765 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.604479695 Apr 15 12:40:18 PM PDT 24 Apr 15 12:40:21 PM PDT 24 38417472 ps
T370 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2247096711 Apr 15 12:40:18 PM PDT 24 Apr 15 12:40:34 PM PDT 24 2173791659 ps
T766 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3424632707 Apr 15 12:40:18 PM PDT 24 Apr 15 12:40:21 PM PDT 24 15329551 ps
T767 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2064560730 Apr 15 12:40:15 PM PDT 24 Apr 15 12:40:17 PM PDT 24 16045000 ps
T127 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1136884670 Apr 15 12:40:22 PM PDT 24 Apr 15 12:40:27 PM PDT 24 448731177 ps
T768 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.19477488 Apr 15 12:40:11 PM PDT 24 Apr 15 12:40:33 PM PDT 24 1139520359 ps
T769 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.469518277 Apr 15 12:40:29 PM PDT 24 Apr 15 12:40:36 PM PDT 24 219421066 ps
T770 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3327415871 Apr 15 12:40:12 PM PDT 24 Apr 15 12:40:16 PM PDT 24 147828905 ps
T771 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.4113132952 Apr 15 12:40:20 PM PDT 24 Apr 15 12:40:22 PM PDT 24 129472517 ps
T772 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3206083705 Apr 15 12:40:20 PM PDT 24 Apr 15 12:40:29 PM PDT 24 1122678087 ps
T773 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.211688661 Apr 15 12:40:12 PM PDT 24 Apr 15 12:40:40 PM PDT 24 1901843733 ps
T774 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1774534309 Apr 15 12:40:16 PM PDT 24 Apr 15 12:40:19 PM PDT 24 63114426 ps
T775 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2229047535 Apr 15 12:40:20 PM PDT 24 Apr 15 12:40:33 PM PDT 24 862639660 ps
T776 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2433198073 Apr 15 12:40:25 PM PDT 24 Apr 15 12:40:26 PM PDT 24 14355875 ps
T98 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3515223021 Apr 15 12:40:18 PM PDT 24 Apr 15 12:40:21 PM PDT 24 58146863 ps
T777 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3376438781 Apr 15 12:40:25 PM PDT 24 Apr 15 12:40:30 PM PDT 24 745370004 ps
T778 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.4039832751 Apr 15 12:40:20 PM PDT 24 Apr 15 12:40:22 PM PDT 24 20151108 ps
T779 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3815842059 Apr 15 12:40:11 PM PDT 24 Apr 15 12:40:16 PM PDT 24 147567969 ps
T780 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2645510139 Apr 15 12:40:07 PM PDT 24 Apr 15 12:40:10 PM PDT 24 80070573 ps
T781 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1976559587 Apr 15 12:40:26 PM PDT 24 Apr 15 12:40:31 PM PDT 24 122394108 ps
T782 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.4138415388 Apr 15 12:40:16 PM PDT 24 Apr 15 12:40:20 PM PDT 24 54438393 ps
T374 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3519957019 Apr 15 12:40:17 PM PDT 24 Apr 15 12:40:41 PM PDT 24 3421095539 ps
T783 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3075156658 Apr 15 12:40:28 PM PDT 24 Apr 15 12:40:29 PM PDT 24 43562510 ps
T784 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2295036767 Apr 15 12:40:15 PM PDT 24 Apr 15 12:40:21 PM PDT 24 618847199 ps
T785 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3346082526 Apr 15 12:40:23 PM PDT 24 Apr 15 12:40:28 PM PDT 24 738424914 ps
T786 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1971771765 Apr 15 12:40:32 PM PDT 24 Apr 15 12:40:34 PM PDT 24 43855719 ps
T787 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2585451389 Apr 15 12:40:21 PM PDT 24 Apr 15 12:40:24 PM PDT 24 38806254 ps
T788 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2263253153 Apr 15 12:40:26 PM PDT 24 Apr 15 12:40:28 PM PDT 24 13090835 ps
T789 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3449145367 Apr 15 12:40:30 PM PDT 24 Apr 15 12:40:35 PM PDT 24 1092282940 ps
T790 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.300458546 Apr 15 12:40:16 PM PDT 24 Apr 15 12:40:24 PM PDT 24 301610303 ps
T791 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1947792238 Apr 15 12:40:20 PM PDT 24 Apr 15 12:40:22 PM PDT 24 42974795 ps
T792 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3423741712 Apr 15 12:40:18 PM PDT 24 Apr 15 12:40:21 PM PDT 24 16456255 ps
T793 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.4147834079 Apr 15 12:40:26 PM PDT 24 Apr 15 12:40:29 PM PDT 24 24919027 ps
T794 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2255118507 Apr 15 12:40:24 PM PDT 24 Apr 15 12:40:25 PM PDT 24 16579564 ps
T795 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.4094525123 Apr 15 12:40:19 PM PDT 24 Apr 15 12:40:21 PM PDT 24 17974687 ps
T796 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.4284418656 Apr 15 12:40:30 PM PDT 24 Apr 15 12:40:32 PM PDT 24 43210479 ps
T797 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2055777489 Apr 15 12:40:17 PM PDT 24 Apr 15 12:40:22 PM PDT 24 41084059 ps
T798 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3158317647 Apr 15 12:40:18 PM PDT 24 Apr 15 12:40:23 PM PDT 24 449929111 ps
T375 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1426449339 Apr 15 12:40:13 PM PDT 24 Apr 15 12:40:22 PM PDT 24 360168776 ps
T799 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.4068722820 Apr 15 12:40:15 PM PDT 24 Apr 15 12:40:17 PM PDT 24 15059075 ps
T800 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2078487956 Apr 15 12:40:27 PM PDT 24 Apr 15 12:40:28 PM PDT 24 13517022 ps
T801 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2913271510 Apr 15 12:40:28 PM PDT 24 Apr 15 12:40:51 PM PDT 24 809569833 ps
T802 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.580876228 Apr 15 12:40:10 PM PDT 24 Apr 15 12:40:11 PM PDT 24 29005092 ps
T803 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3252317440 Apr 15 12:40:24 PM PDT 24 Apr 15 12:40:28 PM PDT 24 191385195 ps
T99 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3386592212 Apr 15 12:40:10 PM PDT 24 Apr 15 12:40:12 PM PDT 24 182775153 ps
T804 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3584066003 Apr 15 12:40:17 PM PDT 24 Apr 15 12:40:20 PM PDT 24 12248512 ps
T805 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3042285088 Apr 15 12:40:11 PM PDT 24 Apr 15 12:40:14 PM PDT 24 40083470 ps
T806 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.949546736 Apr 15 12:40:18 PM PDT 24 Apr 15 12:40:41 PM PDT 24 328613069 ps
T807 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1259052581 Apr 15 12:40:23 PM PDT 24 Apr 15 12:40:25 PM PDT 24 22660489 ps
T808 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2855006694 Apr 15 12:40:16 PM PDT 24 Apr 15 12:40:21 PM PDT 24 124973377 ps
T809 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.267524205 Apr 15 12:40:18 PM PDT 24 Apr 15 12:40:33 PM PDT 24 667953133 ps
T810 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.806613373 Apr 15 12:40:16 PM PDT 24 Apr 15 12:40:19 PM PDT 24 53196439 ps
T811 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3328226759 Apr 15 12:40:18 PM PDT 24 Apr 15 12:40:22 PM PDT 24 218096294 ps
T812 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3224713455 Apr 15 12:40:17 PM PDT 24 Apr 15 12:40:20 PM PDT 24 568022434 ps
T813 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2225080796 Apr 15 12:40:15 PM PDT 24 Apr 15 12:40:19 PM PDT 24 114571730 ps
T814 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2051333733 Apr 15 12:40:32 PM PDT 24 Apr 15 12:40:34 PM PDT 24 41891405 ps
T815 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.4153285843 Apr 15 12:40:17 PM PDT 24 Apr 15 12:40:44 PM PDT 24 6323532936 ps
T816 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2638177169 Apr 15 12:40:16 PM PDT 24 Apr 15 12:40:20 PM PDT 24 100046882 ps
T817 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.841236735 Apr 15 12:40:14 PM PDT 24 Apr 15 12:40:16 PM PDT 24 64746575 ps
T818 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1459858350 Apr 15 12:40:17 PM PDT 24 Apr 15 12:40:21 PM PDT 24 35321626 ps
T819 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.553138116 Apr 15 12:40:16 PM PDT 24 Apr 15 12:40:19 PM PDT 24 93488995 ps
T820 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.5951703 Apr 15 12:40:18 PM PDT 24 Apr 15 12:40:23 PM PDT 24 52607227 ps
T821 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3693697189 Apr 15 12:40:29 PM PDT 24 Apr 15 12:40:32 PM PDT 24 1517227905 ps
T822 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2155772339 Apr 15 12:40:23 PM PDT 24 Apr 15 12:40:26 PM PDT 24 93604679 ps
T823 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2909444280 Apr 15 12:40:19 PM PDT 24 Apr 15 12:40:24 PM PDT 24 45165765 ps
T824 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2377690977 Apr 15 12:40:18 PM PDT 24 Apr 15 12:40:21 PM PDT 24 11453610 ps
T825 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2823813190 Apr 15 12:40:14 PM PDT 24 Apr 15 12:40:17 PM PDT 24 28206191 ps
T826 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2215645865 Apr 15 12:40:16 PM PDT 24 Apr 15 12:40:18 PM PDT 24 13400603 ps
T827 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2233905171 Apr 15 12:40:32 PM PDT 24 Apr 15 12:40:34 PM PDT 24 54866244 ps
T828 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3352424990 Apr 15 12:40:18 PM PDT 24 Apr 15 12:40:24 PM PDT 24 2982356019 ps
T829 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.631308559 Apr 15 12:40:18 PM PDT 24 Apr 15 12:40:24 PM PDT 24 189150167 ps
T830 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2365398998 Apr 15 12:40:30 PM PDT 24 Apr 15 12:40:39 PM PDT 24 1146300887 ps
T831 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1690622920 Apr 15 12:40:15 PM PDT 24 Apr 15 12:40:25 PM PDT 24 406616259 ps
T832 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3207004956 Apr 15 12:40:29 PM PDT 24 Apr 15 12:40:33 PM PDT 24 194602876 ps
T833 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2101139663 Apr 15 12:40:16 PM PDT 24 Apr 15 12:40:19 PM PDT 24 28239219 ps
T834 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.4127503776 Apr 15 12:40:23 PM PDT 24 Apr 15 12:40:26 PM PDT 24 38704514 ps

Test location /workspace/coverage/default/38.spi_device_upload.2838160784
Short name T5
Test name
Test status
Simulation time 591551715 ps
CPU time 4.02 seconds
Started Apr 15 01:21:13 PM PDT 24
Finished Apr 15 01:21:18 PM PDT 24
Peak memory 217356 kb
Host smart-136c2c94-b4a9-4513-b16f-e4f6b2c7c1af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838160784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.2838160784
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.4265422608
Short name T21
Test name
Test status
Simulation time 13244809459 ps
CPU time 23.58 seconds
Started Apr 15 01:21:48 PM PDT 24
Finished Apr 15 01:22:12 PM PDT 24
Peak memory 216256 kb
Host smart-6ded27cd-b0fc-401b-be5f-0404dd590466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265422608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.4265422608
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.50946831
Short name T110
Test name
Test status
Simulation time 3833535112 ps
CPU time 45.22 seconds
Started Apr 15 01:18:48 PM PDT 24
Finished Apr 15 01:19:34 PM PDT 24
Peak memory 221340 kb
Host smart-f53709a2-fe00-4d32-9bff-64b034248f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50946831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.50946831
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1344546639
Short name T112
Test name
Test status
Simulation time 4046934414 ps
CPU time 22.74 seconds
Started Apr 15 12:40:07 PM PDT 24
Finished Apr 15 12:40:31 PM PDT 24
Peak memory 215280 kb
Host smart-e281f454-4c5f-4629-a73b-586f24c9447f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344546639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.1344546639
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.1852453473
Short name T59
Test name
Test status
Simulation time 3573096192 ps
CPU time 35.12 seconds
Started Apr 15 01:18:47 PM PDT 24
Finished Apr 15 01:19:23 PM PDT 24
Peak memory 216480 kb
Host smart-8e01f9b7-6b3b-403b-acb2-0827ec07ef2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852453473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.1852453473
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.848543450
Short name T63
Test name
Test status
Simulation time 26618197108 ps
CPU time 36.63 seconds
Started Apr 15 01:19:25 PM PDT 24
Finished Apr 15 01:20:02 PM PDT 24
Peak memory 230008 kb
Host smart-fa851399-2c22-4e01-b1ea-54c9213c5b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848543450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.848543450
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.1889380088
Short name T33
Test name
Test status
Simulation time 101452388 ps
CPU time 1.32 seconds
Started Apr 15 01:19:01 PM PDT 24
Finished Apr 15 01:19:02 PM PDT 24
Peak memory 207192 kb
Host smart-0cabb6d1-88f5-429d-aa36-885025055530
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889380088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.1889380088
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.2874958373
Short name T1
Test name
Test status
Simulation time 1322207463 ps
CPU time 18.89 seconds
Started Apr 15 01:18:45 PM PDT 24
Finished Apr 15 01:19:05 PM PDT 24
Peak memory 218644 kb
Host smart-f8e4af17-4ba3-45c5-9b07-5205869f2efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874958373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.2874958373
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_upload.693581718
Short name T27
Test name
Test status
Simulation time 3747169412 ps
CPU time 7.3 seconds
Started Apr 15 01:21:27 PM PDT 24
Finished Apr 15 01:21:34 PM PDT 24
Peak memory 232672 kb
Host smart-0c07fcac-ca9a-4245-a63e-3f623955edb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693581718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.693581718
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.2586257719
Short name T61
Test name
Test status
Simulation time 110603361496 ps
CPU time 65.61 seconds
Started Apr 15 01:19:46 PM PDT 24
Finished Apr 15 01:20:52 PM PDT 24
Peak memory 216248 kb
Host smart-6cde8526-6162-4e81-b0f9-be299af4f406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586257719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.2586257719
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.2290465449
Short name T82
Test name
Test status
Simulation time 28454297148 ps
CPU time 54.78 seconds
Started Apr 15 01:18:46 PM PDT 24
Finished Apr 15 01:19:42 PM PDT 24
Peak memory 235016 kb
Host smart-125648c8-2e73-46c5-8d98-2854c8d484d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290465449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.2290465449
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.1003671582
Short name T41
Test name
Test status
Simulation time 18329700 ps
CPU time 0.76 seconds
Started Apr 15 01:18:25 PM PDT 24
Finished Apr 15 01:18:27 PM PDT 24
Peak memory 216188 kb
Host smart-a988e9a7-19b8-4008-bc6f-4da9ab7792a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003671582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.1003671582
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.1019288510
Short name T22
Test name
Test status
Simulation time 50824911330 ps
CPU time 71.55 seconds
Started Apr 15 01:19:18 PM PDT 24
Finished Apr 15 01:20:31 PM PDT 24
Peak memory 216316 kb
Host smart-bbef8cfb-9fe5-4dbe-9e67-06f757fde312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019288510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.1019288510
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_intercept.3254212783
Short name T93
Test name
Test status
Simulation time 5020087015 ps
CPU time 26.28 seconds
Started Apr 15 01:19:37 PM PDT 24
Finished Apr 15 01:20:04 PM PDT 24
Peak memory 224576 kb
Host smart-77ac3a29-67a4-4ed5-ab07-18191ea2be61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254212783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.3254212783
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.3426346882
Short name T6
Test name
Test status
Simulation time 2087518336 ps
CPU time 7.06 seconds
Started Apr 15 01:18:24 PM PDT 24
Finished Apr 15 01:18:32 PM PDT 24
Peak memory 226936 kb
Host smart-6adb0cf5-1aee-4a83-8f1e-508b70b7a530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426346882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.3426346882
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.35918816
Short name T119
Test name
Test status
Simulation time 689602141 ps
CPU time 4.97 seconds
Started Apr 15 12:40:16 PM PDT 24
Finished Apr 15 12:40:22 PM PDT 24
Peak memory 215104 kb
Host smart-96a3f14d-e75a-4944-836a-eb10b2be6e1e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35918816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.35918816
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.4132736428
Short name T72
Test name
Test status
Simulation time 2808141803 ps
CPU time 15.89 seconds
Started Apr 15 01:20:03 PM PDT 24
Finished Apr 15 01:20:19 PM PDT 24
Peak memory 227288 kb
Host smart-c3b61083-69ee-453b-bfd2-828a1f487b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132736428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.4132736428
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.3810701981
Short name T100
Test name
Test status
Simulation time 10103829520 ps
CPU time 51.84 seconds
Started Apr 15 01:21:09 PM PDT 24
Finished Apr 15 01:22:01 PM PDT 24
Peak memory 216212 kb
Host smart-a1ead9d0-4611-49e7-8008-a8e5e1ce8c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810701981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.3810701981
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.3635356499
Short name T31
Test name
Test status
Simulation time 40125142 ps
CPU time 0.77 seconds
Started Apr 15 01:18:37 PM PDT 24
Finished Apr 15 01:18:39 PM PDT 24
Peak memory 205416 kb
Host smart-09d9ccf3-070d-4615-9413-d0e3cebae14d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635356499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.3
635356499
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_intercept.689865560
Short name T92
Test name
Test status
Simulation time 1423029820 ps
CPU time 7.91 seconds
Started Apr 15 01:21:09 PM PDT 24
Finished Apr 15 01:21:18 PM PDT 24
Peak memory 218448 kb
Host smart-d37b798b-be62-46af-a256-7242fa22586a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689865560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.689865560
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_upload.504641855
Short name T162
Test name
Test status
Simulation time 71274422010 ps
CPU time 56.49 seconds
Started Apr 15 01:21:11 PM PDT 24
Finished Apr 15 01:22:08 PM PDT 24
Peak memory 235132 kb
Host smart-35470529-f1aa-4e27-9ee5-7b3ca4933e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504641855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.504641855
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2459319587
Short name T131
Test name
Test status
Simulation time 65455679 ps
CPU time 2.06 seconds
Started Apr 15 12:40:17 PM PDT 24
Finished Apr 15 12:40:20 PM PDT 24
Peak memory 215068 kb
Host smart-d1382b10-8a5f-4d84-bdf5-5f93bb6ebd3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459319587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
2459319587
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.3758640587
Short name T208
Test name
Test status
Simulation time 11954427743 ps
CPU time 28.09 seconds
Started Apr 15 01:18:56 PM PDT 24
Finished Apr 15 01:19:25 PM PDT 24
Peak memory 223332 kb
Host smart-ded9a5c6-bee9-4824-bbd2-e0c6f1ec1d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758640587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.3758640587
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.1384727749
Short name T67
Test name
Test status
Simulation time 16621503239 ps
CPU time 10.17 seconds
Started Apr 15 01:19:22 PM PDT 24
Finished Apr 15 01:19:33 PM PDT 24
Peak memory 222820 kb
Host smart-bef7c949-8b1a-4ff4-8bd1-c1196bb0b9f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384727749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.1384727749
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.4292219463
Short name T215
Test name
Test status
Simulation time 3321288685 ps
CPU time 32.47 seconds
Started Apr 15 01:19:14 PM PDT 24
Finished Apr 15 01:19:47 PM PDT 24
Peak memory 217944 kb
Host smart-3d5058e3-731f-42e9-aeb6-91dae5f915f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292219463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.4292219463
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.1010606493
Short name T346
Test name
Test status
Simulation time 9415141214 ps
CPU time 20.26 seconds
Started Apr 15 01:21:00 PM PDT 24
Finished Apr 15 01:21:20 PM PDT 24
Peak memory 234656 kb
Host smart-f8789bc8-b284-4362-8c0f-d46e380c6de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010606493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.1010606493
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.1969283036
Short name T236
Test name
Test status
Simulation time 3083011983 ps
CPU time 12.13 seconds
Started Apr 15 01:21:25 PM PDT 24
Finished Apr 15 01:21:38 PM PDT 24
Peak memory 224052 kb
Host smart-2db47b79-52ec-49ed-a3e2-1eb2d6d38e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969283036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.1969283036
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.3973558187
Short name T172
Test name
Test status
Simulation time 1580451792 ps
CPU time 11.97 seconds
Started Apr 15 01:21:59 PM PDT 24
Finished Apr 15 01:22:11 PM PDT 24
Peak memory 230044 kb
Host smart-529d1341-b3c9-4ab6-85da-566c8430b9de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973558187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.3973558187
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.3045092202
Short name T391
Test name
Test status
Simulation time 16332483202 ps
CPU time 27.55 seconds
Started Apr 15 01:19:24 PM PDT 24
Finished Apr 15 01:19:52 PM PDT 24
Peak memory 216216 kb
Host smart-a873aca4-1b0d-4683-97fc-dbddc741d092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045092202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.3045092202
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_intercept.3733215871
Short name T270
Test name
Test status
Simulation time 12209653333 ps
CPU time 30.04 seconds
Started Apr 15 01:20:22 PM PDT 24
Finished Apr 15 01:20:52 PM PDT 24
Peak memory 232400 kb
Host smart-105fa5c6-a4b2-4318-82f7-55e88459e127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733215871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.3733215871
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_upload.715481569
Short name T78
Test name
Test status
Simulation time 8344730552 ps
CPU time 25.58 seconds
Started Apr 15 01:22:05 PM PDT 24
Finished Apr 15 01:22:31 PM PDT 24
Peak memory 229208 kb
Host smart-95082ec1-db1e-4452-be3e-4b1803d33f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715481569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.715481569
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.1049119198
Short name T231
Test name
Test status
Simulation time 4755782579 ps
CPU time 8.78 seconds
Started Apr 15 01:19:01 PM PDT 24
Finished Apr 15 01:19:10 PM PDT 24
Peak memory 219092 kb
Host smart-39fd246a-1ef0-4794-a7f0-6923047b9939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049119198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.1049119198
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.1244352082
Short name T305
Test name
Test status
Simulation time 1844952109 ps
CPU time 34.39 seconds
Started Apr 15 01:18:27 PM PDT 24
Finished Apr 15 01:19:02 PM PDT 24
Peak memory 224424 kb
Host smart-cd545624-704e-4821-b4ae-a3683fb40c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244352082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.1244352082
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.83714268
Short name T212
Test name
Test status
Simulation time 5443883712 ps
CPU time 60.56 seconds
Started Apr 15 01:18:47 PM PDT 24
Finished Apr 15 01:19:49 PM PDT 24
Peak memory 235152 kb
Host smart-300527d3-451d-4f96-ba34-f1da07f85390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83714268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.83714268
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.3398767504
Short name T339
Test name
Test status
Simulation time 17311901602 ps
CPU time 27.38 seconds
Started Apr 15 01:20:05 PM PDT 24
Finished Apr 15 01:20:33 PM PDT 24
Peak memory 239112 kb
Host smart-2d93f254-fac1-4b39-ba9c-7d0e022653c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398767504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.3398767504
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.2924091460
Short name T46
Test name
Test status
Simulation time 213417806 ps
CPU time 1.16 seconds
Started Apr 15 01:18:26 PM PDT 24
Finished Apr 15 01:18:28 PM PDT 24
Peak memory 234952 kb
Host smart-cea75431-ad40-4ee7-b7fd-c37773d99379
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924091460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.2924091460
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.2098573449
Short name T271
Test name
Test status
Simulation time 28473841493 ps
CPU time 22.27 seconds
Started Apr 15 01:21:05 PM PDT 24
Finished Apr 15 01:21:28 PM PDT 24
Peak memory 238604 kb
Host smart-00784256-8362-443f-9aaf-6d6692035781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098573449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.2098573449
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_upload.487530467
Short name T66
Test name
Test status
Simulation time 32039388971 ps
CPU time 26.09 seconds
Started Apr 15 01:21:36 PM PDT 24
Finished Apr 15 01:22:02 PM PDT 24
Peak memory 235400 kb
Host smart-974b2342-1600-4dd6-b374-c64b4654a1c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487530467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.487530467
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.232348167
Short name T184
Test name
Test status
Simulation time 1730726903 ps
CPU time 24.59 seconds
Started Apr 15 01:19:42 PM PDT 24
Finished Apr 15 01:20:07 PM PDT 24
Peak memory 238164 kb
Host smart-e6a0be32-66d2-4371-b199-721554a8c2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232348167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.232348167
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.3860864928
Short name T57
Test name
Test status
Simulation time 9773510386 ps
CPU time 19.28 seconds
Started Apr 15 01:19:51 PM PDT 24
Finished Apr 15 01:20:11 PM PDT 24
Peak memory 232388 kb
Host smart-a1f13876-4101-4a12-8566-00034139024a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860864928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.3860864928
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.2833634047
Short name T283
Test name
Test status
Simulation time 1918685424 ps
CPU time 8.38 seconds
Started Apr 15 01:20:02 PM PDT 24
Finished Apr 15 01:20:11 PM PDT 24
Peak memory 223172 kb
Host smart-0fd5f4be-fa24-4afa-afd0-bfebd634df4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833634047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.2833634047
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_intercept.3941665840
Short name T170
Test name
Test status
Simulation time 690950128 ps
CPU time 6.27 seconds
Started Apr 15 01:18:51 PM PDT 24
Finished Apr 15 01:18:58 PM PDT 24
Peak memory 218780 kb
Host smart-3043f3a3-d379-4188-b21b-1295c7da9f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941665840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.3941665840
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.1753475205
Short name T365
Test name
Test status
Simulation time 92359212 ps
CPU time 1.04 seconds
Started Apr 15 01:19:27 PM PDT 24
Finished Apr 15 01:19:29 PM PDT 24
Peak memory 207008 kb
Host smart-1fd30577-6632-482d-897a-4e83ea8d3a3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753475205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.1753475205
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.105846011
Short name T71
Test name
Test status
Simulation time 26697411006 ps
CPU time 21.82 seconds
Started Apr 15 01:20:02 PM PDT 24
Finished Apr 15 01:20:25 PM PDT 24
Peak memory 232044 kb
Host smart-86be0173-39ec-4a8d-abdb-5863f6623ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105846011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap
.105846011
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.1961572416
Short name T387
Test name
Test status
Simulation time 5608768568 ps
CPU time 22.41 seconds
Started Apr 15 01:20:15 PM PDT 24
Finished Apr 15 01:20:38 PM PDT 24
Peak memory 216312 kb
Host smart-cc2952a2-aafd-496b-a22c-54e84368ef54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961572416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.1961572416
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.692932418
Short name T177
Test name
Test status
Simulation time 9539878635 ps
CPU time 24.9 seconds
Started Apr 15 01:19:54 PM PDT 24
Finished Apr 15 01:20:19 PM PDT 24
Peak memory 216520 kb
Host smart-a09898b8-3d64-4c0d-8a8b-90598969897e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692932418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.692932418
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.903351456
Short name T309
Test name
Test status
Simulation time 5129289713 ps
CPU time 67.66 seconds
Started Apr 15 01:21:39 PM PDT 24
Finished Apr 15 01:22:47 PM PDT 24
Peak memory 240812 kb
Host smart-a8ac7a89-b38c-49a3-95e4-c85c525a7d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903351456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.903351456
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.7684962
Short name T73
Test name
Test status
Simulation time 19120381144 ps
CPU time 50.18 seconds
Started Apr 15 01:22:10 PM PDT 24
Finished Apr 15 01:23:00 PM PDT 24
Peak memory 232628 kb
Host smart-1dad9483-9e80-4354-a051-3b28be41babc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7684962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap.7684962
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_intercept.3259444240
Short name T95
Test name
Test status
Simulation time 8220634582 ps
CPU time 6.72 seconds
Started Apr 15 01:21:21 PM PDT 24
Finished Apr 15 01:21:28 PM PDT 24
Peak memory 216524 kb
Host smart-b73103c8-d2bf-4531-9cba-1bf2f63c0ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259444240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.3259444240
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.1159848805
Short name T274
Test name
Test status
Simulation time 7691554860 ps
CPU time 13.66 seconds
Started Apr 15 01:18:27 PM PDT 24
Finished Apr 15 01:18:42 PM PDT 24
Peak memory 224272 kb
Host smart-5691b8a5-4c7c-43c4-8be6-bf018aa1164f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159848805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.1159848805
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.459598680
Short name T317
Test name
Test status
Simulation time 721308642 ps
CPU time 15.67 seconds
Started Apr 15 01:19:36 PM PDT 24
Finished Apr 15 01:19:52 PM PDT 24
Peak memory 230504 kb
Host smart-6dfa5693-b8a1-4927-b2b6-f7d643b9e998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459598680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.459598680
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.1075425859
Short name T643
Test name
Test status
Simulation time 16578409463 ps
CPU time 32.75 seconds
Started Apr 15 01:20:12 PM PDT 24
Finished Apr 15 01:20:45 PM PDT 24
Peak memory 216248 kb
Host smart-3fd0fc5f-168f-4489-84cf-f2453027e24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075425859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.1075425859
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.1461068318
Short name T268
Test name
Test status
Simulation time 58398308301 ps
CPU time 21.37 seconds
Started Apr 15 01:20:35 PM PDT 24
Finished Apr 15 01:20:57 PM PDT 24
Peak memory 232264 kb
Host smart-f2edd718-020d-484e-b8fc-9fa5ab68acaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461068318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.1461068318
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_intercept.2366197352
Short name T234
Test name
Test status
Simulation time 1053916352 ps
CPU time 6.75 seconds
Started Apr 15 01:21:25 PM PDT 24
Finished Apr 15 01:21:32 PM PDT 24
Peak memory 223880 kb
Host smart-5354acf8-6c0b-49d7-b103-b076102c5268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366197352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.2366197352
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.1160789227
Short name T265
Test name
Test status
Simulation time 1330880898 ps
CPU time 7.5 seconds
Started Apr 15 01:21:27 PM PDT 24
Finished Apr 15 01:21:35 PM PDT 24
Peak memory 216728 kb
Host smart-631d2f87-4970-45a2-bc77-7b8ce38c8f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160789227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1160789227
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_intercept.3147106776
Short name T292
Test name
Test status
Simulation time 4391099812 ps
CPU time 24.07 seconds
Started Apr 15 01:22:09 PM PDT 24
Finished Apr 15 01:22:33 PM PDT 24
Peak memory 222764 kb
Host smart-dc7d7e59-174e-4182-8145-5b9f835a1c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147106776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.3147106776
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.2315036831
Short name T83
Test name
Test status
Simulation time 16414528981 ps
CPU time 77.42 seconds
Started Apr 15 01:18:34 PM PDT 24
Finished Apr 15 01:19:52 PM PDT 24
Peak memory 240792 kb
Host smart-86ad2f66-2c75-42d0-af66-4d2c6bfd3e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315036831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.2315036831
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.2901441484
Short name T347
Test name
Test status
Simulation time 2698909844 ps
CPU time 10.96 seconds
Started Apr 15 01:19:24 PM PDT 24
Finished Apr 15 01:19:35 PM PDT 24
Peak memory 223328 kb
Host smart-3731da53-4616-4402-a3ca-8bec82932b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901441484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.2901441484
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.1678990483
Short name T239
Test name
Test status
Simulation time 790028502 ps
CPU time 15.24 seconds
Started Apr 15 01:18:37 PM PDT 24
Finished Apr 15 01:18:52 PM PDT 24
Peak memory 235056 kb
Host smart-f35b0522-4ea5-4d80-b7f0-c5fe2314b2b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678990483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.1678990483
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.1588702737
Short name T101
Test name
Test status
Simulation time 19151829929 ps
CPU time 19.15 seconds
Started Apr 15 01:20:11 PM PDT 24
Finished Apr 15 01:20:31 PM PDT 24
Peak memory 216276 kb
Host smart-ffb4e770-a34a-4dd9-a299-b978c58c828e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588702737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.1588702737
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_intercept.2948499178
Short name T94
Test name
Test status
Simulation time 6620452189 ps
CPU time 16.3 seconds
Started Apr 15 01:18:47 PM PDT 24
Finished Apr 15 01:19:04 PM PDT 24
Peak memory 232524 kb
Host smart-82a2106f-078d-4fbe-8a3c-a6ba94fb1ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948499178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.2948499178
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.2571579389
Short name T76
Test name
Test status
Simulation time 831674711 ps
CPU time 8.73 seconds
Started Apr 15 01:18:50 PM PDT 24
Finished Apr 15 01:19:00 PM PDT 24
Peak memory 218380 kb
Host smart-e93ecc14-1e23-41f7-a825-aaaa9a0c067b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571579389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2571579389
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.123452095
Short name T3
Test name
Test status
Simulation time 347074236 ps
CPU time 1.38 seconds
Started Apr 15 01:20:00 PM PDT 24
Finished Apr 15 01:20:02 PM PDT 24
Peak memory 215956 kb
Host smart-b0fac785-0029-45cd-ae73-50d53d12d27f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123452095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.123452095
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.2135085870
Short name T75
Test name
Test status
Simulation time 587746898 ps
CPU time 3.64 seconds
Started Apr 15 01:18:56 PM PDT 24
Finished Apr 15 01:19:01 PM PDT 24
Peak memory 218352 kb
Host smart-f41a9442-db8a-401d-bda9-7d2420bbf92c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135085870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.2135085870
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.2369850074
Short name T64
Test name
Test status
Simulation time 62479457 ps
CPU time 2.65 seconds
Started Apr 15 01:19:06 PM PDT 24
Finished Apr 15 01:19:09 PM PDT 24
Peak memory 218536 kb
Host smart-8dde6b91-ad7b-4855-9696-96ba6a06ac87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369850074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.2369850074
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.3366102495
Short name T379
Test name
Test status
Simulation time 3535935669 ps
CPU time 23.17 seconds
Started Apr 15 01:19:20 PM PDT 24
Finished Apr 15 01:19:44 PM PDT 24
Peak memory 216324 kb
Host smart-15b480b9-41ab-49a1-9a81-a878e2a3f36c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366102495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.3366102495
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.3395680924
Short name T235
Test name
Test status
Simulation time 14751334311 ps
CPU time 12.84 seconds
Started Apr 15 01:18:37 PM PDT 24
Finished Apr 15 01:18:50 PM PDT 24
Peak memory 226972 kb
Host smart-98153c90-4add-4ab8-b200-454e64bd1ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395680924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.3395680924
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_intercept.2826607474
Short name T79
Test name
Test status
Simulation time 8261577516 ps
CPU time 14.39 seconds
Started Apr 15 01:19:42 PM PDT 24
Finished Apr 15 01:19:57 PM PDT 24
Peak memory 222424 kb
Host smart-999cee68-ab4f-4bb1-b364-7b9621f3ebe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826607474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.2826607474
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_intercept.1056746408
Short name T352
Test name
Test status
Simulation time 14626698340 ps
CPU time 30.13 seconds
Started Apr 15 01:19:50 PM PDT 24
Finished Apr 15 01:20:21 PM PDT 24
Peak memory 218844 kb
Host smart-0cbc76d8-3a76-42be-b3c4-ab0ac6ff8552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056746408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.1056746408
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_intercept.193711942
Short name T278
Test name
Test status
Simulation time 4677773291 ps
CPU time 12.73 seconds
Started Apr 15 01:20:28 PM PDT 24
Finished Apr 15 01:20:41 PM PDT 24
Peak memory 223840 kb
Host smart-d3c39107-ac93-4f82-8bfa-47c0c549d579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193711942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.193711942
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.2702688759
Short name T281
Test name
Test status
Simulation time 54075360521 ps
CPU time 22.38 seconds
Started Apr 15 01:21:05 PM PDT 24
Finished Apr 15 01:21:27 PM PDT 24
Peak memory 224272 kb
Host smart-8eabbc59-86a9-45ce-8477-904b37830a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702688759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.2702688759
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.2315923510
Short name T261
Test name
Test status
Simulation time 28443262121 ps
CPU time 17.78 seconds
Started Apr 15 01:21:39 PM PDT 24
Finished Apr 15 01:21:58 PM PDT 24
Peak memory 238220 kb
Host smart-3077b998-2941-4566-86aa-f69798fb1e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315923510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.2315923510
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.1534862346
Short name T245
Test name
Test status
Simulation time 392934055 ps
CPU time 6.08 seconds
Started Apr 15 01:18:46 PM PDT 24
Finished Apr 15 01:18:53 PM PDT 24
Peak memory 221520 kb
Host smart-478a31fe-f14f-424d-bb53-14eb02ffe58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534862346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.1534862346
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_intercept.2755115161
Short name T8
Test name
Test status
Simulation time 1950293510 ps
CPU time 3.16 seconds
Started Apr 15 01:18:37 PM PDT 24
Finished Apr 15 01:18:41 PM PDT 24
Peak memory 218312 kb
Host smart-94266cef-b390-411b-8c4e-c6cd6a294430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755115161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.2755115161
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1921695745
Short name T118
Test name
Test status
Simulation time 92235514 ps
CPU time 3.57 seconds
Started Apr 15 12:40:29 PM PDT 24
Finished Apr 15 12:40:33 PM PDT 24
Peak memory 216256 kb
Host smart-bf489f8b-ff48-4d24-8fb6-acea90663bc8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921695745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
1921695745
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.4024595408
Short name T38
Test name
Test status
Simulation time 808611205 ps
CPU time 20.26 seconds
Started Apr 15 12:40:15 PM PDT 24
Finished Apr 15 12:40:36 PM PDT 24
Peak memory 214992 kb
Host smart-99eefd1f-290d-47a2-bc10-ed834dcd6eb4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024595408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.4024595408
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.2713914936
Short name T179
Test name
Test status
Simulation time 186263495 ps
CPU time 5.91 seconds
Started Apr 15 01:18:29 PM PDT 24
Finished Apr 15 01:18:35 PM PDT 24
Peak memory 223588 kb
Host smart-7522bc68-8996-491d-bc3b-c5327ad39c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713914936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.2713914936
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_intercept.3233698846
Short name T290
Test name
Test status
Simulation time 545291109 ps
CPU time 6.33 seconds
Started Apr 15 01:18:59 PM PDT 24
Finished Apr 15 01:19:06 PM PDT 24
Peak memory 218604 kb
Host smart-c16c5594-fb89-498d-98fb-4a627da89e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233698846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.3233698846
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.390523169
Short name T228
Test name
Test status
Simulation time 3276297715 ps
CPU time 5.26 seconds
Started Apr 15 01:19:17 PM PDT 24
Finished Apr 15 01:19:23 PM PDT 24
Peak memory 218988 kb
Host smart-6c3526e3-4738-497b-b636-bf36f18b85de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390523169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap
.390523169
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.1944419188
Short name T267
Test name
Test status
Simulation time 1661165665 ps
CPU time 19.33 seconds
Started Apr 15 01:19:20 PM PDT 24
Finished Apr 15 01:19:40 PM PDT 24
Peak memory 216752 kb
Host smart-2bceeaf5-c1d6-4627-b253-60f169ff6a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944419188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.1944419188
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_intercept.370915226
Short name T349
Test name
Test status
Simulation time 300252823 ps
CPU time 4.91 seconds
Started Apr 15 01:19:26 PM PDT 24
Finished Apr 15 01:19:31 PM PDT 24
Peak memory 232268 kb
Host smart-ec2386ea-a187-448f-a280-0dacd288485f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370915226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.370915226
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.3769753464
Short name T301
Test name
Test status
Simulation time 935253969 ps
CPU time 18.57 seconds
Started Apr 15 01:19:34 PM PDT 24
Finished Apr 15 01:19:54 PM PDT 24
Peak memory 248980 kb
Host smart-686d922d-5d0d-4b20-9133-60c2f52d04a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769753464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.3769753464
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.1524139533
Short name T252
Test name
Test status
Simulation time 318506629 ps
CPU time 3.53 seconds
Started Apr 15 01:19:37 PM PDT 24
Finished Apr 15 01:19:41 PM PDT 24
Peak memory 222728 kb
Host smart-55f22f9e-dab6-4cf8-a3d9-c4f42128d14a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524139533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.1524139533
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.878795502
Short name T197
Test name
Test status
Simulation time 3604756293 ps
CPU time 9.17 seconds
Started Apr 15 01:19:28 PM PDT 24
Finished Apr 15 01:19:38 PM PDT 24
Peak memory 236948 kb
Host smart-295827ad-058b-4702-93c4-e54ab6ba7128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878795502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.878795502
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.1970707026
Short name T4
Test name
Test status
Simulation time 5858670881 ps
CPU time 21.21 seconds
Started Apr 15 01:19:37 PM PDT 24
Finished Apr 15 01:19:58 PM PDT 24
Peak memory 233968 kb
Host smart-be742ca6-94f6-4e19-8b09-0be51d534d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970707026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.1970707026
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.3589270959
Short name T89
Test name
Test status
Simulation time 80659421188 ps
CPU time 109.7 seconds
Started Apr 15 01:20:16 PM PDT 24
Finished Apr 15 01:22:06 PM PDT 24
Peak memory 234864 kb
Host smart-fa92abc5-4004-4612-90bd-ca1a3a888dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589270959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.3589270959
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.3862710494
Short name T232
Test name
Test status
Simulation time 6018466686 ps
CPU time 9.04 seconds
Started Apr 15 01:20:01 PM PDT 24
Finished Apr 15 01:20:11 PM PDT 24
Peak memory 220784 kb
Host smart-7c6195f0-92ec-4da8-a5ff-86d210c4f2d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862710494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.3862710494
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_intercept.2121698296
Short name T351
Test name
Test status
Simulation time 3479869064 ps
CPU time 36.92 seconds
Started Apr 15 01:20:01 PM PDT 24
Finished Apr 15 01:20:38 PM PDT 24
Peak memory 218768 kb
Host smart-cb0be45d-9db6-454c-97e5-af084e2c1b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121698296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.2121698296
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.1940779720
Short name T202
Test name
Test status
Simulation time 23910992962 ps
CPU time 13.49 seconds
Started Apr 15 01:20:20 PM PDT 24
Finished Apr 15 01:20:34 PM PDT 24
Peak memory 222896 kb
Host smart-8cb65aee-7c33-45d4-96ff-fce1d080fd59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940779720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.1940779720
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.236513028
Short name T209
Test name
Test status
Simulation time 209630336 ps
CPU time 2.88 seconds
Started Apr 15 01:20:13 PM PDT 24
Finished Apr 15 01:20:17 PM PDT 24
Peak memory 222804 kb
Host smart-472da0d6-269f-46c7-99c3-67b2ef9da0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236513028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap
.236513028
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.2422066161
Short name T74
Test name
Test status
Simulation time 1937615234 ps
CPU time 4.34 seconds
Started Apr 15 01:20:22 PM PDT 24
Finished Apr 15 01:20:26 PM PDT 24
Peak memory 218636 kb
Host smart-25635786-5ed1-45c5-8955-cb3621921e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422066161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.2422066161
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.3481358800
Short name T207
Test name
Test status
Simulation time 1568609235 ps
CPU time 3.58 seconds
Started Apr 15 01:20:29 PM PDT 24
Finished Apr 15 01:20:33 PM PDT 24
Peak memory 218436 kb
Host smart-998782a5-01b1-4cfb-92c8-42ccbb59426f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481358800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.3481358800
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.1725110255
Short name T65
Test name
Test status
Simulation time 17164638926 ps
CPU time 25.17 seconds
Started Apr 15 01:20:46 PM PDT 24
Finished Apr 15 01:21:12 PM PDT 24
Peak memory 224048 kb
Host smart-0c279f17-8337-4843-87b3-2523c55b3954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725110255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.1725110255
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.1888425380
Short name T298
Test name
Test status
Simulation time 8074441841 ps
CPU time 98.77 seconds
Started Apr 15 01:21:03 PM PDT 24
Finished Apr 15 01:22:43 PM PDT 24
Peak memory 250820 kb
Host smart-e7c8b414-a22c-44fc-9f4b-7c6b9ec7628a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888425380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.1888425380
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.4110744255
Short name T272
Test name
Test status
Simulation time 17073318567 ps
CPU time 49.57 seconds
Started Apr 15 01:21:06 PM PDT 24
Finished Apr 15 01:21:56 PM PDT 24
Peak memory 233200 kb
Host smart-535341fc-593a-4c05-8224-3589362b7b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110744255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.4110744255
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.3813398235
Short name T255
Test name
Test status
Simulation time 6740358918 ps
CPU time 56.49 seconds
Started Apr 15 01:21:19 PM PDT 24
Finished Apr 15 01:22:16 PM PDT 24
Peak memory 220908 kb
Host smart-c47e8666-108d-49ad-9dce-a400998e3638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813398235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.3813398235
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.1100704534
Short name T203
Test name
Test status
Simulation time 1769774731 ps
CPU time 20.67 seconds
Started Apr 15 01:21:34 PM PDT 24
Finished Apr 15 01:21:56 PM PDT 24
Peak memory 224180 kb
Host smart-f2385cca-7c32-4286-be9d-d1e2a9f933de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100704534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.1100704534
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_intercept.2913987728
Short name T256
Test name
Test status
Simulation time 1059324396 ps
CPU time 5.48 seconds
Started Apr 15 01:21:39 PM PDT 24
Finished Apr 15 01:21:45 PM PDT 24
Peak memory 223032 kb
Host smart-ab55e891-f493-4f9e-95b0-8427131e023a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913987728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.2913987728
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.462755020
Short name T294
Test name
Test status
Simulation time 1863520618 ps
CPU time 14.48 seconds
Started Apr 15 01:21:40 PM PDT 24
Finished Apr 15 01:21:55 PM PDT 24
Peak memory 240700 kb
Host smart-04bdb6c3-3592-4d94-b61f-0143fddc3b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462755020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap
.462755020
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_intercept.3211847247
Short name T248
Test name
Test status
Simulation time 284892439 ps
CPU time 6.44 seconds
Started Apr 15 01:21:42 PM PDT 24
Finished Apr 15 01:21:49 PM PDT 24
Peak memory 218460 kb
Host smart-805c157e-70ad-4762-83ce-51ca17d8127f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211847247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.3211847247
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_upload.125377103
Short name T331
Test name
Test status
Simulation time 587286245 ps
CPU time 4.2 seconds
Started Apr 15 01:18:41 PM PDT 24
Finished Apr 15 01:18:46 PM PDT 24
Peak memory 218644 kb
Host smart-b321363c-c328-4e00-a412-9838b2c5899b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125377103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.125377103
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.1469381088
Short name T88
Test name
Test status
Simulation time 2937561419 ps
CPU time 11.99 seconds
Started Apr 15 01:21:48 PM PDT 24
Finished Apr 15 01:22:01 PM PDT 24
Peak memory 222068 kb
Host smart-864d2c6b-da07-4929-ae0a-7c7d3921ec80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469381088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.1469381088
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.2727494319
Short name T273
Test name
Test status
Simulation time 781625035 ps
CPU time 6.5 seconds
Started Apr 15 01:19:01 PM PDT 24
Finished Apr 15 01:19:08 PM PDT 24
Peak memory 222904 kb
Host smart-2f828168-7aef-49ef-9b0c-55641df33a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727494319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.2727494319
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.978528165
Short name T293
Test name
Test status
Simulation time 640849838 ps
CPU time 14.36 seconds
Started Apr 15 01:19:04 PM PDT 24
Finished Apr 15 01:19:19 PM PDT 24
Peak memory 233684 kb
Host smart-8b0bf5e5-ba50-41a1-92b4-e21cb9e60b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978528165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.978528165
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.560073118
Short name T276
Test name
Test status
Simulation time 13082341749 ps
CPU time 25.26 seconds
Started Apr 15 01:19:13 PM PDT 24
Finished Apr 15 01:19:39 PM PDT 24
Peak memory 218556 kb
Host smart-73fff3fd-c813-4e0c-9f1d-7c62bbceb03a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560073118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.560073118
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.2950303981
Short name T337
Test name
Test status
Simulation time 2385521394 ps
CPU time 9.09 seconds
Started Apr 15 01:19:14 PM PDT 24
Finished Apr 15 01:19:23 PM PDT 24
Peak memory 220820 kb
Host smart-87148623-8ddf-4187-8c51-350632730d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950303981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.2950303981
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.4222142648
Short name T360
Test name
Test status
Simulation time 849925191 ps
CPU time 4.77 seconds
Started Apr 15 01:19:11 PM PDT 24
Finished Apr 15 01:19:16 PM PDT 24
Peak memory 222536 kb
Host smart-f6a3064d-baff-494f-9347-ed214055a325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222142648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.4222142648
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.271209827
Short name T321
Test name
Test status
Simulation time 2437813724 ps
CPU time 11.92 seconds
Started Apr 15 01:19:17 PM PDT 24
Finished Apr 15 01:19:30 PM PDT 24
Peak memory 225752 kb
Host smart-cc2eaa37-a42f-4f8b-95eb-9fb03274654f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271209827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.271209827
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_upload.2931855825
Short name T69
Test name
Test status
Simulation time 1269489880 ps
CPU time 7.51 seconds
Started Apr 15 01:19:22 PM PDT 24
Finished Apr 15 01:19:30 PM PDT 24
Peak memory 219336 kb
Host smart-b377fb38-cd9b-4f37-9178-5f951ab3d3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931855825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.2931855825
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_intercept.1079961198
Short name T186
Test name
Test status
Simulation time 285455110 ps
CPU time 3.67 seconds
Started Apr 15 01:19:30 PM PDT 24
Finished Apr 15 01:19:34 PM PDT 24
Peak memory 222508 kb
Host smart-1f15ec72-6055-48cb-93bd-d96c31e5eb95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079961198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.1079961198
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.2045835597
Short name T189
Test name
Test status
Simulation time 337027743 ps
CPU time 4.23 seconds
Started Apr 15 01:19:27 PM PDT 24
Finished Apr 15 01:19:32 PM PDT 24
Peak memory 232368 kb
Host smart-11d74a91-112c-4d22-92da-3b6a38e81821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045835597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.2045835597
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.2795322296
Short name T327
Test name
Test status
Simulation time 1495098188 ps
CPU time 4.56 seconds
Started Apr 15 01:19:34 PM PDT 24
Finished Apr 15 01:19:39 PM PDT 24
Peak memory 222332 kb
Host smart-3fd83127-f261-4f07-ae03-c6106e0f4de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795322296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.2795322296
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.600253097
Short name T251
Test name
Test status
Simulation time 8301179752 ps
CPU time 7.91 seconds
Started Apr 15 01:19:33 PM PDT 24
Finished Apr 15 01:19:42 PM PDT 24
Peak memory 218788 kb
Host smart-65615f52-fc91-4ff5-8fcd-7492f93feaf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600253097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap
.600253097
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.1341829720
Short name T218
Test name
Test status
Simulation time 1613409421 ps
CPU time 6.8 seconds
Started Apr 15 01:19:32 PM PDT 24
Finished Apr 15 01:19:39 PM PDT 24
Peak memory 218932 kb
Host smart-4622963f-3c49-4b8b-8486-1a3962b0f7d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341829720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.1341829720
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_intercept.3019256271
Short name T193
Test name
Test status
Simulation time 2502566373 ps
CPU time 29.36 seconds
Started Apr 15 01:18:39 PM PDT 24
Finished Apr 15 01:19:09 PM PDT 24
Peak memory 222544 kb
Host smart-53a8a8c2-1107-4349-9620-3032ad6137ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019256271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.3019256271
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.1654716817
Short name T55
Test name
Test status
Simulation time 8905759572 ps
CPU time 13.46 seconds
Started Apr 15 01:19:41 PM PDT 24
Finished Apr 15 01:19:56 PM PDT 24
Peak memory 238880 kb
Host smart-792571cd-4973-4cae-ba28-c56540d633a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654716817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.1654716817
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.3668342212
Short name T340
Test name
Test status
Simulation time 10237012145 ps
CPU time 12.76 seconds
Started Apr 15 01:19:51 PM PDT 24
Finished Apr 15 01:20:04 PM PDT 24
Peak memory 234720 kb
Host smart-05b52fdc-581b-43e2-8f4f-477d54c6fac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668342212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.3668342212
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_upload.2172501474
Short name T246
Test name
Test status
Simulation time 981042152 ps
CPU time 4.82 seconds
Started Apr 15 01:19:50 PM PDT 24
Finished Apr 15 01:19:55 PM PDT 24
Peak memory 223292 kb
Host smart-d4a463e7-b1ef-4572-b992-499506d52358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172501474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.2172501474
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.3696549848
Short name T176
Test name
Test status
Simulation time 593034450 ps
CPU time 4.46 seconds
Started Apr 15 01:19:59 PM PDT 24
Finished Apr 15 01:20:04 PM PDT 24
Peak memory 223372 kb
Host smart-e6f5265f-3b80-4b37-a921-49b568c6a9dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696549848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.3696549848
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.483949709
Short name T262
Test name
Test status
Simulation time 3503233704 ps
CPU time 33.69 seconds
Started Apr 15 01:20:01 PM PDT 24
Finished Apr 15 01:20:36 PM PDT 24
Peak memory 223636 kb
Host smart-38e7d1e0-619b-49bb-9632-cc624a515762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483949709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.483949709
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.161966289
Short name T343
Test name
Test status
Simulation time 1927482555 ps
CPU time 6.11 seconds
Started Apr 15 01:20:07 PM PDT 24
Finished Apr 15 01:20:13 PM PDT 24
Peak memory 232428 kb
Host smart-421bb0b9-70d2-45e0-b979-e4a87b4a80f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161966289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap
.161966289
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.3337827987
Short name T304
Test name
Test status
Simulation time 650555281 ps
CPU time 11.74 seconds
Started Apr 15 01:20:20 PM PDT 24
Finished Apr 15 01:20:33 PM PDT 24
Peak memory 249248 kb
Host smart-a9fbcf8a-2958-4cb8-9a88-1ad9026dbbf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337827987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.3337827987
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.3525154382
Short name T348
Test name
Test status
Simulation time 163024352 ps
CPU time 3.44 seconds
Started Apr 15 01:20:27 PM PDT 24
Finished Apr 15 01:20:31 PM PDT 24
Peak memory 222796 kb
Host smart-3db963cb-6b50-4344-bb87-4af7f700f39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525154382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.3525154382
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.3014009482
Short name T219
Test name
Test status
Simulation time 2489622046 ps
CPU time 9.1 seconds
Started Apr 15 01:20:39 PM PDT 24
Finished Apr 15 01:20:48 PM PDT 24
Peak memory 221492 kb
Host smart-d413ce7f-5325-400f-90a3-2e0194adaf2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014009482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.3014009482
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_upload.198334530
Short name T205
Test name
Test status
Simulation time 1107140240 ps
CPU time 5.47 seconds
Started Apr 15 01:20:43 PM PDT 24
Finished Apr 15 01:20:48 PM PDT 24
Peak memory 216380 kb
Host smart-96798f97-7707-457f-90d3-625dcccce0c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198334530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.198334530
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.3170256541
Short name T280
Test name
Test status
Simulation time 1322651356 ps
CPU time 5.63 seconds
Started Apr 15 01:20:54 PM PDT 24
Finished Apr 15 01:21:00 PM PDT 24
Peak memory 222928 kb
Host smart-24201c5d-b12b-4587-9bb7-b1dfaf39964e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170256541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.3170256541
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.2594305281
Short name T90
Test name
Test status
Simulation time 1686237635 ps
CPU time 8.59 seconds
Started Apr 15 01:20:59 PM PDT 24
Finished Apr 15 01:21:08 PM PDT 24
Peak memory 233884 kb
Host smart-d7c4f6c7-ec78-4781-af5e-82b4eddd2a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594305281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.2594305281
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.4029918891
Short name T345
Test name
Test status
Simulation time 282144395 ps
CPU time 2.61 seconds
Started Apr 15 01:21:09 PM PDT 24
Finished Apr 15 01:21:12 PM PDT 24
Peak memory 219460 kb
Host smart-efbc616e-e0e3-4d6f-8a89-fee85d581ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029918891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.4029918891
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.3848098704
Short name T287
Test name
Test status
Simulation time 2061968290 ps
CPU time 8.42 seconds
Started Apr 15 01:21:08 PM PDT 24
Finished Apr 15 01:21:17 PM PDT 24
Peak memory 223948 kb
Host smart-f435f04f-a5dd-4ad6-81b7-e9c50c79e03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848098704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.3848098704
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.2909029924
Short name T70
Test name
Test status
Simulation time 78496529242 ps
CPU time 35.4 seconds
Started Apr 15 01:21:11 PM PDT 24
Finished Apr 15 01:21:47 PM PDT 24
Peak memory 239072 kb
Host smart-51f77080-b9f0-419d-bf08-b5269c090582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909029924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.2909029924
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.64394878
Short name T173
Test name
Test status
Simulation time 4113128259 ps
CPU time 7.85 seconds
Started Apr 15 01:21:11 PM PDT 24
Finished Apr 15 01:21:20 PM PDT 24
Peak memory 221748 kb
Host smart-f4a0f77b-5c3d-4804-b0eb-b5a6c85a5b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64394878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.64394878
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.922718942
Short name T182
Test name
Test status
Simulation time 2565334855 ps
CPU time 5.78 seconds
Started Apr 15 01:18:41 PM PDT 24
Finished Apr 15 01:18:48 PM PDT 24
Peak memory 223284 kb
Host smart-94ca633d-4dbb-4e57-b795-cb95c0f61657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922718942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.
922718942
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_upload.2499840000
Short name T9
Test name
Test status
Simulation time 508198536 ps
CPU time 5.08 seconds
Started Apr 15 01:18:41 PM PDT 24
Finished Apr 15 01:18:47 PM PDT 24
Peak memory 222188 kb
Host smart-ff92b8de-3ee8-449e-93dc-00c113f448de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499840000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.2499840000
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_upload.1796751356
Short name T279
Test name
Test status
Simulation time 241212557 ps
CPU time 4.87 seconds
Started Apr 15 01:21:21 PM PDT 24
Finished Apr 15 01:21:26 PM PDT 24
Peak memory 219236 kb
Host smart-f3972426-5a76-42c3-a42e-a4b7c63789eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796751356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.1796751356
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.1788820992
Short name T249
Test name
Test status
Simulation time 27086042095 ps
CPU time 10.18 seconds
Started Apr 15 01:21:27 PM PDT 24
Finished Apr 15 01:21:38 PM PDT 24
Peak memory 218744 kb
Host smart-0e717473-3a06-44e9-b7e5-d9061bb2ff9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788820992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.1788820992
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.3422060619
Short name T275
Test name
Test status
Simulation time 601171177 ps
CPU time 5.47 seconds
Started Apr 15 01:21:40 PM PDT 24
Finished Apr 15 01:21:46 PM PDT 24
Peak memory 222864 kb
Host smart-f58de8f8-00e2-4bad-98f6-df6f903a91ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422060619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.3422060619
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.633889013
Short name T214
Test name
Test status
Simulation time 1336711901 ps
CPU time 6.29 seconds
Started Apr 15 01:21:51 PM PDT 24
Finished Apr 15 01:21:58 PM PDT 24
Peak memory 222404 kb
Host smart-5b6c9bbb-0f21-468d-a4ec-e152cb165ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633889013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap
.633889013
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.4173072171
Short name T161
Test name
Test status
Simulation time 2298667599 ps
CPU time 46.46 seconds
Started Apr 15 01:21:57 PM PDT 24
Finished Apr 15 01:22:44 PM PDT 24
Peak memory 248872 kb
Host smart-65d74923-b3de-4a6d-95c7-66681ad624ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173072171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.4173072171
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.904827472
Short name T206
Test name
Test status
Simulation time 431769989 ps
CPU time 4.36 seconds
Started Apr 15 01:22:04 PM PDT 24
Finished Apr 15 01:22:09 PM PDT 24
Peak memory 222260 kb
Host smart-c14f8cc1-a14c-4169-9767-205e8f5bf532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904827472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap
.904827472
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_intercept.206554870
Short name T269
Test name
Test status
Simulation time 257598140 ps
CPU time 5.05 seconds
Started Apr 15 01:18:49 PM PDT 24
Finished Apr 15 01:18:55 PM PDT 24
Peak memory 218772 kb
Host smart-b587183e-fa39-4c78-9632-ecf2d66e0b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206554870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.206554870
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.194597441
Short name T168
Test name
Test status
Simulation time 12312057752 ps
CPU time 37.56 seconds
Started Apr 15 01:18:47 PM PDT 24
Finished Apr 15 01:19:25 PM PDT 24
Peak memory 223152 kb
Host smart-5551fcf2-bd23-4f8b-81cc-210d6d712116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194597441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.194597441
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.1900079752
Short name T244
Test name
Test status
Simulation time 994069127 ps
CPU time 5.09 seconds
Started Apr 15 01:18:55 PM PDT 24
Finished Apr 15 01:19:01 PM PDT 24
Peak memory 216600 kb
Host smart-b6e22fbc-2f8a-4493-9b01-e26e065a5a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900079752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.1900079752
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.2432055912
Short name T407
Test name
Test status
Simulation time 37869160 ps
CPU time 0.76 seconds
Started Apr 15 01:18:25 PM PDT 24
Finished Apr 15 01:18:27 PM PDT 24
Peak memory 205460 kb
Host smart-f5b44245-ec39-488b-89eb-f5777d316110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432055912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.2432055912
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1136884670
Short name T127
Test name
Test status
Simulation time 448731177 ps
CPU time 4.28 seconds
Started Apr 15 12:40:22 PM PDT 24
Finished Apr 15 12:40:27 PM PDT 24
Peak memory 215192 kb
Host smart-a63b9bc2-bebd-4d2a-bb02-254c61b1d03e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136884670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.1
136884670
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.21926805
Short name T96
Test name
Test status
Simulation time 93687216 ps
CPU time 1.15 seconds
Started Apr 15 12:40:24 PM PDT 24
Finished Apr 15 12:40:26 PM PDT 24
Peak memory 206844 kb
Host smart-9a455004-04d9-4a27-835a-b7b0d09fe6b3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21926805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_
hw_reset.21926805
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1690622920
Short name T831
Test name
Test status
Simulation time 406616259 ps
CPU time 8.23 seconds
Started Apr 15 12:40:15 PM PDT 24
Finished Apr 15 12:40:25 PM PDT 24
Peak memory 206880 kb
Host smart-90b6e0b9-c749-4ed0-a51c-e06b5e24e605
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690622920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.1690622920
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2842796173
Short name T140
Test name
Test status
Simulation time 1891095600 ps
CPU time 37.45 seconds
Started Apr 15 12:40:30 PM PDT 24
Finished Apr 15 12:41:08 PM PDT 24
Peak memory 206844 kb
Host smart-4a274f06-083b-4fc3-84fe-7a8b39a76d11
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842796173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.2842796173
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.553138116
Short name T819
Test name
Test status
Simulation time 93488995 ps
CPU time 1.66 seconds
Started Apr 15 12:40:16 PM PDT 24
Finished Apr 15 12:40:19 PM PDT 24
Peak memory 215204 kb
Host smart-d3f50afe-f4e6-44c6-a4e9-ec69847d15ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553138116 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.553138116
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1526222113
Short name T752
Test name
Test status
Simulation time 356195538 ps
CPU time 2.04 seconds
Started Apr 15 12:40:31 PM PDT 24
Finished Apr 15 12:40:33 PM PDT 24
Peak memory 215060 kb
Host smart-2e45d299-f3fd-44af-983d-a093c5d5572b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526222113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.1
526222113
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.4229364878
Short name T726
Test name
Test status
Simulation time 12669181 ps
CPU time 0.7 seconds
Started Apr 15 12:40:26 PM PDT 24
Finished Apr 15 12:40:27 PM PDT 24
Peak memory 203492 kb
Host smart-0d075cb7-dd89-481a-8d30-8dd134480038
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229364878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.4
229364878
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3430785505
Short name T759
Test name
Test status
Simulation time 32218020 ps
CPU time 1.31 seconds
Started Apr 15 12:40:14 PM PDT 24
Finished Apr 15 12:40:16 PM PDT 24
Peak memory 215104 kb
Host smart-4c470690-c7bb-4f5a-ba7b-5a9ee45a6602
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430785505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.3430785505
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1951951020
Short name T727
Test name
Test status
Simulation time 11869332 ps
CPU time 0.64 seconds
Started Apr 15 12:40:11 PM PDT 24
Finished Apr 15 12:40:13 PM PDT 24
Peak memory 203364 kb
Host smart-d2c54784-85cb-4bea-87d5-b6a2afb7ce28
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951951020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.1951951020
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3294275473
Short name T143
Test name
Test status
Simulation time 197640300 ps
CPU time 4.07 seconds
Started Apr 15 12:40:15 PM PDT 24
Finished Apr 15 12:40:19 PM PDT 24
Peak memory 215020 kb
Host smart-5f40da1f-f8be-4e14-98a8-b93ce0196da6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294275473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.3294275473
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1613727147
Short name T117
Test name
Test status
Simulation time 915706813 ps
CPU time 4.31 seconds
Started Apr 15 12:40:13 PM PDT 24
Finished Apr 15 12:40:19 PM PDT 24
Peak memory 215252 kb
Host smart-51db8eda-f757-43f2-a8b0-46abf75cdf63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613727147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.1
613727147
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.110104732
Short name T135
Test name
Test status
Simulation time 324067649 ps
CPU time 22.19 seconds
Started Apr 15 12:40:18 PM PDT 24
Finished Apr 15 12:40:42 PM PDT 24
Peak memory 215152 kb
Host smart-8d60ff06-3e45-4cb3-9909-4f824d23c27e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110104732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_aliasing.110104732
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.211688661
Short name T773
Test name
Test status
Simulation time 1901843733 ps
CPU time 26.62 seconds
Started Apr 15 12:40:12 PM PDT 24
Finished Apr 15 12:40:40 PM PDT 24
Peak memory 206904 kb
Host smart-1a17a348-b654-4a19-9009-c3589cf6cafd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211688661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_bit_bash.211688661
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3386592212
Short name T99
Test name
Test status
Simulation time 182775153 ps
CPU time 1.41 seconds
Started Apr 15 12:40:10 PM PDT 24
Finished Apr 15 12:40:12 PM PDT 24
Peak memory 206836 kb
Host smart-5c15c4fe-1c85-438b-bcfc-7202461d29d9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386592212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.3386592212
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3747897646
Short name T764
Test name
Test status
Simulation time 256248394 ps
CPU time 1.65 seconds
Started Apr 15 12:40:24 PM PDT 24
Finished Apr 15 12:40:26 PM PDT 24
Peak memory 215196 kb
Host smart-cabf7ee8-b81a-45f0-8a32-a9c8bdb52076
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747897646 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.3747897646
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3404953024
Short name T139
Test name
Test status
Simulation time 107439671 ps
CPU time 1.75 seconds
Started Apr 15 12:40:15 PM PDT 24
Finished Apr 15 12:40:17 PM PDT 24
Peak memory 214996 kb
Host smart-e6418b3d-98f0-4c09-82a6-0835787f1d95
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404953024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
404953024
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.580876228
Short name T802
Test name
Test status
Simulation time 29005092 ps
CPU time 0.75 seconds
Started Apr 15 12:40:10 PM PDT 24
Finished Apr 15 12:40:11 PM PDT 24
Peak memory 203532 kb
Host smart-dba8781b-111d-4b90-94c4-a2adc3038c61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580876228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.580876228
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1921804114
Short name T741
Test name
Test status
Simulation time 86649980 ps
CPU time 1.88 seconds
Started Apr 15 12:40:12 PM PDT 24
Finished Apr 15 12:40:15 PM PDT 24
Peak memory 215212 kb
Host smart-571cb470-7aaf-4cf9-a074-91d5cc252cd8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921804114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.1921804114
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3632905639
Short name T757
Test name
Test status
Simulation time 38446658 ps
CPU time 0.65 seconds
Started Apr 15 12:40:20 PM PDT 24
Finished Apr 15 12:40:22 PM PDT 24
Peak memory 203360 kb
Host smart-e6dd2c9a-9c23-4bc9-ac3d-764fe96ae7e7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632905639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.3632905639
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2225080796
Short name T813
Test name
Test status
Simulation time 114571730 ps
CPU time 3.48 seconds
Started Apr 15 12:40:15 PM PDT 24
Finished Apr 15 12:40:19 PM PDT 24
Peak memory 214952 kb
Host smart-fbdc30e3-7320-4077-826d-84383fdb5cb2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225080796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.2225080796
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3294404699
Short name T372
Test name
Test status
Simulation time 3384439193 ps
CPU time 22.87 seconds
Started Apr 15 12:40:25 PM PDT 24
Finished Apr 15 12:40:49 PM PDT 24
Peak memory 215164 kb
Host smart-a98d2667-8144-4bd7-88b5-5d87665555b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294404699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.3294404699
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2155772339
Short name T822
Test name
Test status
Simulation time 93604679 ps
CPU time 3.1 seconds
Started Apr 15 12:40:23 PM PDT 24
Finished Apr 15 12:40:26 PM PDT 24
Peak memory 217140 kb
Host smart-b72e33b9-8928-4295-8b4f-f8508ba38d06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155772339 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.2155772339
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2118624651
Short name T760
Test name
Test status
Simulation time 486378258 ps
CPU time 2.5 seconds
Started Apr 15 12:40:14 PM PDT 24
Finished Apr 15 12:40:17 PM PDT 24
Peak memory 215080 kb
Host smart-32d55d6b-cd51-4392-a27f-ca7978fb79ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118624651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
2118624651
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.4068722820
Short name T799
Test name
Test status
Simulation time 15059075 ps
CPU time 0.76 seconds
Started Apr 15 12:40:15 PM PDT 24
Finished Apr 15 12:40:17 PM PDT 24
Peak memory 203524 kb
Host smart-bca11f36-6003-40d0-9144-3a8948ba1151
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068722820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
4068722820
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2868413561
Short name T737
Test name
Test status
Simulation time 197431531 ps
CPU time 2.99 seconds
Started Apr 15 12:40:30 PM PDT 24
Finished Apr 15 12:40:34 PM PDT 24
Peak memory 214968 kb
Host smart-210012c6-4287-48b5-b1ab-057376bc1bdc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868413561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.2868413561
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3206083705
Short name T772
Test name
Test status
Simulation time 1122678087 ps
CPU time 8.14 seconds
Started Apr 15 12:40:20 PM PDT 24
Finished Apr 15 12:40:29 PM PDT 24
Peak memory 215248 kb
Host smart-a57b107f-16b2-49df-95a3-5a7fb388874f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206083705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.3206083705
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3207004956
Short name T832
Test name
Test status
Simulation time 194602876 ps
CPU time 2.93 seconds
Started Apr 15 12:40:29 PM PDT 24
Finished Apr 15 12:40:33 PM PDT 24
Peak memory 216172 kb
Host smart-88507d67-62a6-4513-a070-073d20f3eafb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207004956 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.3207004956
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1305921457
Short name T720
Test name
Test status
Simulation time 79661720 ps
CPU time 0.71 seconds
Started Apr 15 12:40:17 PM PDT 24
Finished Apr 15 12:40:20 PM PDT 24
Peak memory 203820 kb
Host smart-0f9ddcf5-8e39-4156-8899-62099df9081f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305921457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
1305921457
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2295036767
Short name T784
Test name
Test status
Simulation time 618847199 ps
CPU time 4.39 seconds
Started Apr 15 12:40:15 PM PDT 24
Finished Apr 15 12:40:21 PM PDT 24
Peak memory 215044 kb
Host smart-8fbb1284-2b26-407d-8189-d6b40704cf0d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295036767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.2295036767
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3346082526
Short name T785
Test name
Test status
Simulation time 738424914 ps
CPU time 4.81 seconds
Started Apr 15 12:40:23 PM PDT 24
Finished Apr 15 12:40:28 PM PDT 24
Peak memory 216476 kb
Host smart-dc213902-c155-411f-b95a-70701bd1861f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346082526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3346082526
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.469518277
Short name T769
Test name
Test status
Simulation time 219421066 ps
CPU time 6.99 seconds
Started Apr 15 12:40:29 PM PDT 24
Finished Apr 15 12:40:36 PM PDT 24
Peak memory 215148 kb
Host smart-ddc46f30-1c78-465f-b5b6-1a55409cf989
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469518277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device
_tl_intg_err.469518277
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3756909159
Short name T151
Test name
Test status
Simulation time 57558730 ps
CPU time 1.66 seconds
Started Apr 15 12:40:17 PM PDT 24
Finished Apr 15 12:40:25 PM PDT 24
Peak memory 216440 kb
Host smart-dfd5df00-8861-4c85-8dbb-2d5e527700c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756909159 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3756909159
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3158317647
Short name T798
Test name
Test status
Simulation time 449929111 ps
CPU time 2.75 seconds
Started Apr 15 12:40:18 PM PDT 24
Finished Apr 15 12:40:23 PM PDT 24
Peak memory 215008 kb
Host smart-689262ba-5bde-4842-bee1-ec1f9ce71fd7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158317647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
3158317647
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2509442046
Short name T744
Test name
Test status
Simulation time 18012995 ps
CPU time 0.72 seconds
Started Apr 15 12:40:17 PM PDT 24
Finished Apr 15 12:40:20 PM PDT 24
Peak memory 203488 kb
Host smart-44c2f533-2ffb-46c9-bf9e-2b5a9c148dcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509442046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
2509442046
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.553265376
Short name T144
Test name
Test status
Simulation time 216898657 ps
CPU time 1.75 seconds
Started Apr 15 12:40:17 PM PDT 24
Finished Apr 15 12:40:20 PM PDT 24
Peak memory 215048 kb
Host smart-2b6da6b3-777b-4fb3-889c-31b8fac5a6ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553265376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.s
pi_device_same_csr_outstanding.553265376
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3727924780
Short name T123
Test name
Test status
Simulation time 51825119 ps
CPU time 3.9 seconds
Started Apr 15 12:40:15 PM PDT 24
Finished Apr 15 12:40:20 PM PDT 24
Peak memory 216240 kb
Host smart-0d296296-df53-46c6-9793-8ee10617d86b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727924780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
3727924780
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2365398998
Short name T830
Test name
Test status
Simulation time 1146300887 ps
CPU time 7.87 seconds
Started Apr 15 12:40:30 PM PDT 24
Finished Apr 15 12:40:39 PM PDT 24
Peak memory 223164 kb
Host smart-dc854a61-aad4-4f21-b974-500f5102c3ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365398998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.2365398998
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2233905171
Short name T827
Test name
Test status
Simulation time 54866244 ps
CPU time 1.79 seconds
Started Apr 15 12:40:32 PM PDT 24
Finished Apr 15 12:40:34 PM PDT 24
Peak memory 215152 kb
Host smart-c7052e70-e280-4ff0-9da5-22c243e85e81
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233905171 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.2233905171
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.338962038
Short name T745
Test name
Test status
Simulation time 45949675 ps
CPU time 1.27 seconds
Started Apr 15 12:40:13 PM PDT 24
Finished Apr 15 12:40:16 PM PDT 24
Peak memory 206936 kb
Host smart-d423941f-49d7-44a9-bea4-ab5fad843780
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338962038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.338962038
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.604479695
Short name T765
Test name
Test status
Simulation time 38417472 ps
CPU time 0.66 seconds
Started Apr 15 12:40:18 PM PDT 24
Finished Apr 15 12:40:21 PM PDT 24
Peak memory 203496 kb
Host smart-ab9140af-c763-44bd-a3a8-0ad78f9d8289
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604479695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.604479695
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.4242792127
Short name T729
Test name
Test status
Simulation time 28323907 ps
CPU time 1.72 seconds
Started Apr 15 12:40:13 PM PDT 24
Finished Apr 15 12:40:16 PM PDT 24
Peak memory 206832 kb
Host smart-b40efeac-a39d-4431-8d75-584be71541e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242792127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.4242792127
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3087639305
Short name T121
Test name
Test status
Simulation time 101891589 ps
CPU time 1.91 seconds
Started Apr 15 12:40:16 PM PDT 24
Finished Apr 15 12:40:19 PM PDT 24
Peak memory 215368 kb
Host smart-bc2f433d-47be-41f5-bead-56c939010e3a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087639305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
3087639305
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3519957019
Short name T374
Test name
Test status
Simulation time 3421095539 ps
CPU time 21.27 seconds
Started Apr 15 12:40:17 PM PDT 24
Finished Apr 15 12:40:41 PM PDT 24
Peak memory 215172 kb
Host smart-50f7b98f-f65a-470f-b36b-02b8db45cb46
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519957019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.3519957019
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3842557622
Short name T149
Test name
Test status
Simulation time 198104771 ps
CPU time 1.69 seconds
Started Apr 15 12:40:21 PM PDT 24
Finished Apr 15 12:40:24 PM PDT 24
Peak memory 216188 kb
Host smart-d63af809-6689-4f71-8e59-a12b94816589
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842557622 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.3842557622
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.4018240657
Short name T134
Test name
Test status
Simulation time 115677460 ps
CPU time 2.63 seconds
Started Apr 15 12:40:20 PM PDT 24
Finished Apr 15 12:40:24 PM PDT 24
Peak memory 215024 kb
Host smart-cb38bb13-9e41-4e68-a3c3-3f9e527b6996
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018240657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
4018240657
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3075156658
Short name T783
Test name
Test status
Simulation time 43562510 ps
CPU time 0.75 seconds
Started Apr 15 12:40:28 PM PDT 24
Finished Apr 15 12:40:29 PM PDT 24
Peak memory 203512 kb
Host smart-51b85487-4635-47e9-9629-49bb61a6d758
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075156658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
3075156658
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1909037917
Short name T731
Test name
Test status
Simulation time 1156227518 ps
CPU time 1.85 seconds
Started Apr 15 12:40:11 PM PDT 24
Finished Apr 15 12:40:14 PM PDT 24
Peak memory 215108 kb
Host smart-0a83d581-9786-411e-bae5-fedcefd14f01
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909037917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.1909037917
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1817232049
Short name T368
Test name
Test status
Simulation time 67499394 ps
CPU time 2.32 seconds
Started Apr 15 12:40:28 PM PDT 24
Finished Apr 15 12:40:31 PM PDT 24
Peak memory 215344 kb
Host smart-3d3d7b18-2d7d-4cd1-baca-877c1f7a2fbe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817232049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
1817232049
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1156217628
Short name T36
Test name
Test status
Simulation time 194644369 ps
CPU time 11.47 seconds
Started Apr 15 12:40:19 PM PDT 24
Finished Apr 15 12:40:32 PM PDT 24
Peak memory 214988 kb
Host smart-2f7a1aec-17da-4e48-a317-32a631b3f3ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156217628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.1156217628
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1971771765
Short name T786
Test name
Test status
Simulation time 43855719 ps
CPU time 1.73 seconds
Started Apr 15 12:40:32 PM PDT 24
Finished Apr 15 12:40:34 PM PDT 24
Peak memory 215144 kb
Host smart-d8bfccff-7d5f-4e35-89d7-28d4373c69a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971771765 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.1971771765
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.4082425788
Short name T142
Test name
Test status
Simulation time 286129794 ps
CPU time 1.82 seconds
Started Apr 15 12:40:19 PM PDT 24
Finished Apr 15 12:40:22 PM PDT 24
Peak memory 215036 kb
Host smart-fa0414af-077d-480d-bab1-c5d282894f89
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082425788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
4082425788
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3679332825
Short name T718
Test name
Test status
Simulation time 44459498 ps
CPU time 0.73 seconds
Started Apr 15 12:40:16 PM PDT 24
Finished Apr 15 12:40:19 PM PDT 24
Peak memory 203816 kb
Host smart-9f0efa6e-c33c-41bc-9785-088f8d791219
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679332825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
3679332825
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3252317440
Short name T803
Test name
Test status
Simulation time 191385195 ps
CPU time 3.92 seconds
Started Apr 15 12:40:24 PM PDT 24
Finished Apr 15 12:40:28 PM PDT 24
Peak memory 215076 kb
Host smart-a68d81af-1a70-4096-8465-e1c175a46994
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252317440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.3252317440
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2201269727
Short name T120
Test name
Test status
Simulation time 41387265 ps
CPU time 2.83 seconds
Started Apr 15 12:40:26 PM PDT 24
Finished Apr 15 12:40:30 PM PDT 24
Peak memory 215280 kb
Host smart-0252c427-08d5-4d30-96af-6b7a8b319186
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201269727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
2201269727
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1606730384
Short name T371
Test name
Test status
Simulation time 109381246 ps
CPU time 7.26 seconds
Started Apr 15 12:40:23 PM PDT 24
Finished Apr 15 12:40:31 PM PDT 24
Peak memory 215064 kb
Host smart-fa623d52-7839-4764-a4f9-4f104c695257
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606730384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.1606730384
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2055777489
Short name T797
Test name
Test status
Simulation time 41084059 ps
CPU time 2.87 seconds
Started Apr 15 12:40:17 PM PDT 24
Finished Apr 15 12:40:22 PM PDT 24
Peak memory 217596 kb
Host smart-b8521d6b-19f0-49ef-a3b3-77bfce8de3df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055777489 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.2055777489
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.4127503776
Short name T834
Test name
Test status
Simulation time 38704514 ps
CPU time 2.73 seconds
Started Apr 15 12:40:23 PM PDT 24
Finished Apr 15 12:40:26 PM PDT 24
Peak memory 214956 kb
Host smart-302e8b5b-1eeb-4179-ac50-3e1e9889d986
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127503776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
4127503776
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.2123080102
Short name T736
Test name
Test status
Simulation time 12202918 ps
CPU time 0.69 seconds
Started Apr 15 12:40:13 PM PDT 24
Finished Apr 15 12:40:15 PM PDT 24
Peak memory 203776 kb
Host smart-f0773852-8d9d-4965-88fb-7e9c1b5b5dce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123080102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
2123080102
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3376438781
Short name T777
Test name
Test status
Simulation time 745370004 ps
CPU time 4.54 seconds
Started Apr 15 12:40:25 PM PDT 24
Finished Apr 15 12:40:30 PM PDT 24
Peak memory 215076 kb
Host smart-0e78d395-53e7-4fdd-a752-c2b83b3aa24f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376438781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.3376438781
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.5951703
Short name T820
Test name
Test status
Simulation time 52607227 ps
CPU time 3.39 seconds
Started Apr 15 12:40:18 PM PDT 24
Finished Apr 15 12:40:23 PM PDT 24
Peak memory 215248 kb
Host smart-495b4c8a-f25f-464f-9665-2a5a60cae24a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5951703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.5951703
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2913271510
Short name T801
Test name
Test status
Simulation time 809569833 ps
CPU time 23.08 seconds
Started Apr 15 12:40:28 PM PDT 24
Finished Apr 15 12:40:51 PM PDT 24
Peak memory 215180 kb
Host smart-cb0159d6-6a76-4653-a39b-beed6dd8efc8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913271510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.2913271510
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1063039627
Short name T150
Test name
Test status
Simulation time 547355165 ps
CPU time 3.67 seconds
Started Apr 15 12:40:26 PM PDT 24
Finished Apr 15 12:40:31 PM PDT 24
Peak memory 216844 kb
Host smart-954c0b14-459f-4278-8fc6-2c1719e71cdb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063039627 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.1063039627
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1459858350
Short name T818
Test name
Test status
Simulation time 35321626 ps
CPU time 2.4 seconds
Started Apr 15 12:40:17 PM PDT 24
Finished Apr 15 12:40:21 PM PDT 24
Peak memory 215004 kb
Host smart-43f6f7fc-6068-4589-b386-dcf848fdad6c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459858350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
1459858350
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3618649159
Short name T719
Test name
Test status
Simulation time 51331733 ps
CPU time 0.66 seconds
Started Apr 15 12:40:47 PM PDT 24
Finished Apr 15 12:40:48 PM PDT 24
Peak memory 203816 kb
Host smart-eb54b79c-5efe-4091-8c7c-251e4e271c17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618649159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
3618649159
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1540271528
Short name T756
Test name
Test status
Simulation time 661182097 ps
CPU time 4.17 seconds
Started Apr 15 12:40:32 PM PDT 24
Finished Apr 15 12:40:36 PM PDT 24
Peak memory 215104 kb
Host smart-41e90718-a973-409c-94c6-0e37ddbdb4b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540271528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.1540271528
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2855006694
Short name T808
Test name
Test status
Simulation time 124973377 ps
CPU time 3.17 seconds
Started Apr 15 12:40:16 PM PDT 24
Finished Apr 15 12:40:21 PM PDT 24
Peak memory 215200 kb
Host smart-166aa22b-cde3-4941-8fad-61fa48419308
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855006694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
2855006694
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1747678643
Short name T753
Test name
Test status
Simulation time 841395148 ps
CPU time 12.72 seconds
Started Apr 15 12:40:22 PM PDT 24
Finished Apr 15 12:40:35 PM PDT 24
Peak memory 215104 kb
Host smart-af8a3fdb-ada0-480e-8a03-acc91082d0c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747678643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.1747678643
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1976559587
Short name T781
Test name
Test status
Simulation time 122394108 ps
CPU time 3.64 seconds
Started Apr 15 12:40:26 PM PDT 24
Finished Apr 15 12:40:31 PM PDT 24
Peak memory 216776 kb
Host smart-c6aa2944-edf6-4713-9709-0159a5bb1777
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976559587 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.1976559587
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3693697189
Short name T821
Test name
Test status
Simulation time 1517227905 ps
CPU time 3.01 seconds
Started Apr 15 12:40:29 PM PDT 24
Finished Apr 15 12:40:32 PM PDT 24
Peak memory 215108 kb
Host smart-22c89da3-c882-4614-8275-ce969fffcca4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693697189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
3693697189
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.806613373
Short name T810
Test name
Test status
Simulation time 53196439 ps
CPU time 0.72 seconds
Started Apr 15 12:40:16 PM PDT 24
Finished Apr 15 12:40:19 PM PDT 24
Peak memory 203816 kb
Host smart-246f5163-d100-4c09-9cb0-6a9997207deb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806613373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.806613373
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.300458546
Short name T790
Test name
Test status
Simulation time 301610303 ps
CPU time 1.65 seconds
Started Apr 15 12:40:16 PM PDT 24
Finished Apr 15 12:40:24 PM PDT 24
Peak memory 215108 kb
Host smart-d5abfcc6-7f7b-495b-91f0-b50361bda875
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300458546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.s
pi_device_same_csr_outstanding.300458546
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.4147834079
Short name T793
Test name
Test status
Simulation time 24919027 ps
CPU time 1.7 seconds
Started Apr 15 12:40:26 PM PDT 24
Finished Apr 15 12:40:29 PM PDT 24
Peak memory 215356 kb
Host smart-99206795-f1da-44f0-836c-00a96370079d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147834079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
4147834079
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2247096711
Short name T370
Test name
Test status
Simulation time 2173791659 ps
CPU time 14.57 seconds
Started Apr 15 12:40:18 PM PDT 24
Finished Apr 15 12:40:34 PM PDT 24
Peak memory 215296 kb
Host smart-312e9136-1709-4f72-b859-afae553fc86e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247096711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.2247096711
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2974477910
Short name T125
Test name
Test status
Simulation time 591965709 ps
CPU time 3.54 seconds
Started Apr 15 12:40:26 PM PDT 24
Finished Apr 15 12:40:30 PM PDT 24
Peak memory 217992 kb
Host smart-2ed968aa-1a13-4ffc-a4d3-e1800b99a0f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974477910 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2974477910
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.4138415388
Short name T782
Test name
Test status
Simulation time 54438393 ps
CPU time 1.78 seconds
Started Apr 15 12:40:16 PM PDT 24
Finished Apr 15 12:40:20 PM PDT 24
Peak memory 215044 kb
Host smart-346acf1b-e29c-4fed-b246-7bd98a066e82
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138415388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
4138415388
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.3384220025
Short name T755
Test name
Test status
Simulation time 24984197 ps
CPU time 0.72 seconds
Started Apr 15 12:40:19 PM PDT 24
Finished Apr 15 12:40:21 PM PDT 24
Peak memory 203780 kb
Host smart-bce07c4c-7017-4eae-8dd9-60bb0b93b297
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384220025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
3384220025
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3449145367
Short name T789
Test name
Test status
Simulation time 1092282940 ps
CPU time 4.04 seconds
Started Apr 15 12:40:30 PM PDT 24
Finished Apr 15 12:40:35 PM PDT 24
Peak memory 215008 kb
Host smart-3a9e42f2-1251-4636-96ab-c87b80c653b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449145367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.3449145367
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.4256929473
Short name T109
Test name
Test status
Simulation time 138242795 ps
CPU time 1.87 seconds
Started Apr 15 12:40:18 PM PDT 24
Finished Apr 15 12:40:22 PM PDT 24
Peak memory 215232 kb
Host smart-2f874fdf-f104-4d59-96a4-b18794583399
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256929473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
4256929473
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.4032158348
Short name T129
Test name
Test status
Simulation time 580960441 ps
CPU time 7.48 seconds
Started Apr 15 12:40:29 PM PDT 24
Finished Apr 15 12:40:37 PM PDT 24
Peak memory 215228 kb
Host smart-b8a50a81-8baa-49cd-a345-0a1f848cef61
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032158348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.4032158348
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3367204461
Short name T763
Test name
Test status
Simulation time 327956698 ps
CPU time 8.26 seconds
Started Apr 15 12:40:15 PM PDT 24
Finished Apr 15 12:40:25 PM PDT 24
Peak memory 216224 kb
Host smart-df2a3a37-86c8-4e89-bddd-23b3db81e584
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367204461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.3367204461
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2568703691
Short name T132
Test name
Test status
Simulation time 6288777890 ps
CPU time 23.13 seconds
Started Apr 15 12:40:10 PM PDT 24
Finished Apr 15 12:40:33 PM PDT 24
Peak memory 206872 kb
Host smart-fb8800ec-0432-4ef8-ad54-0ba629892034
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568703691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.2568703691
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3224713455
Short name T812
Test name
Test status
Simulation time 568022434 ps
CPU time 1.41 seconds
Started Apr 15 12:40:17 PM PDT 24
Finished Apr 15 12:40:20 PM PDT 24
Peak memory 206868 kb
Host smart-30ab3d32-a1d8-47aa-9ad1-6e14c64ca508
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224713455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.3224713455
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.127174725
Short name T749
Test name
Test status
Simulation time 282105410 ps
CPU time 3.57 seconds
Started Apr 15 12:40:29 PM PDT 24
Finished Apr 15 12:40:33 PM PDT 24
Peak memory 216660 kb
Host smart-eb68cd23-ca64-45a5-be24-e2d7555ba996
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127174725 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.127174725
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2049338671
Short name T141
Test name
Test status
Simulation time 68392564 ps
CPU time 1.35 seconds
Started Apr 15 12:40:19 PM PDT 24
Finished Apr 15 12:40:22 PM PDT 24
Peak memory 206856 kb
Host smart-ecafbd98-5fef-452d-a950-2e8830ce3168
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049338671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.2
049338671
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2467804587
Short name T725
Test name
Test status
Simulation time 27728583 ps
CPU time 0.67 seconds
Started Apr 15 12:40:16 PM PDT 24
Finished Apr 15 12:40:19 PM PDT 24
Peak memory 203828 kb
Host smart-a7f312cf-d733-4245-a019-8a70ded89649
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467804587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.2
467804587
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.768810563
Short name T137
Test name
Test status
Simulation time 38955951 ps
CPU time 1.35 seconds
Started Apr 15 12:40:15 PM PDT 24
Finished Apr 15 12:40:17 PM PDT 24
Peak memory 215068 kb
Host smart-0c0cb648-1888-4151-b62b-7d646c739dd4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768810563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_
device_mem_partial_access.768810563
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.686284500
Short name T721
Test name
Test status
Simulation time 34802421 ps
CPU time 0.65 seconds
Started Apr 15 12:40:17 PM PDT 24
Finished Apr 15 12:40:20 PM PDT 24
Peak memory 203712 kb
Host smart-ec028e34-1173-437d-b7d3-92cb43b512fe
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686284500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem
_walk.686284500
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1454742437
Short name T146
Test name
Test status
Simulation time 108806781 ps
CPU time 1.63 seconds
Started Apr 15 12:40:23 PM PDT 24
Finished Apr 15 12:40:26 PM PDT 24
Peak memory 215028 kb
Host smart-47189826-7db5-477a-a4d7-1d6f677c0e69
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454742437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.1454742437
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3815842059
Short name T779
Test name
Test status
Simulation time 147567969 ps
CPU time 3.8 seconds
Started Apr 15 12:40:11 PM PDT 24
Finished Apr 15 12:40:16 PM PDT 24
Peak memory 215224 kb
Host smart-1ac279d5-548c-46c9-a488-5ac2da7003b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815842059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.3
815842059
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.267524205
Short name T809
Test name
Test status
Simulation time 667953133 ps
CPU time 12.33 seconds
Started Apr 15 12:40:18 PM PDT 24
Finished Apr 15 12:40:33 PM PDT 24
Peak memory 215048 kb
Host smart-d61025c2-bc89-4fbd-bbb8-e7c460dbbd1c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267524205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_
tl_intg_err.267524205
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.3282228643
Short name T154
Test name
Test status
Simulation time 50417814 ps
CPU time 0.79 seconds
Started Apr 15 12:40:22 PM PDT 24
Finished Apr 15 12:40:24 PM PDT 24
Peak memory 203748 kb
Host smart-dd207823-b9c8-439a-8912-53c9d76a8503
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282228643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
3282228643
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.4113132952
Short name T771
Test name
Test status
Simulation time 129472517 ps
CPU time 0.75 seconds
Started Apr 15 12:40:20 PM PDT 24
Finished Apr 15 12:40:22 PM PDT 24
Peak memory 203468 kb
Host smart-b713b04f-5d93-4961-9af7-16adf89e2c9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113132952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
4113132952
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2300274794
Short name T153
Test name
Test status
Simulation time 56557113 ps
CPU time 0.73 seconds
Started Apr 15 12:40:25 PM PDT 24
Finished Apr 15 12:40:26 PM PDT 24
Peak memory 203792 kb
Host smart-5f92cf58-7539-4ef5-9d09-d4db97bf9b4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300274794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
2300274794
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.3918554921
Short name T748
Test name
Test status
Simulation time 37117312 ps
CPU time 0.68 seconds
Started Apr 15 12:40:23 PM PDT 24
Finished Apr 15 12:40:24 PM PDT 24
Peak memory 203512 kb
Host smart-f4c5111f-5ae5-4dd9-855f-46e78924ddd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918554921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
3918554921
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.3109552914
Short name T722
Test name
Test status
Simulation time 55103961 ps
CPU time 0.68 seconds
Started Apr 15 12:40:31 PM PDT 24
Finished Apr 15 12:40:32 PM PDT 24
Peak memory 203416 kb
Host smart-a46d4049-e5ee-4cbc-8900-ce2c64b46a48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109552914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
3109552914
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3423741712
Short name T792
Test name
Test status
Simulation time 16456255 ps
CPU time 0.7 seconds
Started Apr 15 12:40:18 PM PDT 24
Finished Apr 15 12:40:21 PM PDT 24
Peak memory 203512 kb
Host smart-8098d5eb-ae37-4525-8eb7-269154ed45c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423741712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
3423741712
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3867479862
Short name T155
Test name
Test status
Simulation time 106057499 ps
CPU time 0.71 seconds
Started Apr 15 12:40:26 PM PDT 24
Finished Apr 15 12:40:27 PM PDT 24
Peak memory 203520 kb
Host smart-30c23a5c-7846-4f57-bd90-a6c02a1c93cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867479862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
3867479862
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2043774095
Short name T157
Test name
Test status
Simulation time 22567727 ps
CPU time 0.76 seconds
Started Apr 15 12:40:25 PM PDT 24
Finished Apr 15 12:40:27 PM PDT 24
Peak memory 203472 kb
Host smart-0edaaf85-26e2-4601-adc1-918dfb6e2c33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043774095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
2043774095
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.3851522396
Short name T732
Test name
Test status
Simulation time 128475154 ps
CPU time 0.7 seconds
Started Apr 15 12:40:20 PM PDT 24
Finished Apr 15 12:40:22 PM PDT 24
Peak memory 203444 kb
Host smart-5513af45-2499-45c0-82ec-43c0922cc166
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851522396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
3851522396
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2263253153
Short name T788
Test name
Test status
Simulation time 13090835 ps
CPU time 0.76 seconds
Started Apr 15 12:40:26 PM PDT 24
Finished Apr 15 12:40:28 PM PDT 24
Peak memory 203448 kb
Host smart-18b58d42-73f1-47b3-b2d8-de11fc58354e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263253153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
2263253153
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.19477488
Short name T768
Test name
Test status
Simulation time 1139520359 ps
CPU time 21.76 seconds
Started Apr 15 12:40:11 PM PDT 24
Finished Apr 15 12:40:33 PM PDT 24
Peak memory 215104 kb
Host smart-fe865099-c5ff-41f4-af8d-1d05d9b9a347
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19477488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_
aliasing.19477488
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2229047535
Short name T775
Test name
Test status
Simulation time 862639660 ps
CPU time 11.66 seconds
Started Apr 15 12:40:20 PM PDT 24
Finished Apr 15 12:40:33 PM PDT 24
Peak memory 206876 kb
Host smart-ef17ae53-b320-4aa1-9ea4-2f1f522db896
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229047535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.2229047535
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3515223021
Short name T98
Test name
Test status
Simulation time 58146863 ps
CPU time 1.13 seconds
Started Apr 15 12:40:18 PM PDT 24
Finished Apr 15 12:40:21 PM PDT 24
Peak memory 206824 kb
Host smart-63dac06d-ad20-4601-a5a8-aa0303d9924f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515223021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.3515223021
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1610166357
Short name T126
Test name
Test status
Simulation time 152303741 ps
CPU time 3.51 seconds
Started Apr 15 12:40:11 PM PDT 24
Finished Apr 15 12:40:16 PM PDT 24
Peak memory 217864 kb
Host smart-8d3ff06c-8a97-4293-a60c-92dcf29059e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610166357 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.1610166357
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1259052581
Short name T807
Test name
Test status
Simulation time 22660489 ps
CPU time 1.38 seconds
Started Apr 15 12:40:23 PM PDT 24
Finished Apr 15 12:40:25 PM PDT 24
Peak memory 214984 kb
Host smart-1e2e1381-253f-4fce-8544-362c0ada9fe1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259052581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.1
259052581
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2101139663
Short name T833
Test name
Test status
Simulation time 28239219 ps
CPU time 0.73 seconds
Started Apr 15 12:40:16 PM PDT 24
Finished Apr 15 12:40:19 PM PDT 24
Peak memory 203432 kb
Host smart-93ac21be-d91b-4043-b5b9-1bf2372f19c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101139663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.2
101139663
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2142874444
Short name T747
Test name
Test status
Simulation time 28410753 ps
CPU time 1.16 seconds
Started Apr 15 12:40:16 PM PDT 24
Finished Apr 15 12:40:18 PM PDT 24
Peak memory 215084 kb
Host smart-03c532bb-9d21-4038-8b62-c5c38d1c78f2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142874444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.2142874444
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.540229506
Short name T730
Test name
Test status
Simulation time 34163547 ps
CPU time 0.66 seconds
Started Apr 15 12:40:18 PM PDT 24
Finished Apr 15 12:40:20 PM PDT 24
Peak memory 203644 kb
Host smart-87e4e24c-ef5b-462f-be31-c71bde22ba38
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540229506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem
_walk.540229506
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.321854722
Short name T145
Test name
Test status
Simulation time 111514050 ps
CPU time 1.84 seconds
Started Apr 15 12:40:16 PM PDT 24
Finished Apr 15 12:40:20 PM PDT 24
Peak memory 215132 kb
Host smart-18dc14f8-47e4-4b2c-861a-0364fbc4a659
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321854722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sp
i_device_same_csr_outstanding.321854722
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.205605019
Short name T128
Test name
Test status
Simulation time 423520526 ps
CPU time 3.28 seconds
Started Apr 15 12:40:07 PM PDT 24
Finished Apr 15 12:40:11 PM PDT 24
Peak memory 216376 kb
Host smart-17bb23f1-4200-4284-8869-2f870e60701d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205605019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.205605019
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1426449339
Short name T375
Test name
Test status
Simulation time 360168776 ps
CPU time 8.17 seconds
Started Apr 15 12:40:13 PM PDT 24
Finished Apr 15 12:40:22 PM PDT 24
Peak memory 215048 kb
Host smart-0236697d-bf75-44e3-a591-79974e7ae19c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426449339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.1426449339
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2255118507
Short name T794
Test name
Test status
Simulation time 16579564 ps
CPU time 0.75 seconds
Started Apr 15 12:40:24 PM PDT 24
Finished Apr 15 12:40:25 PM PDT 24
Peak memory 203812 kb
Host smart-9cdf619d-b667-46f5-a235-b7170bf69423
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255118507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
2255118507
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1158926470
Short name T754
Test name
Test status
Simulation time 28343063 ps
CPU time 0.77 seconds
Started Apr 15 12:40:17 PM PDT 24
Finished Apr 15 12:40:20 PM PDT 24
Peak memory 203456 kb
Host smart-57013f69-975b-47c0-8c3b-b98e685c3f73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158926470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
1158926470
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.1573239493
Short name T739
Test name
Test status
Simulation time 23465907 ps
CPU time 0.68 seconds
Started Apr 15 12:40:13 PM PDT 24
Finished Apr 15 12:40:15 PM PDT 24
Peak memory 203264 kb
Host smart-91699ada-02cb-4078-828b-fb058dd69d4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573239493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
1573239493
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2377690977
Short name T824
Test name
Test status
Simulation time 11453610 ps
CPU time 0.75 seconds
Started Apr 15 12:40:18 PM PDT 24
Finished Apr 15 12:40:21 PM PDT 24
Peak memory 203504 kb
Host smart-702b233c-1e7b-41ee-b218-dde74f2b4ef2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377690977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
2377690977
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.4094525123
Short name T795
Test name
Test status
Simulation time 17974687 ps
CPU time 0.75 seconds
Started Apr 15 12:40:19 PM PDT 24
Finished Apr 15 12:40:21 PM PDT 24
Peak memory 203864 kb
Host smart-837537f5-11d3-4831-a5d0-78b2323b4fb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094525123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
4094525123
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3537661200
Short name T751
Test name
Test status
Simulation time 31131380 ps
CPU time 0.79 seconds
Started Apr 15 12:40:30 PM PDT 24
Finished Apr 15 12:40:32 PM PDT 24
Peak memory 203484 kb
Host smart-0e8f869f-3488-464b-a1c9-6964f707c816
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537661200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
3537661200
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.4187434308
Short name T742
Test name
Test status
Simulation time 16564723 ps
CPU time 0.74 seconds
Started Apr 15 12:40:18 PM PDT 24
Finished Apr 15 12:40:21 PM PDT 24
Peak memory 203820 kb
Host smart-9bb85863-a962-4cbd-9455-8fdfe9a84d10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187434308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
4187434308
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2369366475
Short name T733
Test name
Test status
Simulation time 13709650 ps
CPU time 0.78 seconds
Started Apr 15 12:40:29 PM PDT 24
Finished Apr 15 12:40:31 PM PDT 24
Peak memory 203820 kb
Host smart-3b52392f-03c8-484c-b720-9a7a67e67168
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369366475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
2369366475
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3424632707
Short name T766
Test name
Test status
Simulation time 15329551 ps
CPU time 0.7 seconds
Started Apr 15 12:40:18 PM PDT 24
Finished Apr 15 12:40:21 PM PDT 24
Peak memory 203500 kb
Host smart-389814ba-5f18-450f-9c23-2f023dff9589
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424632707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
3424632707
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2037334664
Short name T723
Test name
Test status
Simulation time 11185179 ps
CPU time 0.74 seconds
Started Apr 15 12:40:15 PM PDT 24
Finished Apr 15 12:40:17 PM PDT 24
Peak memory 203536 kb
Host smart-3b7d0598-f227-4800-9884-227af889b4a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037334664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
2037334664
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2220064468
Short name T136
Test name
Test status
Simulation time 2359346659 ps
CPU time 14.82 seconds
Started Apr 15 12:40:12 PM PDT 24
Finished Apr 15 12:40:27 PM PDT 24
Peak memory 215144 kb
Host smart-dda91b34-9eb5-41d6-b9cc-ab0c2fb1f7fa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220064468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.2220064468
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.677094922
Short name T152
Test name
Test status
Simulation time 2346718793 ps
CPU time 35.63 seconds
Started Apr 15 12:40:18 PM PDT 24
Finished Apr 15 12:40:56 PM PDT 24
Peak memory 206896 kb
Host smart-b8064ed1-dfe7-48f9-a9d0-4e383efaa3d7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677094922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_bit_bash.677094922
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2386145049
Short name T97
Test name
Test status
Simulation time 70415135 ps
CPU time 1.11 seconds
Started Apr 15 12:40:13 PM PDT 24
Finished Apr 15 12:40:15 PM PDT 24
Peak memory 206896 kb
Host smart-df8ecafe-d845-4b0f-9b70-c938f16b6489
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386145049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.2386145049
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2823813190
Short name T825
Test name
Test status
Simulation time 28206191 ps
CPU time 1.87 seconds
Started Apr 15 12:40:14 PM PDT 24
Finished Apr 15 12:40:17 PM PDT 24
Peak memory 215180 kb
Host smart-c4a981a1-c48c-4cd1-81c6-6584857ae44c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823813190 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.2823813190
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2585451389
Short name T787
Test name
Test status
Simulation time 38806254 ps
CPU time 2.43 seconds
Started Apr 15 12:40:21 PM PDT 24
Finished Apr 15 12:40:24 PM PDT 24
Peak memory 215040 kb
Host smart-fa1bff27-06da-47a7-9b72-d8ccb55389e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585451389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.2
585451389
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3487830767
Short name T738
Test name
Test status
Simulation time 14821305 ps
CPU time 0.81 seconds
Started Apr 15 12:40:17 PM PDT 24
Finished Apr 15 12:40:19 PM PDT 24
Peak memory 203496 kb
Host smart-f3e22938-3ea1-40d9-8cc5-27e730547c05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487830767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.3
487830767
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.632027451
Short name T133
Test name
Test status
Simulation time 126427395 ps
CPU time 1.21 seconds
Started Apr 15 12:40:17 PM PDT 24
Finished Apr 15 12:40:21 PM PDT 24
Peak memory 215132 kb
Host smart-d004501d-fa6e-478b-8ce1-e45e5d933fc9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632027451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_
device_mem_partial_access.632027451
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3326520136
Short name T728
Test name
Test status
Simulation time 62882256 ps
CPU time 0.65 seconds
Started Apr 15 12:40:13 PM PDT 24
Finished Apr 15 12:40:14 PM PDT 24
Peak memory 203360 kb
Host smart-2f661459-9ed8-49ce-8e63-cc35e6790ffa
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326520136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.3326520136
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3294316897
Short name T124
Test name
Test status
Simulation time 174715102 ps
CPU time 1.75 seconds
Started Apr 15 12:40:25 PM PDT 24
Finished Apr 15 12:40:27 PM PDT 24
Peak memory 214980 kb
Host smart-043d242e-5dfd-4245-9b7d-7f7c0d51e129
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294316897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.3294316897
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2689201898
Short name T35
Test name
Test status
Simulation time 112523058 ps
CPU time 2.18 seconds
Started Apr 15 12:40:19 PM PDT 24
Finished Apr 15 12:40:23 PM PDT 24
Peak memory 215304 kb
Host smart-c1b29a7d-8fac-4eb5-ac5b-af4a8d9b0668
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689201898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2
689201898
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.4039832751
Short name T778
Test name
Test status
Simulation time 20151108 ps
CPU time 0.76 seconds
Started Apr 15 12:40:20 PM PDT 24
Finished Apr 15 12:40:22 PM PDT 24
Peak memory 203512 kb
Host smart-6ce105fe-f726-48af-aee5-2f967511fa81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039832751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
4039832751
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.498182951
Short name T762
Test name
Test status
Simulation time 40108104 ps
CPU time 0.76 seconds
Started Apr 15 12:40:34 PM PDT 24
Finished Apr 15 12:40:35 PM PDT 24
Peak memory 203436 kb
Host smart-38ad520b-469a-47f0-9c70-c4da96e111d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498182951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.498182951
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3803923526
Short name T740
Test name
Test status
Simulation time 26305074 ps
CPU time 0.71 seconds
Started Apr 15 12:40:26 PM PDT 24
Finished Apr 15 12:40:27 PM PDT 24
Peak memory 203488 kb
Host smart-b36b5573-f57c-40af-b863-3416583358b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803923526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
3803923526
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2078487956
Short name T800
Test name
Test status
Simulation time 13517022 ps
CPU time 0.7 seconds
Started Apr 15 12:40:27 PM PDT 24
Finished Apr 15 12:40:28 PM PDT 24
Peak memory 203476 kb
Host smart-e4d5fd8b-35ef-48e7-9614-3ac0f0f606bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078487956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
2078487956
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1947792238
Short name T791
Test name
Test status
Simulation time 42974795 ps
CPU time 0.71 seconds
Started Apr 15 12:40:20 PM PDT 24
Finished Apr 15 12:40:22 PM PDT 24
Peak memory 203484 kb
Host smart-821eb88b-3192-4857-855a-e01cd9a618c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947792238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
1947792238
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.815185140
Short name T156
Test name
Test status
Simulation time 37379067 ps
CPU time 0.77 seconds
Started Apr 15 12:40:31 PM PDT 24
Finished Apr 15 12:40:32 PM PDT 24
Peak memory 203500 kb
Host smart-f355b441-3e33-4b76-8547-8e69f4596af7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815185140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.815185140
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.4284418656
Short name T796
Test name
Test status
Simulation time 43210479 ps
CPU time 0.71 seconds
Started Apr 15 12:40:30 PM PDT 24
Finished Apr 15 12:40:32 PM PDT 24
Peak memory 203780 kb
Host smart-1d76196a-f7a7-4630-9335-9fef263810da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284418656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
4284418656
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2936980140
Short name T746
Test name
Test status
Simulation time 12384354 ps
CPU time 0.67 seconds
Started Apr 15 12:40:18 PM PDT 24
Finished Apr 15 12:40:21 PM PDT 24
Peak memory 203480 kb
Host smart-a5085e48-3bf3-4437-9ae7-1143a1094f4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936980140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
2936980140
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2051333733
Short name T814
Test name
Test status
Simulation time 41891405 ps
CPU time 0.73 seconds
Started Apr 15 12:40:32 PM PDT 24
Finished Apr 15 12:40:34 PM PDT 24
Peak memory 203488 kb
Host smart-371ab122-8d88-4f0a-8ad1-966217c5c76a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051333733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2051333733
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2433198073
Short name T776
Test name
Test status
Simulation time 14355875 ps
CPU time 0.78 seconds
Started Apr 15 12:40:25 PM PDT 24
Finished Apr 15 12:40:26 PM PDT 24
Peak memory 203816 kb
Host smart-fdb56e4e-8a9b-4324-ab41-142cf56ea6b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433198073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
2433198073
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.249654482
Short name T122
Test name
Test status
Simulation time 39043807 ps
CPU time 2.58 seconds
Started Apr 15 12:40:09 PM PDT 24
Finished Apr 15 12:40:12 PM PDT 24
Peak memory 216188 kb
Host smart-c4c5cc4e-c260-4fd4-9ecd-ca6dabda280c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249654482 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.249654482
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1497643390
Short name T138
Test name
Test status
Simulation time 140476354 ps
CPU time 1.94 seconds
Started Apr 15 12:40:13 PM PDT 24
Finished Apr 15 12:40:16 PM PDT 24
Peak memory 206804 kb
Host smart-331e1fe0-c0b5-4679-9709-8e6b573c7de2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497643390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.1
497643390
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2215645865
Short name T826
Test name
Test status
Simulation time 13400603 ps
CPU time 0.7 seconds
Started Apr 15 12:40:16 PM PDT 24
Finished Apr 15 12:40:18 PM PDT 24
Peak memory 203752 kb
Host smart-681510a9-36ac-433e-89e8-eeadc97fae15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215645865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.2
215645865
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2645510139
Short name T780
Test name
Test status
Simulation time 80070573 ps
CPU time 1.95 seconds
Started Apr 15 12:40:07 PM PDT 24
Finished Apr 15 12:40:10 PM PDT 24
Peak memory 215092 kb
Host smart-dd3d9e07-1c58-46cd-8876-f0e7be70d2c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645510139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.2645510139
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3753696687
Short name T37
Test name
Test status
Simulation time 70070643 ps
CPU time 2.41 seconds
Started Apr 15 12:40:09 PM PDT 24
Finished Apr 15 12:40:12 PM PDT 24
Peak memory 215320 kb
Host smart-d07d5f12-c8fa-43b9-bec9-d2c2493e8eae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753696687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.3
753696687
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3921715712
Short name T373
Test name
Test status
Simulation time 974134833 ps
CPU time 20.98 seconds
Started Apr 15 12:40:18 PM PDT 24
Finished Apr 15 12:40:41 PM PDT 24
Peak memory 215060 kb
Host smart-2810e0d5-0fc1-4aad-a103-32b507580d1e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921715712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.3921715712
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2909444280
Short name T823
Test name
Test status
Simulation time 45165765 ps
CPU time 2.93 seconds
Started Apr 15 12:40:19 PM PDT 24
Finished Apr 15 12:40:24 PM PDT 24
Peak memory 217464 kb
Host smart-1766c326-6b5f-4422-948e-87b63feffd7e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909444280 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.2909444280
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.841236735
Short name T817
Test name
Test status
Simulation time 64746575 ps
CPU time 1.18 seconds
Started Apr 15 12:40:14 PM PDT 24
Finished Apr 15 12:40:16 PM PDT 24
Peak memory 214996 kb
Host smart-88a3dca3-301f-4dbc-8f55-814b9874224f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841236735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.841236735
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1175158226
Short name T761
Test name
Test status
Simulation time 37568350 ps
CPU time 0.69 seconds
Started Apr 15 12:40:26 PM PDT 24
Finished Apr 15 12:40:27 PM PDT 24
Peak memory 203476 kb
Host smart-b38851f3-d843-4b43-a3ca-5d376e1d0944
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175158226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.1
175158226
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2097158233
Short name T735
Test name
Test status
Simulation time 161615788 ps
CPU time 2.59 seconds
Started Apr 15 12:40:24 PM PDT 24
Finished Apr 15 12:40:27 PM PDT 24
Peak memory 215076 kb
Host smart-c6a6fa1b-7dc7-4d4a-8465-d716c00c6a48
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097158233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.2097158233
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3327415871
Short name T770
Test name
Test status
Simulation time 147828905 ps
CPU time 2.93 seconds
Started Apr 15 12:40:12 PM PDT 24
Finished Apr 15 12:40:16 PM PDT 24
Peak memory 215312 kb
Host smart-39d249a9-97bc-4ee5-9af8-8d2150584743
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327415871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.3
327415871
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.4153285843
Short name T815
Test name
Test status
Simulation time 6323532936 ps
CPU time 24.05 seconds
Started Apr 15 12:40:17 PM PDT 24
Finished Apr 15 12:40:44 PM PDT 24
Peak memory 215120 kb
Host smart-7b76c216-0fae-4148-8a75-c1ee3d93051d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153285843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.4153285843
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1774534309
Short name T774
Test name
Test status
Simulation time 63114426 ps
CPU time 1.79 seconds
Started Apr 15 12:40:16 PM PDT 24
Finished Apr 15 12:40:19 PM PDT 24
Peak memory 215228 kb
Host smart-8cd408d1-1650-4b8a-88e4-24889eaea653
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774534309 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.1774534309
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3966898761
Short name T750
Test name
Test status
Simulation time 28961543 ps
CPU time 1.21 seconds
Started Apr 15 12:40:16 PM PDT 24
Finished Apr 15 12:40:18 PM PDT 24
Peak memory 206936 kb
Host smart-6a22cb6b-44ba-4942-b35b-5387ff7cce2c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966898761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.3
966898761
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3584066003
Short name T804
Test name
Test status
Simulation time 12248512 ps
CPU time 0.68 seconds
Started Apr 15 12:40:17 PM PDT 24
Finished Apr 15 12:40:20 PM PDT 24
Peak memory 203816 kb
Host smart-b3ca8595-8522-4ca6-a8b6-d13b3268edf5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584066003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.3
584066003
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3328226759
Short name T811
Test name
Test status
Simulation time 218096294 ps
CPU time 1.72 seconds
Started Apr 15 12:40:18 PM PDT 24
Finished Apr 15 12:40:22 PM PDT 24
Peak memory 215136 kb
Host smart-b779bd4a-3827-44d6-ac4a-cf49d35d7f65
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328226759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.3328226759
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2638177169
Short name T816
Test name
Test status
Simulation time 100046882 ps
CPU time 2.52 seconds
Started Apr 15 12:40:16 PM PDT 24
Finished Apr 15 12:40:20 PM PDT 24
Peak memory 215192 kb
Host smart-dbd3f19f-50ff-4037-bca4-c0e12f163e7e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638177169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.2
638177169
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.342753589
Short name T758
Test name
Test status
Simulation time 404107424 ps
CPU time 7.81 seconds
Started Apr 15 12:40:13 PM PDT 24
Finished Apr 15 12:40:22 PM PDT 24
Peak memory 215060 kb
Host smart-e8780152-c50b-4380-8eac-c3f654da1abf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342753589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_
tl_intg_err.342753589
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.82752939
Short name T734
Test name
Test status
Simulation time 238599190 ps
CPU time 4.18 seconds
Started Apr 15 12:40:22 PM PDT 24
Finished Apr 15 12:40:27 PM PDT 24
Peak memory 217472 kb
Host smart-00f1fd69-4bc3-4a71-898a-0938560d0685
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82752939 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.82752939
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3042285088
Short name T805
Test name
Test status
Simulation time 40083470 ps
CPU time 1.26 seconds
Started Apr 15 12:40:11 PM PDT 24
Finished Apr 15 12:40:14 PM PDT 24
Peak memory 206556 kb
Host smart-98474f90-54d5-4fd1-a214-a8bb78164d17
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042285088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.3
042285088
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.292470360
Short name T724
Test name
Test status
Simulation time 72512180 ps
CPU time 0.73 seconds
Started Apr 15 12:40:17 PM PDT 24
Finished Apr 15 12:40:20 PM PDT 24
Peak memory 203816 kb
Host smart-212e687e-0c3e-41eb-9dfc-c478edf1fdfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292470360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.292470360
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3352424990
Short name T828
Test name
Test status
Simulation time 2982356019 ps
CPU time 3.78 seconds
Started Apr 15 12:40:18 PM PDT 24
Finished Apr 15 12:40:24 PM PDT 24
Peak memory 215200 kb
Host smart-9f488a2e-55b6-4ecc-903e-b1ac808a2c09
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352424990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.3352424990
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.631308559
Short name T829
Test name
Test status
Simulation time 189150167 ps
CPU time 3.56 seconds
Started Apr 15 12:40:18 PM PDT 24
Finished Apr 15 12:40:24 PM PDT 24
Peak memory 216288 kb
Host smart-e105bdc1-b4fa-4c37-805c-483636d8a037
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631308559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.631308559
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.4284522705
Short name T369
Test name
Test status
Simulation time 877470085 ps
CPU time 22.5 seconds
Started Apr 15 12:40:19 PM PDT 24
Finished Apr 15 12:40:43 PM PDT 24
Peak memory 215320 kb
Host smart-f4cd1b72-490d-435b-ac0c-42fa4de606ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284522705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.4284522705
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2343936596
Short name T743
Test name
Test status
Simulation time 49722444 ps
CPU time 1.69 seconds
Started Apr 15 12:40:14 PM PDT 24
Finished Apr 15 12:40:16 PM PDT 24
Peak memory 215260 kb
Host smart-7856b863-5f10-423b-80e4-1391b8b87ba2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343936596 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.2343936596
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1711274328
Short name T147
Test name
Test status
Simulation time 1023501267 ps
CPU time 1.96 seconds
Started Apr 15 12:40:31 PM PDT 24
Finished Apr 15 12:40:33 PM PDT 24
Peak memory 215060 kb
Host smart-643ad281-0c63-4432-a57e-4fa37f24e45c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711274328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.1
711274328
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2064560730
Short name T767
Test name
Test status
Simulation time 16045000 ps
CPU time 0.75 seconds
Started Apr 15 12:40:15 PM PDT 24
Finished Apr 15 12:40:17 PM PDT 24
Peak memory 203544 kb
Host smart-642e4da6-238a-4ed2-b82f-bebeace4b3a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064560730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.2
064560730
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1872439090
Short name T39
Test name
Test status
Simulation time 146346143 ps
CPU time 1.91 seconds
Started Apr 15 12:40:23 PM PDT 24
Finished Apr 15 12:40:25 PM PDT 24
Peak memory 214992 kb
Host smart-3647d6d1-8e3e-4366-a52d-3701e5bfa271
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872439090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.1872439090
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.949546736
Short name T806
Test name
Test status
Simulation time 328613069 ps
CPU time 20.52 seconds
Started Apr 15 12:40:18 PM PDT 24
Finished Apr 15 12:40:41 PM PDT 24
Peak memory 215160 kb
Host smart-923bac18-2c21-4ef1-b8ec-71a3ec067cdf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949546736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_
tl_intg_err.949546736
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.2601642108
Short name T610
Test name
Test status
Simulation time 12036814 ps
CPU time 0.74 seconds
Started Apr 15 01:18:31 PM PDT 24
Finished Apr 15 01:18:32 PM PDT 24
Peak memory 205316 kb
Host smart-0d3dc32f-2dd8-453d-9e4d-e394cc7bae83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601642108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.2
601642108
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_intercept.4128037816
Short name T704
Test name
Test status
Simulation time 163450185 ps
CPU time 4.46 seconds
Started Apr 15 01:18:29 PM PDT 24
Finished Apr 15 01:18:34 PM PDT 24
Peak memory 218716 kb
Host smart-7a430aaa-4b0c-4a67-b8b4-919ea8b10bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128037816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.4128037816
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.3369613620
Short name T201
Test name
Test status
Simulation time 747930518 ps
CPU time 4.01 seconds
Started Apr 15 01:18:27 PM PDT 24
Finished Apr 15 01:18:31 PM PDT 24
Peak memory 219964 kb
Host smart-ab8e0dee-5001-4223-be3d-e5eeaaf4f99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369613620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.3369613620
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.3906515294
Short name T108
Test name
Test status
Simulation time 124861137 ps
CPU time 3.65 seconds
Started Apr 15 01:18:29 PM PDT 24
Finished Apr 15 01:18:33 PM PDT 24
Peak memory 218664 kb
Host smart-4370e927-03e7-457a-a072-22e5c14b4dc3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3906515294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.3906515294
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.4262130372
Short name T388
Test name
Test status
Simulation time 2792964477 ps
CPU time 10.24 seconds
Started Apr 15 01:18:23 PM PDT 24
Finished Apr 15 01:18:34 PM PDT 24
Peak memory 216236 kb
Host smart-e1eba898-e0eb-4fcc-9583-b5b45dc4a976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262130372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.4262130372
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.2106839772
Short name T680
Test name
Test status
Simulation time 2179205470 ps
CPU time 9.57 seconds
Started Apr 15 01:18:27 PM PDT 24
Finished Apr 15 01:18:37 PM PDT 24
Peak memory 216240 kb
Host smart-4f2f42b3-917d-4250-85bb-de56088acc7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106839772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.2106839772
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.199894298
Short name T458
Test name
Test status
Simulation time 242265554 ps
CPU time 2.67 seconds
Started Apr 15 01:18:25 PM PDT 24
Finished Apr 15 01:18:29 PM PDT 24
Peak memory 216264 kb
Host smart-19f24a2d-4207-4bfa-a872-43470fc88d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199894298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.199894298
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.460796351
Short name T685
Test name
Test status
Simulation time 46269778 ps
CPU time 0.82 seconds
Started Apr 15 01:18:30 PM PDT 24
Finished Apr 15 01:18:32 PM PDT 24
Peak memory 205640 kb
Host smart-7baf1049-daaa-4f49-84fd-63e584d04d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460796351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.460796351
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.232786402
Short name T605
Test name
Test status
Simulation time 19535536 ps
CPU time 0.75 seconds
Started Apr 15 01:18:31 PM PDT 24
Finished Apr 15 01:18:32 PM PDT 24
Peak memory 205328 kb
Host smart-b830779e-bf66-4eff-905c-cf0bb7d51dcf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232786402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.232786402
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.2586538905
Short name T486
Test name
Test status
Simulation time 19408210 ps
CPU time 0.77 seconds
Started Apr 15 01:18:27 PM PDT 24
Finished Apr 15 01:18:29 PM PDT 24
Peak memory 205832 kb
Host smart-e14d3ec6-be40-4059-9242-dc3d291ddfc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586538905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.2586538905
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.3941285184
Short name T311
Test name
Test status
Simulation time 453745576 ps
CPU time 12.91 seconds
Started Apr 15 01:18:31 PM PDT 24
Finished Apr 15 01:18:45 PM PDT 24
Peak memory 240656 kb
Host smart-77212be4-ee6f-4f45-b647-b7984e9dcd38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941285184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.3941285184
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.2179671629
Short name T178
Test name
Test status
Simulation time 888725051 ps
CPU time 4.25 seconds
Started Apr 15 01:18:27 PM PDT 24
Finished Apr 15 01:18:32 PM PDT 24
Peak memory 223076 kb
Host smart-09d257a1-bd55-477f-8f96-9558c51a095f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179671629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.2179671629
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.1430884581
Short name T169
Test name
Test status
Simulation time 1458007813 ps
CPU time 11.41 seconds
Started Apr 15 01:18:26 PM PDT 24
Finished Apr 15 01:18:38 PM PDT 24
Peak memory 227856 kb
Host smart-da27dd29-4fca-4805-a879-23c68cd82828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430884581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.1430884581
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.1586578478
Short name T222
Test name
Test status
Simulation time 13570884921 ps
CPU time 19.34 seconds
Started Apr 15 01:18:28 PM PDT 24
Finished Apr 15 01:18:48 PM PDT 24
Peak memory 234136 kb
Host smart-dd075e2a-c7a1-4770-b2ff-37ce38d2efa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586578478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.1586578478
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.3421665292
Short name T696
Test name
Test status
Simulation time 4097052523 ps
CPU time 18.45 seconds
Started Apr 15 01:18:34 PM PDT 24
Finished Apr 15 01:18:53 PM PDT 24
Peak memory 221924 kb
Host smart-f168ab00-56e9-48b2-9371-aba345425bc6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3421665292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.3421665292
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.3912048220
Short name T45
Test name
Test status
Simulation time 331145972 ps
CPU time 1.04 seconds
Started Apr 15 01:18:32 PM PDT 24
Finished Apr 15 01:18:34 PM PDT 24
Peak memory 234952 kb
Host smart-3a2755c4-fa94-4767-b807-a1f3efb1543d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912048220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.3912048220
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.3640311814
Short name T54
Test name
Test status
Simulation time 3832012525 ps
CPU time 23.84 seconds
Started Apr 15 01:18:26 PM PDT 24
Finished Apr 15 01:18:50 PM PDT 24
Peak memory 216248 kb
Host smart-a837da86-529f-4d39-80f4-dc45665fa5c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640311814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.3640311814
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.2096509619
Short name T526
Test name
Test status
Simulation time 2256857898 ps
CPU time 4.88 seconds
Started Apr 15 01:18:26 PM PDT 24
Finished Apr 15 01:18:32 PM PDT 24
Peak memory 216256 kb
Host smart-9d5b5b7c-9034-4824-bc5a-39a3c164cc80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096509619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.2096509619
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.3028985882
Short name T525
Test name
Test status
Simulation time 399814635 ps
CPU time 2.78 seconds
Started Apr 15 01:18:27 PM PDT 24
Finished Apr 15 01:18:30 PM PDT 24
Peak memory 216352 kb
Host smart-2b07f813-9d77-4fba-85c1-d5361998b9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028985882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.3028985882
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.857208105
Short name T437
Test name
Test status
Simulation time 55388757 ps
CPU time 0.88 seconds
Started Apr 15 01:18:28 PM PDT 24
Finished Apr 15 01:18:30 PM PDT 24
Peak memory 205684 kb
Host smart-54ed1093-fd43-4457-a589-14b442bb9115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857208105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.857208105
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.1568951347
Short name T492
Test name
Test status
Simulation time 23304156 ps
CPU time 0.8 seconds
Started Apr 15 01:19:01 PM PDT 24
Finished Apr 15 01:19:03 PM PDT 24
Peak memory 204800 kb
Host smart-7c53a553-8d49-4df4-8dc2-f0875dfa9b6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568951347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
1568951347
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.2813830157
Short name T494
Test name
Test status
Simulation time 23106361 ps
CPU time 0.79 seconds
Started Apr 15 01:18:56 PM PDT 24
Finished Apr 15 01:18:58 PM PDT 24
Peak memory 206464 kb
Host smart-7baca9cd-2890-4294-903a-4af7ed996f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813830157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.2813830157
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.2573281515
Short name T357
Test name
Test status
Simulation time 22367513871 ps
CPU time 73.22 seconds
Started Apr 15 01:18:55 PM PDT 24
Finished Apr 15 01:20:09 PM PDT 24
Peak memory 232688 kb
Host smart-22b1f41b-09e7-45a0-9cb7-766a611d6656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573281515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.2573281515
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.2247114122
Short name T329
Test name
Test status
Simulation time 26201064965 ps
CPU time 22.63 seconds
Started Apr 15 01:18:56 PM PDT 24
Finished Apr 15 01:19:19 PM PDT 24
Peak memory 222636 kb
Host smart-d70a933e-32b6-4ad2-8bb4-de2d4bcc9702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247114122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.2247114122
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.546259687
Short name T513
Test name
Test status
Simulation time 677471880 ps
CPU time 6.25 seconds
Started Apr 15 01:18:57 PM PDT 24
Finished Apr 15 01:19:03 PM PDT 24
Peak memory 219640 kb
Host smart-459e1c42-c114-4e97-8498-37746bc09506
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=546259687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dire
ct.546259687
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.2825951342
Short name T381
Test name
Test status
Simulation time 2638429952 ps
CPU time 10.56 seconds
Started Apr 15 01:18:57 PM PDT 24
Finished Apr 15 01:19:08 PM PDT 24
Peak memory 216212 kb
Host smart-aad3c8ec-32ed-4a70-af96-511b6fa0b555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825951342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.2825951342
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.3795716821
Short name T571
Test name
Test status
Simulation time 8296509484 ps
CPU time 27.23 seconds
Started Apr 15 01:18:59 PM PDT 24
Finished Apr 15 01:19:27 PM PDT 24
Peak memory 216220 kb
Host smart-2646405c-f651-4760-a663-15d55498dd7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795716821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.3795716821
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.1004455842
Short name T604
Test name
Test status
Simulation time 472820044 ps
CPU time 2.15 seconds
Started Apr 15 01:18:56 PM PDT 24
Finished Apr 15 01:18:59 PM PDT 24
Peak memory 216200 kb
Host smart-77ad9fe4-7d1f-4d0e-ba85-8bc805d4f7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004455842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.1004455842
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.782448019
Short name T467
Test name
Test status
Simulation time 147041015 ps
CPU time 1.21 seconds
Started Apr 15 01:18:58 PM PDT 24
Finished Apr 15 01:19:00 PM PDT 24
Peak memory 206744 kb
Host smart-7908d3a9-82ad-44c7-8b87-2f534ed5e7f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782448019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.782448019
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.17348925
Short name T563
Test name
Test status
Simulation time 27488265 ps
CPU time 0.75 seconds
Started Apr 15 01:19:08 PM PDT 24
Finished Apr 15 01:19:09 PM PDT 24
Peak memory 205724 kb
Host smart-3548856d-5218-4f00-b367-f8edf57fe472
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17348925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.17348925
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.2118976808
Short name T26
Test name
Test status
Simulation time 669787602 ps
CPU time 8.87 seconds
Started Apr 15 01:19:05 PM PDT 24
Finished Apr 15 01:19:14 PM PDT 24
Peak memory 223380 kb
Host smart-c2bb76ca-d0bf-48de-8671-6ec0517a04e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118976808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.2118976808
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.648712027
Short name T51
Test name
Test status
Simulation time 17310938 ps
CPU time 0.84 seconds
Started Apr 15 01:19:01 PM PDT 24
Finished Apr 15 01:19:03 PM PDT 24
Peak memory 206264 kb
Host smart-a63d1958-0be3-4c88-ac52-cabe5027e7df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648712027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.648712027
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_intercept.558575034
Short name T555
Test name
Test status
Simulation time 2117141445 ps
CPU time 24.09 seconds
Started Apr 15 01:19:02 PM PDT 24
Finished Apr 15 01:19:27 PM PDT 24
Peak memory 218620 kb
Host smart-5aa1d0d4-8421-4fd1-87b8-6e046e351972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558575034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.558575034
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.167002606
Short name T326
Test name
Test status
Simulation time 4240209848 ps
CPU time 42.95 seconds
Started Apr 15 01:19:00 PM PDT 24
Finished Apr 15 01:19:43 PM PDT 24
Peak memory 223100 kb
Host smart-cd8f9c23-abd7-4942-8ea3-0589ee224db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167002606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.167002606
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.2780969552
Short name T2
Test name
Test status
Simulation time 390893320 ps
CPU time 4.88 seconds
Started Apr 15 01:19:01 PM PDT 24
Finished Apr 15 01:19:06 PM PDT 24
Peak memory 221776 kb
Host smart-db3e2b97-d3d1-48f1-88cd-59e04706095f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2780969552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.2780969552
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.2434312788
Short name T400
Test name
Test status
Simulation time 5324461739 ps
CPU time 13.8 seconds
Started Apr 15 01:19:07 PM PDT 24
Finished Apr 15 01:19:21 PM PDT 24
Peak memory 216268 kb
Host smart-f17ac747-0c5d-4a2d-8ebd-a9db96e6ccb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434312788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.2434312788
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.4074894462
Short name T497
Test name
Test status
Simulation time 7313123630 ps
CPU time 6.32 seconds
Started Apr 15 01:19:01 PM PDT 24
Finished Apr 15 01:19:08 PM PDT 24
Peak memory 216276 kb
Host smart-66f47b26-59c5-4b40-8224-919144f9995f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074894462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.4074894462
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.2826623748
Short name T406
Test name
Test status
Simulation time 135500437 ps
CPU time 0.94 seconds
Started Apr 15 01:19:01 PM PDT 24
Finished Apr 15 01:19:02 PM PDT 24
Peak memory 207100 kb
Host smart-688a05bb-b39f-4aae-991b-50c899a08628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826623748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.2826623748
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.1102057245
Short name T509
Test name
Test status
Simulation time 197329960 ps
CPU time 1.29 seconds
Started Apr 15 01:19:01 PM PDT 24
Finished Apr 15 01:19:03 PM PDT 24
Peak memory 206492 kb
Host smart-7bfc416b-3054-4bd8-a0a7-6224b440c426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102057245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.1102057245
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.2976575213
Short name T633
Test name
Test status
Simulation time 834253121 ps
CPU time 7.19 seconds
Started Apr 15 01:19:00 PM PDT 24
Finished Apr 15 01:19:08 PM PDT 24
Peak memory 232384 kb
Host smart-c1701e6f-c047-492b-b2dd-0986f8a1eccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976575213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.2976575213
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.3484199919
Short name T588
Test name
Test status
Simulation time 43627588 ps
CPU time 0.7 seconds
Started Apr 15 01:19:07 PM PDT 24
Finished Apr 15 01:19:09 PM PDT 24
Peak memory 205736 kb
Host smart-5640d19f-84e0-4c62-96c3-d729217d241c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484199919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
3484199919
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.1174212849
Short name T621
Test name
Test status
Simulation time 1626824035 ps
CPU time 5.58 seconds
Started Apr 15 01:19:09 PM PDT 24
Finished Apr 15 01:19:16 PM PDT 24
Peak memory 221404 kb
Host smart-e7b38b51-9096-4313-8cee-6c1ce04be225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174212849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.1174212849
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.2293297697
Short name T514
Test name
Test status
Simulation time 22408891 ps
CPU time 0.8 seconds
Started Apr 15 01:19:08 PM PDT 24
Finished Apr 15 01:19:09 PM PDT 24
Peak memory 206552 kb
Host smart-708cacf8-be99-490c-958f-0950f65ab60b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293297697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.2293297697
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_intercept.150241357
Short name T313
Test name
Test status
Simulation time 445019319 ps
CPU time 5.01 seconds
Started Apr 15 01:19:06 PM PDT 24
Finished Apr 15 01:19:11 PM PDT 24
Peak memory 219152 kb
Host smart-0713f494-9e20-4581-85b5-2f0d0094a207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150241357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.150241357
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.2433839590
Short name T376
Test name
Test status
Simulation time 35966201985 ps
CPU time 21.9 seconds
Started Apr 15 01:19:05 PM PDT 24
Finished Apr 15 01:19:27 PM PDT 24
Peak memory 221204 kb
Host smart-c46914ef-911d-4293-9a38-7ae3b46f5789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433839590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.2433839590
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.2114465913
Short name T517
Test name
Test status
Simulation time 1163911937 ps
CPU time 7.21 seconds
Started Apr 15 01:19:10 PM PDT 24
Finished Apr 15 01:19:18 PM PDT 24
Peak memory 222356 kb
Host smart-b20381cd-557c-430f-86e7-61839bbc71a5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2114465913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.2114465913
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.2970868160
Short name T40
Test name
Test status
Simulation time 35615257 ps
CPU time 0.9 seconds
Started Apr 15 01:19:12 PM PDT 24
Finished Apr 15 01:19:14 PM PDT 24
Peak memory 206844 kb
Host smart-0334a01d-90ce-493d-ba07-2000a27e066d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970868160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.2970868160
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.839916758
Short name T383
Test name
Test status
Simulation time 2393380076 ps
CPU time 4.12 seconds
Started Apr 15 01:19:05 PM PDT 24
Finished Apr 15 01:19:10 PM PDT 24
Peak memory 216260 kb
Host smart-ce226031-1dc9-4ac4-bddc-a8ea2c3d8894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839916758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.839916758
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.2755074634
Short name T551
Test name
Test status
Simulation time 30670892465 ps
CPU time 22.34 seconds
Started Apr 15 01:19:06 PM PDT 24
Finished Apr 15 01:19:29 PM PDT 24
Peak memory 216272 kb
Host smart-5145e5d5-8719-4131-8d97-cd6c3d708b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755074634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.2755074634
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.3324485877
Short name T677
Test name
Test status
Simulation time 281105214 ps
CPU time 2.31 seconds
Started Apr 15 01:19:07 PM PDT 24
Finished Apr 15 01:19:10 PM PDT 24
Peak memory 216196 kb
Host smart-3f9aab7e-0f4e-4e45-9c7e-83366fb582f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324485877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.3324485877
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.1521767223
Short name T676
Test name
Test status
Simulation time 107640299 ps
CPU time 0.84 seconds
Started Apr 15 01:19:05 PM PDT 24
Finished Apr 15 01:19:06 PM PDT 24
Peak memory 205700 kb
Host smart-e00d7b59-5de9-4482-bada-a14bedcd3285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521767223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.1521767223
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.2632103430
Short name T552
Test name
Test status
Simulation time 22545172 ps
CPU time 0.73 seconds
Started Apr 15 01:19:15 PM PDT 24
Finished Apr 15 01:19:16 PM PDT 24
Peak memory 205420 kb
Host smart-4860e2a8-267c-44ae-9dfb-aa75aff611fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632103430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
2632103430
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.4188218651
Short name T690
Test name
Test status
Simulation time 13599103 ps
CPU time 0.8 seconds
Started Apr 15 01:19:08 PM PDT 24
Finished Apr 15 01:19:10 PM PDT 24
Peak memory 206828 kb
Host smart-eb0a61ab-514b-4a29-88ad-4ce07162196d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188218651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.4188218651
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_intercept.4285252804
Short name T479
Test name
Test status
Simulation time 1592136439 ps
CPU time 7.69 seconds
Started Apr 15 01:19:13 PM PDT 24
Finished Apr 15 01:19:21 PM PDT 24
Peak memory 218648 kb
Host smart-734c9268-80e1-4d89-b3da-c74d18f0956c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285252804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.4285252804
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.875928631
Short name T541
Test name
Test status
Simulation time 2325982383 ps
CPU time 4.24 seconds
Started Apr 15 01:19:13 PM PDT 24
Finished Apr 15 01:19:18 PM PDT 24
Peak memory 219268 kb
Host smart-fc3a82bd-b7e7-49ed-bd4d-b4336fc684ec
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=875928631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dire
ct.875928631
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.3061541340
Short name T384
Test name
Test status
Simulation time 12590724512 ps
CPU time 49.22 seconds
Started Apr 15 01:19:08 PM PDT 24
Finished Apr 15 01:19:58 PM PDT 24
Peak memory 216288 kb
Host smart-8bd8a164-da44-4002-87b4-f64493ec3537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061541340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.3061541340
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.110929510
Short name T561
Test name
Test status
Simulation time 15307328003 ps
CPU time 22.03 seconds
Started Apr 15 01:19:07 PM PDT 24
Finished Apr 15 01:19:30 PM PDT 24
Peak memory 216204 kb
Host smart-dc13ab85-c684-460c-8a3e-edb354bd6368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110929510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.110929510
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.2870522834
Short name T448
Test name
Test status
Simulation time 314234367 ps
CPU time 3.59 seconds
Started Apr 15 01:19:11 PM PDT 24
Finished Apr 15 01:19:15 PM PDT 24
Peak memory 216260 kb
Host smart-eb388b04-6a96-4ef1-9bc1-9483c37a35f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870522834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.2870522834
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.2824474955
Short name T501
Test name
Test status
Simulation time 35862915 ps
CPU time 0.77 seconds
Started Apr 15 01:19:11 PM PDT 24
Finished Apr 15 01:19:12 PM PDT 24
Peak memory 205744 kb
Host smart-faeab948-cb40-4818-81c1-9794a5da2081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824474955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.2824474955
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.2616771433
Short name T336
Test name
Test status
Simulation time 19155220688 ps
CPU time 19.08 seconds
Started Apr 15 01:19:12 PM PDT 24
Finished Apr 15 01:19:31 PM PDT 24
Peak memory 224020 kb
Host smart-cae7e252-b266-4df7-9dc5-369352c74540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616771433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.2616771433
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.1961518463
Short name T475
Test name
Test status
Simulation time 36954724 ps
CPU time 0.74 seconds
Started Apr 15 01:19:23 PM PDT 24
Finished Apr 15 01:19:24 PM PDT 24
Peak memory 205328 kb
Host smart-ae84329c-37f2-4d92-9d52-98d904ac6608
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961518463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
1961518463
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.278796821
Short name T412
Test name
Test status
Simulation time 50838897 ps
CPU time 0.73 seconds
Started Apr 15 01:19:17 PM PDT 24
Finished Apr 15 01:19:19 PM PDT 24
Peak memory 205516 kb
Host smart-6e30e232-2d54-4e4a-a9bc-c43abebdaae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278796821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.278796821
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.3638216280
Short name T297
Test name
Test status
Simulation time 3315970931 ps
CPU time 41.39 seconds
Started Apr 15 01:19:17 PM PDT 24
Finished Apr 15 01:19:59 PM PDT 24
Peak memory 232624 kb
Host smart-cd2d5aa7-8e83-4630-b7d5-f77417e190e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638216280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.3638216280
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.580272766
Short name T224
Test name
Test status
Simulation time 756721882 ps
CPU time 9.67 seconds
Started Apr 15 01:19:16 PM PDT 24
Finished Apr 15 01:19:26 PM PDT 24
Peak memory 218736 kb
Host smart-4c74f6ed-3754-470a-b900-2b3e129ebc77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580272766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.580272766
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.3980200292
Short name T181
Test name
Test status
Simulation time 11387386876 ps
CPU time 38.06 seconds
Started Apr 15 01:19:16 PM PDT 24
Finished Apr 15 01:19:54 PM PDT 24
Peak memory 235992 kb
Host smart-b340b11d-803c-49ae-83ae-d35d744fcc71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980200292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.3980200292
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.3678779602
Short name T465
Test name
Test status
Simulation time 143150070 ps
CPU time 4.23 seconds
Started Apr 15 01:19:18 PM PDT 24
Finished Apr 15 01:19:23 PM PDT 24
Peak memory 220032 kb
Host smart-4cc946e4-862c-41e6-86b2-d9424d9a1e1c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3678779602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.3678779602
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.3001462924
Short name T598
Test name
Test status
Simulation time 3000373742 ps
CPU time 10.45 seconds
Started Apr 15 01:19:18 PM PDT 24
Finished Apr 15 01:19:29 PM PDT 24
Peak memory 216360 kb
Host smart-7b25eba6-21d3-44d9-b32b-4b39c01bbf1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001462924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.3001462924
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.1346075238
Short name T536
Test name
Test status
Simulation time 105493497 ps
CPU time 1.13 seconds
Started Apr 15 01:19:15 PM PDT 24
Finished Apr 15 01:19:16 PM PDT 24
Peak memory 206720 kb
Host smart-048e32f9-27ec-4964-aada-eb83f5d652f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346075238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.1346075238
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.4264098136
Short name T471
Test name
Test status
Simulation time 192421724 ps
CPU time 0.74 seconds
Started Apr 15 01:19:16 PM PDT 24
Finished Apr 15 01:19:17 PM PDT 24
Peak memory 205692 kb
Host smart-32151d21-22d5-44cb-b91b-c353fb10af99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264098136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.4264098136
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.3580294588
Short name T314
Test name
Test status
Simulation time 15854791073 ps
CPU time 43.21 seconds
Started Apr 15 01:19:15 PM PDT 24
Finished Apr 15 01:19:58 PM PDT 24
Peak memory 235700 kb
Host smart-4e91bec2-4bd4-497c-858a-6beb411962cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580294588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.3580294588
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.1883047572
Short name T567
Test name
Test status
Simulation time 12597053 ps
CPU time 0.72 seconds
Started Apr 15 01:19:30 PM PDT 24
Finished Apr 15 01:19:31 PM PDT 24
Peak memory 205664 kb
Host smart-e5d12fd9-e4b8-49b3-b4ac-033dc55bb808
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883047572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
1883047572
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.4270930886
Short name T10
Test name
Test status
Simulation time 18922480373 ps
CPU time 18.3 seconds
Started Apr 15 01:19:21 PM PDT 24
Finished Apr 15 01:19:40 PM PDT 24
Peak memory 217276 kb
Host smart-daf09af6-cb36-4d6c-8de0-82175ebd65e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270930886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.4270930886
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.1157704969
Short name T460
Test name
Test status
Simulation time 98364306 ps
CPU time 0.76 seconds
Started Apr 15 01:19:22 PM PDT 24
Finished Apr 15 01:19:23 PM PDT 24
Peak memory 205500 kb
Host smart-77060c19-ef3b-4ccc-be7a-eb7ba182d152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157704969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.1157704969
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.596516684
Short name T328
Test name
Test status
Simulation time 9622392476 ps
CPU time 25.26 seconds
Started Apr 15 01:19:22 PM PDT 24
Finished Apr 15 01:19:48 PM PDT 24
Peak memory 222832 kb
Host smart-dcdba428-bd2d-49c4-8dee-9621573c0217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596516684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.596516684
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.4288364769
Short name T11
Test name
Test status
Simulation time 98075031 ps
CPU time 4.29 seconds
Started Apr 15 01:19:20 PM PDT 24
Finished Apr 15 01:19:24 PM PDT 24
Peak memory 222912 kb
Host smart-9ba7406e-8802-46a3-a62d-9b3bb9316f82
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4288364769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.4288364769
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.1676295752
Short name T502
Test name
Test status
Simulation time 82044367 ps
CPU time 1.01 seconds
Started Apr 15 01:19:30 PM PDT 24
Finished Apr 15 01:19:32 PM PDT 24
Peak memory 207120 kb
Host smart-b629f08b-48d7-45e0-bb24-13e3ea0c9e25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676295752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.1676295752
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.1903833366
Short name T495
Test name
Test status
Simulation time 3704865662 ps
CPU time 12.27 seconds
Started Apr 15 01:19:21 PM PDT 24
Finished Apr 15 01:19:34 PM PDT 24
Peak memory 216152 kb
Host smart-169d2671-d72f-43db-92de-e9466c64ceb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903833366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.1903833366
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.1669209929
Short name T450
Test name
Test status
Simulation time 595545655 ps
CPU time 1.91 seconds
Started Apr 15 01:19:21 PM PDT 24
Finished Apr 15 01:19:24 PM PDT 24
Peak memory 216260 kb
Host smart-b8145dc8-9ac2-4c4a-b77e-38ac92a9afd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669209929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.1669209929
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.2875361285
Short name T615
Test name
Test status
Simulation time 56199902 ps
CPU time 0.94 seconds
Started Apr 15 01:19:27 PM PDT 24
Finished Apr 15 01:19:28 PM PDT 24
Peak memory 206752 kb
Host smart-7f7229e3-9234-4fad-b8e9-57b67a560d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875361285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.2875361285
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.931052148
Short name T16
Test name
Test status
Simulation time 28953699 ps
CPU time 0.69 seconds
Started Apr 15 01:19:27 PM PDT 24
Finished Apr 15 01:19:28 PM PDT 24
Peak memory 204764 kb
Host smart-e64e6327-cc66-4c10-8951-d3fa351a36e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931052148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.931052148
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.4276180140
Short name T506
Test name
Test status
Simulation time 99857395 ps
CPU time 3.33 seconds
Started Apr 15 01:19:25 PM PDT 24
Finished Apr 15 01:19:29 PM PDT 24
Peak memory 222848 kb
Host smart-5a853ab4-6d8c-4116-b712-ca2c0d32108a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276180140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.4276180140
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.4074335295
Short name T602
Test name
Test status
Simulation time 63395380 ps
CPU time 0.75 seconds
Started Apr 15 01:19:24 PM PDT 24
Finished Apr 15 01:19:25 PM PDT 24
Peak memory 206732 kb
Host smart-5e3490bb-b04d-4eb7-a0b0-83d23a73ece0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074335295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.4074335295
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.3738676676
Short name T468
Test name
Test status
Simulation time 1361870963 ps
CPU time 16.06 seconds
Started Apr 15 01:19:24 PM PDT 24
Finished Apr 15 01:19:41 PM PDT 24
Peak memory 219744 kb
Host smart-0b40ef3b-c67f-47a3-9eca-e2b7c0646b97
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3738676676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.3738676676
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.3716792082
Short name T678
Test name
Test status
Simulation time 4831526646 ps
CPU time 15.41 seconds
Started Apr 15 01:19:26 PM PDT 24
Finished Apr 15 01:19:42 PM PDT 24
Peak memory 216272 kb
Host smart-163afcfb-37c6-4bc2-82c7-6b919141e27e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716792082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.3716792082
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.530895468
Short name T402
Test name
Test status
Simulation time 25855437 ps
CPU time 0.99 seconds
Started Apr 15 01:19:25 PM PDT 24
Finished Apr 15 01:19:26 PM PDT 24
Peak memory 206880 kb
Host smart-56924efc-5ad0-45fb-87fe-39dda93c4eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530895468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.530895468
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.1178810454
Short name T436
Test name
Test status
Simulation time 214773628 ps
CPU time 0.92 seconds
Started Apr 15 01:19:28 PM PDT 24
Finished Apr 15 01:19:30 PM PDT 24
Peak memory 206740 kb
Host smart-8749f116-3dd7-4380-aa83-6401dd55409d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178810454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.1178810454
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.2904751930
Short name T572
Test name
Test status
Simulation time 24876972 ps
CPU time 0.74 seconds
Started Apr 15 01:19:29 PM PDT 24
Finished Apr 15 01:19:31 PM PDT 24
Peak memory 205300 kb
Host smart-58910125-f809-42c5-a49a-b21cd591c578
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904751930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
2904751930
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.1455566937
Short name T549
Test name
Test status
Simulation time 55630441 ps
CPU time 0.74 seconds
Started Apr 15 01:19:26 PM PDT 24
Finished Apr 15 01:19:27 PM PDT 24
Peak memory 205964 kb
Host smart-f5641624-a4ca-4ba4-95f1-4ef13274d244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455566937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.1455566937
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.314483599
Short name T300
Test name
Test status
Simulation time 3846627081 ps
CPU time 13.91 seconds
Started Apr 15 01:19:27 PM PDT 24
Finished Apr 15 01:19:41 PM PDT 24
Peak memory 232648 kb
Host smart-4e90405c-7201-407e-970f-719114b33dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314483599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.314483599
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.2977978671
Short name T341
Test name
Test status
Simulation time 16419262260 ps
CPU time 10.52 seconds
Started Apr 15 01:19:29 PM PDT 24
Finished Apr 15 01:19:40 PM PDT 24
Peak memory 232684 kb
Host smart-79a6a4fe-ff4b-49fe-8bde-2a70167dc3f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977978671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.2977978671
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.3086324430
Short name T325
Test name
Test status
Simulation time 515798363 ps
CPU time 3.05 seconds
Started Apr 15 01:19:30 PM PDT 24
Finished Apr 15 01:19:34 PM PDT 24
Peak memory 218540 kb
Host smart-ebdfcc51-da6d-4abe-945d-7ed5713b8b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086324430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.3086324430
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.15715557
Short name T705
Test name
Test status
Simulation time 87683316 ps
CPU time 4.48 seconds
Started Apr 15 01:19:29 PM PDT 24
Finished Apr 15 01:19:34 PM PDT 24
Peak memory 222880 kb
Host smart-37d977e6-210b-4b5e-8b92-c104818c48ff
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=15715557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_direc
t.15715557
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.1803460902
Short name T380
Test name
Test status
Simulation time 4204810507 ps
CPU time 34.1 seconds
Started Apr 15 01:19:30 PM PDT 24
Finished Apr 15 01:20:05 PM PDT 24
Peak memory 216404 kb
Host smart-6422520e-2407-41d6-a5a4-6d58d2960ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803460902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.1803460902
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.4006719945
Short name T576
Test name
Test status
Simulation time 34760447491 ps
CPU time 13.39 seconds
Started Apr 15 01:19:25 PM PDT 24
Finished Apr 15 01:19:39 PM PDT 24
Peak memory 216212 kb
Host smart-402cca4a-c468-4fbd-a1bb-bbe5f131a6b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006719945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.4006719945
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.3717045372
Short name T405
Test name
Test status
Simulation time 558679101 ps
CPU time 10.12 seconds
Started Apr 15 01:19:34 PM PDT 24
Finished Apr 15 01:19:45 PM PDT 24
Peak memory 216264 kb
Host smart-fc9690bd-3ae1-44af-8a64-d45f16dad008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717045372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.3717045372
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.3727877160
Short name T532
Test name
Test status
Simulation time 144758087 ps
CPU time 0.84 seconds
Started Apr 15 01:19:29 PM PDT 24
Finished Apr 15 01:19:31 PM PDT 24
Peak memory 205672 kb
Host smart-e1964f63-edfe-4632-8d02-10d2d611841b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727877160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.3727877160
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.1898176041
Short name T320
Test name
Test status
Simulation time 1392758327 ps
CPU time 4.77 seconds
Started Apr 15 01:19:34 PM PDT 24
Finished Apr 15 01:19:39 PM PDT 24
Peak memory 224448 kb
Host smart-94f51651-5b65-480b-9df2-e27a29a527c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898176041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.1898176041
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.4283614929
Short name T658
Test name
Test status
Simulation time 29322361 ps
CPU time 0.71 seconds
Started Apr 15 01:19:34 PM PDT 24
Finished Apr 15 01:19:35 PM PDT 24
Peak memory 205684 kb
Host smart-d620489e-85c3-4f6e-9b67-a3935be3e0a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283614929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
4283614929
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.2492086944
Short name T688
Test name
Test status
Simulation time 16370920 ps
CPU time 0.81 seconds
Started Apr 15 01:19:34 PM PDT 24
Finished Apr 15 01:19:36 PM PDT 24
Peak memory 206832 kb
Host smart-48152ddb-736e-4a13-9db6-873841c31cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492086944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2492086944
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.439379714
Short name T195
Test name
Test status
Simulation time 11356344024 ps
CPU time 21.62 seconds
Started Apr 15 01:19:33 PM PDT 24
Finished Apr 15 01:19:55 PM PDT 24
Peak memory 221408 kb
Host smart-88cd4817-447b-48b5-8c34-fae7e5cca1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439379714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.439379714
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.1905546721
Short name T570
Test name
Test status
Simulation time 851042199 ps
CPU time 13.92 seconds
Started Apr 15 01:19:33 PM PDT 24
Finished Apr 15 01:19:47 PM PDT 24
Peak memory 220116 kb
Host smart-767b986a-70b9-4e6f-8afb-8532d115ec2a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1905546721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.1905546721
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.1055447174
Short name T364
Test name
Test status
Simulation time 197724499 ps
CPU time 1.04 seconds
Started Apr 15 01:19:33 PM PDT 24
Finished Apr 15 01:19:34 PM PDT 24
Peak memory 206992 kb
Host smart-0cdde448-3028-4cbd-94cc-287267646d70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055447174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.1055447174
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.3497677416
Short name T714
Test name
Test status
Simulation time 5702859794 ps
CPU time 22.99 seconds
Started Apr 15 01:19:31 PM PDT 24
Finished Apr 15 01:19:55 PM PDT 24
Peak memory 216312 kb
Host smart-b91850f7-b194-4664-afe2-6cee47f26877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497677416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3497677416
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.443671557
Short name T550
Test name
Test status
Simulation time 1210154765 ps
CPU time 5.53 seconds
Started Apr 15 01:19:28 PM PDT 24
Finished Apr 15 01:19:34 PM PDT 24
Peak memory 216172 kb
Host smart-6417ccb2-9a01-4912-b760-bf31a4533b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443671557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.443671557
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.3823298261
Short name T539
Test name
Test status
Simulation time 48528119 ps
CPU time 0.97 seconds
Started Apr 15 01:19:29 PM PDT 24
Finished Apr 15 01:19:31 PM PDT 24
Peak memory 207568 kb
Host smart-fb8c0f98-a977-45e7-993c-394821b8c98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823298261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.3823298261
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.3981734429
Short name T548
Test name
Test status
Simulation time 159780550 ps
CPU time 1.11 seconds
Started Apr 15 01:19:34 PM PDT 24
Finished Apr 15 01:19:36 PM PDT 24
Peak memory 206744 kb
Host smart-0c4f6e7d-102b-4bf6-8bb6-f1dbe11fec42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981734429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.3981734429
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.609940156
Short name T250
Test name
Test status
Simulation time 282885380 ps
CPU time 3.38 seconds
Started Apr 15 01:19:35 PM PDT 24
Finished Apr 15 01:19:39 PM PDT 24
Peak memory 222008 kb
Host smart-0b323c57-eb8a-4638-943e-ad055668b55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609940156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.609940156
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.2907740733
Short name T466
Test name
Test status
Simulation time 15716829 ps
CPU time 0.74 seconds
Started Apr 15 01:19:37 PM PDT 24
Finished Apr 15 01:19:39 PM PDT 24
Peak memory 205336 kb
Host smart-74391dd2-9692-4825-a571-09125e648991
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907740733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
2907740733
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.898137420
Short name T518
Test name
Test status
Simulation time 69621025 ps
CPU time 0.81 seconds
Started Apr 15 01:19:35 PM PDT 24
Finished Apr 15 01:19:36 PM PDT 24
Peak memory 206524 kb
Host smart-690d68e5-3f0a-4b40-bc3b-9a214a89201e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898137420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.898137420
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.3893853446
Short name T620
Test name
Test status
Simulation time 3126138379 ps
CPU time 13.55 seconds
Started Apr 15 01:19:37 PM PDT 24
Finished Apr 15 01:19:51 PM PDT 24
Peak memory 249024 kb
Host smart-593b3d6a-6312-47a1-b1a1-46ea40e86043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893853446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.3893853446
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.448860636
Short name T44
Test name
Test status
Simulation time 3436866595 ps
CPU time 30.65 seconds
Started Apr 15 01:19:31 PM PDT 24
Finished Apr 15 01:20:02 PM PDT 24
Peak memory 223792 kb
Host smart-a8b621fa-2028-4f4f-baef-171b20289205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448860636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.448860636
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.2219476894
Short name T613
Test name
Test status
Simulation time 172170428 ps
CPU time 3.65 seconds
Started Apr 15 01:19:36 PM PDT 24
Finished Apr 15 01:19:40 PM PDT 24
Peak memory 220364 kb
Host smart-ade0b895-d723-4ad3-a709-ff3ca19a91e1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2219476894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.2219476894
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.3116660727
Short name T699
Test name
Test status
Simulation time 19163983914 ps
CPU time 37.47 seconds
Started Apr 15 01:19:37 PM PDT 24
Finished Apr 15 01:20:16 PM PDT 24
Peak memory 216324 kb
Host smart-beb72d22-519f-40e0-a8dc-8808c4058d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116660727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.3116660727
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.4064409490
Short name T547
Test name
Test status
Simulation time 4116925536 ps
CPU time 6.42 seconds
Started Apr 15 01:19:32 PM PDT 24
Finished Apr 15 01:19:39 PM PDT 24
Peak memory 216260 kb
Host smart-9172a642-38c1-49d6-a853-8f68e57a1c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064409490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.4064409490
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.1217697354
Short name T645
Test name
Test status
Simulation time 4315504357 ps
CPU time 4.1 seconds
Started Apr 15 01:19:33 PM PDT 24
Finished Apr 15 01:19:37 PM PDT 24
Peak memory 216264 kb
Host smart-43460786-6d8d-47b4-b6cd-75d77eb92c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217697354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.1217697354
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.2965918393
Short name T13
Test name
Test status
Simulation time 99849380 ps
CPU time 1.02 seconds
Started Apr 15 01:19:35 PM PDT 24
Finished Apr 15 01:19:36 PM PDT 24
Peak memory 206108 kb
Host smart-318fb168-ce72-4958-aea6-ec9f08086991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965918393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.2965918393
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.1439835812
Short name T116
Test name
Test status
Simulation time 8497368884 ps
CPU time 6.09 seconds
Started Apr 15 01:19:38 PM PDT 24
Finished Apr 15 01:19:44 PM PDT 24
Peak memory 224424 kb
Host smart-d6efce8f-fe50-4c6e-b471-71b7bb96df07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439835812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.1439835812
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.3664265948
Short name T519
Test name
Test status
Simulation time 16859579 ps
CPU time 0.75 seconds
Started Apr 15 01:18:35 PM PDT 24
Finished Apr 15 01:18:36 PM PDT 24
Peak memory 205436 kb
Host smart-b64cc84c-eea6-4a74-98b7-0ff9521a53b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664265948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.3664265948
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.4283763986
Short name T335
Test name
Test status
Simulation time 1177147766 ps
CPU time 3.37 seconds
Started Apr 15 01:18:34 PM PDT 24
Finished Apr 15 01:18:38 PM PDT 24
Peak memory 218236 kb
Host smart-4468905b-1a63-4d11-9b16-3f746faa100b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283763986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.4283763986
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.843391146
Short name T664
Test name
Test status
Simulation time 4748236262 ps
CPU time 13.08 seconds
Started Apr 15 01:18:40 PM PDT 24
Finished Apr 15 01:18:53 PM PDT 24
Peak memory 222948 kb
Host smart-e68405cb-5190-44e5-906b-61a97057fc89
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=843391146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direc
t.843391146
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.831139842
Short name T47
Test name
Test status
Simulation time 234231086 ps
CPU time 1.12 seconds
Started Apr 15 01:18:35 PM PDT 24
Finished Apr 15 01:18:37 PM PDT 24
Peak memory 234892 kb
Host smart-610de1f6-abcd-43b5-a47a-36b05dfef0b4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831139842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.831139842
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.269075937
Short name T529
Test name
Test status
Simulation time 15062891926 ps
CPU time 34.55 seconds
Started Apr 15 01:18:29 PM PDT 24
Finished Apr 15 01:19:04 PM PDT 24
Peak memory 216332 kb
Host smart-ef744c9d-adc9-4ae0-81e3-23596562ff3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269075937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.269075937
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.1451843377
Short name T711
Test name
Test status
Simulation time 22943778335 ps
CPU time 11.47 seconds
Started Apr 15 01:18:33 PM PDT 24
Finished Apr 15 01:18:45 PM PDT 24
Peak memory 216284 kb
Host smart-b616ec20-70d5-4787-ab27-ae37a2a2916a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451843377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.1451843377
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.985581684
Short name T461
Test name
Test status
Simulation time 201689024 ps
CPU time 2.61 seconds
Started Apr 15 01:18:36 PM PDT 24
Finished Apr 15 01:18:39 PM PDT 24
Peak memory 216228 kb
Host smart-6041b00c-b2ac-456c-9744-92e46703f6c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985581684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.985581684
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.1576095690
Short name T23
Test name
Test status
Simulation time 54543235 ps
CPU time 0.73 seconds
Started Apr 15 01:18:32 PM PDT 24
Finished Apr 15 01:18:33 PM PDT 24
Peak memory 205704 kb
Host smart-fb481291-55b4-4af1-8075-6efdf6fa90c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576095690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.1576095690
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.3292965290
Short name T463
Test name
Test status
Simulation time 39948161 ps
CPU time 0.71 seconds
Started Apr 15 01:19:45 PM PDT 24
Finished Apr 15 01:19:46 PM PDT 24
Peak memory 205344 kb
Host smart-b8fc47f8-587b-4256-a7f6-f1adecee07ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292965290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
3292965290
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.2306461607
Short name T421
Test name
Test status
Simulation time 23054920 ps
CPU time 0.76 seconds
Started Apr 15 01:19:36 PM PDT 24
Finished Apr 15 01:19:37 PM PDT 24
Peak memory 206496 kb
Host smart-faa35dc0-51ec-4ab9-8bce-1f9f3326e57d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306461607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.2306461607
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.200415317
Short name T659
Test name
Test status
Simulation time 11734632013 ps
CPU time 81.26 seconds
Started Apr 15 01:19:40 PM PDT 24
Finished Apr 15 01:21:02 PM PDT 24
Peak memory 255604 kb
Host smart-2b97668d-d197-43f2-9f13-07712b615810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200415317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.200415317
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.3736474034
Short name T107
Test name
Test status
Simulation time 523320963 ps
CPU time 3.79 seconds
Started Apr 15 01:19:40 PM PDT 24
Finished Apr 15 01:19:44 PM PDT 24
Peak memory 218592 kb
Host smart-2e2d6ac8-278c-4c0f-bf51-8fe564e729d3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3736474034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.3736474034
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.1445479665
Short name T385
Test name
Test status
Simulation time 1253253646 ps
CPU time 14.18 seconds
Started Apr 15 01:19:39 PM PDT 24
Finished Apr 15 01:19:53 PM PDT 24
Peak memory 219288 kb
Host smart-86e57dcb-f65f-4ad4-b98b-5286839e8dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445479665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.1445479665
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.1385275299
Short name T485
Test name
Test status
Simulation time 1782886172 ps
CPU time 9 seconds
Started Apr 15 01:19:37 PM PDT 24
Finished Apr 15 01:19:46 PM PDT 24
Peak memory 216336 kb
Host smart-25d6f241-cbbb-42d2-b90b-b00101e91e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385275299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.1385275299
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.1095172888
Short name T464
Test name
Test status
Simulation time 45688917 ps
CPU time 1.76 seconds
Started Apr 15 01:19:41 PM PDT 24
Finished Apr 15 01:19:43 PM PDT 24
Peak memory 216232 kb
Host smart-fd1bb0be-ad4b-4a11-af4a-6325316cd908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095172888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.1095172888
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.1454518185
Short name T482
Test name
Test status
Simulation time 217508511 ps
CPU time 1.24 seconds
Started Apr 15 01:19:38 PM PDT 24
Finished Apr 15 01:19:40 PM PDT 24
Peak memory 206744 kb
Host smart-9fbb80e8-134f-428b-83c5-71c694066a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454518185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.1454518185
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.2325628851
Short name T183
Test name
Test status
Simulation time 29790133087 ps
CPU time 51.74 seconds
Started Apr 15 01:19:41 PM PDT 24
Finished Apr 15 01:20:33 PM PDT 24
Peak memory 225784 kb
Host smart-920a7a0c-dd31-4d8f-873a-95791ae80b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325628851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.2325628851
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.1759142497
Short name T697
Test name
Test status
Simulation time 26385557 ps
CPU time 0.67 seconds
Started Apr 15 01:19:47 PM PDT 24
Finished Apr 15 01:19:48 PM PDT 24
Peak memory 204836 kb
Host smart-7e4a3ed6-8881-4901-9aec-289ae029ebec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759142497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
1759142497
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.163259529
Short name T484
Test name
Test status
Simulation time 15014834 ps
CPU time 0.76 seconds
Started Apr 15 01:19:41 PM PDT 24
Finished Apr 15 01:19:42 PM PDT 24
Peak memory 206528 kb
Host smart-3d5473c1-f3d7-41c1-910e-d759a03ea84a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163259529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.163259529
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.3488862405
Short name T307
Test name
Test status
Simulation time 112004096641 ps
CPU time 131.15 seconds
Started Apr 15 01:19:47 PM PDT 24
Finished Apr 15 01:21:58 PM PDT 24
Peak memory 240840 kb
Host smart-a617a2a9-e089-40d9-98b7-26e2214d9a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488862405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.3488862405
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.934236995
Short name T114
Test name
Test status
Simulation time 8498781733 ps
CPU time 19.77 seconds
Started Apr 15 01:19:42 PM PDT 24
Finished Apr 15 01:20:02 PM PDT 24
Peak memory 219016 kb
Host smart-9b899696-3e13-4494-9910-e5b7f5ae9d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934236995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.934236995
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.1749098988
Short name T338
Test name
Test status
Simulation time 12876822266 ps
CPU time 35.11 seconds
Started Apr 15 01:19:42 PM PDT 24
Finished Apr 15 01:20:17 PM PDT 24
Peak memory 235328 kb
Host smart-c3ab5a92-a54f-4eb3-a044-1faab7cb2958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749098988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.1749098988
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.2378002956
Short name T227
Test name
Test status
Simulation time 220551123 ps
CPU time 3.1 seconds
Started Apr 15 01:19:41 PM PDT 24
Finished Apr 15 01:19:44 PM PDT 24
Peak memory 218588 kb
Host smart-b40e7da4-75e2-4308-a4e4-43882f52bbfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378002956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.2378002956
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.2411629822
Short name T534
Test name
Test status
Simulation time 4772710613 ps
CPU time 18.67 seconds
Started Apr 15 01:19:44 PM PDT 24
Finished Apr 15 01:20:03 PM PDT 24
Peak memory 219080 kb
Host smart-0994f933-5364-4ef0-a920-87f5cd7e2a5f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2411629822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.2411629822
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.3263111466
Short name T392
Test name
Test status
Simulation time 51591179984 ps
CPU time 73.64 seconds
Started Apr 15 01:19:40 PM PDT 24
Finished Apr 15 01:20:54 PM PDT 24
Peak memory 216224 kb
Host smart-fa3bf464-a791-4fb2-921e-53776e43ff52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263111466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3263111466
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.3416575956
Short name T163
Test name
Test status
Simulation time 10813202402 ps
CPU time 9.27 seconds
Started Apr 15 01:19:42 PM PDT 24
Finished Apr 15 01:19:52 PM PDT 24
Peak memory 216284 kb
Host smart-8a3c5a28-6dcc-4eaf-9638-f0def5100e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416575956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.3416575956
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.494711846
Short name T537
Test name
Test status
Simulation time 16405962 ps
CPU time 1.09 seconds
Started Apr 15 01:19:40 PM PDT 24
Finished Apr 15 01:19:42 PM PDT 24
Peak memory 216016 kb
Host smart-b2d1cd0c-0a2a-4c61-ac4f-687941f6a8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494711846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.494711846
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.2381534191
Short name T105
Test name
Test status
Simulation time 85981918 ps
CPU time 0.82 seconds
Started Apr 15 01:19:41 PM PDT 24
Finished Apr 15 01:19:42 PM PDT 24
Peak memory 205716 kb
Host smart-6427ca32-fd9d-4b1b-ac28-f636d1e7b6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381534191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.2381534191
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.349167294
Short name T221
Test name
Test status
Simulation time 5457627081 ps
CPU time 19 seconds
Started Apr 15 01:19:47 PM PDT 24
Finished Apr 15 01:20:07 PM PDT 24
Peak memory 232696 kb
Host smart-60bcb2a8-7a29-476e-9d65-4f498b758882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349167294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.349167294
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.3597865798
Short name T408
Test name
Test status
Simulation time 64443968 ps
CPU time 0.76 seconds
Started Apr 15 01:19:50 PM PDT 24
Finished Apr 15 01:19:51 PM PDT 24
Peak memory 204812 kb
Host smart-3624bff7-3888-4a89-ace9-ee128184ffc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597865798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
3597865798
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.2001236299
Short name T614
Test name
Test status
Simulation time 68753575 ps
CPU time 0.79 seconds
Started Apr 15 01:19:47 PM PDT 24
Finished Apr 15 01:19:48 PM PDT 24
Peak memory 206528 kb
Host smart-31201082-81b8-49a4-ad52-57cefe558295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001236299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.2001236299
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.1993905803
Short name T302
Test name
Test status
Simulation time 5988254694 ps
CPU time 54.14 seconds
Started Apr 15 01:19:50 PM PDT 24
Finished Apr 15 01:20:45 PM PDT 24
Peak memory 255140 kb
Host smart-1f70bb11-8390-41d4-adaa-b83078e7c18e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993905803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.1993905803
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.3740791363
Short name T322
Test name
Test status
Simulation time 5633396477 ps
CPU time 8.94 seconds
Started Apr 15 01:19:47 PM PDT 24
Finished Apr 15 01:19:57 PM PDT 24
Peak memory 222920 kb
Host smart-921f9e45-2641-4031-8bb1-8399a7993280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740791363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.3740791363
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.1153934850
Short name T148
Test name
Test status
Simulation time 220939583 ps
CPU time 5.5 seconds
Started Apr 15 01:19:50 PM PDT 24
Finished Apr 15 01:19:56 PM PDT 24
Peak memory 222360 kb
Host smart-880b7b13-cf1f-44a0-8b77-b06cb0d0f9ea
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1153934850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.1153934850
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.101211377
Short name T686
Test name
Test status
Simulation time 1146383237 ps
CPU time 4.3 seconds
Started Apr 15 01:19:44 PM PDT 24
Finished Apr 15 01:19:49 PM PDT 24
Peak memory 216172 kb
Host smart-68d209db-bb59-4365-a03d-6c7a9973d157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101211377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.101211377
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.2807815075
Short name T500
Test name
Test status
Simulation time 649470413 ps
CPU time 6.68 seconds
Started Apr 15 01:19:47 PM PDT 24
Finished Apr 15 01:19:54 PM PDT 24
Peak memory 216120 kb
Host smart-3f6675d5-9af5-49c0-b40b-584e84857c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807815075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.2807815075
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.3584645803
Short name T617
Test name
Test status
Simulation time 422769365 ps
CPU time 0.99 seconds
Started Apr 15 01:19:45 PM PDT 24
Finished Apr 15 01:19:46 PM PDT 24
Peak memory 206732 kb
Host smart-916f6637-58d6-4d4a-86f7-02ccb2e9fda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584645803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.3584645803
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.2739593805
Short name T516
Test name
Test status
Simulation time 11472825 ps
CPU time 0.77 seconds
Started Apr 15 01:19:57 PM PDT 24
Finished Apr 15 01:19:58 PM PDT 24
Peak memory 205300 kb
Host smart-861c4989-e087-41d2-a624-ea0f1ea3cd8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739593805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
2739593805
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.1038821393
Short name T440
Test name
Test status
Simulation time 17092350 ps
CPU time 0.78 seconds
Started Apr 15 01:19:49 PM PDT 24
Finished Apr 15 01:19:51 PM PDT 24
Peak memory 206832 kb
Host smart-c4ad1029-0c32-4b7f-845b-bb6092508835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038821393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.1038821393
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.2262017901
Short name T361
Test name
Test status
Simulation time 8975507445 ps
CPU time 107.57 seconds
Started Apr 15 01:19:53 PM PDT 24
Finished Apr 15 01:21:41 PM PDT 24
Peak memory 252252 kb
Host smart-ce219e7d-99f9-4b2e-a10c-69873da98870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262017901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.2262017901
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.1810567937
Short name T334
Test name
Test status
Simulation time 273065319 ps
CPU time 3.72 seconds
Started Apr 15 01:19:52 PM PDT 24
Finished Apr 15 01:19:56 PM PDT 24
Peak memory 217204 kb
Host smart-6e0b9473-a18e-4f07-a386-ed091da4edcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810567937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.1810567937
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.4075831772
Short name T413
Test name
Test status
Simulation time 895531915 ps
CPU time 4.4 seconds
Started Apr 15 01:19:54 PM PDT 24
Finished Apr 15 01:19:58 PM PDT 24
Peak memory 221912 kb
Host smart-3d3151e4-b6d9-486a-8fb0-7c8c383446e5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4075831772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.4075831772
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.4068182138
Short name T625
Test name
Test status
Simulation time 1999346033 ps
CPU time 4.5 seconds
Started Apr 15 01:19:50 PM PDT 24
Finished Apr 15 01:19:55 PM PDT 24
Peak memory 216380 kb
Host smart-cb901072-91c8-4718-a54a-745ccadf1493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068182138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.4068182138
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.750929156
Short name T444
Test name
Test status
Simulation time 7387891722 ps
CPU time 12.46 seconds
Started Apr 15 01:19:50 PM PDT 24
Finished Apr 15 01:20:03 PM PDT 24
Peak memory 216228 kb
Host smart-16009b84-e830-42f3-b999-fddae0965b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750929156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.750929156
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.794571086
Short name T584
Test name
Test status
Simulation time 144600318 ps
CPU time 1.39 seconds
Started Apr 15 01:19:53 PM PDT 24
Finished Apr 15 01:19:55 PM PDT 24
Peak memory 208036 kb
Host smart-314a13a7-1710-4b07-92c9-774378139439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794571086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.794571086
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.2675584824
Short name T511
Test name
Test status
Simulation time 335144345 ps
CPU time 0.82 seconds
Started Apr 15 01:19:53 PM PDT 24
Finished Apr 15 01:19:55 PM PDT 24
Peak memory 205736 kb
Host smart-c34dad8a-eb4c-4858-b4ce-692c70e5483f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675584824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.2675584824
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.3195586795
Short name T213
Test name
Test status
Simulation time 6165508864 ps
CPU time 18.05 seconds
Started Apr 15 01:19:52 PM PDT 24
Finished Apr 15 01:20:10 PM PDT 24
Peak memory 220432 kb
Host smart-467adc76-4db4-4676-857e-df58cea9336d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195586795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.3195586795
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.2567668904
Short name T624
Test name
Test status
Simulation time 16623318 ps
CPU time 0.74 seconds
Started Apr 15 01:20:07 PM PDT 24
Finished Apr 15 01:20:09 PM PDT 24
Peak memory 205680 kb
Host smart-043c38e1-f20c-473c-a84a-d48f915dee59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567668904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
2567668904
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.1731816084
Short name T533
Test name
Test status
Simulation time 15784221 ps
CPU time 0.73 seconds
Started Apr 15 01:19:58 PM PDT 24
Finished Apr 15 01:19:59 PM PDT 24
Peak memory 205816 kb
Host smart-30da865f-4b0a-446d-a012-a826b1e8c67e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731816084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1731816084
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.956705745
Short name T665
Test name
Test status
Simulation time 4836883028 ps
CPU time 73.36 seconds
Started Apr 15 01:20:01 PM PDT 24
Finished Apr 15 01:21:15 PM PDT 24
Peak memory 235624 kb
Host smart-b3f6b5b1-45ef-463e-ba91-7967ce2eb786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956705745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.956705745
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.2091996112
Short name T359
Test name
Test status
Simulation time 57951909 ps
CPU time 2.15 seconds
Started Apr 15 01:19:58 PM PDT 24
Finished Apr 15 01:20:01 PM PDT 24
Peak memory 218556 kb
Host smart-2d795dcf-95d4-468e-b786-1f3afeea57ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091996112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.2091996112
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.896499022
Short name T673
Test name
Test status
Simulation time 8459952049 ps
CPU time 81.14 seconds
Started Apr 15 01:19:58 PM PDT 24
Finished Apr 15 01:21:20 PM PDT 24
Peak memory 232016 kb
Host smart-aa2bf71d-6192-48e0-85db-7f908042f21f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896499022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.896499022
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.2363545543
Short name T442
Test name
Test status
Simulation time 318584907 ps
CPU time 3.79 seconds
Started Apr 15 01:20:08 PM PDT 24
Finished Apr 15 01:20:12 PM PDT 24
Peak memory 223060 kb
Host smart-588bd077-b544-489e-93d1-e33d7324b635
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2363545543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.2363545543
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.3930540710
Short name T707
Test name
Test status
Simulation time 23375931020 ps
CPU time 56.57 seconds
Started Apr 15 01:19:56 PM PDT 24
Finished Apr 15 01:20:53 PM PDT 24
Peak memory 216168 kb
Host smart-886b6a33-c975-4e3f-9ff2-f46ebc8bbe17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930540710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.3930540710
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.1305393678
Short name T478
Test name
Test status
Simulation time 904678215 ps
CPU time 6.5 seconds
Started Apr 15 01:20:02 PM PDT 24
Finished Apr 15 01:20:09 PM PDT 24
Peak memory 216128 kb
Host smart-71a3943b-47d5-4d41-92a6-0a16243564ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305393678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.1305393678
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.1248296385
Short name T12
Test name
Test status
Simulation time 20637040 ps
CPU time 0.83 seconds
Started Apr 15 01:19:57 PM PDT 24
Finished Apr 15 01:19:59 PM PDT 24
Peak memory 206808 kb
Host smart-853267c5-2cbd-41dc-9e93-299ed5121aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248296385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.1248296385
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.3994075764
Short name T414
Test name
Test status
Simulation time 216751484 ps
CPU time 1 seconds
Started Apr 15 01:20:02 PM PDT 24
Finished Apr 15 01:20:04 PM PDT 24
Peak memory 206696 kb
Host smart-2e789314-132c-418c-ba4c-a2a1867ade71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994075764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.3994075764
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.1111385675
Short name T194
Test name
Test status
Simulation time 1434549445 ps
CPU time 3 seconds
Started Apr 15 01:19:59 PM PDT 24
Finished Apr 15 01:20:03 PM PDT 24
Peak memory 222908 kb
Host smart-fc86c351-505d-455a-891a-b938e82574e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111385675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.1111385675
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.658355268
Short name T476
Test name
Test status
Simulation time 12523622 ps
CPU time 0.71 seconds
Started Apr 15 01:20:04 PM PDT 24
Finished Apr 15 01:20:06 PM PDT 24
Peak memory 205336 kb
Host smart-bfbba401-f4b2-4714-a74a-2498fdbdd915
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658355268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.658355268
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.509280059
Short name T717
Test name
Test status
Simulation time 8631581229 ps
CPU time 11.06 seconds
Started Apr 15 01:20:13 PM PDT 24
Finished Apr 15 01:20:24 PM PDT 24
Peak memory 232348 kb
Host smart-ff8f72ae-76bf-4f99-a0f7-b3bfa4cd5574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509280059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.509280059
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.413387801
Short name T24
Test name
Test status
Simulation time 48452269 ps
CPU time 0.78 seconds
Started Apr 15 01:20:04 PM PDT 24
Finished Apr 15 01:20:05 PM PDT 24
Peak memory 206828 kb
Host smart-9dcc3a31-b984-46f3-a51a-d464cceb2eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413387801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.413387801
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.1713097093
Short name T303
Test name
Test status
Simulation time 15878174068 ps
CPU time 43.12 seconds
Started Apr 15 01:20:06 PM PDT 24
Finished Apr 15 01:20:50 PM PDT 24
Peak memory 252904 kb
Host smart-f96776a3-4419-401c-b6af-ab7583f6454f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713097093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.1713097093
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.2784507564
Short name T594
Test name
Test status
Simulation time 989496708 ps
CPU time 13.02 seconds
Started Apr 15 01:20:06 PM PDT 24
Finished Apr 15 01:20:19 PM PDT 24
Peak memory 219300 kb
Host smart-d2bb8acb-9359-449d-843e-c48392c7ef2f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2784507564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.2784507564
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.1454647463
Short name T657
Test name
Test status
Simulation time 2979998627 ps
CPU time 43.58 seconds
Started Apr 15 01:20:05 PM PDT 24
Finished Apr 15 01:20:50 PM PDT 24
Peak memory 216272 kb
Host smart-4e8c342b-2b7b-41c5-b831-010bb1dcd83a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454647463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.1454647463
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.2204671864
Short name T439
Test name
Test status
Simulation time 1389367244 ps
CPU time 10.43 seconds
Started Apr 15 01:20:01 PM PDT 24
Finished Apr 15 01:20:12 PM PDT 24
Peak memory 216140 kb
Host smart-6120c48b-f236-42b4-97a4-dbd1eca6277c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204671864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.2204671864
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.1404846399
Short name T469
Test name
Test status
Simulation time 371183484 ps
CPU time 0.98 seconds
Started Apr 15 01:20:04 PM PDT 24
Finished Apr 15 01:20:06 PM PDT 24
Peak memory 206164 kb
Host smart-d8e16e6c-e0dd-42ca-bd40-75bb084768ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404846399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.1404846399
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.1267688471
Short name T695
Test name
Test status
Simulation time 8058718647 ps
CPU time 20.02 seconds
Started Apr 15 01:20:07 PM PDT 24
Finished Apr 15 01:20:27 PM PDT 24
Peak memory 220016 kb
Host smart-ddfc2bda-277c-4f99-b80b-6eaf9cc25fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267688471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.1267688471
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.917530804
Short name T710
Test name
Test status
Simulation time 81074326 ps
CPU time 0.74 seconds
Started Apr 15 01:20:11 PM PDT 24
Finished Apr 15 01:20:13 PM PDT 24
Peak memory 204812 kb
Host smart-1f003041-15f3-4111-bd85-98c51a5e0972
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917530804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.917530804
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.2295733630
Short name T210
Test name
Test status
Simulation time 1194225735 ps
CPU time 4.64 seconds
Started Apr 15 01:20:05 PM PDT 24
Finished Apr 15 01:20:11 PM PDT 24
Peak memory 223956 kb
Host smart-68b09140-6768-472a-9f2e-d7bb0968bf3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295733630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.2295733630
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.1551328984
Short name T17
Test name
Test status
Simulation time 177428487 ps
CPU time 0.76 seconds
Started Apr 15 01:20:12 PM PDT 24
Finished Apr 15 01:20:14 PM PDT 24
Peak memory 205808 kb
Host smart-07d4eb2e-41b3-4437-8d69-143077e41308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551328984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.1551328984
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.3418772870
Short name T80
Test name
Test status
Simulation time 2907668326 ps
CPU time 29.65 seconds
Started Apr 15 01:20:13 PM PDT 24
Finished Apr 15 01:20:43 PM PDT 24
Peak memory 248496 kb
Host smart-f5a6ffd8-e628-4b12-b366-f61444c212e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418772870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.3418772870
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.3707090027
Short name T167
Test name
Test status
Simulation time 6855854395 ps
CPU time 27.81 seconds
Started Apr 15 01:20:08 PM PDT 24
Finished Apr 15 01:20:37 PM PDT 24
Peak memory 224084 kb
Host smart-f18c1523-0866-46f4-bd8e-ec0ea41a934d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707090027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.3707090027
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.1458215230
Short name T266
Test name
Test status
Simulation time 713242113 ps
CPU time 14.83 seconds
Started Apr 15 01:20:06 PM PDT 24
Finished Apr 15 01:20:22 PM PDT 24
Peak memory 235992 kb
Host smart-5c6edaa2-6d3d-4f19-9d7e-eddac1ef5605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458215230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.1458215230
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.742284777
Short name T260
Test name
Test status
Simulation time 632349375 ps
CPU time 9.57 seconds
Started Apr 15 01:20:12 PM PDT 24
Finished Apr 15 01:20:22 PM PDT 24
Peak memory 232620 kb
Host smart-4bd1eeff-2333-49c8-9ba9-58ff6f53031d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742284777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.742284777
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.909946384
Short name T488
Test name
Test status
Simulation time 7483602498 ps
CPU time 9.7 seconds
Started Apr 15 01:20:04 PM PDT 24
Finished Apr 15 01:20:15 PM PDT 24
Peak memory 221992 kb
Host smart-2e191b20-6e9b-44f1-885e-520affe7dd6a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=909946384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dire
ct.909946384
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.3809451010
Short name T378
Test name
Test status
Simulation time 7585359405 ps
CPU time 41.28 seconds
Started Apr 15 01:20:05 PM PDT 24
Finished Apr 15 01:20:48 PM PDT 24
Peak memory 216224 kb
Host smart-e4031f7b-d86f-47b5-8019-5d0dd2832b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809451010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.3809451010
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.4183053447
Short name T543
Test name
Test status
Simulation time 7267320626 ps
CPU time 20.23 seconds
Started Apr 15 01:20:05 PM PDT 24
Finished Apr 15 01:20:26 PM PDT 24
Peak memory 216260 kb
Host smart-03339529-7a05-4416-80d8-c0e55a3b3cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183053447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.4183053447
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.597802159
Short name T53
Test name
Test status
Simulation time 71015937 ps
CPU time 0.8 seconds
Started Apr 15 01:20:12 PM PDT 24
Finished Apr 15 01:20:13 PM PDT 24
Peak memory 205740 kb
Host smart-1fbac882-4bb8-47b3-8c98-b7b28729a4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597802159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.597802159
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.3111480663
Short name T14
Test name
Test status
Simulation time 108442276 ps
CPU time 1.09 seconds
Started Apr 15 01:20:07 PM PDT 24
Finished Apr 15 01:20:09 PM PDT 24
Peak memory 206708 kb
Host smart-43e999d0-0aa2-4d59-bf8d-3976793ee094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111480663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.3111480663
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.2656032772
Short name T565
Test name
Test status
Simulation time 12437845 ps
CPU time 0.69 seconds
Started Apr 15 01:20:23 PM PDT 24
Finished Apr 15 01:20:24 PM PDT 24
Peak memory 205384 kb
Host smart-90ee584d-afba-4472-a563-310b574a1e40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656032772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
2656032772
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.2416260821
Short name T694
Test name
Test status
Simulation time 16832160 ps
CPU time 0.89 seconds
Started Apr 15 01:20:09 PM PDT 24
Finished Apr 15 01:20:10 PM PDT 24
Peak memory 206840 kb
Host smart-e7a2b77c-3a3b-45d4-a5aa-c74bb9308f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416260821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.2416260821
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_intercept.2534097911
Short name T316
Test name
Test status
Simulation time 97148794 ps
CPU time 3.66 seconds
Started Apr 15 01:20:23 PM PDT 24
Finished Apr 15 01:20:27 PM PDT 24
Peak memory 222728 kb
Host smart-58408f4b-c520-4bb4-8489-0f0fb319a326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534097911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.2534097911
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.1492400980
Short name T200
Test name
Test status
Simulation time 1173451840 ps
CPU time 6.73 seconds
Started Apr 15 01:20:25 PM PDT 24
Finished Apr 15 01:20:32 PM PDT 24
Peak memory 218608 kb
Host smart-faa4b5a3-8e13-4a44-875b-d2d7b27ec84f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492400980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.1492400980
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.1730047539
Short name T289
Test name
Test status
Simulation time 4894267497 ps
CPU time 6.29 seconds
Started Apr 15 01:20:08 PM PDT 24
Finished Apr 15 01:20:14 PM PDT 24
Peak memory 222252 kb
Host smart-4b5ef5b1-d892-410d-8051-3983db383560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730047539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.1730047539
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.1126422888
Short name T424
Test name
Test status
Simulation time 135684151 ps
CPU time 4.82 seconds
Started Apr 15 01:20:23 PM PDT 24
Finished Apr 15 01:20:29 PM PDT 24
Peak memory 222796 kb
Host smart-137d62ac-81ba-4f73-9f65-7ffb663d6f57
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1126422888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.1126422888
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.711310900
Short name T367
Test name
Test status
Simulation time 69116779 ps
CPU time 0.99 seconds
Started Apr 15 01:20:21 PM PDT 24
Finished Apr 15 01:20:22 PM PDT 24
Peak memory 206540 kb
Host smart-2ecd28d8-acb8-487e-a8d3-f1ed49a95875
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711310900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stres
s_all.711310900
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.3249876097
Short name T542
Test name
Test status
Simulation time 74084299 ps
CPU time 1.43 seconds
Started Apr 15 01:20:09 PM PDT 24
Finished Apr 15 01:20:11 PM PDT 24
Peak memory 216096 kb
Host smart-f8f61cf6-0930-49c8-a316-0a2f6900684b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249876097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.3249876097
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.950800619
Short name T417
Test name
Test status
Simulation time 140006948 ps
CPU time 1.05 seconds
Started Apr 15 01:20:13 PM PDT 24
Finished Apr 15 01:20:15 PM PDT 24
Peak memory 205704 kb
Host smart-31a13a43-5798-48e3-9b37-47dad71058b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950800619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.950800619
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.2367102803
Short name T85
Test name
Test status
Simulation time 1810586571 ps
CPU time 4.9 seconds
Started Apr 15 01:20:22 PM PDT 24
Finished Apr 15 01:20:27 PM PDT 24
Peak memory 219152 kb
Host smart-49a84133-e957-4e1c-b611-0e503843db39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367102803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.2367102803
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.4061473501
Short name T425
Test name
Test status
Simulation time 37325830 ps
CPU time 0.74 seconds
Started Apr 15 01:20:21 PM PDT 24
Finished Apr 15 01:20:22 PM PDT 24
Peak memory 205300 kb
Host smart-d2a1a0c7-91af-4e9c-ac7f-ccf11cbb6c46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061473501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
4061473501
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.356050094
Short name T87
Test name
Test status
Simulation time 71862007 ps
CPU time 2.58 seconds
Started Apr 15 01:20:20 PM PDT 24
Finished Apr 15 01:20:23 PM PDT 24
Peak memory 222772 kb
Host smart-e90ea21c-503d-449e-ae6d-04d51be24ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356050094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.356050094
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.4208013068
Short name T449
Test name
Test status
Simulation time 45220754 ps
CPU time 0.77 seconds
Started Apr 15 01:20:15 PM PDT 24
Finished Apr 15 01:20:16 PM PDT 24
Peak memory 206508 kb
Host smart-12b0d2f7-c2a9-4839-9152-9f4ca0fe18da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208013068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.4208013068
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.1914657884
Short name T358
Test name
Test status
Simulation time 10800306154 ps
CPU time 157.97 seconds
Started Apr 15 01:20:15 PM PDT 24
Finished Apr 15 01:22:54 PM PDT 24
Peak memory 250196 kb
Host smart-a220dbda-dbac-46a2-ae65-7b567932e758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914657884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.1914657884
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.516792155
Short name T192
Test name
Test status
Simulation time 375365532 ps
CPU time 3.22 seconds
Started Apr 15 01:20:12 PM PDT 24
Finished Apr 15 01:20:16 PM PDT 24
Peak memory 218648 kb
Host smart-cade5884-bed7-4638-9ee8-7bd49801842c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516792155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.516792155
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.2926500143
Short name T318
Test name
Test status
Simulation time 6921499159 ps
CPU time 20.84 seconds
Started Apr 15 01:20:23 PM PDT 24
Finished Apr 15 01:20:44 PM PDT 24
Peak memory 237864 kb
Host smart-aa15883a-52f3-45a8-82bf-612ac258564d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926500143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.2926500143
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.2684812009
Short name T233
Test name
Test status
Simulation time 8611843495 ps
CPU time 26.33 seconds
Started Apr 15 01:20:23 PM PDT 24
Finished Apr 15 01:20:50 PM PDT 24
Peak memory 231348 kb
Host smart-e7e16b0f-951c-4ff2-8ad6-01f08a852be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684812009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.2684812009
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.1905839111
Short name T553
Test name
Test status
Simulation time 9269120966 ps
CPU time 17.55 seconds
Started Apr 15 01:20:21 PM PDT 24
Finished Apr 15 01:20:39 PM PDT 24
Peak memory 218860 kb
Host smart-3a67a8be-c18b-488f-b46e-8f1b1d67ef42
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1905839111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.1905839111
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.3296971301
Short name T507
Test name
Test status
Simulation time 3536621550 ps
CPU time 9.47 seconds
Started Apr 15 01:20:24 PM PDT 24
Finished Apr 15 01:20:33 PM PDT 24
Peak memory 216212 kb
Host smart-124f0ebb-9912-46db-99f4-3954f05f3f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296971301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.3296971301
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.3754426753
Short name T15
Test name
Test status
Simulation time 125711745 ps
CPU time 3.49 seconds
Started Apr 15 01:20:21 PM PDT 24
Finished Apr 15 01:20:25 PM PDT 24
Peak memory 216268 kb
Host smart-35fd6e24-eeee-4199-a7be-97a10f051f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754426753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.3754426753
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.261089046
Short name T498
Test name
Test status
Simulation time 233807650 ps
CPU time 0.89 seconds
Started Apr 15 01:20:21 PM PDT 24
Finished Apr 15 01:20:22 PM PDT 24
Peak memory 205704 kb
Host smart-82d28606-281e-43a2-a1f7-d1f12edb2f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261089046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.261089046
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.625742098
Short name T312
Test name
Test status
Simulation time 6050849721 ps
CPU time 9.55 seconds
Started Apr 15 01:20:22 PM PDT 24
Finished Apr 15 01:20:32 PM PDT 24
Peak memory 237000 kb
Host smart-2260fcdc-a26b-481a-b3c0-9a38564d89cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625742098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.625742098
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.1014216650
Short name T433
Test name
Test status
Simulation time 35979225 ps
CPU time 0.7 seconds
Started Apr 15 01:20:25 PM PDT 24
Finished Apr 15 01:20:26 PM PDT 24
Peak memory 205384 kb
Host smart-86834d08-28e3-407c-ab73-5ca886e8cfd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014216650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
1014216650
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.3392168073
Short name T578
Test name
Test status
Simulation time 27646172 ps
CPU time 0.81 seconds
Started Apr 15 01:20:21 PM PDT 24
Finished Apr 15 01:20:22 PM PDT 24
Peak memory 206512 kb
Host smart-58b7fe70-ce77-4a6f-8082-9f6351c4df13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392168073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.3392168073
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.3438106251
Short name T622
Test name
Test status
Simulation time 11951592809 ps
CPU time 159.68 seconds
Started Apr 15 01:20:23 PM PDT 24
Finished Apr 15 01:23:04 PM PDT 24
Peak memory 248756 kb
Host smart-330102d2-919b-4e53-a8d9-7eb3430fe8f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438106251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.3438106251
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.3919072534
Short name T174
Test name
Test status
Simulation time 205749071 ps
CPU time 5.35 seconds
Started Apr 15 01:20:23 PM PDT 24
Finished Apr 15 01:20:29 PM PDT 24
Peak memory 224104 kb
Host smart-d533a35b-68ac-49d2-ac60-c0810349bd40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919072534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.3919072534
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.3264160883
Short name T188
Test name
Test status
Simulation time 6279793589 ps
CPU time 9.62 seconds
Started Apr 15 01:20:23 PM PDT 24
Finished Apr 15 01:20:33 PM PDT 24
Peak memory 237024 kb
Host smart-3287ab89-56f3-4859-aad7-562518d2f334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264160883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3264160883
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.3539017932
Short name T607
Test name
Test status
Simulation time 981083953 ps
CPU time 5.11 seconds
Started Apr 15 01:20:24 PM PDT 24
Finished Apr 15 01:20:30 PM PDT 24
Peak memory 219800 kb
Host smart-99a31de8-9fc0-4f02-968e-13ace4185d4a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3539017932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.3539017932
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.2758688680
Short name T32
Test name
Test status
Simulation time 219779621 ps
CPU time 1.03 seconds
Started Apr 15 01:20:24 PM PDT 24
Finished Apr 15 01:20:25 PM PDT 24
Peak memory 206512 kb
Host smart-b33feec3-5161-4b85-8db9-55183e796e79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758688680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.2758688680
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.1776514298
Short name T560
Test name
Test status
Simulation time 3497318418 ps
CPU time 16.93 seconds
Started Apr 15 01:20:22 PM PDT 24
Finished Apr 15 01:20:39 PM PDT 24
Peak memory 216324 kb
Host smart-786ff695-3b51-41b9-90ea-617249e7772f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776514298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.1776514298
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.644318426
Short name T423
Test name
Test status
Simulation time 4235328911 ps
CPU time 7.24 seconds
Started Apr 15 01:20:20 PM PDT 24
Finished Apr 15 01:20:27 PM PDT 24
Peak memory 216208 kb
Host smart-2ec6be01-84f2-4789-9bad-799eab50749d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644318426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.644318426
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.4275436073
Short name T522
Test name
Test status
Simulation time 684581292 ps
CPU time 3.5 seconds
Started Apr 15 01:20:20 PM PDT 24
Finished Apr 15 01:20:24 PM PDT 24
Peak memory 216144 kb
Host smart-addf9ac8-a81d-4782-9150-57ae0251faea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275436073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.4275436073
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.3646762185
Short name T631
Test name
Test status
Simulation time 102231505 ps
CPU time 0.78 seconds
Started Apr 15 01:20:21 PM PDT 24
Finished Apr 15 01:20:22 PM PDT 24
Peak memory 205708 kb
Host smart-5128197b-ccf0-4202-9bab-5a1a56f2b3cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646762185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.3646762185
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.2103573007
Short name T29
Test name
Test status
Simulation time 3312241552 ps
CPU time 7.95 seconds
Started Apr 15 01:20:26 PM PDT 24
Finished Apr 15 01:20:34 PM PDT 24
Peak memory 223168 kb
Host smart-9c12e1b2-2390-4f47-8c67-d3964cbd548f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103573007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.2103573007
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.3431090427
Short name T428
Test name
Test status
Simulation time 22188036 ps
CPU time 0.75 seconds
Started Apr 15 01:18:44 PM PDT 24
Finished Apr 15 01:18:45 PM PDT 24
Peak memory 205376 kb
Host smart-41f40599-cfd8-4f61-9e4e-d0658e693c0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431090427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.3
431090427
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.117064251
Short name T19
Test name
Test status
Simulation time 28212536 ps
CPU time 0.76 seconds
Started Apr 15 01:18:34 PM PDT 24
Finished Apr 15 01:18:35 PM PDT 24
Peak memory 206836 kb
Host smart-cfae232e-4546-452d-b939-5600e48bb2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117064251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.117064251
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.2967582555
Short name T691
Test name
Test status
Simulation time 785665569 ps
CPU time 28.2 seconds
Started Apr 15 01:18:41 PM PDT 24
Finished Apr 15 01:19:10 PM PDT 24
Peak memory 239228 kb
Host smart-f5b6c0fd-d596-4df5-a4c1-fba89b7b8b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967582555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.2967582555
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.1791860644
Short name T443
Test name
Test status
Simulation time 106888075278 ps
CPU time 53.84 seconds
Started Apr 15 01:18:38 PM PDT 24
Finished Apr 15 01:19:33 PM PDT 24
Peak memory 236836 kb
Host smart-2620e6dc-2bcc-4f13-970e-07829a0c4217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791860644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.1791860644
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.2229541491
Short name T247
Test name
Test status
Simulation time 1744203081 ps
CPU time 6.66 seconds
Started Apr 15 01:18:46 PM PDT 24
Finished Apr 15 01:18:54 PM PDT 24
Peak memory 233804 kb
Host smart-d223c7bd-b9b2-4da0-8564-0dca8fc1faae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229541491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.2229541491
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.1628608159
Short name T333
Test name
Test status
Simulation time 1283202037 ps
CPU time 5.61 seconds
Started Apr 15 01:18:47 PM PDT 24
Finished Apr 15 01:18:53 PM PDT 24
Peak memory 231980 kb
Host smart-4d66f75a-4f4f-4b7f-9549-9506040cda28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628608159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1628608159
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.66103005
Short name T452
Test name
Test status
Simulation time 1083845817 ps
CPU time 8.71 seconds
Started Apr 15 01:18:46 PM PDT 24
Finished Apr 15 01:18:56 PM PDT 24
Peak memory 222992 kb
Host smart-de61e8c9-85e2-40cb-b18c-90708ede062d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=66103005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direct
.66103005
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.3169835487
Short name T49
Test name
Test status
Simulation time 237840297 ps
CPU time 1.02 seconds
Started Apr 15 01:18:40 PM PDT 24
Finished Apr 15 01:18:42 PM PDT 24
Peak memory 234844 kb
Host smart-2ac74c5c-01c9-4348-8e3c-2b46d6e814f2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169835487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.3169835487
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.2701208368
Short name T401
Test name
Test status
Simulation time 28078733900 ps
CPU time 36.44 seconds
Started Apr 15 01:18:42 PM PDT 24
Finished Apr 15 01:19:19 PM PDT 24
Peak memory 216248 kb
Host smart-a705ba27-7d8a-4af0-980e-010960f0f1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701208368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.2701208368
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.254385596
Short name T670
Test name
Test status
Simulation time 2617574554 ps
CPU time 11.29 seconds
Started Apr 15 01:18:35 PM PDT 24
Finished Apr 15 01:18:47 PM PDT 24
Peak memory 216444 kb
Host smart-43933593-0b29-4f71-924c-eb825044817f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254385596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.254385596
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.985686511
Short name T505
Test name
Test status
Simulation time 470452107 ps
CPU time 2.83 seconds
Started Apr 15 01:18:39 PM PDT 24
Finished Apr 15 01:18:43 PM PDT 24
Peak memory 216192 kb
Host smart-215161b7-29c7-4eb5-9abb-855600b95219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985686511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.985686511
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.1383912176
Short name T445
Test name
Test status
Simulation time 413497341 ps
CPU time 0.95 seconds
Started Apr 15 01:18:36 PM PDT 24
Finished Apr 15 01:18:37 PM PDT 24
Peak memory 205688 kb
Host smart-a2fb3e0b-8fde-456b-a247-984cbfadaf5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383912176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.1383912176
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.2716386265
Short name T223
Test name
Test status
Simulation time 17367157301 ps
CPU time 50.8 seconds
Started Apr 15 01:18:41 PM PDT 24
Finished Apr 15 01:19:33 PM PDT 24
Peak memory 218392 kb
Host smart-c9845875-d7f5-4dfc-8453-d385902805a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716386265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.2716386265
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.4077533661
Short name T30
Test name
Test status
Simulation time 15648361 ps
CPU time 0.73 seconds
Started Apr 15 01:20:28 PM PDT 24
Finished Apr 15 01:20:29 PM PDT 24
Peak memory 204820 kb
Host smart-37403000-e722-4f00-a90b-cb2563aa583b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077533661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
4077533661
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.3914247132
Short name T596
Test name
Test status
Simulation time 64544179 ps
CPU time 0.77 seconds
Started Apr 15 01:20:25 PM PDT 24
Finished Apr 15 01:20:26 PM PDT 24
Peak memory 206548 kb
Host smart-416a6149-da53-4d9b-9e6b-666649654c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914247132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.3914247132
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.3260084287
Short name T354
Test name
Test status
Simulation time 5162266044 ps
CPU time 68.04 seconds
Started Apr 15 01:20:26 PM PDT 24
Finished Apr 15 01:21:34 PM PDT 24
Peak memory 250404 kb
Host smart-c1f4c68a-db3d-4795-aaaf-f14ab04f513a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260084287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.3260084287
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.1654336537
Short name T470
Test name
Test status
Simulation time 1081307928 ps
CPU time 13.95 seconds
Started Apr 15 01:20:25 PM PDT 24
Finished Apr 15 01:20:39 PM PDT 24
Peak memory 223888 kb
Host smart-e54565f2-016b-488b-9039-1a3f4e76a758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654336537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.1654336537
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.2078229897
Short name T286
Test name
Test status
Simulation time 553244522 ps
CPU time 8.32 seconds
Started Apr 15 01:20:24 PM PDT 24
Finished Apr 15 01:20:33 PM PDT 24
Peak memory 223128 kb
Host smart-19f5873f-78db-4a8b-ad1b-d038f590c5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078229897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.2078229897
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.1233077622
Short name T191
Test name
Test status
Simulation time 15280341735 ps
CPU time 24.08 seconds
Started Apr 15 01:20:28 PM PDT 24
Finished Apr 15 01:20:52 PM PDT 24
Peak memory 239848 kb
Host smart-162be09f-3db5-4505-b3f2-5287e00cdb4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233077622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.1233077622
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.739240288
Short name T562
Test name
Test status
Simulation time 213022072 ps
CPU time 4.37 seconds
Started Apr 15 01:20:28 PM PDT 24
Finished Apr 15 01:20:33 PM PDT 24
Peak memory 222860 kb
Host smart-ed9671c3-5f50-4368-af74-f5f0fbec7d31
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=739240288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dire
ct.739240288
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.2939836988
Short name T393
Test name
Test status
Simulation time 4757836339 ps
CPU time 28.07 seconds
Started Apr 15 01:20:26 PM PDT 24
Finished Apr 15 01:20:55 PM PDT 24
Peak memory 216248 kb
Host smart-cf766965-b3a4-47da-a932-099692dffceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939836988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.2939836988
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.1193328838
Short name T559
Test name
Test status
Simulation time 385052061 ps
CPU time 2.69 seconds
Started Apr 15 01:20:28 PM PDT 24
Finished Apr 15 01:20:31 PM PDT 24
Peak memory 216240 kb
Host smart-9e4f1475-cfa1-4639-8975-486cdb5bb9b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193328838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.1193328838
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.2595599903
Short name T435
Test name
Test status
Simulation time 427793297 ps
CPU time 2.86 seconds
Started Apr 15 01:20:27 PM PDT 24
Finished Apr 15 01:20:30 PM PDT 24
Peak memory 216184 kb
Host smart-c8728b43-7bd2-491f-a3bd-064ccab5a204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595599903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.2595599903
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.3780177134
Short name T672
Test name
Test status
Simulation time 145644362 ps
CPU time 1.11 seconds
Started Apr 15 01:20:27 PM PDT 24
Finished Apr 15 01:20:28 PM PDT 24
Peak memory 206732 kb
Host smart-fee71267-bbf6-4799-afb1-409f201c00cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780177134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.3780177134
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.351312070
Short name T487
Test name
Test status
Simulation time 38364473 ps
CPU time 0.69 seconds
Started Apr 15 01:20:33 PM PDT 24
Finished Apr 15 01:20:34 PM PDT 24
Peak memory 205340 kb
Host smart-f0e0dd26-8c9e-485c-bc1f-b326fa2365f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351312070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.351312070
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.2187648756
Short name T480
Test name
Test status
Simulation time 13435375 ps
CPU time 0.75 seconds
Started Apr 15 01:20:30 PM PDT 24
Finished Apr 15 01:20:31 PM PDT 24
Peak memory 205744 kb
Host smart-88f4fda7-5add-4fd4-80aa-16e3e6e0f987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187648756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.2187648756
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.1479298573
Short name T7
Test name
Test status
Simulation time 53804840141 ps
CPU time 89.86 seconds
Started Apr 15 01:20:29 PM PDT 24
Finished Apr 15 01:21:59 PM PDT 24
Peak memory 238432 kb
Host smart-2bc1bebe-ff3e-4b8b-87e3-d0b4766f1c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479298573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1479298573
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.4243599949
Short name T504
Test name
Test status
Simulation time 4819545878 ps
CPU time 36.11 seconds
Started Apr 15 01:20:32 PM PDT 24
Finished Apr 15 01:21:08 PM PDT 24
Peak memory 232524 kb
Host smart-a143c03f-1cea-4439-a12a-f97c6196bbbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243599949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.4243599949
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.1378232715
Short name T264
Test name
Test status
Simulation time 5474983703 ps
CPU time 6.82 seconds
Started Apr 15 01:20:29 PM PDT 24
Finished Apr 15 01:20:36 PM PDT 24
Peak memory 218736 kb
Host smart-5a3b443a-9de8-44bc-813f-71f5eb6a4134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378232715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.1378232715
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.3057281597
Short name T666
Test name
Test status
Simulation time 662553583 ps
CPU time 8.52 seconds
Started Apr 15 01:20:31 PM PDT 24
Finished Apr 15 01:20:40 PM PDT 24
Peak memory 219592 kb
Host smart-f7bcd6cf-5578-4860-9b83-b87b5b2b8d15
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3057281597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.3057281597
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.387479839
Short name T366
Test name
Test status
Simulation time 102008947 ps
CPU time 0.85 seconds
Started Apr 15 01:20:37 PM PDT 24
Finished Apr 15 01:20:39 PM PDT 24
Peak memory 206536 kb
Host smart-77effece-adf8-4006-944c-c71457318186
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387479839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stres
s_all.387479839
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.4072030288
Short name T693
Test name
Test status
Simulation time 8615148669 ps
CPU time 36.57 seconds
Started Apr 15 01:20:28 PM PDT 24
Finished Apr 15 01:21:06 PM PDT 24
Peak memory 216588 kb
Host smart-5bb5d551-5be0-47cc-9797-8cc5473d2c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072030288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.4072030288
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.1836490357
Short name T434
Test name
Test status
Simulation time 565889569 ps
CPU time 2.18 seconds
Started Apr 15 01:20:31 PM PDT 24
Finished Apr 15 01:20:34 PM PDT 24
Peak memory 216160 kb
Host smart-10579d9c-79df-4747-9848-cabf87155c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836490357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.1836490357
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.3649974750
Short name T636
Test name
Test status
Simulation time 94793587 ps
CPU time 0.96 seconds
Started Apr 15 01:20:31 PM PDT 24
Finished Apr 15 01:20:33 PM PDT 24
Peak memory 206736 kb
Host smart-1edb812e-8086-404e-b4fa-5f4f6fbabac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649974750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.3649974750
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.3511393563
Short name T422
Test name
Test status
Simulation time 105843134 ps
CPU time 0.9 seconds
Started Apr 15 01:20:29 PM PDT 24
Finished Apr 15 01:20:30 PM PDT 24
Peak memory 206712 kb
Host smart-abbf8cbd-fdb2-4c2c-8bc0-cf2a68c0d14f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511393563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.3511393563
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.793219454
Short name T263
Test name
Test status
Simulation time 33491971944 ps
CPU time 22.97 seconds
Started Apr 15 01:20:30 PM PDT 24
Finished Apr 15 01:20:53 PM PDT 24
Peak memory 216312 kb
Host smart-d34bbb62-ea39-415d-ad54-19edddf85c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793219454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.793219454
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.2392253157
Short name T587
Test name
Test status
Simulation time 16548880 ps
CPU time 0.72 seconds
Started Apr 15 01:20:40 PM PDT 24
Finished Apr 15 01:20:42 PM PDT 24
Peak memory 205376 kb
Host smart-341383b4-2862-475f-ad82-5c75976a743a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392253157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
2392253157
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.94328595
Short name T515
Test name
Test status
Simulation time 264365046 ps
CPU time 0.76 seconds
Started Apr 15 01:20:36 PM PDT 24
Finished Apr 15 01:20:37 PM PDT 24
Peak memory 206528 kb
Host smart-038f589b-99f7-442e-9dc1-9e2eb2b7024c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94328595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.94328595
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_intercept.5402527
Short name T288
Test name
Test status
Simulation time 1119985419 ps
CPU time 5.49 seconds
Started Apr 15 01:20:36 PM PDT 24
Finished Apr 15 01:20:42 PM PDT 24
Peak memory 223276 kb
Host smart-51bfeb04-0e2b-4339-b479-68cf472fb842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5402527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.5402527
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.1013397800
Short name T644
Test name
Test status
Simulation time 3959324578 ps
CPU time 44.23 seconds
Started Apr 15 01:20:39 PM PDT 24
Finished Apr 15 01:21:24 PM PDT 24
Peak memory 234992 kb
Host smart-d9a0c987-43b1-4c11-9332-ee8e82127c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013397800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.1013397800
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.72946497
Short name T220
Test name
Test status
Simulation time 1247967750 ps
CPU time 10.1 seconds
Started Apr 15 01:20:40 PM PDT 24
Finished Apr 15 01:20:50 PM PDT 24
Peak memory 235136 kb
Host smart-45652877-a562-4900-b70c-e85e81d33c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72946497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap.72946497
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.4209918772
Short name T58
Test name
Test status
Simulation time 10430745793 ps
CPU time 19.46 seconds
Started Apr 15 01:20:40 PM PDT 24
Finished Apr 15 01:21:00 PM PDT 24
Peak memory 222888 kb
Host smart-35fc9ab3-8d55-42bf-ba3b-4cca386a0ffe
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4209918772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.4209918772
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.4175965625
Short name T609
Test name
Test status
Simulation time 5275167974 ps
CPU time 15.09 seconds
Started Apr 15 01:20:33 PM PDT 24
Finished Apr 15 01:20:49 PM PDT 24
Peak memory 216516 kb
Host smart-0cf3b061-26cc-4042-ab8e-f15b137bd301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175965625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.4175965625
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.2919102778
Short name T671
Test name
Test status
Simulation time 2947665001 ps
CPU time 4.71 seconds
Started Apr 15 01:20:35 PM PDT 24
Finished Apr 15 01:20:40 PM PDT 24
Peak memory 216268 kb
Host smart-a1994189-a7e9-46a6-9121-1c4c6d3314a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919102778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.2919102778
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.1226297679
Short name T642
Test name
Test status
Simulation time 1229441404 ps
CPU time 2.31 seconds
Started Apr 15 01:20:35 PM PDT 24
Finished Apr 15 01:20:38 PM PDT 24
Peak memory 216168 kb
Host smart-accb73e1-7456-4872-9b81-f972a7891f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226297679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1226297679
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.1406992128
Short name T106
Test name
Test status
Simulation time 377623388 ps
CPU time 1.03 seconds
Started Apr 15 01:20:35 PM PDT 24
Finished Apr 15 01:20:36 PM PDT 24
Peak memory 206700 kb
Host smart-7c99def8-c298-421f-aeed-a693809260d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406992128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.1406992128
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.3517811492
Short name T18
Test name
Test status
Simulation time 39615292 ps
CPU time 0.74 seconds
Started Apr 15 01:20:44 PM PDT 24
Finished Apr 15 01:20:45 PM PDT 24
Peak memory 204792 kb
Host smart-5de4437b-df74-4160-a5f1-0e476806d595
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517811492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
3517811492
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.142563715
Short name T640
Test name
Test status
Simulation time 1811462980 ps
CPU time 5.77 seconds
Started Apr 15 01:20:43 PM PDT 24
Finished Apr 15 01:20:49 PM PDT 24
Peak memory 218532 kb
Host smart-00c93c43-8ceb-4c1e-93af-31075bba4697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142563715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.142563715
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.3751593230
Short name T667
Test name
Test status
Simulation time 58458047 ps
CPU time 0.79 seconds
Started Apr 15 01:20:39 PM PDT 24
Finished Apr 15 01:20:40 PM PDT 24
Peak memory 206456 kb
Host smart-5e49cbb5-1771-4d5a-87ba-6a052dd33a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751593230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.3751593230
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.642807653
Short name T353
Test name
Test status
Simulation time 5790908758 ps
CPU time 90.58 seconds
Started Apr 15 01:20:41 PM PDT 24
Finished Apr 15 01:22:12 PM PDT 24
Peak memory 232692 kb
Host smart-b8000fcd-acde-4ffb-a684-bd171e74e978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642807653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.642807653
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.426685890
Short name T198
Test name
Test status
Simulation time 6607002196 ps
CPU time 31.51 seconds
Started Apr 15 01:20:37 PM PDT 24
Finished Apr 15 01:21:09 PM PDT 24
Peak memory 232640 kb
Host smart-96463f34-e73c-49f8-afbe-84fdc7c9924e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426685890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.426685890
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.1893299802
Short name T238
Test name
Test status
Simulation time 2079900318 ps
CPU time 5.45 seconds
Started Apr 15 01:20:41 PM PDT 24
Finished Apr 15 01:20:47 PM PDT 24
Peak memory 221720 kb
Host smart-5551a8fd-675e-49a3-938b-1c47fbc3aa44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893299802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.1893299802
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.2281841358
Short name T628
Test name
Test status
Simulation time 1891969335 ps
CPU time 4.04 seconds
Started Apr 15 01:20:43 PM PDT 24
Finished Apr 15 01:20:47 PM PDT 24
Peak memory 218748 kb
Host smart-df0c78df-a229-4352-87f0-ffb1349b32d3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2281841358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.2281841358
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.2503197746
Short name T377
Test name
Test status
Simulation time 37263053541 ps
CPU time 42.17 seconds
Started Apr 15 01:20:40 PM PDT 24
Finished Apr 15 01:21:23 PM PDT 24
Peak memory 216144 kb
Host smart-40371b68-bb16-41c0-9439-092a62d5142f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503197746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.2503197746
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.1786243152
Short name T546
Test name
Test status
Simulation time 9521865370 ps
CPU time 30.76 seconds
Started Apr 15 01:20:39 PM PDT 24
Finished Apr 15 01:21:11 PM PDT 24
Peak memory 216244 kb
Host smart-a7e10b49-84b6-4387-becc-84bafe152f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786243152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.1786243152
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.654128537
Short name T477
Test name
Test status
Simulation time 1208762370 ps
CPU time 4.49 seconds
Started Apr 15 01:20:39 PM PDT 24
Finished Apr 15 01:20:44 PM PDT 24
Peak memory 216144 kb
Host smart-f86c9f5b-51d1-405f-b96a-349a01f23d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654128537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.654128537
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.3369657062
Short name T582
Test name
Test status
Simulation time 337299951 ps
CPU time 0.95 seconds
Started Apr 15 01:20:42 PM PDT 24
Finished Apr 15 01:20:44 PM PDT 24
Peak memory 205720 kb
Host smart-d95dd483-3f2d-49d5-bba3-6dd952fcf882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369657062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.3369657062
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.3839048788
Short name T700
Test name
Test status
Simulation time 39454004 ps
CPU time 0.72 seconds
Started Apr 15 01:20:51 PM PDT 24
Finished Apr 15 01:20:52 PM PDT 24
Peak memory 205348 kb
Host smart-09b384e3-70cd-4de6-9ab0-739c6e3da223
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839048788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
3839048788
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.4240278548
Short name T25
Test name
Test status
Simulation time 29419243434 ps
CPU time 29.65 seconds
Started Apr 15 01:20:47 PM PDT 24
Finished Apr 15 01:21:17 PM PDT 24
Peak memory 224232 kb
Host smart-a69403f2-6268-4013-9a41-6a2236659d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240278548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.4240278548
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.2415924963
Short name T499
Test name
Test status
Simulation time 76979474 ps
CPU time 0.76 seconds
Started Apr 15 01:20:43 PM PDT 24
Finished Apr 15 01:20:45 PM PDT 24
Peak memory 206432 kb
Host smart-7d0c88b3-2633-40a9-ae1a-975a836d0fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415924963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.2415924963
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.3737946288
Short name T503
Test name
Test status
Simulation time 12491619878 ps
CPU time 54.7 seconds
Started Apr 15 01:20:45 PM PDT 24
Finished Apr 15 01:21:40 PM PDT 24
Peak memory 254628 kb
Host smart-117d8085-f95c-4938-a659-9c8adac8c18c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737946288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.3737946288
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.593587316
Short name T240
Test name
Test status
Simulation time 898438201 ps
CPU time 6.63 seconds
Started Apr 15 01:20:48 PM PDT 24
Finished Apr 15 01:20:55 PM PDT 24
Peak memory 232536 kb
Host smart-eaf48fd6-af23-48e0-a086-3036ee240fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593587316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.593587316
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.1063922825
Short name T166
Test name
Test status
Simulation time 834529514 ps
CPU time 10.17 seconds
Started Apr 15 01:20:49 PM PDT 24
Finished Apr 15 01:20:59 PM PDT 24
Peak memory 219500 kb
Host smart-6cacbb78-13d1-483d-84ce-8c05041fcb0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063922825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.1063922825
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.177097407
Short name T225
Test name
Test status
Simulation time 927054755 ps
CPU time 2.66 seconds
Started Apr 15 01:20:42 PM PDT 24
Finished Apr 15 01:20:45 PM PDT 24
Peak memory 220992 kb
Host smart-44c134be-3eec-4a5c-8949-758fcc097746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177097407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.177097407
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.613499380
Short name T418
Test name
Test status
Simulation time 1362513028 ps
CPU time 9.42 seconds
Started Apr 15 01:20:47 PM PDT 24
Finished Apr 15 01:20:56 PM PDT 24
Peak memory 222040 kb
Host smart-96b3702c-c55d-43bc-a16d-8dd0c33415cb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=613499380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dire
ct.613499380
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.2776534730
Short name T399
Test name
Test status
Simulation time 3062244845 ps
CPU time 9.64 seconds
Started Apr 15 01:20:45 PM PDT 24
Finished Apr 15 01:20:55 PM PDT 24
Peak memory 216284 kb
Host smart-53371325-3ecf-4dcf-bda1-83ae95a20d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776534730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.2776534730
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.3144521928
Short name T102
Test name
Test status
Simulation time 852610619 ps
CPU time 6.72 seconds
Started Apr 15 01:20:44 PM PDT 24
Finished Apr 15 01:20:51 PM PDT 24
Peak memory 216208 kb
Host smart-fb05a29f-30f1-4f5b-ba1a-54a355528647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144521928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.3144521928
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.2900197203
Short name T656
Test name
Test status
Simulation time 147042928 ps
CPU time 0.83 seconds
Started Apr 15 01:20:42 PM PDT 24
Finished Apr 15 01:20:43 PM PDT 24
Peak memory 206356 kb
Host smart-94f88ce7-a614-4d49-b074-624b10358dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900197203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.2900197203
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.3817455513
Short name T627
Test name
Test status
Simulation time 48380656 ps
CPU time 0.78 seconds
Started Apr 15 01:20:44 PM PDT 24
Finished Apr 15 01:20:46 PM PDT 24
Peak memory 205668 kb
Host smart-d4b94377-ba26-46dc-9978-b92c3ed71080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817455513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.3817455513
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.1585930035
Short name T211
Test name
Test status
Simulation time 9514374037 ps
CPU time 11.31 seconds
Started Apr 15 01:20:46 PM PDT 24
Finished Apr 15 01:20:58 PM PDT 24
Peak memory 220104 kb
Host smart-dbda8f24-f692-4221-866a-f2801135cc21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585930035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.1585930035
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.3971800066
Short name T655
Test name
Test status
Simulation time 11804793 ps
CPU time 0.71 seconds
Started Apr 15 01:21:13 PM PDT 24
Finished Apr 15 01:21:14 PM PDT 24
Peak memory 205296 kb
Host smart-55a48bff-890c-4545-a2cd-3b62075d53f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971800066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
3971800066
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.2058983518
Short name T472
Test name
Test status
Simulation time 50700862 ps
CPU time 0.73 seconds
Started Apr 15 01:20:55 PM PDT 24
Finished Apr 15 01:20:56 PM PDT 24
Peak memory 206536 kb
Host smart-90f4ca21-3637-4513-9a61-6c34b6cbbc11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058983518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.2058983518
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.2812704559
Short name T299
Test name
Test status
Simulation time 953897550 ps
CPU time 19.76 seconds
Started Apr 15 01:20:57 PM PDT 24
Finished Apr 15 01:21:17 PM PDT 24
Peak memory 232588 kb
Host smart-1a782bd2-1df4-4d9b-a048-0127e661c068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812704559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.2812704559
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.836265009
Short name T196
Test name
Test status
Simulation time 39006022219 ps
CPU time 114.36 seconds
Started Apr 15 01:20:57 PM PDT 24
Finished Apr 15 01:22:52 PM PDT 24
Peak memory 221276 kb
Host smart-fc23c9a7-a6c8-40f0-9cfc-79675c2e1c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836265009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.836265009
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.1730610644
Short name T531
Test name
Test status
Simulation time 206243215 ps
CPU time 4.78 seconds
Started Apr 15 01:20:59 PM PDT 24
Finished Apr 15 01:21:04 PM PDT 24
Peak memory 220360 kb
Host smart-ea73a6aa-cf0e-4253-879a-82355af49970
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1730610644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.1730610644
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.1090842582
Short name T601
Test name
Test status
Simulation time 13944083497 ps
CPU time 19.48 seconds
Started Apr 15 01:20:50 PM PDT 24
Finished Apr 15 01:21:10 PM PDT 24
Peak memory 216300 kb
Host smart-ac939f01-fe4b-4728-b87d-1390ec3462db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090842582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.1090842582
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.2409592549
Short name T684
Test name
Test status
Simulation time 7663272761 ps
CPU time 18.31 seconds
Started Apr 15 01:20:51 PM PDT 24
Finished Apr 15 01:21:10 PM PDT 24
Peak memory 216232 kb
Host smart-e58ac4a4-874b-4ac2-a2a1-f4d988c323d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409592549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.2409592549
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.531631880
Short name T647
Test name
Test status
Simulation time 125126195 ps
CPU time 1.06 seconds
Started Apr 15 01:20:53 PM PDT 24
Finished Apr 15 01:20:55 PM PDT 24
Peak memory 207776 kb
Host smart-13309907-9f17-4e70-b4d8-234b323235df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531631880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.531631880
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.4183969394
Short name T104
Test name
Test status
Simulation time 315211426 ps
CPU time 1.11 seconds
Started Apr 15 01:20:51 PM PDT 24
Finished Apr 15 01:20:53 PM PDT 24
Peak memory 206716 kb
Host smart-5528d51c-188a-4ea6-9c6b-bb122ba5be08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183969394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.4183969394
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.2315059472
Short name T216
Test name
Test status
Simulation time 6974550616 ps
CPU time 9.79 seconds
Started Apr 15 01:20:55 PM PDT 24
Finished Apr 15 01:21:06 PM PDT 24
Peak memory 235540 kb
Host smart-7f60ed50-4b73-4c87-a702-1b75c6a8d0a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315059472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.2315059472
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.3998971689
Short name T429
Test name
Test status
Simulation time 14457747 ps
CPU time 0.7 seconds
Started Apr 15 01:21:07 PM PDT 24
Finished Apr 15 01:21:08 PM PDT 24
Peak memory 205312 kb
Host smart-f5380110-8f8c-4d93-ae6b-e45ef76fe439
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998971689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
3998971689
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.2969241113
Short name T580
Test name
Test status
Simulation time 52196841 ps
CPU time 0.78 seconds
Started Apr 15 01:21:01 PM PDT 24
Finished Apr 15 01:21:02 PM PDT 24
Peak memory 205804 kb
Host smart-d10de7a5-c337-4a5f-8c5c-ac24e800e53a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969241113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.2969241113
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.2656304502
Short name T585
Test name
Test status
Simulation time 957957778 ps
CPU time 21.66 seconds
Started Apr 15 01:21:08 PM PDT 24
Finished Apr 15 01:21:30 PM PDT 24
Peak memory 251856 kb
Host smart-9569f10a-7f33-4dcc-97c7-8d9a0d827efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656304502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.2656304502
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.2356746175
Short name T660
Test name
Test status
Simulation time 45136992930 ps
CPU time 30.1 seconds
Started Apr 15 01:21:08 PM PDT 24
Finished Apr 15 01:21:39 PM PDT 24
Peak memory 237428 kb
Host smart-50edf54e-0feb-4a61-a899-cf328cf067e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356746175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.2356746175
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.1085046306
Short name T634
Test name
Test status
Simulation time 691954096 ps
CPU time 7.4 seconds
Started Apr 15 01:20:59 PM PDT 24
Finished Apr 15 01:21:07 PM PDT 24
Peak memory 221908 kb
Host smart-620d6795-72c9-4e3f-952e-451efd935bb6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1085046306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.1085046306
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.4188525717
Short name T396
Test name
Test status
Simulation time 1861532203 ps
CPU time 34.18 seconds
Started Apr 15 01:21:00 PM PDT 24
Finished Apr 15 01:21:34 PM PDT 24
Peak memory 216260 kb
Host smart-6cd4b6d0-27c1-4dc8-aba0-4be5a50606a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188525717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.4188525717
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.954572144
Short name T430
Test name
Test status
Simulation time 1675986694 ps
CPU time 9.08 seconds
Started Apr 15 01:20:59 PM PDT 24
Finished Apr 15 01:21:09 PM PDT 24
Peak memory 216152 kb
Host smart-b1f909b4-c6b5-41ce-80ef-c4241edfca93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954572144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.954572144
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.4127700896
Short name T20
Test name
Test status
Simulation time 32716971 ps
CPU time 1.14 seconds
Started Apr 15 01:20:59 PM PDT 24
Finished Apr 15 01:21:00 PM PDT 24
Peak memory 216172 kb
Host smart-81a07b51-6e4e-41f4-9bc6-59dea12a2f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127700896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.4127700896
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.269029318
Short name T709
Test name
Test status
Simulation time 210143603 ps
CPU time 0.77 seconds
Started Apr 15 01:20:59 PM PDT 24
Finished Apr 15 01:21:00 PM PDT 24
Peak memory 205708 kb
Host smart-aef57913-90f7-452e-b217-053022ea20c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269029318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.269029318
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.2709713165
Short name T652
Test name
Test status
Simulation time 16835114 ps
CPU time 0.68 seconds
Started Apr 15 01:21:06 PM PDT 24
Finished Apr 15 01:21:07 PM PDT 24
Peak memory 204784 kb
Host smart-de8e9127-d549-40e3-ba24-f9c4230f2da0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709713165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
2709713165
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.85652089
Short name T566
Test name
Test status
Simulation time 13298361 ps
CPU time 0.75 seconds
Started Apr 15 01:21:05 PM PDT 24
Finished Apr 15 01:21:06 PM PDT 24
Peak memory 206780 kb
Host smart-8a03cb78-3211-47d7-b573-ccc7a7e161b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85652089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.85652089
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.3072918162
Short name T323
Test name
Test status
Simulation time 774519602 ps
CPU time 8.3 seconds
Started Apr 15 01:21:09 PM PDT 24
Finished Apr 15 01:21:17 PM PDT 24
Peak memory 224044 kb
Host smart-ea30930f-a824-4c01-93a2-5a232481b6b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072918162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.3072918162
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.418613022
Short name T568
Test name
Test status
Simulation time 1077224555 ps
CPU time 6.79 seconds
Started Apr 15 01:21:07 PM PDT 24
Finished Apr 15 01:21:15 PM PDT 24
Peak memory 222776 kb
Host smart-54693465-54d5-4531-badf-710622ef7ef2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=418613022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dire
ct.418613022
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.2868657935
Short name T521
Test name
Test status
Simulation time 176543057 ps
CPU time 0.97 seconds
Started Apr 15 01:21:10 PM PDT 24
Finished Apr 15 01:21:12 PM PDT 24
Peak memory 206616 kb
Host smart-a2e1143f-0666-4719-9c4e-e41f377f1237
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868657935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.2868657935
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.3786081494
Short name T447
Test name
Test status
Simulation time 1168290946 ps
CPU time 4.18 seconds
Started Apr 15 01:21:03 PM PDT 24
Finished Apr 15 01:21:07 PM PDT 24
Peak memory 216200 kb
Host smart-968f0523-95aa-4853-b482-231783c8a3e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786081494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.3786081494
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.3617048442
Short name T668
Test name
Test status
Simulation time 129144872 ps
CPU time 1.21 seconds
Started Apr 15 01:21:04 PM PDT 24
Finished Apr 15 01:21:05 PM PDT 24
Peak memory 216212 kb
Host smart-03be9c88-1a2a-4cfa-bd99-003b3ad318ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617048442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.3617048442
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.1067851641
Short name T409
Test name
Test status
Simulation time 64825401 ps
CPU time 0.84 seconds
Started Apr 15 01:21:09 PM PDT 24
Finished Apr 15 01:21:10 PM PDT 24
Peak memory 205720 kb
Host smart-c784872a-77c5-49a4-ba62-290bb7abb80c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067851641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.1067851641
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.870428749
Short name T230
Test name
Test status
Simulation time 2833193316 ps
CPU time 10.27 seconds
Started Apr 15 01:21:03 PM PDT 24
Finished Apr 15 01:21:13 PM PDT 24
Peak memory 219868 kb
Host smart-10687d67-1d5a-43fe-aebe-ea767eaeda12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870428749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.870428749
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.964281543
Short name T632
Test name
Test status
Simulation time 97242268 ps
CPU time 0.69 seconds
Started Apr 15 01:21:13 PM PDT 24
Finished Apr 15 01:21:15 PM PDT 24
Peak memory 204820 kb
Host smart-736c0581-7144-4189-8180-5e12119ee707
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964281543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.964281543
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.4164649057
Short name T28
Test name
Test status
Simulation time 1763783918 ps
CPU time 9.06 seconds
Started Apr 15 01:21:06 PM PDT 24
Finished Apr 15 01:21:16 PM PDT 24
Peak memory 218976 kb
Host smart-60ce51db-23bb-4a81-813a-e32ee7ded803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164649057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.4164649057
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.1508710103
Short name T583
Test name
Test status
Simulation time 18748487 ps
CPU time 0.78 seconds
Started Apr 15 01:21:06 PM PDT 24
Finished Apr 15 01:21:07 PM PDT 24
Peak memory 206496 kb
Host smart-6bff2aab-041c-4d0e-b733-7216e58f2c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508710103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.1508710103
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.788158257
Short name T296
Test name
Test status
Simulation time 5125292447 ps
CPU time 30.08 seconds
Started Apr 15 01:21:11 PM PDT 24
Finished Apr 15 01:21:42 PM PDT 24
Peak memory 236968 kb
Host smart-9cf1bd65-33fa-436e-8d8d-57dfb412569f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788158257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.788158257
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.1940828388
Short name T68
Test name
Test status
Simulation time 8732438621 ps
CPU time 14.47 seconds
Started Apr 15 01:21:08 PM PDT 24
Finished Apr 15 01:21:23 PM PDT 24
Peak memory 231508 kb
Host smart-b4355eb7-7e6b-4c54-ac31-4dacada40b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940828388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.1940828388
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.1231607999
Short name T662
Test name
Test status
Simulation time 2063588402 ps
CPU time 6.91 seconds
Started Apr 15 01:21:08 PM PDT 24
Finished Apr 15 01:21:16 PM PDT 24
Peak memory 218892 kb
Host smart-85fb5738-6e50-4680-a1fb-1619adcc2ee4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1231607999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.1231607999
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.1590070800
Short name T530
Test name
Test status
Simulation time 12841208840 ps
CPU time 8.66 seconds
Started Apr 15 01:21:06 PM PDT 24
Finished Apr 15 01:21:15 PM PDT 24
Peak memory 216264 kb
Host smart-6deeb66a-045c-42a6-8845-3f9c9d9cd084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590070800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.1590070800
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.716687140
Short name T675
Test name
Test status
Simulation time 16099890679 ps
CPU time 9.38 seconds
Started Apr 15 01:21:07 PM PDT 24
Finished Apr 15 01:21:16 PM PDT 24
Peak memory 216128 kb
Host smart-985d9bdd-4f11-4d6d-bf95-bc7438bf333a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716687140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.716687140
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.453030884
Short name T50
Test name
Test status
Simulation time 65107722 ps
CPU time 1.03 seconds
Started Apr 15 01:21:10 PM PDT 24
Finished Apr 15 01:21:12 PM PDT 24
Peak memory 207824 kb
Host smart-00676c48-bc1c-41e0-b975-7c8077114cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453030884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.453030884
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.2364088080
Short name T527
Test name
Test status
Simulation time 478687828 ps
CPU time 0.84 seconds
Started Apr 15 01:21:08 PM PDT 24
Finished Apr 15 01:21:09 PM PDT 24
Peak memory 205736 kb
Host smart-714ca386-ae6d-4f24-8e98-640b6462353d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364088080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.2364088080
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.1934386165
Short name T603
Test name
Test status
Simulation time 10977900 ps
CPU time 0.72 seconds
Started Apr 15 01:21:16 PM PDT 24
Finished Apr 15 01:21:17 PM PDT 24
Peak memory 205388 kb
Host smart-a72719d7-cf2f-41d3-b0c6-debc9a026616
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934386165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
1934386165
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.4043493632
Short name T86
Test name
Test status
Simulation time 409401547 ps
CPU time 3.97 seconds
Started Apr 15 01:21:13 PM PDT 24
Finished Apr 15 01:21:17 PM PDT 24
Peak memory 218532 kb
Host smart-c4309aa4-af89-4fb2-a3a5-35cb2a293fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043493632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.4043493632
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.1708773563
Short name T459
Test name
Test status
Simulation time 90464537 ps
CPU time 0.81 seconds
Started Apr 15 01:21:11 PM PDT 24
Finished Apr 15 01:21:12 PM PDT 24
Peak memory 206460 kb
Host smart-b60cd106-2980-4198-bb63-5fba1b883986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708773563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.1708773563
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.1716732464
Short name T81
Test name
Test status
Simulation time 1076912590 ps
CPU time 14.97 seconds
Started Apr 15 01:21:16 PM PDT 24
Finished Apr 15 01:21:31 PM PDT 24
Peak memory 248976 kb
Host smart-4c80ff5a-cdb6-4770-a801-a58062b4e436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716732464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.1716732464
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.53967511
Short name T253
Test name
Test status
Simulation time 1895255413 ps
CPU time 12.47 seconds
Started Apr 15 01:21:12 PM PDT 24
Finished Apr 15 01:21:25 PM PDT 24
Peak memory 222048 kb
Host smart-294b4b83-000e-488f-a309-6264658fa764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53967511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.53967511
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.1927305302
Short name T462
Test name
Test status
Simulation time 742799372 ps
CPU time 4.47 seconds
Started Apr 15 01:21:15 PM PDT 24
Finished Apr 15 01:21:21 PM PDT 24
Peak memory 222868 kb
Host smart-cca20ced-df6f-466d-a142-fdf48e9b37a5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1927305302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.1927305302
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.42777806
Short name T389
Test name
Test status
Simulation time 7786308863 ps
CPU time 22.53 seconds
Started Apr 15 01:21:14 PM PDT 24
Finished Apr 15 01:21:37 PM PDT 24
Peak memory 216312 kb
Host smart-ad66c196-17b7-44b4-9196-e07df990e4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42777806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.42777806
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.2352214718
Short name T674
Test name
Test status
Simulation time 9388353702 ps
CPU time 30.27 seconds
Started Apr 15 01:21:14 PM PDT 24
Finished Apr 15 01:21:45 PM PDT 24
Peak memory 216300 kb
Host smart-db87afec-1562-4d21-9be2-207743f26e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352214718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.2352214718
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.305511377
Short name T60
Test name
Test status
Simulation time 188165140 ps
CPU time 3.58 seconds
Started Apr 15 01:21:11 PM PDT 24
Finished Apr 15 01:21:15 PM PDT 24
Peak memory 216208 kb
Host smart-287cb0ef-cfdc-4d7d-ba5a-4270c8a69501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305511377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.305511377
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.4235198824
Short name T592
Test name
Test status
Simulation time 12197660 ps
CPU time 0.72 seconds
Started Apr 15 01:21:12 PM PDT 24
Finished Apr 15 01:21:13 PM PDT 24
Peak memory 205680 kb
Host smart-f75a5814-6fc8-4c6c-ad8c-fbfb4eb7deb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235198824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.4235198824
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.1414621762
Short name T508
Test name
Test status
Simulation time 13224065 ps
CPU time 0.71 seconds
Started Apr 15 01:18:42 PM PDT 24
Finished Apr 15 01:18:44 PM PDT 24
Peak memory 205212 kb
Host smart-25bfd430-7fdc-4be4-a6a2-efcdddec092a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414621762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.1
414621762
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.968093308
Short name T319
Test name
Test status
Simulation time 202087776 ps
CPU time 2.19 seconds
Started Apr 15 01:18:40 PM PDT 24
Finished Apr 15 01:18:43 PM PDT 24
Peak memory 220344 kb
Host smart-30bd5c94-0104-4b8d-8cc1-b3993b019c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968093308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.968093308
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.4112644471
Short name T554
Test name
Test status
Simulation time 15887160 ps
CPU time 0.77 seconds
Started Apr 15 01:18:50 PM PDT 24
Finished Apr 15 01:18:52 PM PDT 24
Peak memory 205792 kb
Host smart-5254e55b-6589-4909-b99f-c03f2a9fb5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112644471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.4112644471
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.1770804522
Short name T43
Test name
Test status
Simulation time 4762786457 ps
CPU time 58.66 seconds
Started Apr 15 01:18:40 PM PDT 24
Finished Apr 15 01:19:40 PM PDT 24
Peak memory 235360 kb
Host smart-0a4197df-82f3-4c70-a722-24bda874da19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770804522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.1770804522
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.2590918539
Short name T545
Test name
Test status
Simulation time 700558783 ps
CPU time 3.92 seconds
Started Apr 15 01:18:41 PM PDT 24
Finished Apr 15 01:18:46 PM PDT 24
Peak memory 222292 kb
Host smart-0c22b63d-b07f-4ac7-bc9d-630c2cfcff63
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2590918539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.2590918539
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.3144072220
Short name T48
Test name
Test status
Simulation time 168438752 ps
CPU time 0.98 seconds
Started Apr 15 01:18:45 PM PDT 24
Finished Apr 15 01:18:47 PM PDT 24
Peak memory 234944 kb
Host smart-b3521e24-5864-4285-bab4-3ec168d992fb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144072220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.3144072220
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.1984940323
Short name T608
Test name
Test status
Simulation time 5186009300 ps
CPU time 12.52 seconds
Started Apr 15 01:18:47 PM PDT 24
Finished Apr 15 01:19:00 PM PDT 24
Peak memory 216280 kb
Host smart-4503db6c-0a3a-454b-8648-76055202c9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984940323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.1984940323
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.3682306273
Short name T538
Test name
Test status
Simulation time 7019548321 ps
CPU time 10.09 seconds
Started Apr 15 01:18:40 PM PDT 24
Finished Apr 15 01:18:51 PM PDT 24
Peak memory 216232 kb
Host smart-09d1fdc0-c6b8-40b8-a7b1-c066703b5dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682306273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.3682306273
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.3864250780
Short name T404
Test name
Test status
Simulation time 657898014 ps
CPU time 2.84 seconds
Started Apr 15 01:18:40 PM PDT 24
Finished Apr 15 01:18:44 PM PDT 24
Peak memory 216328 kb
Host smart-083d6218-ac34-4c3b-8146-58a503530e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864250780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.3864250780
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.1459885948
Short name T593
Test name
Test status
Simulation time 80763159 ps
CPU time 0.87 seconds
Started Apr 15 01:18:42 PM PDT 24
Finished Apr 15 01:18:44 PM PDT 24
Peak memory 205672 kb
Host smart-a0999fb6-ae08-4a97-9dd6-386f22ab6367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459885948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.1459885948
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.691542358
Short name T544
Test name
Test status
Simulation time 12311214 ps
CPU time 0.75 seconds
Started Apr 15 01:21:25 PM PDT 24
Finished Apr 15 01:21:26 PM PDT 24
Peak memory 205348 kb
Host smart-0fca6006-4ab4-4cb3-a048-1cc7f7721c20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691542358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.691542358
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.4284304301
Short name T651
Test name
Test status
Simulation time 53442490 ps
CPU time 0.77 seconds
Started Apr 15 01:21:15 PM PDT 24
Finished Apr 15 01:21:17 PM PDT 24
Peak memory 206536 kb
Host smart-164a6204-ab96-4faa-b049-24022ea2c64a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284304301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.4284304301
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.2396527695
Short name T310
Test name
Test status
Simulation time 329771613 ps
CPU time 18.58 seconds
Started Apr 15 01:21:21 PM PDT 24
Finished Apr 15 01:21:40 PM PDT 24
Peak memory 232492 kb
Host smart-7c312851-9ff3-4508-8576-90035dd9aa57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396527695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2396527695
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.723218941
Short name T237
Test name
Test status
Simulation time 34539171174 ps
CPU time 20.75 seconds
Started Apr 15 01:21:18 PM PDT 24
Finished Apr 15 01:21:40 PM PDT 24
Peak memory 219192 kb
Host smart-38862081-81aa-4d4a-8da8-e79c3da6adb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723218941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap
.723218941
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.3218363149
Short name T258
Test name
Test status
Simulation time 54739671867 ps
CPU time 18.16 seconds
Started Apr 15 01:21:19 PM PDT 24
Finished Apr 15 01:21:38 PM PDT 24
Peak memory 237308 kb
Host smart-12635dcd-a428-4016-92a3-c3894021f349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218363149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.3218363149
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.3399979008
Short name T496
Test name
Test status
Simulation time 1873366896 ps
CPU time 9.09 seconds
Started Apr 15 01:21:18 PM PDT 24
Finished Apr 15 01:21:27 PM PDT 24
Peak memory 218736 kb
Host smart-5ad79f34-f81a-463e-bd4c-71c0f568f9b5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3399979008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.3399979008
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.1133682910
Short name T638
Test name
Test status
Simulation time 6768027169 ps
CPU time 10.67 seconds
Started Apr 15 01:21:22 PM PDT 24
Finished Apr 15 01:21:33 PM PDT 24
Peak memory 216240 kb
Host smart-48c9071d-7117-461e-aa01-c54caf63a727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133682910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.1133682910
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.1951722064
Short name T635
Test name
Test status
Simulation time 10757819144 ps
CPU time 31.79 seconds
Started Apr 15 01:21:21 PM PDT 24
Finished Apr 15 01:21:53 PM PDT 24
Peak memory 216008 kb
Host smart-be191013-d772-43ad-83ef-3b00d1a60a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951722064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.1951722064
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.564307708
Short name T683
Test name
Test status
Simulation time 176298881 ps
CPU time 1.3 seconds
Started Apr 15 01:21:19 PM PDT 24
Finished Apr 15 01:21:21 PM PDT 24
Peak memory 207956 kb
Host smart-1fabd7ba-fbe4-4ad8-849f-7adcf744b4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564307708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.564307708
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.18082112
Short name T535
Test name
Test status
Simulation time 166302927 ps
CPU time 0.97 seconds
Started Apr 15 01:21:18 PM PDT 24
Finished Apr 15 01:21:20 PM PDT 24
Peak memory 206656 kb
Host smart-24b48d20-3c04-492f-9478-6a7f310f7856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18082112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.18082112
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.2841139751
Short name T558
Test name
Test status
Simulation time 13925449 ps
CPU time 0.69 seconds
Started Apr 15 01:21:27 PM PDT 24
Finished Apr 15 01:21:28 PM PDT 24
Peak memory 204800 kb
Host smart-e83746d0-0e35-419e-b223-1b11f96acd1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841139751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
2841139751
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.1183805326
Short name T611
Test name
Test status
Simulation time 165659118 ps
CPU time 3.14 seconds
Started Apr 15 01:21:24 PM PDT 24
Finished Apr 15 01:21:27 PM PDT 24
Peak memory 222764 kb
Host smart-241e862c-c426-4a7b-93d7-f451251460af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183805326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.1183805326
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.1651912815
Short name T653
Test name
Test status
Simulation time 30039252 ps
CPU time 0.77 seconds
Started Apr 15 01:21:22 PM PDT 24
Finished Apr 15 01:21:23 PM PDT 24
Peak memory 206496 kb
Host smart-6e7135a7-8aa0-47d7-9950-59485f48009d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651912815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.1651912815
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.3720790075
Short name T355
Test name
Test status
Simulation time 4667293354 ps
CPU time 67.72 seconds
Started Apr 15 01:21:24 PM PDT 24
Finished Apr 15 01:22:32 PM PDT 24
Peak memory 249068 kb
Host smart-0302ab5d-62b0-4aef-8ff1-fb7465be1c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720790075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.3720790075
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.3454540851
Short name T254
Test name
Test status
Simulation time 5551898783 ps
CPU time 54.44 seconds
Started Apr 15 01:21:26 PM PDT 24
Finished Apr 15 01:22:21 PM PDT 24
Peak memory 234764 kb
Host smart-d6212bb6-1dab-4b34-ad7c-2e99f2088f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454540851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.3454540851
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.4118852939
Short name T350
Test name
Test status
Simulation time 1408008674 ps
CPU time 4.97 seconds
Started Apr 15 01:21:24 PM PDT 24
Finished Apr 15 01:21:29 PM PDT 24
Peak memory 222820 kb
Host smart-dab1240c-0f2b-448b-a342-fedf1df5ac0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118852939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.4118852939
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.3167447657
Short name T130
Test name
Test status
Simulation time 5938472756 ps
CPU time 6.78 seconds
Started Apr 15 01:21:26 PM PDT 24
Finished Apr 15 01:21:33 PM PDT 24
Peak memory 222800 kb
Host smart-c4c96001-be23-42b8-840b-bf3855b14fc1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3167447657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.3167447657
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.3910628243
Short name T390
Test name
Test status
Simulation time 1308473789 ps
CPU time 12.76 seconds
Started Apr 15 01:21:23 PM PDT 24
Finished Apr 15 01:21:37 PM PDT 24
Peak memory 217868 kb
Host smart-db081692-6885-4fac-be98-ec4630e0c660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910628243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.3910628243
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.1755733541
Short name T491
Test name
Test status
Simulation time 1654048850 ps
CPU time 10.69 seconds
Started Apr 15 01:21:25 PM PDT 24
Finished Apr 15 01:21:36 PM PDT 24
Peak memory 216160 kb
Host smart-2191b883-8e0d-46ba-b0dd-f12446fe28a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755733541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.1755733541
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.234457703
Short name T489
Test name
Test status
Simulation time 1020699323 ps
CPU time 3.12 seconds
Started Apr 15 01:21:23 PM PDT 24
Finished Apr 15 01:21:27 PM PDT 24
Peak memory 216208 kb
Host smart-c831d14a-f39f-4b3e-ad44-e456a6ff1598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234457703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.234457703
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.1032329828
Short name T474
Test name
Test status
Simulation time 26192555 ps
CPU time 0.75 seconds
Started Apr 15 01:21:23 PM PDT 24
Finished Apr 15 01:21:24 PM PDT 24
Peak memory 205668 kb
Host smart-b5b53a4a-88f6-479e-ba07-e0734713481c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032329828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.1032329828
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.3386722439
Short name T579
Test name
Test status
Simulation time 14367234 ps
CPU time 0.71 seconds
Started Apr 15 01:21:37 PM PDT 24
Finished Apr 15 01:21:39 PM PDT 24
Peak memory 205348 kb
Host smart-cbde4755-a646-4b34-a6f9-b2b49cb5d020
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386722439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
3386722439
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.2686410213
Short name T52
Test name
Test status
Simulation time 56057890 ps
CPU time 0.78 seconds
Started Apr 15 01:21:27 PM PDT 24
Finished Apr 15 01:21:28 PM PDT 24
Peak memory 206824 kb
Host smart-7960b26c-12b9-439b-96d5-c8cdae01cd65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686410213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2686410213
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.1944520257
Short name T306
Test name
Test status
Simulation time 15032327863 ps
CPU time 25.22 seconds
Started Apr 15 01:21:36 PM PDT 24
Finished Apr 15 01:22:02 PM PDT 24
Peak memory 250592 kb
Host smart-c918de0a-c5b5-44c3-92e7-a45442acab1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944520257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.1944520257
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.652259026
Short name T165
Test name
Test status
Simulation time 571182416 ps
CPU time 8.31 seconds
Started Apr 15 01:21:28 PM PDT 24
Finished Apr 15 01:21:37 PM PDT 24
Peak memory 223312 kb
Host smart-4cec8abd-b682-4527-b17b-0258bfa56bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652259026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.652259026
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.2163302305
Short name T577
Test name
Test status
Simulation time 115055551 ps
CPU time 4.01 seconds
Started Apr 15 01:21:37 PM PDT 24
Finished Apr 15 01:21:41 PM PDT 24
Peak memory 222312 kb
Host smart-568e7126-9482-4e03-8c79-cd92db86eac7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2163302305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.2163302305
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.1145074703
Short name T382
Test name
Test status
Simulation time 7907140686 ps
CPU time 13.04 seconds
Started Apr 15 01:21:28 PM PDT 24
Finished Apr 15 01:21:41 PM PDT 24
Peak memory 216376 kb
Host smart-fce5425e-f9db-4901-ac45-f0524d58513b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145074703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.1145074703
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.1183574951
Short name T589
Test name
Test status
Simulation time 3124523032 ps
CPU time 12.09 seconds
Started Apr 15 01:21:28 PM PDT 24
Finished Apr 15 01:21:40 PM PDT 24
Peak memory 216256 kb
Host smart-af7d3a62-a099-4844-a75d-401bf5ae93c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183574951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.1183574951
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.456037736
Short name T398
Test name
Test status
Simulation time 422676079 ps
CPU time 1.92 seconds
Started Apr 15 01:21:28 PM PDT 24
Finished Apr 15 01:21:31 PM PDT 24
Peak memory 216248 kb
Host smart-c0e078da-a0c9-4309-993d-1245ffe24701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456037736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.456037736
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.3796337099
Short name T483
Test name
Test status
Simulation time 44071766 ps
CPU time 0.9 seconds
Started Apr 15 01:21:29 PM PDT 24
Finished Apr 15 01:21:30 PM PDT 24
Peak memory 205684 kb
Host smart-191436dd-479a-4d21-9c1b-c39d365756ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796337099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.3796337099
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.886132168
Short name T687
Test name
Test status
Simulation time 12844353 ps
CPU time 0.73 seconds
Started Apr 15 01:21:44 PM PDT 24
Finished Apr 15 01:21:45 PM PDT 24
Peak memory 204760 kb
Host smart-5d54eff9-54f4-4053-8ce7-40d6d3d4512d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886132168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.886132168
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.273250553
Short name T330
Test name
Test status
Simulation time 43338832115 ps
CPU time 27.5 seconds
Started Apr 15 01:21:41 PM PDT 24
Finished Apr 15 01:22:09 PM PDT 24
Peak memory 219316 kb
Host smart-a1fcea58-d484-4e65-bc56-41bc2630e5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273250553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.273250553
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.1155579500
Short name T158
Test name
Test status
Simulation time 50325934 ps
CPU time 0.78 seconds
Started Apr 15 01:21:34 PM PDT 24
Finished Apr 15 01:21:35 PM PDT 24
Peak memory 206500 kb
Host smart-d2afa080-de02-4069-bc2e-6ded778d310a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155579500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.1155579500
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.114667190
Short name T438
Test name
Test status
Simulation time 148446731 ps
CPU time 3.53 seconds
Started Apr 15 01:21:41 PM PDT 24
Finished Apr 15 01:21:45 PM PDT 24
Peak memory 222972 kb
Host smart-b8b4996d-5edf-4807-9c34-2c7dd8e8c441
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=114667190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dire
ct.114667190
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.337847423
Short name T403
Test name
Test status
Simulation time 14320311495 ps
CPU time 38.72 seconds
Started Apr 15 01:21:41 PM PDT 24
Finished Apr 15 01:22:20 PM PDT 24
Peak memory 216236 kb
Host smart-c3d5327f-2a47-421b-b6a4-e73850826790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337847423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.337847423
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.1907072650
Short name T716
Test name
Test status
Simulation time 7681488164 ps
CPU time 21.25 seconds
Started Apr 15 01:21:35 PM PDT 24
Finished Apr 15 01:21:57 PM PDT 24
Peak memory 216228 kb
Host smart-746c726a-439e-45bd-b15c-bb8f8e309378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907072650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.1907072650
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.3164243823
Short name T510
Test name
Test status
Simulation time 182792403 ps
CPU time 2.17 seconds
Started Apr 15 01:21:40 PM PDT 24
Finished Apr 15 01:21:42 PM PDT 24
Peak memory 216244 kb
Host smart-90e8efc4-4cc5-4670-a094-551d084d1efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164243823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.3164243823
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.4268546595
Short name T56
Test name
Test status
Simulation time 112519559 ps
CPU time 1.06 seconds
Started Apr 15 01:21:40 PM PDT 24
Finished Apr 15 01:21:42 PM PDT 24
Peak memory 206740 kb
Host smart-d487b671-4297-41a0-9bfe-20a5f1caa81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268546595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.4268546595
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.3498345405
Short name T441
Test name
Test status
Simulation time 53877805 ps
CPU time 0.76 seconds
Started Apr 15 01:21:46 PM PDT 24
Finished Apr 15 01:21:47 PM PDT 24
Peak memory 204844 kb
Host smart-5e074cfe-d992-4777-931f-71d683ea1e14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498345405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
3498345405
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.501476510
Short name T557
Test name
Test status
Simulation time 39620194 ps
CPU time 0.75 seconds
Started Apr 15 01:21:43 PM PDT 24
Finished Apr 15 01:21:44 PM PDT 24
Peak memory 206368 kb
Host smart-d32e5f2d-c2c8-414c-8842-5e0240414e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501476510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.501476510
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.3647827470
Short name T363
Test name
Test status
Simulation time 2220922965 ps
CPU time 13.51 seconds
Started Apr 15 01:21:48 PM PDT 24
Finished Apr 15 01:22:02 PM PDT 24
Peak memory 240864 kb
Host smart-0fe2b475-96e7-421a-8737-bc29baebfee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647827470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.3647827470
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.3112330021
Short name T42
Test name
Test status
Simulation time 1706244127 ps
CPU time 23.32 seconds
Started Apr 15 01:21:44 PM PDT 24
Finished Apr 15 01:22:08 PM PDT 24
Peak memory 223784 kb
Host smart-1b5cb33e-e5bd-479a-9bde-fe2460711ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112330021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.3112330021
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.1695018639
Short name T295
Test name
Test status
Simulation time 19463399537 ps
CPU time 21.56 seconds
Started Apr 15 01:21:43 PM PDT 24
Finished Apr 15 01:22:05 PM PDT 24
Peak memory 233264 kb
Host smart-d5797e1d-a0c0-464d-9941-07e68c37b18d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695018639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.1695018639
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.4015427127
Short name T91
Test name
Test status
Simulation time 367632472 ps
CPU time 6.32 seconds
Started Apr 15 01:21:44 PM PDT 24
Finished Apr 15 01:21:50 PM PDT 24
Peak memory 232904 kb
Host smart-f2abce4a-3ffa-4257-b9b2-833b31163f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015427127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.4015427127
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.3361559149
Short name T160
Test name
Test status
Simulation time 1524037587 ps
CPU time 6.18 seconds
Started Apr 15 01:21:49 PM PDT 24
Finished Apr 15 01:21:55 PM PDT 24
Peak memory 218780 kb
Host smart-22646604-fc66-4714-b556-d1d54ecac64f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3361559149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.3361559149
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.2995263936
Short name T679
Test name
Test status
Simulation time 179576689 ps
CPU time 0.97 seconds
Started Apr 15 01:21:47 PM PDT 24
Finished Apr 15 01:21:49 PM PDT 24
Peak memory 206900 kb
Host smart-2a16fa72-d268-4f62-925d-e91e52bda0f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995263936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.2995263936
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.2108486848
Short name T702
Test name
Test status
Simulation time 1187786703 ps
CPU time 2.11 seconds
Started Apr 15 01:21:46 PM PDT 24
Finished Apr 15 01:21:48 PM PDT 24
Peak memory 215736 kb
Host smart-a0b39b6d-c001-4f6a-85ef-8b69eead60a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108486848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.2108486848
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.2508875145
Short name T599
Test name
Test status
Simulation time 343385860 ps
CPU time 3.4 seconds
Started Apr 15 01:21:45 PM PDT 24
Finished Apr 15 01:21:49 PM PDT 24
Peak memory 216208 kb
Host smart-7fcd59f1-b6d2-40a2-8f17-9a1f54c31a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508875145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.2508875145
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.2986547174
Short name T575
Test name
Test status
Simulation time 481653623 ps
CPU time 1.04 seconds
Started Apr 15 01:21:46 PM PDT 24
Finished Apr 15 01:21:48 PM PDT 24
Peak memory 206692 kb
Host smart-8914382c-7b46-49fa-b50c-e8a6835b450d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986547174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.2986547174
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.274636455
Short name T681
Test name
Test status
Simulation time 38508451856 ps
CPU time 55.85 seconds
Started Apr 15 01:21:44 PM PDT 24
Finished Apr 15 01:22:40 PM PDT 24
Peak memory 240148 kb
Host smart-68f72e47-d14d-48f3-9e01-a9b8911664ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274636455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.274636455
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.2595992355
Short name T512
Test name
Test status
Simulation time 23360533 ps
CPU time 0.69 seconds
Started Apr 15 01:21:53 PM PDT 24
Finished Apr 15 01:21:54 PM PDT 24
Peak memory 205400 kb
Host smart-85e60403-7fb9-4d5c-8f46-d8a96a40a053
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595992355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
2595992355
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.1126666468
Short name T84
Test name
Test status
Simulation time 1257058700 ps
CPU time 14.92 seconds
Started Apr 15 01:21:54 PM PDT 24
Finished Apr 15 01:22:09 PM PDT 24
Peak memory 218180 kb
Host smart-14cf4cb0-0bd0-4b4c-9279-c5bdc30a8993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126666468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.1126666468
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.3043164993
Short name T618
Test name
Test status
Simulation time 13983541 ps
CPU time 0.79 seconds
Started Apr 15 01:21:48 PM PDT 24
Finished Apr 15 01:21:50 PM PDT 24
Peak memory 206496 kb
Host smart-0737081d-555f-41c5-89ae-ba85dbf9f769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043164993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.3043164993
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.1936105955
Short name T362
Test name
Test status
Simulation time 6841785355 ps
CPU time 57.75 seconds
Started Apr 15 01:21:54 PM PDT 24
Finished Apr 15 01:22:53 PM PDT 24
Peak memory 240868 kb
Host smart-1170fc1d-56dd-45af-8de5-f6fd05b3ad6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936105955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.1936105955
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.3482902566
Short name T259
Test name
Test status
Simulation time 17651606578 ps
CPU time 23.53 seconds
Started Apr 15 01:21:53 PM PDT 24
Finished Apr 15 01:22:17 PM PDT 24
Peak memory 232504 kb
Host smart-fdc82e8d-5530-4d24-8989-410f492c5c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482902566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.3482902566
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.939969519
Short name T226
Test name
Test status
Simulation time 40112423904 ps
CPU time 102.88 seconds
Started Apr 15 01:21:52 PM PDT 24
Finished Apr 15 01:23:35 PM PDT 24
Peak memory 238924 kb
Host smart-3ecb46f0-3a57-4ee8-8cf2-76fdccf90593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939969519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.939969519
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.4141776853
Short name T229
Test name
Test status
Simulation time 5625071542 ps
CPU time 12.31 seconds
Started Apr 15 01:21:47 PM PDT 24
Finished Apr 15 01:22:00 PM PDT 24
Peak memory 236592 kb
Host smart-b5554ba6-3e25-476f-ad87-1fee32d3c867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141776853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.4141776853
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.3080716037
Short name T654
Test name
Test status
Simulation time 2936571174 ps
CPU time 7.7 seconds
Started Apr 15 01:21:53 PM PDT 24
Finished Apr 15 01:22:01 PM PDT 24
Peak memory 220108 kb
Host smart-9b59c189-c9bf-4579-bc16-3cdf610db4f6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3080716037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.3080716037
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.1510770150
Short name T556
Test name
Test status
Simulation time 196100415 ps
CPU time 1.07 seconds
Started Apr 15 01:21:53 PM PDT 24
Finished Apr 15 01:21:55 PM PDT 24
Peak memory 206928 kb
Host smart-60fc4c5c-0747-4be8-ac78-8dd761ab343b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510770150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.1510770150
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.4281545765
Short name T103
Test name
Test status
Simulation time 10567533547 ps
CPU time 35.26 seconds
Started Apr 15 01:21:47 PM PDT 24
Finished Apr 15 01:22:23 PM PDT 24
Peak memory 216244 kb
Host smart-96391e5f-9e99-4c81-b3e4-7792c74c6505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281545765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.4281545765
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.2040337371
Short name T574
Test name
Test status
Simulation time 42175372989 ps
CPU time 28.44 seconds
Started Apr 15 01:21:50 PM PDT 24
Finished Apr 15 01:22:18 PM PDT 24
Peak memory 216272 kb
Host smart-42bc362c-be06-4064-93d1-8b33c5d93281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040337371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.2040337371
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.3244608307
Short name T591
Test name
Test status
Simulation time 792327712 ps
CPU time 2.46 seconds
Started Apr 15 01:21:49 PM PDT 24
Finished Apr 15 01:21:52 PM PDT 24
Peak memory 215984 kb
Host smart-f2fc9a1e-d505-4445-92c7-e0a65cb15a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244608307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.3244608307
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.714716403
Short name T451
Test name
Test status
Simulation time 202096300 ps
CPU time 0.8 seconds
Started Apr 15 01:21:47 PM PDT 24
Finished Apr 15 01:21:48 PM PDT 24
Peak memory 205736 kb
Host smart-930e879a-bb53-42c9-a86b-ae7919f346a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714716403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.714716403
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.3126005969
Short name T115
Test name
Test status
Simulation time 2981356189 ps
CPU time 7.37 seconds
Started Apr 15 01:21:53 PM PDT 24
Finished Apr 15 01:22:01 PM PDT 24
Peak memory 216244 kb
Host smart-ff1bc9ca-830d-41e7-a3a0-7f41cfb4aac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126005969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.3126005969
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.1190717939
Short name T650
Test name
Test status
Simulation time 27984995 ps
CPU time 0.75 seconds
Started Apr 15 01:22:02 PM PDT 24
Finished Apr 15 01:22:03 PM PDT 24
Peak memory 204780 kb
Host smart-8693528a-ce1d-4efd-99f4-6b1187d087b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190717939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
1190717939
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.2278712043
Short name T648
Test name
Test status
Simulation time 819951509 ps
CPU time 5.18 seconds
Started Apr 15 01:21:55 PM PDT 24
Finished Apr 15 01:22:01 PM PDT 24
Peak memory 223344 kb
Host smart-f68cc4e9-5fc0-49d3-b44c-122277b2037f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278712043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.2278712043
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.4149107276
Short name T619
Test name
Test status
Simulation time 23969172 ps
CPU time 0.75 seconds
Started Apr 15 01:21:53 PM PDT 24
Finished Apr 15 01:21:54 PM PDT 24
Peak memory 206800 kb
Host smart-4b5fcacd-5cfd-4076-bacf-21ebe7644b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149107276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.4149107276
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_intercept.2049141369
Short name T171
Test name
Test status
Simulation time 1725585641 ps
CPU time 5.37 seconds
Started Apr 15 01:21:55 PM PDT 24
Finished Apr 15 01:22:01 PM PDT 24
Peak memory 221052 kb
Host smart-8b10abcc-9bed-42e6-93a5-b031600adf8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049141369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.2049141369
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.811543540
Short name T315
Test name
Test status
Simulation time 7654807120 ps
CPU time 14.43 seconds
Started Apr 15 01:21:56 PM PDT 24
Finished Apr 15 01:22:11 PM PDT 24
Peak memory 222808 kb
Host smart-41ba0f96-1ec6-4346-8ae0-ba91d533c9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811543540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.811543540
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.3560375751
Short name T639
Test name
Test status
Simulation time 967304995 ps
CPU time 5.06 seconds
Started Apr 15 01:21:56 PM PDT 24
Finished Apr 15 01:22:02 PM PDT 24
Peak memory 219072 kb
Host smart-8ff4fd2b-76ee-4ec6-aec0-f9255a699df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560375751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.3560375751
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.3486642878
Short name T564
Test name
Test status
Simulation time 531689626 ps
CPU time 7.21 seconds
Started Apr 15 01:21:55 PM PDT 24
Finished Apr 15 01:22:03 PM PDT 24
Peak memory 219152 kb
Host smart-6a973a77-2323-4f5b-b4d6-89fb4aed1d20
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3486642878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.3486642878
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.861933981
Short name T386
Test name
Test status
Simulation time 13688726318 ps
CPU time 56.98 seconds
Started Apr 15 01:21:54 PM PDT 24
Finished Apr 15 01:22:52 PM PDT 24
Peak memory 216336 kb
Host smart-e111bf5d-950d-45a5-af7e-22f6f18c0b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861933981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.861933981
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2441123685
Short name T689
Test name
Test status
Simulation time 1063584662 ps
CPU time 1.66 seconds
Started Apr 15 01:21:53 PM PDT 24
Finished Apr 15 01:21:55 PM PDT 24
Peak memory 207780 kb
Host smart-ec70f407-9278-454e-a58e-aba40ed11955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441123685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2441123685
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.447390277
Short name T397
Test name
Test status
Simulation time 153716190 ps
CPU time 2.22 seconds
Started Apr 15 01:21:53 PM PDT 24
Finished Apr 15 01:21:56 PM PDT 24
Peak memory 216160 kb
Host smart-3e87217c-c1b8-40f3-ac8e-1be56ee2ec28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447390277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.447390277
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.2811356316
Short name T415
Test name
Test status
Simulation time 108045978 ps
CPU time 0.98 seconds
Started Apr 15 01:21:52 PM PDT 24
Finished Apr 15 01:21:53 PM PDT 24
Peak memory 206712 kb
Host smart-e6f92cb7-2072-4992-a6e4-86c96965e38c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811356316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.2811356316
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.3103824168
Short name T713
Test name
Test status
Simulation time 98975838 ps
CPU time 0.72 seconds
Started Apr 15 01:22:05 PM PDT 24
Finished Apr 15 01:22:06 PM PDT 24
Peak memory 205388 kb
Host smart-5734fd81-5b94-4b68-8092-0e10e8e66d55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103824168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
3103824168
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.939089142
Short name T190
Test name
Test status
Simulation time 1903759141 ps
CPU time 6.13 seconds
Started Apr 15 01:22:02 PM PDT 24
Finished Apr 15 01:22:08 PM PDT 24
Peak memory 231640 kb
Host smart-2d778cad-3963-4e4f-beee-a54bb9a6a1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939089142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.939089142
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.4227334935
Short name T581
Test name
Test status
Simulation time 13350148 ps
CPU time 0.76 seconds
Started Apr 15 01:22:04 PM PDT 24
Finished Apr 15 01:22:05 PM PDT 24
Peak memory 206524 kb
Host smart-34f5b712-5ad6-4806-a15b-3e705903deeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227334935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.4227334935
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.781537210
Short name T356
Test name
Test status
Simulation time 6523669428 ps
CPU time 20.61 seconds
Started Apr 15 01:22:01 PM PDT 24
Finished Apr 15 01:22:22 PM PDT 24
Peak memory 249052 kb
Host smart-65f1f2cc-8c66-4f07-9c57-fa2b5aac8409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781537210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.781537210
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.3842871764
Short name T164
Test name
Test status
Simulation time 6118323840 ps
CPU time 14.83 seconds
Started Apr 15 01:22:03 PM PDT 24
Finished Apr 15 01:22:18 PM PDT 24
Peak memory 223840 kb
Host smart-1a966bee-c9a3-4a97-85ff-e093fcf3436c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842871764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.3842871764
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.1794746597
Short name T284
Test name
Test status
Simulation time 4889364973 ps
CPU time 27.82 seconds
Started Apr 15 01:22:01 PM PDT 24
Finished Apr 15 01:22:30 PM PDT 24
Peak memory 239928 kb
Host smart-47941f1f-03a4-4796-832a-d9260a022f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794746597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.1794746597
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.3940302941
Short name T277
Test name
Test status
Simulation time 5587344577 ps
CPU time 9.33 seconds
Started Apr 15 01:22:00 PM PDT 24
Finished Apr 15 01:22:10 PM PDT 24
Peak memory 218704 kb
Host smart-16f5fda2-9812-4d6e-8b2a-37043950a9c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940302941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.3940302941
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.2317875434
Short name T455
Test name
Test status
Simulation time 1276536222 ps
CPU time 18.41 seconds
Started Apr 15 01:22:02 PM PDT 24
Finished Apr 15 01:22:21 PM PDT 24
Peak memory 219060 kb
Host smart-ff55b81e-d07b-4e2e-9390-45566493d837
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2317875434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.2317875434
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.1428807499
Short name T394
Test name
Test status
Simulation time 47462416975 ps
CPU time 31.3 seconds
Started Apr 15 01:22:00 PM PDT 24
Finished Apr 15 01:22:32 PM PDT 24
Peak memory 216120 kb
Host smart-dee05ed4-9c8d-48ca-9d59-1cb1e3a5f41e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428807499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.1428807499
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.2280828523
Short name T623
Test name
Test status
Simulation time 5383494167 ps
CPU time 19.51 seconds
Started Apr 15 01:22:03 PM PDT 24
Finished Apr 15 01:22:23 PM PDT 24
Peak memory 216220 kb
Host smart-725741a3-e99e-46ed-9eca-6dfbfd25d1fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280828523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.2280828523
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.2001244619
Short name T62
Test name
Test status
Simulation time 179238377 ps
CPU time 1.96 seconds
Started Apr 15 01:22:02 PM PDT 24
Finished Apr 15 01:22:04 PM PDT 24
Peak memory 215628 kb
Host smart-85a2eae9-9910-459f-bbcf-6cc4fb3542d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001244619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.2001244619
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.1042287712
Short name T540
Test name
Test status
Simulation time 39865011 ps
CPU time 0.91 seconds
Started Apr 15 01:22:02 PM PDT 24
Finished Apr 15 01:22:03 PM PDT 24
Peak memory 206728 kb
Host smart-15ae2ead-a662-4c5c-804c-205d18bba596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042287712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.1042287712
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.1402818660
Short name T698
Test name
Test status
Simulation time 42417114 ps
CPU time 0.7 seconds
Started Apr 15 01:22:11 PM PDT 24
Finished Apr 15 01:22:12 PM PDT 24
Peak memory 205352 kb
Host smart-eb549ad3-8dbb-4649-ad95-953db399d86d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402818660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
1402818660
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.3119038311
Short name T416
Test name
Test status
Simulation time 206523976 ps
CPU time 0.81 seconds
Started Apr 15 01:22:11 PM PDT 24
Finished Apr 15 01:22:13 PM PDT 24
Peak memory 206456 kb
Host smart-aedab7a9-aa0f-4e68-820a-fd13007f0dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119038311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.3119038311
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.4061832329
Short name T308
Test name
Test status
Simulation time 17976694542 ps
CPU time 71.65 seconds
Started Apr 15 01:22:07 PM PDT 24
Finished Apr 15 01:23:19 PM PDT 24
Peak memory 232608 kb
Host smart-f2eba215-ba09-4f03-b9bb-795d3bc07a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061832329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.4061832329
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.2123418964
Short name T111
Test name
Test status
Simulation time 2252772411 ps
CPU time 15.71 seconds
Started Apr 15 01:22:07 PM PDT 24
Finished Apr 15 01:22:23 PM PDT 24
Peak memory 221924 kb
Host smart-989e867a-0fbf-4afa-8a37-fb66077172e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123418964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.2123418964
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.3943436484
Short name T257
Test name
Test status
Simulation time 2419133123 ps
CPU time 4.99 seconds
Started Apr 15 01:22:09 PM PDT 24
Finished Apr 15 01:22:15 PM PDT 24
Peak memory 218704 kb
Host smart-c85ad64e-4dd2-44c6-85b0-89574d9826db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943436484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.3943436484
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.372785292
Short name T630
Test name
Test status
Simulation time 4598010914 ps
CPU time 12.97 seconds
Started Apr 15 01:22:09 PM PDT 24
Finished Apr 15 01:22:23 PM PDT 24
Peak memory 219928 kb
Host smart-24e2b3e1-f8ed-4f8a-bc5b-fce25a4fc0cd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=372785292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dire
ct.372785292
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.2387648555
Short name T34
Test name
Test status
Simulation time 37218348 ps
CPU time 0.94 seconds
Started Apr 15 01:22:11 PM PDT 24
Finished Apr 15 01:22:12 PM PDT 24
Peak memory 206504 kb
Host smart-8ef85f95-c5d7-4d3c-811a-ab87d05d09b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387648555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.2387648555
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.2412734584
Short name T669
Test name
Test status
Simulation time 2134769611 ps
CPU time 13.78 seconds
Started Apr 15 01:22:04 PM PDT 24
Finished Apr 15 01:22:18 PM PDT 24
Peak memory 216172 kb
Host smart-d14832a3-55b7-4152-9a03-4556dfaf8ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412734584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.2412734584
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.343472613
Short name T520
Test name
Test status
Simulation time 876767065 ps
CPU time 4.03 seconds
Started Apr 15 01:22:05 PM PDT 24
Finished Apr 15 01:22:10 PM PDT 24
Peak memory 216136 kb
Host smart-e66ce5d7-144a-4b7d-a37f-8a99c35335de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343472613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.343472613
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.2138224165
Short name T569
Test name
Test status
Simulation time 198826776 ps
CPU time 1.36 seconds
Started Apr 15 01:22:08 PM PDT 24
Finished Apr 15 01:22:10 PM PDT 24
Peak memory 216100 kb
Host smart-9197915c-5e47-4e7a-8df6-62f754093430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138224165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.2138224165
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.980455753
Short name T473
Test name
Test status
Simulation time 219483549 ps
CPU time 0.85 seconds
Started Apr 15 01:22:09 PM PDT 24
Finished Apr 15 01:22:10 PM PDT 24
Peak memory 205692 kb
Host smart-6efd118c-d405-4b53-ad05-da5583f23bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980455753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.980455753
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.4073143151
Short name T282
Test name
Test status
Simulation time 23135913074 ps
CPU time 18.42 seconds
Started Apr 15 01:22:07 PM PDT 24
Finished Apr 15 01:22:25 PM PDT 24
Peak memory 224496 kb
Host smart-a138d968-26e4-4f7c-8346-3d092806c01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073143151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.4073143151
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.3111874564
Short name T420
Test name
Test status
Simulation time 30371753 ps
CPU time 0.73 seconds
Started Apr 15 01:22:21 PM PDT 24
Finished Apr 15 01:22:22 PM PDT 24
Peak memory 205752 kb
Host smart-3d0b3229-6b07-49de-bb44-96f50a04d7a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111874564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
3111874564
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.2258400756
Short name T612
Test name
Test status
Simulation time 252969680 ps
CPU time 0.79 seconds
Started Apr 15 01:22:10 PM PDT 24
Finished Apr 15 01:22:12 PM PDT 24
Peak memory 206860 kb
Host smart-0c1d9a4f-c95a-4e00-87c8-3b97fe31255d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258400756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.2258400756
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.168778479
Short name T180
Test name
Test status
Simulation time 2154264536 ps
CPU time 15.74 seconds
Started Apr 15 01:22:15 PM PDT 24
Finished Apr 15 01:22:31 PM PDT 24
Peak memory 232468 kb
Host smart-766a2319-3de7-4ef6-9732-b1b02b8851f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168778479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.168778479
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.3035266966
Short name T217
Test name
Test status
Simulation time 661626668 ps
CPU time 8.08 seconds
Started Apr 15 01:22:14 PM PDT 24
Finished Apr 15 01:22:22 PM PDT 24
Peak memory 219052 kb
Host smart-88b814bb-1815-47dd-8b21-a59acc8b5263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035266966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.3035266966
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.2146085045
Short name T242
Test name
Test status
Simulation time 1719196886 ps
CPU time 4.07 seconds
Started Apr 15 01:22:17 PM PDT 24
Finished Apr 15 01:22:21 PM PDT 24
Peak memory 219876 kb
Host smart-9a7691d1-79e3-41cd-9730-92f3ca5d0ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146085045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.2146085045
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.4214474508
Short name T708
Test name
Test status
Simulation time 2053725549 ps
CPU time 8.78 seconds
Started Apr 15 01:22:15 PM PDT 24
Finished Apr 15 01:22:25 PM PDT 24
Peak memory 218900 kb
Host smart-cdf72f66-16ce-416d-a22a-3fe86d47e968
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4214474508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.4214474508
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.3821919309
Short name T637
Test name
Test status
Simulation time 23332328713 ps
CPU time 31.25 seconds
Started Apr 15 01:22:13 PM PDT 24
Finished Apr 15 01:22:45 PM PDT 24
Peak memory 216272 kb
Host smart-8a34f690-fc98-4233-9324-46369b114894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821919309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.3821919309
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.4180797469
Short name T682
Test name
Test status
Simulation time 9433786259 ps
CPU time 27.13 seconds
Started Apr 15 01:22:11 PM PDT 24
Finished Apr 15 01:22:39 PM PDT 24
Peak memory 216304 kb
Host smart-01b6c3dd-b685-4c95-a766-60547c07e3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180797469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.4180797469
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.2902000373
Short name T641
Test name
Test status
Simulation time 973001462 ps
CPU time 4.12 seconds
Started Apr 15 01:22:10 PM PDT 24
Finished Apr 15 01:22:15 PM PDT 24
Peak memory 216212 kb
Host smart-956837ac-c29a-4f40-8aee-37cb96bafc64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902000373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.2902000373
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.1415618500
Short name T432
Test name
Test status
Simulation time 725793989 ps
CPU time 0.85 seconds
Started Apr 15 01:22:13 PM PDT 24
Finished Apr 15 01:22:14 PM PDT 24
Peak memory 205684 kb
Host smart-751adc59-92b9-4f2d-95c0-5acacd94045f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415618500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.1415618500
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.1962795744
Short name T175
Test name
Test status
Simulation time 2702449675 ps
CPU time 6.27 seconds
Started Apr 15 01:22:16 PM PDT 24
Finished Apr 15 01:22:23 PM PDT 24
Peak memory 219552 kb
Host smart-37882454-39f1-48a6-87ec-b7a439ca598c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962795744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.1962795744
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.1767724605
Short name T456
Test name
Test status
Simulation time 25049673 ps
CPU time 0.78 seconds
Started Apr 15 01:18:48 PM PDT 24
Finished Apr 15 01:18:49 PM PDT 24
Peak memory 204836 kb
Host smart-bdfc6968-4526-482b-9669-385ec92397e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767724605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.1
767724605
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.2546456004
Short name T712
Test name
Test status
Simulation time 19493972 ps
CPU time 0.82 seconds
Started Apr 15 01:18:40 PM PDT 24
Finished Apr 15 01:18:42 PM PDT 24
Peak memory 206828 kb
Host smart-b6e59f12-0c5d-40fe-a75a-8734134a6bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546456004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.2546456004
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.1370462036
Short name T204
Test name
Test status
Simulation time 13464594377 ps
CPU time 65.29 seconds
Started Apr 15 01:18:39 PM PDT 24
Finished Apr 15 01:19:45 PM PDT 24
Peak memory 218464 kb
Host smart-41fef6b8-8ee9-477a-a3dc-f130f1b17971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370462036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.1370462036
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.3479609600
Short name T285
Test name
Test status
Simulation time 8185048047 ps
CPU time 13.59 seconds
Started Apr 15 01:18:45 PM PDT 24
Finished Apr 15 01:19:00 PM PDT 24
Peak memory 232104 kb
Host smart-66d221a8-b230-459f-a1d9-8001cd84142e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479609600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.3479609600
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.660749320
Short name T291
Test name
Test status
Simulation time 4681014837 ps
CPU time 12.11 seconds
Started Apr 15 01:18:42 PM PDT 24
Finished Apr 15 01:18:55 PM PDT 24
Peak memory 222400 kb
Host smart-74d6ab6f-4ed5-4682-836d-177a968a5411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660749320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.660749320
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.143439957
Short name T411
Test name
Test status
Simulation time 1264587902 ps
CPU time 16.07 seconds
Started Apr 15 01:18:41 PM PDT 24
Finished Apr 15 01:18:58 PM PDT 24
Peak memory 218992 kb
Host smart-bd1e3343-8190-44a4-b783-a37cdeb0618e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=143439957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direc
t.143439957
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.2243213988
Short name T395
Test name
Test status
Simulation time 103867988324 ps
CPU time 46.78 seconds
Started Apr 15 01:18:50 PM PDT 24
Finished Apr 15 01:19:38 PM PDT 24
Peak memory 216264 kb
Host smart-b2af9577-a9cd-416f-ae1d-bf86718eabd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243213988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.2243213988
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.3932209628
Short name T573
Test name
Test status
Simulation time 3618404063 ps
CPU time 11.04 seconds
Started Apr 15 01:19:00 PM PDT 24
Finished Apr 15 01:19:12 PM PDT 24
Peak memory 216252 kb
Host smart-80371f5e-c5ba-442e-bb79-bbc819f58168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932209628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.3932209628
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.1898537410
Short name T453
Test name
Test status
Simulation time 1351661452 ps
CPU time 7.09 seconds
Started Apr 15 01:18:46 PM PDT 24
Finished Apr 15 01:18:54 PM PDT 24
Peak memory 216244 kb
Host smart-69f5ee04-a729-408c-8674-4dccedffec99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898537410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.1898537410
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.2833325788
Short name T528
Test name
Test status
Simulation time 155750314 ps
CPU time 0.82 seconds
Started Apr 15 01:18:44 PM PDT 24
Finished Apr 15 01:18:45 PM PDT 24
Peak memory 205700 kb
Host smart-b11571f5-6d1d-413a-899b-249c8bf43821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833325788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.2833325788
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.2183927328
Short name T595
Test name
Test status
Simulation time 32388579 ps
CPU time 0.7 seconds
Started Apr 15 01:18:53 PM PDT 24
Finished Apr 15 01:18:55 PM PDT 24
Peak memory 205716 kb
Host smart-675728d9-dfb9-435a-a667-46a0258aa385
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183927328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.2
183927328
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.1613900549
Short name T701
Test name
Test status
Simulation time 66456860 ps
CPU time 0.77 seconds
Started Apr 15 01:18:48 PM PDT 24
Finished Apr 15 01:18:49 PM PDT 24
Peak memory 206808 kb
Host smart-ac43cee8-a9a9-4ea6-a7d0-58a2a87e16da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613900549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.1613900549
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_intercept.1126755376
Short name T324
Test name
Test status
Simulation time 352057136 ps
CPU time 4.73 seconds
Started Apr 15 01:18:48 PM PDT 24
Finished Apr 15 01:18:53 PM PDT 24
Peak memory 232468 kb
Host smart-8369d9f4-a4e7-4ce7-82c4-e884a48d2e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126755376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.1126755376
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.3417196671
Short name T332
Test name
Test status
Simulation time 27460979469 ps
CPU time 20.22 seconds
Started Apr 15 01:18:47 PM PDT 24
Finished Apr 15 01:19:09 PM PDT 24
Peak memory 238792 kb
Host smart-f96ef98f-0667-412f-9f74-7f39f8ac6958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417196671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.3417196671
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.3970974431
Short name T454
Test name
Test status
Simulation time 242412369 ps
CPU time 5.66 seconds
Started Apr 15 01:18:42 PM PDT 24
Finished Apr 15 01:18:48 PM PDT 24
Peak memory 218668 kb
Host smart-4d9fd4e0-2193-42b1-a3ba-c405dbf80688
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3970974431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.3970974431
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.4053004099
Short name T606
Test name
Test status
Simulation time 1066122756 ps
CPU time 18.76 seconds
Started Apr 15 01:18:45 PM PDT 24
Finished Apr 15 01:19:04 PM PDT 24
Peak memory 216200 kb
Host smart-80bb53ba-dce1-4cb4-9d36-7c328ff95155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053004099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.4053004099
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.1757735786
Short name T446
Test name
Test status
Simulation time 166387966 ps
CPU time 1.42 seconds
Started Apr 15 01:18:45 PM PDT 24
Finished Apr 15 01:18:47 PM PDT 24
Peak memory 207560 kb
Host smart-28a7d203-291c-47a8-9a59-39a275e7426d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757735786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.1757735786
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.1871646239
Short name T431
Test name
Test status
Simulation time 208806239 ps
CPU time 1.08 seconds
Started Apr 15 01:18:50 PM PDT 24
Finished Apr 15 01:18:52 PM PDT 24
Peak memory 207588 kb
Host smart-738bc2d8-109e-42fc-99d0-d18db3ea0b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871646239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.1871646239
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.1810562060
Short name T524
Test name
Test status
Simulation time 22634338 ps
CPU time 0.8 seconds
Started Apr 15 01:18:45 PM PDT 24
Finished Apr 15 01:18:47 PM PDT 24
Peak memory 205588 kb
Host smart-873b9808-aa0d-4c4a-b3d1-78ffebc0754f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810562060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.1810562060
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.2363131920
Short name T426
Test name
Test status
Simulation time 24957062 ps
CPU time 0.73 seconds
Started Apr 15 01:18:48 PM PDT 24
Finished Apr 15 01:18:49 PM PDT 24
Peak memory 205312 kb
Host smart-c5f4c949-354e-4523-9495-80d64d68aa0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363131920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.2
363131920
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.3113074984
Short name T692
Test name
Test status
Simulation time 778699470 ps
CPU time 11.85 seconds
Started Apr 15 01:18:49 PM PDT 24
Finished Apr 15 01:19:02 PM PDT 24
Peak memory 218664 kb
Host smart-600ff491-64f1-4419-9d22-9170e505f95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113074984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.3113074984
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.1810550233
Short name T661
Test name
Test status
Simulation time 181034064 ps
CPU time 0.78 seconds
Started Apr 15 01:18:48 PM PDT 24
Finished Apr 15 01:18:49 PM PDT 24
Peak memory 206540 kb
Host smart-7b8c9014-bdc7-4d00-b0cd-d5b0b1e72e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810550233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.1810550233
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.1159365989
Short name T649
Test name
Test status
Simulation time 587838078 ps
CPU time 20.61 seconds
Started Apr 15 01:18:49 PM PDT 24
Finished Apr 15 01:19:10 PM PDT 24
Peak memory 240208 kb
Host smart-952a5309-2ada-4efb-8344-fb8b67afa9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159365989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.1159365989
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.2996435476
Short name T342
Test name
Test status
Simulation time 632140183 ps
CPU time 8.13 seconds
Started Apr 15 01:18:47 PM PDT 24
Finished Apr 15 01:18:56 PM PDT 24
Peak memory 224020 kb
Host smart-c3d96362-c73b-43f3-b8f8-eef70399f47b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996435476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.2996435476
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.297389309
Short name T600
Test name
Test status
Simulation time 179349539 ps
CPU time 5.39 seconds
Started Apr 15 01:18:46 PM PDT 24
Finished Apr 15 01:18:52 PM PDT 24
Peak memory 222040 kb
Host smart-df382237-00f7-458a-9d47-83a520c4bf51
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=297389309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direc
t.297389309
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.2030097856
Short name T597
Test name
Test status
Simulation time 2495833882 ps
CPU time 9.27 seconds
Started Apr 15 01:18:44 PM PDT 24
Finished Apr 15 01:18:55 PM PDT 24
Peak memory 216232 kb
Host smart-f57cdcc0-cea1-4643-8cef-7a3be1341600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030097856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.2030097856
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.735930538
Short name T493
Test name
Test status
Simulation time 239244882 ps
CPU time 2.12 seconds
Started Apr 15 01:18:51 PM PDT 24
Finished Apr 15 01:18:54 PM PDT 24
Peak memory 216176 kb
Host smart-85a14a5d-183f-4a7c-8dde-9de4b2b5f961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735930538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.735930538
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.274992705
Short name T523
Test name
Test status
Simulation time 223161867 ps
CPU time 0.88 seconds
Started Apr 15 01:18:47 PM PDT 24
Finished Apr 15 01:18:48 PM PDT 24
Peak memory 205656 kb
Host smart-f54b576b-f17a-467b-a970-863013b80fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274992705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.274992705
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.4043719211
Short name T77
Test name
Test status
Simulation time 837430338 ps
CPU time 6.39 seconds
Started Apr 15 01:18:48 PM PDT 24
Finished Apr 15 01:18:56 PM PDT 24
Peak memory 218780 kb
Host smart-2a6ccd14-dc9c-4d72-9e5b-6896d4151f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043719211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.4043719211
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.2057386406
Short name T457
Test name
Test status
Simulation time 13872230 ps
CPU time 0.77 seconds
Started Apr 15 01:18:52 PM PDT 24
Finished Apr 15 01:18:54 PM PDT 24
Peak memory 205692 kb
Host smart-c991e4f4-06dd-4ec9-a72a-b596244cae48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057386406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.2
057386406
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.1458495907
Short name T241
Test name
Test status
Simulation time 2564909139 ps
CPU time 21.27 seconds
Started Apr 15 01:18:50 PM PDT 24
Finished Apr 15 01:19:13 PM PDT 24
Peak memory 217332 kb
Host smart-54e2de4b-6bac-481b-9da5-2a77bbdd941f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458495907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.1458495907
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.3650643569
Short name T419
Test name
Test status
Simulation time 34805309 ps
CPU time 0.76 seconds
Started Apr 15 01:18:49 PM PDT 24
Finished Apr 15 01:18:51 PM PDT 24
Peak memory 206508 kb
Host smart-e79db48e-88be-4b3a-ba90-3325f6c1bf68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650643569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.3650643569
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.2528978320
Short name T706
Test name
Test status
Simulation time 4064051762 ps
CPU time 59.47 seconds
Started Apr 15 01:18:49 PM PDT 24
Finished Apr 15 01:19:49 PM PDT 24
Peak memory 232632 kb
Host smart-96d3d8c6-65b1-4c86-a792-fec7039e8412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528978320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.2528978320
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.85823713
Short name T185
Test name
Test status
Simulation time 550077048 ps
CPU time 9.66 seconds
Started Apr 15 01:18:53 PM PDT 24
Finished Apr 15 01:19:03 PM PDT 24
Peak memory 224032 kb
Host smart-799bdd4a-3c84-452a-b8b2-765e4c749d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85823713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.85823713
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.761917846
Short name T344
Test name
Test status
Simulation time 3790716372 ps
CPU time 14.01 seconds
Started Apr 15 01:18:54 PM PDT 24
Finished Apr 15 01:19:08 PM PDT 24
Peak memory 222516 kb
Host smart-a2af6820-8590-4481-be11-d37324242a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761917846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.
761917846
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.433541118
Short name T113
Test name
Test status
Simulation time 454144518 ps
CPU time 5.88 seconds
Started Apr 15 01:18:45 PM PDT 24
Finished Apr 15 01:18:51 PM PDT 24
Peak memory 231860 kb
Host smart-89ecce1c-1081-4b51-bb04-55863f84a584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433541118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.433541118
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.1497938748
Short name T590
Test name
Test status
Simulation time 1791729672 ps
CPU time 19.52 seconds
Started Apr 15 01:18:53 PM PDT 24
Finished Apr 15 01:19:14 PM PDT 24
Peak memory 222796 kb
Host smart-3d1afb01-0ad0-4c6d-8b2b-88ef8aaa4d26
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1497938748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.1497938748
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.1874790480
Short name T626
Test name
Test status
Simulation time 19334187703 ps
CPU time 25.21 seconds
Started Apr 15 01:18:52 PM PDT 24
Finished Apr 15 01:19:17 PM PDT 24
Peak memory 216252 kb
Host smart-b204927f-0d5e-494b-84cd-3d77f1e7079c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874790480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.1874790480
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.3380790259
Short name T703
Test name
Test status
Simulation time 19808601358 ps
CPU time 8.14 seconds
Started Apr 15 01:18:51 PM PDT 24
Finished Apr 15 01:19:00 PM PDT 24
Peak memory 216064 kb
Host smart-da670dfb-9352-400a-a815-f56310f2aa45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380790259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.3380790259
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.3104474822
Short name T715
Test name
Test status
Simulation time 278000100 ps
CPU time 2.43 seconds
Started Apr 15 01:18:50 PM PDT 24
Finished Apr 15 01:18:54 PM PDT 24
Peak memory 216260 kb
Host smart-56ab582c-6ec1-4d95-9995-d465b56f6e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104474822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.3104474822
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.2236071679
Short name T616
Test name
Test status
Simulation time 62464832 ps
CPU time 1.03 seconds
Started Apr 15 01:18:53 PM PDT 24
Finished Apr 15 01:18:54 PM PDT 24
Peak memory 206748 kb
Host smart-53adb068-5663-4ce2-b44f-589410415d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236071679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.2236071679
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.2648914543
Short name T243
Test name
Test status
Simulation time 9692453859 ps
CPU time 18.99 seconds
Started Apr 15 01:18:48 PM PDT 24
Finished Apr 15 01:19:08 PM PDT 24
Peak memory 232700 kb
Host smart-10f0550e-749b-43bd-b7c9-eb97d3cc748f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648914543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.2648914543
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.2029491451
Short name T481
Test name
Test status
Simulation time 44834971 ps
CPU time 0.71 seconds
Started Apr 15 01:18:58 PM PDT 24
Finished Apr 15 01:18:59 PM PDT 24
Peak memory 205372 kb
Host smart-8d6a534e-e150-4a2c-9c76-51aadc5cfdf6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029491451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.2
029491451
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.488739309
Short name T427
Test name
Test status
Simulation time 18171018 ps
CPU time 0.82 seconds
Started Apr 15 01:18:55 PM PDT 24
Finished Apr 15 01:18:56 PM PDT 24
Peak memory 206508 kb
Host smart-5d9c0572-5724-43ea-98b0-4b190574d725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488739309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.488739309
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.1572873165
Short name T629
Test name
Test status
Simulation time 987924469 ps
CPU time 26.76 seconds
Started Apr 15 01:18:59 PM PDT 24
Finished Apr 15 01:19:27 PM PDT 24
Peak memory 249004 kb
Host smart-35515838-cde7-4d48-9f62-bf28ae7eb583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572873165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1572873165
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.254709472
Short name T159
Test name
Test status
Simulation time 855926249 ps
CPU time 7.64 seconds
Started Apr 15 01:18:57 PM PDT 24
Finished Apr 15 01:19:05 PM PDT 24
Peak memory 233084 kb
Host smart-9dc5a8d1-74cf-41de-854a-915f083c38df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254709472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.254709472
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.4071363058
Short name T187
Test name
Test status
Simulation time 4159201348 ps
CPU time 16.73 seconds
Started Apr 15 01:18:54 PM PDT 24
Finished Apr 15 01:19:11 PM PDT 24
Peak memory 235248 kb
Host smart-f858b140-115b-47d7-a249-63ee1d535a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071363058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.4071363058
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.1231005846
Short name T410
Test name
Test status
Simulation time 125615645 ps
CPU time 4.5 seconds
Started Apr 15 01:18:59 PM PDT 24
Finished Apr 15 01:19:04 PM PDT 24
Peak memory 222000 kb
Host smart-2cfe0362-7648-4018-8aa4-3f3fe9bf9d32
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1231005846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.1231005846
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.2880112362
Short name T646
Test name
Test status
Simulation time 2587611380 ps
CPU time 33.56 seconds
Started Apr 15 01:18:54 PM PDT 24
Finished Apr 15 01:19:28 PM PDT 24
Peak memory 216284 kb
Host smart-366d5811-cb2e-4e65-aa55-4ca6c122f517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880112362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.2880112362
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.124183607
Short name T586
Test name
Test status
Simulation time 21653615364 ps
CPU time 22.78 seconds
Started Apr 15 01:18:54 PM PDT 24
Finished Apr 15 01:19:18 PM PDT 24
Peak memory 216264 kb
Host smart-f32361fb-4f98-43f9-bd3e-691e35f68730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124183607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.124183607
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.51481041
Short name T490
Test name
Test status
Simulation time 97942658 ps
CPU time 1.7 seconds
Started Apr 15 01:18:55 PM PDT 24
Finished Apr 15 01:18:58 PM PDT 24
Peak memory 216224 kb
Host smart-cc99b132-6b9c-408e-ad2a-bb178f6db5ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51481041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.51481041
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.440565265
Short name T663
Test name
Test status
Simulation time 164565787 ps
CPU time 0.87 seconds
Started Apr 15 01:18:53 PM PDT 24
Finished Apr 15 01:18:55 PM PDT 24
Peak memory 205684 kb
Host smart-c895acf6-9119-43a0-a853-8f78971cf9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440565265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.440565265
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.777607095
Short name T199
Test name
Test status
Simulation time 285792931 ps
CPU time 6.25 seconds
Started Apr 15 01:18:55 PM PDT 24
Finished Apr 15 01:19:02 PM PDT 24
Peak memory 232632 kb
Host smart-8ffa442f-12b4-4120-8e27-05bba1bee7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777607095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.777607095
Directory /workspace/9.spi_device_upload/latest
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