Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1616007	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1804399

1

T1

65

T2

3276

T3

17036

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2729556	1			T1	144		T2	9171		T3	32344
values[0x0]	345076	1			T1	33		T2	1585		T3	445
values[0x1]	345774	1			T1	24		T2	1587		T3	459

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1235429	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2184977

1

T1

97

T2

6113

T3

20347

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9530	1			T2	359		T3	140		T4	2
valid_sources[0x01]	9771	1			T3	123		T4	1		T5	8
valid_sources[0x02]	9681	1			T2	97		T3	187		T4	3
valid_sources[0x03]	9468	1			T3	98		T4	5		T5	2
valid_sources[0x04]	12511	1			T2	570		T3	119		T4	2
valid_sources[0x05]	17235	1			T2	229		T3	121		T4	2
valid_sources[0x06]	9216	1			T3	126		T4	3		T5	7
valid_sources[0x07]	21672	1			T3	158		T4	5		T5	7
valid_sources[0x08]	29714	1			T2	1		T3	116		T4	2
valid_sources[0x09]	9807	1			T3	113		T4	1		T5	3
valid_sources[0x0a]	9387	1			T1	3		T3	133		T4	3
valid_sources[0x0b]	9305	1			T3	143		T4	6		T5	6
valid_sources[0x0c]	10653	1			T2	3		T3	106		T4	3
valid_sources[0x0d]	9443	1			T1	7		T3	177		T4	9
valid_sources[0x0e]	9619	1			T1	1		T3	103		T4	10
valid_sources[0x0f]	14842	1			T3	107		T4	5		T5	7
valid_sources[0x10]	9577	1			T3	138		T4	2		T5	3
valid_sources[0x11]	25727	1			T3	130		T4	1		T5	6
valid_sources[0x12]	10954	1			T2	2		T3	132		T4	4
valid_sources[0x13]	8988	1			T3	107		T4	1		T5	2
valid_sources[0x14]	9444	1			T3	90		T4	2		T5	2
valid_sources[0x15]	112912	1			T3	126		T4	3		T5	6
valid_sources[0x16]	9006	1			T1	3		T2	151		T3	138
valid_sources[0x17]	18644	1			T3	143		T4	7		T5	3
valid_sources[0x18]	9219	1			T3	128		T4	4		T5	3
valid_sources[0x19]	9989	1			T3	145		T4	3		T5	5
valid_sources[0x1a]	11431	1			T1	2		T2	16		T3	128
valid_sources[0x1b]	12940	1			T1	2		T3	120		T4	2
valid_sources[0x1c]	10572	1			T3	126		T4	5		T5	10
valid_sources[0x1d]	13120	1			T2	1		T3	131		T4	3
valid_sources[0x1e]	10437	1			T3	109		T4	4		T5	10
valid_sources[0x1f]	24220	1			T3	144		T4	5		T5	5
valid_sources[0x20]	10050	1			T2	24		T3	75		T4	1
valid_sources[0x21]	10897	1			T3	131		T4	3		T5	4
valid_sources[0x22]	11611	1			T2	298		T3	112		T4	5
valid_sources[0x23]	16923	1			T2	785		T3	164		T4	3
valid_sources[0x24]	11205	1			T3	125		T4	4		T5	7
valid_sources[0x25]	10944	1			T1	5		T2	231		T3	158
valid_sources[0x26]	9446	1			T2	120		T3	106		T4	2
valid_sources[0x27]	10697	1			T3	124		T4	3		T5	4
valid_sources[0x28]	9837	1			T3	157		T4	5		T5	6
valid_sources[0x29]	9341	1			T3	129		T4	4		T5	5
valid_sources[0x2a]	9198	1			T3	135		T4	1		T5	2
valid_sources[0x2b]	77434	1			T2	174		T3	188		T4	3
valid_sources[0x2c]	13228	1			T3	130		T4	6		T5	3
valid_sources[0x2d]	12332	1			T1	1		T3	137		T4	4
valid_sources[0x2e]	9883	1			T3	120		T4	3		T5	6
valid_sources[0x2f]	14197	1			T3	134		T5	4		T14	1
valid_sources[0x30]	10977	1			T3	121		T4	1		T5	5
valid_sources[0x31]	13577	1			T3	127		T4	1		T5	4
valid_sources[0x32]	12722	1			T2	3		T3	167		T4	2
valid_sources[0x33]	10799	1			T1	1		T2	504		T3	102
valid_sources[0x34]	9762	1			T1	5		T3	154		T4	2
valid_sources[0x35]	9206	1			T3	129		T4	4		T5	11
valid_sources[0x36]	9913	1			T3	169		T4	2		T5	4
valid_sources[0x37]	10192	1			T1	2		T3	125		T4	3
valid_sources[0x38]	14981	1			T2	4		T3	104		T4	4
valid_sources[0x39]	9688	1			T3	159		T4	4		T5	5
valid_sources[0x3a]	10619	1			T3	133		T4	4		T5	2
valid_sources[0x3b]	10148	1			T3	137		T4	7		T5	2
valid_sources[0x3c]	66954	1			T2	1		T3	153		T4	4
valid_sources[0x3d]	10974	1			T2	36		T3	110		T4	2
valid_sources[0x3e]	9581	1			T1	3		T2	1		T3	90
valid_sources[0x3f]	9349	1			T3	102		T4	5		T5	3
valid_sources[0x40]	26088	1			T2	529		T3	126		T4	3
valid_sources[0x41]	15855	1			T3	124		T4	1		T5	14
valid_sources[0x42]	10564	1			T3	133		T4	2		T5	7
valid_sources[0x43]	10640	1			T1	3		T3	142		T4	7
valid_sources[0x44]	9838	1			T2	327		T3	85		T4	1
valid_sources[0x45]	8506	1			T2	1		T3	110		T4	6
valid_sources[0x46]	11297	1			T2	1		T3	133		T4	1
valid_sources[0x47]	12970	1			T2	25		T3	154		T5	11
valid_sources[0x48]	9553	1			T2	3		T3	134		T4	1
valid_sources[0x49]	20054	1			T3	109		T4	4		T5	2
valid_sources[0x4a]	9070	1			T3	134		T4	2		T5	7
valid_sources[0x4b]	9900	1			T3	126		T4	4		T5	6
valid_sources[0x4c]	8789	1			T1	1		T3	134		T4	1
valid_sources[0x4d]	12028	1			T3	142		T4	3		T5	5
valid_sources[0x4e]	11766	1			T3	144		T4	9		T5	6
valid_sources[0x4f]	12765	1			T2	3		T3	86		T4	4
valid_sources[0x50]	10247	1			T1	7		T2	166		T3	142
valid_sources[0x51]	34395	1			T2	3		T3	131		T4	2
valid_sources[0x52]	9617	1			T3	130		T4	4		T14	10
valid_sources[0x53]	12243	1			T2	74		T3	107		T4	3
valid_sources[0x54]	10236	1			T3	132		T4	5		T5	2
valid_sources[0x55]	10687	1			T3	151		T4	3		T5	9
valid_sources[0x56]	49534	1			T3	152		T4	2		T5	4
valid_sources[0x57]	10676	1			T1	8		T3	95		T4	3
valid_sources[0x58]	13269	1			T2	126		T3	126		T5	6
valid_sources[0x59]	26820	1			T3	106		T4	3		T5	6
valid_sources[0x5a]	10510	1			T1	4		T3	124		T4	4
valid_sources[0x5b]	10729	1			T1	1		T3	171		T4	2
valid_sources[0x5c]	9375	1			T3	103		T4	2		T5	2
valid_sources[0x5d]	8972	1			T3	131		T4	2		T5	2
valid_sources[0x5e]	14393	1			T1	4		T3	120		T4	3
valid_sources[0x5f]	10366	1			T1	1		T2	195		T3	137
valid_sources[0x60]	10077	1			T2	585		T3	111		T4	2
valid_sources[0x61]	31918	1			T3	94		T4	4		T5	5
valid_sources[0x62]	9475	1			T3	92		T4	2		T5	2
valid_sources[0x63]	9481	1			T3	124		T4	8		T5	6
valid_sources[0x64]	9734	1			T3	143		T4	2		T5	5
valid_sources[0x65]	10069	1			T1	5		T2	1		T3	132
valid_sources[0x66]	9645	1			T2	121		T3	140		T4	8
valid_sources[0x67]	9415	1			T3	134		T5	6		T14	4
valid_sources[0x68]	10548	1			T1	2		T3	98		T4	3
valid_sources[0x69]	10217	1			T1	1		T3	149		T4	5
valid_sources[0x6a]	9337	1			T3	150		T4	2		T5	6
valid_sources[0x6b]	9258	1			T2	30		T3	92		T4	2
valid_sources[0x6c]	9277	1			T2	226		T3	187		T4	3
valid_sources[0x6d]	22981	1			T1	1		T2	383		T3	126
valid_sources[0x6e]	9089	1			T2	4		T3	118		T4	2
valid_sources[0x6f]	16706	1			T1	4		T3	149		T4	4
valid_sources[0x70]	10249	1			T3	172		T4	1		T5	5
valid_sources[0x71]	9567	1			T3	118		T4	3		T5	10
valid_sources[0x72]	9881	1			T2	2		T3	119		T4	4
valid_sources[0x73]	10929	1			T2	1052		T3	101		T4	3
valid_sources[0x74]	13910	1			T3	145		T4	5		T5	7
valid_sources[0x75]	13068	1			T3	127		T4	6		T5	3
valid_sources[0x76]	11340	1			T2	1066		T3	113		T4	2
valid_sources[0x77]	8894	1			T3	122		T4	4		T5	7
valid_sources[0x78]	12949	1			T3	137		T4	7		T5	9
valid_sources[0x79]	12059	1			T1	11		T3	112		T4	2
valid_sources[0x7a]	11121	1			T3	150		T4	6		T5	2
valid_sources[0x7b]	9519	1			T3	108		T4	1		T5	6
valid_sources[0x7c]	9476	1			T2	52		T3	154		T4	2
valid_sources[0x7d]	9270	1			T1	12		T3	135		T4	2
valid_sources[0x7e]	9308	1			T3	163		T4	4		T5	3
valid_sources[0x7f]	9503	1			T3	171		T4	2		T5	7
valid_sources[0x80]	9618	1			T3	137		T4	4		T5	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1180757

1

T1

25

T2

933

T3

16141

values[0x0]

all_enables

biggest_size

315489

1

T1

24

T2

1197

T3

444

values[0x1]

all_enables

biggest_size

308153

1

T1

16

T2

1146

T3

451